31 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)  in sirfsoc_alloc_gc()  argument
43 	gc->reg_base = base;  in sirfsoc_alloc_gc()
52 	void __iomem *base = sirfsoc_irqdomain->host_data;  in sirfsoc_handle_irq()  local
55 	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);  in sirfsoc_handle_irq()
62 	void __iomem *base = of_iomap(np, 0);  in sirfsoc_irq_init()  local
63 	if (!base)  in sirfsoc_irq_init()
67 		&irq_generic_chip_ops, base);  in sirfsoc_irq_init()
69 	sirfsoc_alloc_gc(base, 0, 32);  in sirfsoc_irq_init()
70 	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);  in sirfsoc_irq_init()
72 	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);  in sirfsoc_irq_init()
73 	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);  in sirfsoc_irq_init()
75 	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);  in sirfsoc_irq_init()
76 	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);  in sirfsoc_irq_init()
95 	void __iomem *base = sirfsoc_irqdomain->host_data;  in sirfsoc_irq_suspend()  local
97 	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);  in sirfsoc_irq_suspend()
98 	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);  in sirfsoc_irq_suspend()
99 	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);  in sirfsoc_irq_suspend()
100 	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);  in sirfsoc_irq_suspend()
107 	void __iomem *base = sirfsoc_irqdomain->host_data;  in sirfsoc_irq_resume()  local
109 	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);  in sirfsoc_irq_resume()
110 	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);  in sirfsoc_irq_resume()
111 	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);  in sirfsoc_irq_resume()
112 	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);  in sirfsoc_irq_resume()