37 	void __iomem *base;  member
175 	void __iomem *base = phy->reg_base;  in dsi_28nm_phy_regulator_ctrl()  local
178 		dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);  in dsi_28nm_phy_regulator_ctrl()
182 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);  in dsi_28nm_phy_regulator_ctrl()
183 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1);  in dsi_28nm_phy_regulator_ctrl()
184 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0);  in dsi_28nm_phy_regulator_ctrl()
185 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);  in dsi_28nm_phy_regulator_ctrl()
186 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3);  in dsi_28nm_phy_regulator_ctrl()
187 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9);  in dsi_28nm_phy_regulator_ctrl()
188 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7);  in dsi_28nm_phy_regulator_ctrl()
189 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);  in dsi_28nm_phy_regulator_ctrl()
197 	void __iomem *base = phy->base;  in dsi_28nm_phy_enable()  local
206 	dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff);  in dsi_28nm_phy_enable()
210 	dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);  in dsi_28nm_phy_enable()
212 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0,  in dsi_28nm_phy_enable()
214 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1,  in dsi_28nm_phy_enable()
216 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2,  in dsi_28nm_phy_enable()
219 		dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3,  in dsi_28nm_phy_enable()
221 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4,  in dsi_28nm_phy_enable()
223 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5,  in dsi_28nm_phy_enable()
225 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6,  in dsi_28nm_phy_enable()
227 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7,  in dsi_28nm_phy_enable()
229 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8,  in dsi_28nm_phy_enable()
231 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9,  in dsi_28nm_phy_enable()
234 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10,  in dsi_28nm_phy_enable()
236 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11,  in dsi_28nm_phy_enable()
239 	dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00);  in dsi_28nm_phy_enable()
240 	dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);  in dsi_28nm_phy_enable()
242 	dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6);  in dsi_28nm_phy_enable()
245 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0);  in dsi_28nm_phy_enable()
246 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);  in dsi_28nm_phy_enable()
247 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);  in dsi_28nm_phy_enable()
248 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);  in dsi_28nm_phy_enable()
249 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);  in dsi_28nm_phy_enable()
250 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);  in dsi_28nm_phy_enable()
251 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);  in dsi_28nm_phy_enable()
252 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);  in dsi_28nm_phy_enable()
254 	dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0);  in dsi_28nm_phy_enable()
255 	dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5);  in dsi_28nm_phy_enable()
256 	dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa);  in dsi_28nm_phy_enable()
257 	dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf);  in dsi_28nm_phy_enable()
259 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);  in dsi_28nm_phy_enable()
260 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);  in dsi_28nm_phy_enable()
261 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);  in dsi_28nm_phy_enable()
263 	dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);  in dsi_28nm_phy_enable()
266 		dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, 0x00);  in dsi_28nm_phy_enable()
268 		dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, 0x01);  in dsi_28nm_phy_enable()
275 	dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0);  in dsi_28nm_phy_disable()
302 	phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");  in msm_dsi_phy_init()
303 	if (IS_ERR_OR_NULL(phy->base)) {  in msm_dsi_phy_init()