Searched refs:hw (Results 1 - 200 of 2813) sorted by relevance

1234567891011>>

/linux-4.4.14/drivers/gpu/host1x/
H A DMakefile11 hw/host1x01.o \
12 hw/host1x02.o \
13 hw/host1x04.o
/linux-4.4.14/drivers/media/platform/s5p-jpeg/
H A DMakefile1 s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
/linux-4.4.14/drivers/spi/
H A Dspi-oc-tiny.c67 struct tiny_spi *hw = tiny_spi_to_hw(spi); tiny_spi_baud() local
69 return min(DIV_ROUND_UP(hw->freq, hz * 2), (1U << hw->baudwidth)) - 1; tiny_spi_baud()
74 struct tiny_spi *hw = tiny_spi_to_hw(spi); tiny_spi_chipselect() local
76 if (hw->gpio_cs_count > 0) { tiny_spi_chipselect()
77 gpio_set_value(hw->gpio_cs[spi->chip_select], tiny_spi_chipselect()
85 struct tiny_spi *hw = tiny_spi_to_hw(spi); tiny_spi_setup_transfer() local
86 unsigned int baud = hw->baud; tiny_spi_setup_transfer()
89 if (t->speed_hz && t->speed_hz != hw->speed_hz) tiny_spi_setup_transfer()
92 writel(baud, hw->base + TINY_SPI_BAUD); tiny_spi_setup_transfer()
93 writel(hw->mode, hw->base + TINY_SPI_CONTROL); tiny_spi_setup_transfer()
99 struct tiny_spi *hw = tiny_spi_to_hw(spi); tiny_spi_setup() local
101 if (spi->max_speed_hz != hw->speed_hz) { tiny_spi_setup()
102 hw->speed_hz = spi->max_speed_hz; tiny_spi_setup()
103 hw->baud = tiny_spi_baud(spi, hw->speed_hz); tiny_spi_setup()
105 hw->mode = spi->mode & (SPI_CPOL | SPI_CPHA); tiny_spi_setup()
109 static inline void tiny_spi_wait_txr(struct tiny_spi *hw) tiny_spi_wait_txr() argument
111 while (!(readb(hw->base + TINY_SPI_STATUS) & tiny_spi_wait_txr()
116 static inline void tiny_spi_wait_txe(struct tiny_spi *hw) tiny_spi_wait_txe() argument
118 while (!(readb(hw->base + TINY_SPI_STATUS) & tiny_spi_wait_txe()
125 struct tiny_spi *hw = tiny_spi_to_hw(spi); tiny_spi_txrx_bufs() local
130 if (hw->irq >= 0) { tiny_spi_txrx_bufs()
132 hw->len = t->len; tiny_spi_txrx_bufs()
133 hw->txp = t->tx_buf; tiny_spi_txrx_bufs()
134 hw->rxp = t->rx_buf; tiny_spi_txrx_bufs()
135 hw->txc = 0; tiny_spi_txrx_bufs()
136 hw->rxc = 0; tiny_spi_txrx_bufs()
140 writeb(hw->txp ? *hw->txp++ : 0, tiny_spi_txrx_bufs()
141 hw->base + TINY_SPI_TXDATA); tiny_spi_txrx_bufs()
142 hw->txc++; tiny_spi_txrx_bufs()
143 writeb(hw->txp ? *hw->txp++ : 0, tiny_spi_txrx_bufs()
144 hw->base + TINY_SPI_TXDATA); tiny_spi_txrx_bufs()
145 hw->txc++; tiny_spi_txrx_bufs()
146 writeb(TINY_SPI_STATUS_TXR, hw->base + TINY_SPI_STATUS); tiny_spi_txrx_bufs()
148 writeb(hw->txp ? *hw->txp++ : 0, tiny_spi_txrx_bufs()
149 hw->base + TINY_SPI_TXDATA); tiny_spi_txrx_bufs()
150 hw->txc++; tiny_spi_txrx_bufs()
151 writeb(TINY_SPI_STATUS_TXE, hw->base + TINY_SPI_STATUS); tiny_spi_txrx_bufs()
154 wait_for_completion(&hw->done); tiny_spi_txrx_bufs()
157 writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA); tiny_spi_txrx_bufs()
159 writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA); tiny_spi_txrx_bufs()
162 tiny_spi_wait_txr(hw); tiny_spi_txrx_bufs()
164 *rxp++ = readb(hw->base + TINY_SPI_TXDATA); tiny_spi_txrx_bufs()
166 tiny_spi_wait_txe(hw); tiny_spi_txrx_bufs()
168 *rxp++ = readb(hw->base + TINY_SPI_RXDATA); tiny_spi_txrx_bufs()
176 struct tiny_spi *hw = dev; tiny_spi_irq() local
178 writeb(0, hw->base + TINY_SPI_STATUS); tiny_spi_irq()
179 if (hw->rxc + 1 == hw->len) { tiny_spi_irq()
180 if (hw->rxp) tiny_spi_irq()
181 *hw->rxp++ = readb(hw->base + TINY_SPI_RXDATA); tiny_spi_irq()
182 hw->rxc++; tiny_spi_irq()
183 complete(&hw->done); tiny_spi_irq()
185 if (hw->rxp) tiny_spi_irq()
186 *hw->rxp++ = readb(hw->base + TINY_SPI_TXDATA); tiny_spi_irq()
187 hw->rxc++; tiny_spi_irq()
188 if (hw->txc < hw->len) { tiny_spi_irq()
189 writeb(hw->txp ? *hw->txp++ : 0, tiny_spi_irq()
190 hw->base + TINY_SPI_TXDATA); tiny_spi_irq()
191 hw->txc++; tiny_spi_irq()
193 hw->base + TINY_SPI_STATUS); tiny_spi_irq()
196 hw->base + TINY_SPI_STATUS); tiny_spi_irq()
207 struct tiny_spi *hw = platform_get_drvdata(pdev); tiny_spi_of_probe() local
214 hw->gpio_cs_count = of_gpio_count(np); tiny_spi_of_probe()
215 if (hw->gpio_cs_count > 0) { tiny_spi_of_probe()
216 hw->gpio_cs = devm_kzalloc(&pdev->dev, tiny_spi_of_probe()
217 hw->gpio_cs_count * sizeof(unsigned int), tiny_spi_of_probe()
219 if (!hw->gpio_cs) tiny_spi_of_probe()
222 for (i = 0; i < hw->gpio_cs_count; i++) { tiny_spi_of_probe()
223 hw->gpio_cs[i] = of_get_gpio_flags(np, i, NULL); tiny_spi_of_probe()
224 if (hw->gpio_cs[i] < 0) tiny_spi_of_probe()
227 hw->bitbang.master->dev.of_node = pdev->dev.of_node; tiny_spi_of_probe()
229 hw->freq = val; tiny_spi_of_probe()
231 hw->baudwidth = val; tiny_spi_of_probe()
244 struct tiny_spi *hw; tiny_spi_probe() local
260 hw = spi_master_get_devdata(master); tiny_spi_probe()
261 platform_set_drvdata(pdev, hw); tiny_spi_probe()
264 hw->bitbang.master = master; tiny_spi_probe()
265 hw->bitbang.setup_transfer = tiny_spi_setup_transfer; tiny_spi_probe()
266 hw->bitbang.chipselect = tiny_spi_chipselect; tiny_spi_probe()
267 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs; tiny_spi_probe()
271 hw->base = devm_ioremap_resource(&pdev->dev, res); tiny_spi_probe()
272 if (IS_ERR(hw->base)) { tiny_spi_probe()
273 err = PTR_ERR(hw->base); tiny_spi_probe()
277 hw->irq = platform_get_irq(pdev, 0); tiny_spi_probe()
278 if (hw->irq >= 0) { tiny_spi_probe()
279 init_completion(&hw->done); tiny_spi_probe()
280 err = devm_request_irq(&pdev->dev, hw->irq, tiny_spi_irq, 0, tiny_spi_probe()
281 pdev->name, hw); tiny_spi_probe()
287 hw->gpio_cs_count = platp->gpio_cs_count; tiny_spi_probe()
288 hw->gpio_cs = platp->gpio_cs; tiny_spi_probe()
293 hw->freq = platp->freq; tiny_spi_probe()
294 hw->baudwidth = platp->baudwidth; tiny_spi_probe()
300 for (i = 0; i < hw->gpio_cs_count; i++) { tiny_spi_probe()
301 err = gpio_request(hw->gpio_cs[i], dev_name(&pdev->dev)); tiny_spi_probe()
304 gpio_direction_output(hw->gpio_cs[i], 1); tiny_spi_probe()
306 hw->bitbang.master->num_chipselect = max(1, hw->gpio_cs_count); tiny_spi_probe()
309 err = spi_bitbang_start(&hw->bitbang); tiny_spi_probe()
312 dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq); tiny_spi_probe()
318 gpio_free(hw->gpio_cs[i]); tiny_spi_probe()
326 struct tiny_spi *hw = platform_get_drvdata(pdev); tiny_spi_remove() local
327 struct spi_master *master = hw->bitbang.master; tiny_spi_remove()
330 spi_bitbang_stop(&hw->bitbang); tiny_spi_remove()
331 for (i = 0; i < hw->gpio_cs_count; i++) tiny_spi_remove()
332 gpio_free(hw->gpio_cs[i]); tiny_spi_remove()
H A Dspi-altera.c71 struct altera_spi *hw = altera_spi_to_hw(spi); altera_spi_chipsel() local
77 hw->base + ALTERA_SPI_SLAVE_SEL); altera_spi_chipsel()
78 hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK; altera_spi_chipsel()
79 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
83 hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK; altera_spi_chipsel()
84 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
85 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL); altera_spi_chipsel()
91 hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK; altera_spi_chipsel()
92 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
97 hw->base + ALTERA_SPI_SLAVE_SEL); altera_spi_chipsel()
98 hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK; altera_spi_chipsel()
99 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
105 static inline unsigned int hw_txbyte(struct altera_spi *hw, int count) hw_txbyte() argument
107 if (hw->tx) { hw_txbyte()
108 switch (hw->bytes_per_word) { hw_txbyte()
110 return hw->tx[count]; hw_txbyte()
112 return (hw->tx[count * 2] hw_txbyte()
113 | (hw->tx[count * 2 + 1] << 8)); hw_txbyte()
121 struct altera_spi *hw = altera_spi_to_hw(spi); altera_spi_txrx() local
123 hw->tx = t->tx_buf; altera_spi_txrx()
124 hw->rx = t->rx_buf; altera_spi_txrx()
125 hw->count = 0; altera_spi_txrx()
126 hw->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8); altera_spi_txrx()
127 hw->len = t->len / hw->bytes_per_word; altera_spi_txrx()
129 if (hw->irq >= 0) { altera_spi_txrx()
131 hw->imr |= ALTERA_SPI_CONTROL_IRRDY_MSK; altera_spi_txrx()
132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_txrx()
135 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA); altera_spi_txrx()
137 wait_for_completion(&hw->done); altera_spi_txrx()
139 hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK; altera_spi_txrx()
140 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_txrx()
142 while (hw->count < hw->len) { altera_spi_txrx()
145 writel(hw_txbyte(hw, hw->count), altera_spi_txrx()
146 hw->base + ALTERA_SPI_TXDATA); altera_spi_txrx()
148 while (!(readl(hw->base + ALTERA_SPI_STATUS) & altera_spi_txrx()
152 rxd = readl(hw->base + ALTERA_SPI_RXDATA); altera_spi_txrx()
153 if (hw->rx) { altera_spi_txrx()
154 switch (hw->bytes_per_word) { altera_spi_txrx()
156 hw->rx[hw->count] = rxd; altera_spi_txrx()
159 hw->rx[hw->count * 2] = rxd; altera_spi_txrx()
160 hw->rx[hw->count * 2 + 1] = rxd >> 8; altera_spi_txrx()
165 hw->count++; altera_spi_txrx()
169 return hw->count * hw->bytes_per_word; altera_spi_txrx()
174 struct altera_spi *hw = dev; altera_spi_irq() local
177 rxd = readl(hw->base + ALTERA_SPI_RXDATA); altera_spi_irq()
178 if (hw->rx) { altera_spi_irq()
179 switch (hw->bytes_per_word) { altera_spi_irq()
181 hw->rx[hw->count] = rxd; altera_spi_irq()
184 hw->rx[hw->count * 2] = rxd; altera_spi_irq()
185 hw->rx[hw->count * 2 + 1] = rxd >> 8; altera_spi_irq()
190 hw->count++; altera_spi_irq()
192 if (hw->count < hw->len) altera_spi_irq()
193 writel(hw_txbyte(hw, hw->count), hw->base + ALTERA_SPI_TXDATA); altera_spi_irq()
195 complete(&hw->done); altera_spi_irq()
202 struct altera_spi *hw; altera_spi_probe() local
218 hw = spi_master_get_devdata(master); altera_spi_probe()
219 platform_set_drvdata(pdev, hw); altera_spi_probe()
222 hw->bitbang.master = master; altera_spi_probe()
223 hw->bitbang.chipselect = altera_spi_chipsel; altera_spi_probe()
224 hw->bitbang.txrx_bufs = altera_spi_txrx; altera_spi_probe()
228 hw->base = devm_ioremap_resource(&pdev->dev, res); altera_spi_probe()
229 if (IS_ERR(hw->base)) { altera_spi_probe()
230 err = PTR_ERR(hw->base); altera_spi_probe()
234 hw->imr = 0; /* disable spi interrupts */ altera_spi_probe()
235 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_probe()
236 writel(0, hw->base + ALTERA_SPI_STATUS); /* clear status reg */ altera_spi_probe()
237 if (readl(hw->base + ALTERA_SPI_STATUS) & ALTERA_SPI_STATUS_RRDY_MSK) altera_spi_probe()
238 readl(hw->base + ALTERA_SPI_RXDATA); /* flush rxdata */ altera_spi_probe()
240 hw->irq = platform_get_irq(pdev, 0); altera_spi_probe()
241 if (hw->irq >= 0) { altera_spi_probe()
242 init_completion(&hw->done); altera_spi_probe()
243 err = devm_request_irq(&pdev->dev, hw->irq, altera_spi_irq, 0, altera_spi_probe()
244 pdev->name, hw); altera_spi_probe()
250 err = spi_bitbang_start(&hw->bitbang); altera_spi_probe()
253 dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq); altera_spi_probe()
263 struct altera_spi *hw = platform_get_drvdata(dev); altera_spi_remove() local
264 struct spi_master *master = hw->bitbang.master; altera_spi_remove()
266 spi_bitbang_stop(&hw->bitbang); altera_spi_remove()
H A Dspi-nuc900.c72 struct nuc900_spi *hw = to_hw(spi); nuc900_slave_select() local
78 spin_lock_irqsave(&hw->lock, flags); nuc900_slave_select()
80 val = __raw_readl(hw->regs + USI_SSR); nuc900_slave_select()
92 __raw_writel(val, hw->regs + USI_SSR); nuc900_slave_select()
94 val = __raw_readl(hw->regs + USI_CNT); nuc900_slave_select()
101 __raw_writel(val, hw->regs + USI_CNT); nuc900_slave_select()
103 spin_unlock_irqrestore(&hw->lock, flags); nuc900_slave_select()
119 static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum) nuc900_spi_setup_txnum() argument
124 spin_lock_irqsave(&hw->lock, flags); nuc900_spi_setup_txnum()
126 val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM; nuc900_spi_setup_txnum()
131 __raw_writel(val, hw->regs + USI_CNT); nuc900_spi_setup_txnum()
133 spin_unlock_irqrestore(&hw->lock, flags); nuc900_spi_setup_txnum()
137 static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw, nuc900_spi_setup_txbitlen() argument
143 spin_lock_irqsave(&hw->lock, flags); nuc900_spi_setup_txbitlen()
145 val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN; nuc900_spi_setup_txbitlen()
149 __raw_writel(val, hw->regs + USI_CNT); nuc900_spi_setup_txbitlen()
151 spin_unlock_irqrestore(&hw->lock, flags); nuc900_spi_setup_txbitlen()
154 static void nuc900_spi_gobusy(struct nuc900_spi *hw) nuc900_spi_gobusy() argument
159 spin_lock_irqsave(&hw->lock, flags); nuc900_spi_gobusy()
161 val = __raw_readl(hw->regs + USI_CNT); nuc900_spi_gobusy()
165 __raw_writel(val, hw->regs + USI_CNT); nuc900_spi_gobusy()
167 spin_unlock_irqrestore(&hw->lock, flags); nuc900_spi_gobusy()
170 static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count) hw_txbyte() argument
172 return hw->tx ? hw->tx[count] : 0; hw_txbyte()
177 struct nuc900_spi *hw = to_hw(spi); nuc900_spi_txrx() local
179 hw->tx = t->tx_buf; nuc900_spi_txrx()
180 hw->rx = t->rx_buf; nuc900_spi_txrx()
181 hw->len = t->len; nuc900_spi_txrx()
182 hw->count = 0; nuc900_spi_txrx()
184 __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0); nuc900_spi_txrx()
186 nuc900_spi_gobusy(hw); nuc900_spi_txrx()
188 wait_for_completion(&hw->done); nuc900_spi_txrx()
190 return hw->count; nuc900_spi_txrx()
195 struct nuc900_spi *hw = dev; nuc900_spi_irq() local
197 unsigned int count = hw->count; nuc900_spi_irq()
199 status = __raw_readl(hw->regs + USI_CNT); nuc900_spi_irq()
200 __raw_writel(status, hw->regs + USI_CNT); nuc900_spi_irq()
203 hw->count++; nuc900_spi_irq()
205 if (hw->rx) nuc900_spi_irq()
206 hw->rx[count] = __raw_readl(hw->regs + USI_RX0); nuc900_spi_irq()
209 if (count < hw->len) { nuc900_spi_irq()
210 __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0); nuc900_spi_irq()
211 nuc900_spi_gobusy(hw); nuc900_spi_irq()
213 complete(&hw->done); nuc900_spi_irq()
219 complete(&hw->done); nuc900_spi_irq()
223 static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge) nuc900_tx_edge() argument
228 spin_lock_irqsave(&hw->lock, flags); nuc900_tx_edge()
230 val = __raw_readl(hw->regs + USI_CNT); nuc900_tx_edge()
236 __raw_writel(val, hw->regs + USI_CNT); nuc900_tx_edge()
238 spin_unlock_irqrestore(&hw->lock, flags); nuc900_tx_edge()
241 static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge) nuc900_rx_edge() argument
246 spin_lock_irqsave(&hw->lock, flags); nuc900_rx_edge()
248 val = __raw_readl(hw->regs + USI_CNT); nuc900_rx_edge()
254 __raw_writel(val, hw->regs + USI_CNT); nuc900_rx_edge()
256 spin_unlock_irqrestore(&hw->lock, flags); nuc900_rx_edge()
259 static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb) nuc900_send_first() argument
264 spin_lock_irqsave(&hw->lock, flags); nuc900_send_first()
266 val = __raw_readl(hw->regs + USI_CNT); nuc900_send_first()
272 __raw_writel(val, hw->regs + USI_CNT); nuc900_send_first()
274 spin_unlock_irqrestore(&hw->lock, flags); nuc900_send_first()
277 static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep) nuc900_set_sleep() argument
282 spin_lock_irqsave(&hw->lock, flags); nuc900_set_sleep()
284 val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP; nuc900_set_sleep()
289 __raw_writel(val, hw->regs + USI_CNT); nuc900_set_sleep()
291 spin_unlock_irqrestore(&hw->lock, flags); nuc900_set_sleep()
294 static void nuc900_enable_int(struct nuc900_spi *hw) nuc900_enable_int() argument
299 spin_lock_irqsave(&hw->lock, flags); nuc900_enable_int()
301 val = __raw_readl(hw->regs + USI_CNT); nuc900_enable_int()
305 __raw_writel(val, hw->regs + USI_CNT); nuc900_enable_int()
307 spin_unlock_irqrestore(&hw->lock, flags); nuc900_enable_int()
310 static void nuc900_set_divider(struct nuc900_spi *hw) nuc900_set_divider() argument
312 __raw_writel(hw->pdata->divider, hw->regs + USI_DIV); nuc900_set_divider()
315 static void nuc900_init_spi(struct nuc900_spi *hw) nuc900_init_spi() argument
317 clk_enable(hw->clk); nuc900_init_spi()
318 spin_lock_init(&hw->lock); nuc900_init_spi()
320 nuc900_tx_edge(hw, hw->pdata->txneg); nuc900_init_spi()
321 nuc900_rx_edge(hw, hw->pdata->rxneg); nuc900_init_spi()
322 nuc900_send_first(hw, hw->pdata->lsb); nuc900_init_spi()
323 nuc900_set_sleep(hw, hw->pdata->sleep); nuc900_init_spi()
324 nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen); nuc900_init_spi()
325 nuc900_spi_setup_txnum(hw, hw->pdata->txnum); nuc900_init_spi()
326 nuc900_set_divider(hw); nuc900_init_spi()
327 nuc900_enable_int(hw); nuc900_init_spi()
332 struct nuc900_spi *hw; nuc900_spi_probe() local
343 hw = spi_master_get_devdata(master); nuc900_spi_probe()
344 hw->master = master; nuc900_spi_probe()
345 hw->pdata = dev_get_platdata(&pdev->dev); nuc900_spi_probe()
347 if (hw->pdata == NULL) { nuc900_spi_probe()
353 platform_set_drvdata(pdev, hw); nuc900_spi_probe()
354 init_completion(&hw->done); nuc900_spi_probe()
357 if (hw->pdata->lsb) nuc900_spi_probe()
359 master->num_chipselect = hw->pdata->num_cs; nuc900_spi_probe()
360 master->bus_num = hw->pdata->bus_num; nuc900_spi_probe()
361 hw->bitbang.master = hw->master; nuc900_spi_probe()
362 hw->bitbang.chipselect = nuc900_spi_chipsel; nuc900_spi_probe()
363 hw->bitbang.txrx_bufs = nuc900_spi_txrx; nuc900_spi_probe()
366 hw->regs = devm_ioremap_resource(&pdev->dev, res); nuc900_spi_probe()
367 if (IS_ERR(hw->regs)) { nuc900_spi_probe()
368 err = PTR_ERR(hw->regs); nuc900_spi_probe()
372 hw->irq = platform_get_irq(pdev, 0); nuc900_spi_probe()
373 if (hw->irq < 0) { nuc900_spi_probe()
379 err = devm_request_irq(&pdev->dev, hw->irq, nuc900_spi_irq, 0, nuc900_spi_probe()
380 pdev->name, hw); nuc900_spi_probe()
386 hw->clk = devm_clk_get(&pdev->dev, "spi"); nuc900_spi_probe()
387 if (IS_ERR(hw->clk)) { nuc900_spi_probe()
389 err = PTR_ERR(hw->clk); nuc900_spi_probe()
394 nuc900_init_spi(hw); nuc900_spi_probe()
396 err = spi_bitbang_start(&hw->bitbang); nuc900_spi_probe()
405 clk_disable(hw->clk); nuc900_spi_probe()
407 spi_master_put(hw->master); nuc900_spi_probe()
413 struct nuc900_spi *hw = platform_get_drvdata(dev); nuc900_spi_remove() local
415 spi_bitbang_stop(&hw->bitbang); nuc900_spi_remove()
416 clk_disable(hw->clk); nuc900_spi_remove()
417 spi_master_put(hw->master); nuc900_spi_remove()
H A Dspi-sc18is602.c55 static int sc18is602_wait_ready(struct sc18is602 *hw, int len) sc18is602_wait_ready() argument
58 int usecs = 1000000 * len / hw->speed + 1; sc18is602_wait_ready()
62 err = i2c_master_recv(hw->client, dummy, 1); sc18is602_wait_ready()
70 static int sc18is602_txrx(struct sc18is602 *hw, struct spi_message *msg, sc18is602_txrx() argument
76 if (hw->tlen == 0) { sc18is602_txrx()
78 hw->buffer[0] = 1 << msg->spi->chip_select; sc18is602_txrx()
79 hw->tlen = 1; sc18is602_txrx()
80 hw->rindex = 0; sc18is602_txrx()
88 memcpy(&hw->buffer[hw->tlen], t->tx_buf, len); sc18is602_txrx()
89 hw->tlen += len; sc18is602_txrx()
93 hw->rindex = hw->tlen - 1; sc18is602_txrx()
101 hw->rindex = hw->tlen - 1; sc18is602_txrx()
102 memset(&hw->buffer[hw->tlen], 0, len); sc18is602_txrx()
103 hw->tlen += len; sc18is602_txrx()
107 if (do_transfer && hw->tlen > 1) { sc18is602_txrx()
108 ret = sc18is602_wait_ready(hw, SC18IS602_BUFSIZ); sc18is602_txrx()
111 ret = i2c_master_send(hw->client, hw->buffer, hw->tlen); sc18is602_txrx()
114 if (ret != hw->tlen) sc18is602_txrx()
118 int rlen = hw->rindex + len; sc18is602_txrx()
120 ret = sc18is602_wait_ready(hw, hw->tlen); sc18is602_txrx()
123 ret = i2c_master_recv(hw->client, hw->buffer, rlen); sc18is602_txrx()
128 memcpy(t->rx_buf, &hw->buffer[hw->rindex], len); sc18is602_txrx()
130 hw->tlen = 0; sc18is602_txrx()
135 static int sc18is602_setup_transfer(struct sc18is602 *hw, u32 hz, u8 mode) sc18is602_setup_transfer() argument
148 if (hz >= hw->freq / 4) { sc18is602_setup_transfer()
150 hw->speed = hw->freq / 4; sc18is602_setup_transfer()
151 } else if (hz >= hw->freq / 16) { sc18is602_setup_transfer()
153 hw->speed = hw->freq / 16; sc18is602_setup_transfer()
154 } else if (hz >= hw->freq / 64) { sc18is602_setup_transfer()
156 hw->speed = hw->freq / 64; sc18is602_setup_transfer()
159 hw->speed = hw->freq / 128; sc18is602_setup_transfer()
164 * value of 0xff for hw->ctrl ensures that the correct mode will be set sc18is602_setup_transfer()
167 if (ctrl == hw->ctrl) sc18is602_setup_transfer()
170 ret = i2c_smbus_write_byte_data(hw->client, 0xf0, ctrl); sc18is602_setup_transfer()
174 hw->ctrl = ctrl; sc18is602_setup_transfer()
191 struct sc18is602 *hw = spi_master_get_devdata(master); sc18is602_transfer_one() local
196 hw->tlen = 0; sc18is602_transfer_one()
200 status = sc18is602_check_transfer(spi, t, hw->tlen); sc18is602_transfer_one()
204 status = sc18is602_setup_transfer(hw, t->speed_hz, spi->mode); sc18is602_transfer_one()
212 status = sc18is602_txrx(hw, m, t, do_transfer); sc18is602_transfer_one()
230 struct sc18is602 *hw = spi_master_get_devdata(spi->master); sc18is602_setup() local
233 if (hw->id == sc18is602 && spi->chip_select == 2) sc18is602_setup()
245 struct sc18is602 *hw; sc18is602_probe() local
257 hw = spi_master_get_devdata(master); sc18is602_probe()
258 i2c_set_clientdata(client, hw); sc18is602_probe()
260 hw->master = master; sc18is602_probe()
261 hw->client = client; sc18is602_probe()
262 hw->dev = dev; sc18is602_probe()
263 hw->ctrl = 0xff; sc18is602_probe()
265 hw->id = id->driver_data; sc18is602_probe()
267 switch (hw->id) { sc18is602_probe()
271 hw->freq = SC18IS602_CLOCK; sc18is602_probe()
276 hw->freq = pdata->clock_frequency; sc18is602_probe()
283 hw->freq = be32_to_cpup(val); sc18is602_probe()
285 if (!hw->freq) sc18is602_probe()
286 hw->freq = SC18IS602_CLOCK; sc18is602_probe()
295 master->min_speed_hz = hw->freq / 128; sc18is602_probe()
296 master->max_speed_hz = hw->freq / 4; sc18is602_probe()
H A Dspi-au1550.c61 void (*rx_word)(struct au1550_spi *hw);
62 void (*tx_word)(struct au1550_spi *hw);
64 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
99 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
111 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz) au1550_spi_baudcfg() argument
113 u32 mainclk_hz = hw->pdata->mainclk_hz; au1550_spi_baudcfg()
134 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) au1550_spi_mask_ack_all() argument
136 hw->regs->psc_spimsk = au1550_spi_mask_ack_all()
142 hw->regs->psc_spievent = au1550_spi_mask_ack_all()
149 static void au1550_spi_reset_fifos(struct au1550_spi *hw) au1550_spi_reset_fifos() argument
153 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; au1550_spi_reset_fifos()
156 pcr = hw->regs->psc_spipcr; au1550_spi_reset_fifos()
172 struct au1550_spi *hw = spi_master_get_devdata(spi->master); au1550_spi_chipsel() local
178 if (hw->pdata->deactivate_cs) au1550_spi_chipsel()
179 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select, au1550_spi_chipsel()
184 au1550_spi_bits_handlers_set(hw, spi->bits_per_word); au1550_spi_chipsel()
186 cfg = hw->regs->psc_spicfg; au1550_spi_chipsel()
188 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; au1550_spi_chipsel()
205 if (hw->usedma && spi->bits_per_word <= 8) au1550_spi_chipsel()
214 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); au1550_spi_chipsel()
216 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; au1550_spi_chipsel()
219 stat = hw->regs->psc_spistat; au1550_spi_chipsel()
223 if (hw->pdata->activate_cs) au1550_spi_chipsel()
224 hw->pdata->activate_cs(hw->pdata, spi->chip_select, au1550_spi_chipsel()
232 struct au1550_spi *hw = spi_master_get_devdata(spi->master); au1550_spi_setupxfer() local
247 au1550_spi_bits_handlers_set(hw, spi->bits_per_word); au1550_spi_setupxfer()
249 cfg = hw->regs->psc_spicfg; au1550_spi_setupxfer()
251 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; au1550_spi_setupxfer()
254 if (hw->usedma && bpw <= 8) au1550_spi_setupxfer()
263 cfg |= au1550_spi_baudcfg(hw, hz); au1550_spi_setupxfer()
265 hw->regs->psc_spicfg = cfg; au1550_spi_setupxfer()
270 stat = hw->regs->psc_spistat; au1550_spi_setupxfer()
275 au1550_spi_reset_fifos(hw); au1550_spi_setupxfer()
276 au1550_spi_mask_ack_all(hw); au1550_spi_setupxfer()
288 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size) au1550_spi_dma_rxtmp_alloc() argument
290 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL); au1550_spi_dma_rxtmp_alloc()
291 if (!hw->dma_rx_tmpbuf) au1550_spi_dma_rxtmp_alloc()
293 hw->dma_rx_tmpbuf_size = size; au1550_spi_dma_rxtmp_alloc()
294 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf, au1550_spi_dma_rxtmp_alloc()
296 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) { au1550_spi_dma_rxtmp_alloc()
297 kfree(hw->dma_rx_tmpbuf); au1550_spi_dma_rxtmp_alloc()
298 hw->dma_rx_tmpbuf = 0; au1550_spi_dma_rxtmp_alloc()
299 hw->dma_rx_tmpbuf_size = 0; au1550_spi_dma_rxtmp_alloc()
305 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw) au1550_spi_dma_rxtmp_free() argument
307 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr, au1550_spi_dma_rxtmp_free()
308 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE); au1550_spi_dma_rxtmp_free()
309 kfree(hw->dma_rx_tmpbuf); au1550_spi_dma_rxtmp_free()
310 hw->dma_rx_tmpbuf = 0; au1550_spi_dma_rxtmp_free()
311 hw->dma_rx_tmpbuf_size = 0; au1550_spi_dma_rxtmp_free()
316 struct au1550_spi *hw = spi_master_get_devdata(spi->master); au1550_spi_dma_txrxb() local
321 hw->len = t->len; au1550_spi_dma_txrxb()
322 hw->tx_count = 0; au1550_spi_dma_txrxb()
323 hw->rx_count = 0; au1550_spi_dma_txrxb()
325 hw->tx = t->tx_buf; au1550_spi_dma_txrxb()
326 hw->rx = t->rx_buf; au1550_spi_dma_txrxb()
340 dma_tx_addr = dma_map_single(hw->dev, au1550_spi_dma_txrxb()
343 if (dma_mapping_error(hw->dev, dma_tx_addr)) au1550_spi_dma_txrxb()
344 dev_err(hw->dev, "tx dma map error\n"); au1550_spi_dma_txrxb()
350 dma_rx_addr = dma_map_single(hw->dev, au1550_spi_dma_txrxb()
353 if (dma_mapping_error(hw->dev, dma_rx_addr)) au1550_spi_dma_txrxb()
354 dev_err(hw->dev, "rx dma map error\n"); au1550_spi_dma_txrxb()
357 if (t->len > hw->dma_rx_tmpbuf_size) { au1550_spi_dma_txrxb()
360 au1550_spi_dma_rxtmp_free(hw); au1550_spi_dma_txrxb()
361 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len, au1550_spi_dma_txrxb()
366 hw->rx = hw->dma_rx_tmpbuf; au1550_spi_dma_txrxb()
367 dma_rx_addr = hw->dma_rx_tmpbuf_addr; au1550_spi_dma_txrxb()
368 dma_sync_single_for_device(hw->dev, dma_rx_addr, au1550_spi_dma_txrxb()
373 dma_sync_single_for_device(hw->dev, dma_rx_addr, au1550_spi_dma_txrxb()
375 hw->tx = hw->rx; au1550_spi_dma_txrxb()
379 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx), au1550_spi_dma_txrxb()
382 dev_err(hw->dev, "rx dma put dest error\n"); au1550_spi_dma_txrxb()
384 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx), au1550_spi_dma_txrxb()
387 dev_err(hw->dev, "tx dma put source error\n"); au1550_spi_dma_txrxb()
389 au1xxx_dbdma_start(hw->dma_rx_ch); au1550_spi_dma_txrxb()
390 au1xxx_dbdma_start(hw->dma_tx_ch); au1550_spi_dma_txrxb()
393 hw->regs->psc_spimsk = PSC_SPIMSK_SD; au1550_spi_dma_txrxb()
397 hw->regs->psc_spipcr = PSC_SPIPCR_MS; au1550_spi_dma_txrxb()
400 wait_for_completion(&hw->master_done); au1550_spi_dma_txrxb()
402 au1xxx_dbdma_stop(hw->dma_tx_ch); au1550_spi_dma_txrxb()
403 au1xxx_dbdma_stop(hw->dma_rx_ch); au1550_spi_dma_txrxb()
407 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len, au1550_spi_dma_txrxb()
412 dma_unmap_single(hw->dev, dma_rx_addr, t->len, au1550_spi_dma_txrxb()
415 dma_unmap_single(hw->dev, dma_tx_addr, t->len, au1550_spi_dma_txrxb()
418 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; au1550_spi_dma_txrxb()
421 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) au1550_spi_dma_irq_callback() argument
425 stat = hw->regs->psc_spistat; au1550_spi_dma_irq_callback()
426 evnt = hw->regs->psc_spievent; au1550_spi_dma_irq_callback()
429 dev_err(hw->dev, "Unexpected IRQ!\n"); au1550_spi_dma_irq_callback()
442 au1550_spi_mask_ack_all(hw); au1550_spi_dma_irq_callback()
443 au1xxx_dbdma_stop(hw->dma_rx_ch); au1550_spi_dma_irq_callback()
444 au1xxx_dbdma_stop(hw->dma_tx_ch); au1550_spi_dma_irq_callback()
447 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch); au1550_spi_dma_irq_callback()
448 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch); au1550_spi_dma_irq_callback()
450 au1xxx_dbdma_reset(hw->dma_rx_ch); au1550_spi_dma_irq_callback()
451 au1xxx_dbdma_reset(hw->dma_tx_ch); au1550_spi_dma_irq_callback()
452 au1550_spi_reset_fifos(hw); au1550_spi_dma_irq_callback()
455 dev_err(hw->dev, au1550_spi_dma_irq_callback()
458 dev_err(hw->dev, au1550_spi_dma_irq_callback()
462 complete(&hw->master_done); au1550_spi_dma_irq_callback()
468 au1550_spi_mask_ack_all(hw); au1550_spi_dma_irq_callback()
469 hw->rx_count = hw->len; au1550_spi_dma_irq_callback()
470 hw->tx_count = hw->len; au1550_spi_dma_irq_callback()
471 complete(&hw->master_done); au1550_spi_dma_irq_callback()
479 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
481 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
483 if (hw->rx) { \
484 *(u##size *)hw->rx = (u##size)fifoword; \
485 hw->rx += (size) / 8; \
487 hw->rx_count += (size) / 8; \
491 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
494 if (hw->tx) { \
495 fifoword = *(u##size *)hw->tx & (u32)(mask); \
496 hw->tx += (size) / 8; \
498 hw->tx_count += (size) / 8; \
499 if (hw->tx_count >= hw->len) \
501 hw->regs->psc_spitxrx = fifoword; \
515 struct au1550_spi *hw = spi_master_get_devdata(spi->master); au1550_spi_pio_txrxb() local
517 hw->tx = t->tx_buf; au1550_spi_pio_txrxb()
518 hw->rx = t->rx_buf; au1550_spi_pio_txrxb()
519 hw->len = t->len; au1550_spi_pio_txrxb()
520 hw->tx_count = 0; au1550_spi_pio_txrxb()
521 hw->rx_count = 0; au1550_spi_pio_txrxb()
527 while (hw->tx_count < hw->len) { au1550_spi_pio_txrxb()
529 hw->tx_word(hw); au1550_spi_pio_txrxb()
531 if (hw->tx_count >= hw->len) { au1550_spi_pio_txrxb()
536 stat = hw->regs->psc_spistat; au1550_spi_pio_txrxb()
543 hw->regs->psc_spimsk = mask; au1550_spi_pio_txrxb()
547 hw->regs->psc_spipcr = PSC_SPIPCR_MS; au1550_spi_pio_txrxb()
550 wait_for_completion(&hw->master_done); au1550_spi_pio_txrxb()
552 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; au1550_spi_pio_txrxb()
555 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) au1550_spi_pio_irq_callback() argument
560 stat = hw->regs->psc_spistat; au1550_spi_pio_irq_callback()
561 evnt = hw->regs->psc_spievent; au1550_spi_pio_irq_callback()
564 dev_err(hw->dev, "Unexpected IRQ!\n"); au1550_spi_pio_irq_callback()
576 au1550_spi_mask_ack_all(hw); au1550_spi_pio_irq_callback()
577 au1550_spi_reset_fifos(hw); au1550_spi_pio_irq_callback()
578 dev_err(hw->dev, au1550_spi_pio_irq_callback()
581 complete(&hw->master_done); au1550_spi_pio_irq_callback()
591 stat = hw->regs->psc_spistat; au1550_spi_pio_irq_callback()
603 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) { au1550_spi_pio_irq_callback()
604 hw->rx_word(hw); au1550_spi_pio_irq_callback()
607 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len) au1550_spi_pio_irq_callback()
608 hw->tx_word(hw); au1550_spi_pio_irq_callback()
612 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; au1550_spi_pio_irq_callback()
631 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; au1550_spi_pio_irq_callback()
633 hw->regs->psc_spipcr = PSC_SPIPCR_MS; au1550_spi_pio_irq_callback()
637 if (hw->rx_count >= hw->len) { au1550_spi_pio_irq_callback()
639 au1550_spi_mask_ack_all(hw); au1550_spi_pio_irq_callback()
640 complete(&hw->master_done); au1550_spi_pio_irq_callback()
647 struct au1550_spi *hw = spi_master_get_devdata(spi->master); au1550_spi_txrx_bufs() local
648 return hw->txrx_bufs(spi, t); au1550_spi_txrx_bufs()
653 struct au1550_spi *hw = dev; au1550_spi_irq() local
654 return hw->irq_callback(hw); au1550_spi_irq()
657 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw) au1550_spi_bits_handlers_set() argument
660 if (hw->usedma) { au1550_spi_bits_handlers_set()
661 hw->txrx_bufs = &au1550_spi_dma_txrxb; au1550_spi_bits_handlers_set()
662 hw->irq_callback = &au1550_spi_dma_irq_callback; au1550_spi_bits_handlers_set()
664 hw->rx_word = &au1550_spi_rx_word_8; au1550_spi_bits_handlers_set()
665 hw->tx_word = &au1550_spi_tx_word_8; au1550_spi_bits_handlers_set()
666 hw->txrx_bufs = &au1550_spi_pio_txrxb; au1550_spi_bits_handlers_set()
667 hw->irq_callback = &au1550_spi_pio_irq_callback; au1550_spi_bits_handlers_set()
670 hw->rx_word = &au1550_spi_rx_word_16; au1550_spi_bits_handlers_set()
671 hw->tx_word = &au1550_spi_tx_word_16; au1550_spi_bits_handlers_set()
672 hw->txrx_bufs = &au1550_spi_pio_txrxb; au1550_spi_bits_handlers_set()
673 hw->irq_callback = &au1550_spi_pio_irq_callback; au1550_spi_bits_handlers_set()
675 hw->rx_word = &au1550_spi_rx_word_32; au1550_spi_bits_handlers_set()
676 hw->tx_word = &au1550_spi_tx_word_32; au1550_spi_bits_handlers_set()
677 hw->txrx_bufs = &au1550_spi_pio_txrxb; au1550_spi_bits_handlers_set()
678 hw->irq_callback = &au1550_spi_pio_irq_callback; au1550_spi_bits_handlers_set()
682 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) au1550_spi_setup_psc_as_spi() argument
687 hw->regs->psc_ctrl = PSC_CTRL_DISABLE; au1550_spi_setup_psc_as_spi()
689 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; au1550_spi_setup_psc_as_spi()
692 hw->regs->psc_spicfg = 0; au1550_spi_setup_psc_as_spi()
695 hw->regs->psc_ctrl = PSC_CTRL_ENABLE; au1550_spi_setup_psc_as_spi()
699 stat = hw->regs->psc_spistat; au1550_spi_setup_psc_as_spi()
704 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE; au1550_spi_setup_psc_as_spi()
714 hw->regs->psc_spicfg = cfg; au1550_spi_setup_psc_as_spi()
717 au1550_spi_mask_ack_all(hw); au1550_spi_setup_psc_as_spi()
719 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; au1550_spi_setup_psc_as_spi()
723 stat = hw->regs->psc_spistat; au1550_spi_setup_psc_as_spi()
727 au1550_spi_reset_fifos(hw); au1550_spi_setup_psc_as_spi()
733 struct au1550_spi *hw; au1550_spi_probe() local
749 hw = spi_master_get_devdata(master); au1550_spi_probe()
751 hw->master = master; au1550_spi_probe()
752 hw->pdata = dev_get_platdata(&pdev->dev); au1550_spi_probe()
753 hw->dev = &pdev->dev; au1550_spi_probe()
755 if (hw->pdata == NULL) { au1550_spi_probe()
767 hw->irq = r->start; au1550_spi_probe()
769 hw->usedma = 0; au1550_spi_probe()
772 hw->dma_tx_id = r->start; au1550_spi_probe()
775 hw->dma_rx_id = r->start; au1550_spi_probe()
780 hw->usedma = 1; au1550_spi_probe()
792 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t), au1550_spi_probe()
794 if (!hw->ioarea) { au1550_spi_probe()
800 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t)); au1550_spi_probe()
801 if (!hw->regs) { au1550_spi_probe()
807 platform_set_drvdata(pdev, hw); au1550_spi_probe()
809 init_completion(&hw->master_done); au1550_spi_probe()
811 hw->bitbang.master = hw->master; au1550_spi_probe()
812 hw->bitbang.setup_transfer = au1550_spi_setupxfer; au1550_spi_probe()
813 hw->bitbang.chipselect = au1550_spi_chipsel; au1550_spi_probe()
814 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; au1550_spi_probe()
816 if (hw->usedma) { au1550_spi_probe()
817 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid, au1550_spi_probe()
818 hw->dma_tx_id, NULL, (void *)hw); au1550_spi_probe()
819 if (hw->dma_tx_ch == 0) { au1550_spi_probe()
825 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8); au1550_spi_probe()
826 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch, au1550_spi_probe()
835 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id, au1550_spi_probe()
836 ddma_memid, NULL, (void *)hw); au1550_spi_probe()
837 if (hw->dma_rx_ch == 0) { au1550_spi_probe()
843 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8); au1550_spi_probe()
844 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch, au1550_spi_probe()
852 err = au1550_spi_dma_rxtmp_alloc(hw, au1550_spi_probe()
861 au1550_spi_bits_handlers_set(hw, 8); au1550_spi_probe()
863 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw); au1550_spi_probe()
870 master->num_chipselect = hw->pdata->num_chipselect; au1550_spi_probe()
884 master->max_speed_hz = hw->pdata->mainclk_hz / min_div; au1550_spi_probe()
886 hw->pdata->mainclk_hz / (max_div + 1) + 1; au1550_spi_probe()
889 au1550_spi_setup_psc_as_spi(hw); au1550_spi_probe()
891 err = spi_bitbang_start(&hw->bitbang); au1550_spi_probe()
904 free_irq(hw->irq, hw); au1550_spi_probe()
907 au1550_spi_dma_rxtmp_free(hw); au1550_spi_probe()
911 if (hw->usedma) au1550_spi_probe()
912 au1xxx_dbdma_chan_free(hw->dma_rx_ch); au1550_spi_probe()
916 if (hw->usedma) au1550_spi_probe()
917 au1xxx_dbdma_chan_free(hw->dma_tx_ch); au1550_spi_probe()
920 iounmap((void __iomem *)hw->regs); au1550_spi_probe()
927 spi_master_put(hw->master); au1550_spi_probe()
935 struct au1550_spi *hw = platform_get_drvdata(pdev); au1550_spi_remove() local
938 hw->master->bus_num); au1550_spi_remove()
940 spi_bitbang_stop(&hw->bitbang); au1550_spi_remove()
941 free_irq(hw->irq, hw); au1550_spi_remove()
942 iounmap((void __iomem *)hw->regs); au1550_spi_remove()
943 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t)); au1550_spi_remove()
945 if (hw->usedma) { au1550_spi_remove()
946 au1550_spi_dma_rxtmp_free(hw); au1550_spi_remove()
947 au1xxx_dbdma_chan_free(hw->dma_rx_ch); au1550_spi_remove()
948 au1xxx_dbdma_chan_free(hw->dma_tx_ch); au1550_spi_remove()
951 spi_master_put(hw->master); au1550_spi_remove()
H A Dspi-s3c24xx.c100 struct s3c24xx_spi *hw = to_hw(spi); s3c24xx_spi_chipsel() local
107 hw->set_cs(hw->pdata, spi->chip_select, cspol^1); s3c24xx_spi_chipsel()
108 writeb(cs->spcon, hw->regs + S3C2410_SPCON); s3c24xx_spi_chipsel()
113 hw->regs + S3C2410_SPCON); s3c24xx_spi_chipsel()
114 hw->set_cs(hw->pdata, spi->chip_select, cspol); s3c24xx_spi_chipsel()
122 struct s3c24xx_spi *hw = to_hw(spi); s3c24xx_spi_update_state() local
147 clk = clk_get_rate(hw->clk); s3c24xx_spi_update_state()
167 struct s3c24xx_spi *hw = to_hw(spi); s3c24xx_spi_setupxfer() local
172 writeb(cs->sppre, hw->regs + S3C2410_SPPRE); s3c24xx_spi_setupxfer()
180 struct s3c24xx_spi *hw = to_hw(spi); s3c24xx_spi_setup() local
201 mutex_lock(&hw->bitbang.lock); s3c24xx_spi_setup()
202 if (!hw->bitbang.busy) { s3c24xx_spi_setup()
203 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); s3c24xx_spi_setup()
206 mutex_unlock(&hw->bitbang.lock); s3c24xx_spi_setup()
211 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) hw_txbyte() argument
213 return hw->tx ? hw->tx[count] : 0; hw_txbyte()
254 * @hw: The hardware state.
263 static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw) s3c24xx_spi_tryfiq() argument
270 if (!hw->fiq_claimed) { s3c24xx_spi_tryfiq()
274 ret = claim_fiq(&hw->fiq_handler); s3c24xx_spi_tryfiq()
279 if (hw->tx && !hw->rx) s3c24xx_spi_tryfiq()
281 else if (hw->rx && !hw->tx) s3c24xx_spi_tryfiq()
286 regs.uregs[fiq_rspi] = (long)hw->regs; s3c24xx_spi_tryfiq()
287 regs.uregs[fiq_rrx] = (long)hw->rx; s3c24xx_spi_tryfiq()
288 regs.uregs[fiq_rtx] = (long)hw->tx + 1; s3c24xx_spi_tryfiq()
289 regs.uregs[fiq_rcount] = hw->len - 1; s3c24xx_spi_tryfiq()
294 if (hw->fiq_mode != mode) { s3c24xx_spi_tryfiq()
297 hw->fiq_mode = mode; s3c24xx_spi_tryfiq()
316 *ack_ptr = ack_bit(hw->irq); s3c24xx_spi_tryfiq()
321 s3c24xx_set_fiq(hw->irq, true); s3c24xx_spi_tryfiq()
323 hw->fiq_mode = mode; s3c24xx_spi_tryfiq()
324 hw->fiq_inuse = 1; s3c24xx_spi_tryfiq()
338 struct s3c24xx_spi *hw = pw; s3c24xx_spi_fiqop() local
342 if (hw->fiq_inuse) s3c24xx_spi_fiqop()
348 hw->fiq_mode = FIQ_MODE_NONE; s3c24xx_spi_fiqop()
349 hw->fiq_claimed = 0; s3c24xx_spi_fiqop()
351 hw->fiq_claimed = 1; s3c24xx_spi_fiqop()
359 * @hw: The hardware state.
363 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw) s3c24xx_spi_initfiq() argument
365 hw->fiq_handler.dev_id = hw; s3c24xx_spi_initfiq()
366 hw->fiq_handler.name = dev_name(hw->dev); s3c24xx_spi_initfiq()
367 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; s3c24xx_spi_initfiq()
372 * @hw: The hardware state.
377 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw) s3c24xx_spi_usefiq() argument
379 return hw->pdata->use_fiq; s3c24xx_spi_usefiq()
404 struct s3c24xx_spi *hw = to_hw(spi); s3c24xx_spi_txrx() local
406 hw->tx = t->tx_buf; s3c24xx_spi_txrx()
407 hw->rx = t->rx_buf; s3c24xx_spi_txrx()
408 hw->len = t->len; s3c24xx_spi_txrx()
409 hw->count = 0; s3c24xx_spi_txrx()
411 init_completion(&hw->done); s3c24xx_spi_txrx()
413 hw->fiq_inuse = 0; s3c24xx_spi_txrx()
414 if (s3c24xx_spi_usefiq(hw) && t->len >= 3) s3c24xx_spi_txrx()
415 s3c24xx_spi_tryfiq(hw); s3c24xx_spi_txrx()
418 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); s3c24xx_spi_txrx()
420 wait_for_completion(&hw->done); s3c24xx_spi_txrx()
421 return hw->count; s3c24xx_spi_txrx()
426 struct s3c24xx_spi *hw = dev; s3c24xx_spi_irq() local
427 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); s3c24xx_spi_irq()
428 unsigned int count = hw->count; s3c24xx_spi_irq()
431 dev_dbg(hw->dev, "data-collision\n"); s3c24xx_spi_irq()
432 complete(&hw->done); s3c24xx_spi_irq()
437 dev_dbg(hw->dev, "spi not ready for tx?\n"); s3c24xx_spi_irq()
438 complete(&hw->done); s3c24xx_spi_irq()
442 if (!s3c24xx_spi_usingfiq(hw)) { s3c24xx_spi_irq()
443 hw->count++; s3c24xx_spi_irq()
445 if (hw->rx) s3c24xx_spi_irq()
446 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); s3c24xx_spi_irq()
450 if (count < hw->len) s3c24xx_spi_irq()
451 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); s3c24xx_spi_irq()
453 complete(&hw->done); s3c24xx_spi_irq()
455 hw->count = hw->len; s3c24xx_spi_irq()
456 hw->fiq_inuse = 0; s3c24xx_spi_irq()
458 if (hw->rx) s3c24xx_spi_irq()
459 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); s3c24xx_spi_irq()
461 complete(&hw->done); s3c24xx_spi_irq()
468 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) s3c24xx_spi_initialsetup() argument
472 clk_enable(hw->clk); s3c24xx_spi_initialsetup()
476 writeb(0xff, hw->regs + S3C2410_SPPRE); s3c24xx_spi_initialsetup()
477 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); s3c24xx_spi_initialsetup()
478 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); s3c24xx_spi_initialsetup()
480 if (hw->pdata) { s3c24xx_spi_initialsetup()
481 if (hw->set_cs == s3c24xx_spi_gpiocs) s3c24xx_spi_initialsetup()
482 gpio_direction_output(hw->pdata->pin_cs, 1); s3c24xx_spi_initialsetup()
484 if (hw->pdata->gpio_setup) s3c24xx_spi_initialsetup()
485 hw->pdata->gpio_setup(hw->pdata, 1); s3c24xx_spi_initialsetup()
492 struct s3c24xx_spi *hw; s3c24xx_spi_probe() local
503 hw = spi_master_get_devdata(master); s3c24xx_spi_probe()
505 hw->master = master; s3c24xx_spi_probe()
506 hw->pdata = pdata = dev_get_platdata(&pdev->dev); s3c24xx_spi_probe()
507 hw->dev = &pdev->dev; s3c24xx_spi_probe()
515 platform_set_drvdata(pdev, hw); s3c24xx_spi_probe()
516 init_completion(&hw->done); s3c24xx_spi_probe()
520 s3c24xx_spi_initfiq(hw); s3c24xx_spi_probe()
527 master->num_chipselect = hw->pdata->num_cs; s3c24xx_spi_probe()
533 hw->bitbang.master = hw->master; s3c24xx_spi_probe()
534 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; s3c24xx_spi_probe()
535 hw->bitbang.chipselect = s3c24xx_spi_chipsel; s3c24xx_spi_probe()
536 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; s3c24xx_spi_probe()
538 hw->master->setup = s3c24xx_spi_setup; s3c24xx_spi_probe()
540 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); s3c24xx_spi_probe()
544 hw->regs = devm_ioremap_resource(&pdev->dev, res); s3c24xx_spi_probe()
545 if (IS_ERR(hw->regs)) { s3c24xx_spi_probe()
546 err = PTR_ERR(hw->regs); s3c24xx_spi_probe()
550 hw->irq = platform_get_irq(pdev, 0); s3c24xx_spi_probe()
551 if (hw->irq < 0) { s3c24xx_spi_probe()
557 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, s3c24xx_spi_probe()
558 pdev->name, hw); s3c24xx_spi_probe()
564 hw->clk = devm_clk_get(&pdev->dev, "spi"); s3c24xx_spi_probe()
565 if (IS_ERR(hw->clk)) { s3c24xx_spi_probe()
567 err = PTR_ERR(hw->clk); s3c24xx_spi_probe()
587 hw->set_cs = s3c24xx_spi_gpiocs; s3c24xx_spi_probe()
590 hw->set_cs = pdata->set_cs; s3c24xx_spi_probe()
592 s3c24xx_spi_initialsetup(hw); s3c24xx_spi_probe()
596 err = spi_bitbang_start(&hw->bitbang); s3c24xx_spi_probe()
605 clk_disable(hw->clk); s3c24xx_spi_probe()
608 spi_master_put(hw->master); s3c24xx_spi_probe()
614 struct s3c24xx_spi *hw = platform_get_drvdata(dev); s3c24xx_spi_remove() local
616 spi_bitbang_stop(&hw->bitbang); s3c24xx_spi_remove()
617 clk_disable(hw->clk); s3c24xx_spi_remove()
618 spi_master_put(hw->master); s3c24xx_spi_remove()
627 struct s3c24xx_spi *hw = dev_get_drvdata(dev); s3c24xx_spi_suspend() local
630 ret = spi_master_suspend(hw->master); s3c24xx_spi_suspend()
634 if (hw->pdata && hw->pdata->gpio_setup) s3c24xx_spi_suspend()
635 hw->pdata->gpio_setup(hw->pdata, 0); s3c24xx_spi_suspend()
637 clk_disable(hw->clk); s3c24xx_spi_suspend()
643 struct s3c24xx_spi *hw = dev_get_drvdata(dev); s3c24xx_spi_resume() local
645 s3c24xx_spi_initialsetup(hw); s3c24xx_spi_resume()
646 return spi_master_resume(hw->master); s3c24xx_spi_resume()
H A Dspi-clps711x.c52 struct spi_clps711x_data *hw = spi_master_get_devdata(master); spi_clps711x_prepare_message() local
56 return regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCKNSEN, spi_clps711x_prepare_message()
65 struct spi_clps711x_data *hw = spi_master_get_devdata(master); spi_clps711x_transfer_one() local
68 clk_set_rate(hw->spi_clk, xfer->speed_hz ? : spi->max_speed_hz); spi_clps711x_transfer_one()
70 hw->len = xfer->len; spi_clps711x_transfer_one()
71 hw->bpw = xfer->bits_per_word; spi_clps711x_transfer_one()
72 hw->tx_buf = (u8 *)xfer->tx_buf; spi_clps711x_transfer_one()
73 hw->rx_buf = (u8 *)xfer->rx_buf; spi_clps711x_transfer_one()
76 data = hw->tx_buf ? *hw->tx_buf++ : 0; spi_clps711x_transfer_one()
77 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, hw->syncio); spi_clps711x_transfer_one()
85 struct spi_clps711x_data *hw = spi_master_get_devdata(master); spi_clps711x_isr() local
89 data = readb(hw->syncio); spi_clps711x_isr()
90 if (hw->rx_buf) spi_clps711x_isr()
91 *hw->rx_buf++ = data; spi_clps711x_isr()
94 if (--hw->len > 0) { spi_clps711x_isr()
95 data = hw->tx_buf ? *hw->tx_buf++ : 0; spi_clps711x_isr()
96 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, spi_clps711x_isr()
97 hw->syncio); spi_clps711x_isr()
106 struct spi_clps711x_data *hw; spi_clps711x_probe() local
126 master = spi_alloc_master(&pdev->dev, sizeof(*hw)); spi_clps711x_probe()
145 hw = spi_master_get_devdata(master); spi_clps711x_probe()
157 hw->spi_clk = devm_clk_get(&pdev->dev, NULL); spi_clps711x_probe()
158 if (IS_ERR(hw->spi_clk)) { spi_clps711x_probe()
159 ret = PTR_ERR(hw->spi_clk); spi_clps711x_probe()
163 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3"); spi_clps711x_probe()
164 if (IS_ERR(hw->syscon)) { spi_clps711x_probe()
165 ret = PTR_ERR(hw->syscon); spi_clps711x_probe()
170 hw->syncio = devm_ioremap_resource(&pdev->dev, res); spi_clps711x_probe()
171 if (IS_ERR(hw->syncio)) { spi_clps711x_probe()
172 ret = PTR_ERR(hw->syncio); spi_clps711x_probe()
177 regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0); spi_clps711x_probe()
180 readl(hw->syncio); spi_clps711x_probe()
H A Dspi-ppc4xx.c147 struct ppc4xx_spi *hw; spi_ppc4xx_txrx() local
153 hw = spi_master_get_devdata(spi->master); spi_ppc4xx_txrx()
155 hw->tx = t->tx_buf; spi_ppc4xx_txrx()
156 hw->rx = t->rx_buf; spi_ppc4xx_txrx()
157 hw->len = t->len; spi_ppc4xx_txrx()
158 hw->count = 0; spi_ppc4xx_txrx()
161 data = hw->tx ? hw->tx[0] : 0; spi_ppc4xx_txrx()
162 out_8(&hw->regs->txd, data); spi_ppc4xx_txrx()
163 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); spi_ppc4xx_txrx()
164 wait_for_completion(&hw->done); spi_ppc4xx_txrx()
166 return hw->count; spi_ppc4xx_txrx()
171 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); spi_ppc4xx_setupxfer() local
200 out_8(&hw->regs->mode, cs->mode); spi_ppc4xx_setupxfer()
204 scr = (hw->opb_freq / speed) - 1; spi_ppc4xx_setupxfer()
210 if (in_8(&hw->regs->cdm) != cdm) spi_ppc4xx_setupxfer()
211 out_8(&hw->regs->cdm, cdm); spi_ppc4xx_setupxfer()
213 mutex_lock(&hw->bitbang.lock); spi_ppc4xx_setupxfer()
214 if (!hw->bitbang.busy) { spi_ppc4xx_setupxfer()
215 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); spi_ppc4xx_setupxfer()
218 mutex_unlock(&hw->bitbang.lock); spi_ppc4xx_setupxfer()
268 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); spi_ppc4xx_chipsel() local
277 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST) spi_ppc4xx_chipsel()
284 gpio_set_value(hw->gpios[cs], cspol); spi_ppc4xx_chipsel()
289 struct ppc4xx_spi *hw; spi_ppc4xx_int() local
294 hw = (struct ppc4xx_spi *)dev_id; spi_ppc4xx_int()
296 status = in_8(&hw->regs->sr); spi_ppc4xx_int()
310 dev_dbg(hw->dev, "got interrupt but spi still busy?\n"); spi_ppc4xx_int()
313 lstatus = in_8(&hw->regs->sr); spi_ppc4xx_int()
317 dev_err(hw->dev, "busywait: too many loops!\n"); spi_ppc4xx_int()
318 complete(&hw->done); spi_ppc4xx_int()
322 status = in_8(&hw->regs->sr); spi_ppc4xx_int()
323 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status); spi_ppc4xx_int()
327 count = hw->count; spi_ppc4xx_int()
328 hw->count++; spi_ppc4xx_int()
331 data = in_8(&hw->regs->rxd); spi_ppc4xx_int()
332 if (hw->rx) spi_ppc4xx_int()
333 hw->rx[count] = data; spi_ppc4xx_int()
337 if (count < hw->len) { spi_ppc4xx_int()
338 data = hw->tx ? hw->tx[count] : 0; spi_ppc4xx_int()
339 out_8(&hw->regs->txd, data); spi_ppc4xx_int()
340 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); spi_ppc4xx_int()
342 complete(&hw->done); spi_ppc4xx_int()
353 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw) spi_ppc4xx_enable() argument
365 static void free_gpios(struct ppc4xx_spi *hw) free_gpios() argument
367 if (hw->master->num_chipselect) { free_gpios()
369 for (i = 0; i < hw->master->num_chipselect; i++) free_gpios()
370 if (gpio_is_valid(hw->gpios[i])) free_gpios()
371 gpio_free(hw->gpios[i]); free_gpios()
373 kfree(hw->gpios); free_gpios()
374 hw->gpios = NULL; free_gpios()
383 struct ppc4xx_spi *hw; spi_ppc4xx_of_probe() local
394 master = spi_alloc_master(dev, sizeof *hw); spi_ppc4xx_of_probe()
399 hw = spi_master_get_devdata(master); spi_ppc4xx_of_probe()
400 hw->master = master; spi_ppc4xx_of_probe()
401 hw->dev = dev; spi_ppc4xx_of_probe()
403 init_completion(&hw->done); spi_ppc4xx_of_probe()
414 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL); spi_ppc4xx_of_probe()
415 if (!hw->gpios) { spi_ppc4xx_of_probe()
425 hw->gpios[i] = gpio; spi_ppc4xx_of_probe()
449 bbp = &hw->bitbang; spi_ppc4xx_of_probe()
450 bbp->master = hw->master; spi_ppc4xx_of_probe()
481 hw->opb_freq = *clk; spi_ppc4xx_of_probe()
482 hw->opb_freq >>= 2; spi_ppc4xx_of_probe()
490 hw->mapbase = resource.start; spi_ppc4xx_of_probe()
491 hw->mapsize = resource_size(&resource); spi_ppc4xx_of_probe()
494 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) { spi_ppc4xx_of_probe()
501 hw->irqnum = irq_of_parse_and_map(np, 0); spi_ppc4xx_of_probe()
502 ret = request_irq(hw->irqnum, spi_ppc4xx_int, spi_ppc4xx_of_probe()
503 0, "spi_ppc4xx_of", (void *)hw); spi_ppc4xx_of_probe()
509 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) { spi_ppc4xx_of_probe()
515 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs)); spi_ppc4xx_of_probe()
517 if (!hw->regs) { spi_ppc4xx_of_probe()
523 spi_ppc4xx_enable(hw); spi_ppc4xx_of_probe()
538 iounmap(hw->regs); spi_ppc4xx_of_probe()
540 release_mem_region(hw->mapbase, hw->mapsize); spi_ppc4xx_of_probe()
542 free_irq(hw->irqnum, hw); spi_ppc4xx_of_probe()
544 free_gpios(hw); spi_ppc4xx_of_probe()
555 struct ppc4xx_spi *hw = spi_master_get_devdata(master); spi_ppc4xx_of_remove() local
557 spi_bitbang_stop(&hw->bitbang); spi_ppc4xx_of_remove()
558 release_mem_region(hw->mapbase, hw->mapsize); spi_ppc4xx_of_remove()
559 free_irq(hw->irqnum, hw); spi_ppc4xx_of_remove()
560 iounmap(hw->regs); spi_ppc4xx_of_remove()
561 free_gpios(hw); spi_ppc4xx_of_remove()
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
H A Dmac.h25 s32 e1000e_blink_led_generic(struct e1000_hw *hw);
26 s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
27 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
28 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
29 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
30 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
31 s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
32 s32 e1000e_force_mac_fc(struct e1000_hw *hw);
33 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
34 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
35 void e1000_set_lan_id_single_port(struct e1000_hw *hw);
36 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
37 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
39 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
41 s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
42 s32 e1000e_led_on_generic(struct e1000_hw *hw);
43 s32 e1000e_led_off_generic(struct e1000_hw *hw);
44 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
46 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
47 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
48 s32 e1000e_setup_led_generic(struct e1000_hw *hw);
49 s32 e1000e_setup_link_generic(struct e1000_hw *hw);
50 s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw);
51 s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);
53 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
54 void e1000_clear_vfta_generic(struct e1000_hw *hw);
55 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
56 void e1000e_put_hw_semaphore(struct e1000_hw *hw);
57 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
58 void e1000e_reset_adaptive(struct e1000_hw *hw);
59 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
60 void e1000e_update_adaptive(struct e1000_hw *hw);
61 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
63 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
64 u32 e1000e_rar_get_count_generic(struct e1000_hw *hw);
65 int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
66 void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
H A Dphy.h25 s32 e1000e_check_downshift(struct e1000_hw *hw);
26 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
27 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
28 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
29 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
30 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
31 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
32 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
33 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
34 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
35 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
36 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
37 s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
38 s32 e1000e_get_phy_id(struct e1000_hw *hw);
39 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
40 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
41 s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
42 s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
43 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
44 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
45 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
46 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
47 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
48 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
49 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
50 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
51 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
52 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
53 s32 e1000e_setup_copper_link(struct e1000_hw *hw);
54 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
55 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
56 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
57 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
58 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
59 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
61 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
63 s32 e1000e_determine_phy_address(struct e1000_hw *hw);
64 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
65 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
66 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
67 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
68 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
69 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
70 void e1000_power_up_phy_copper(struct e1000_hw *hw);
71 void e1000_power_down_phy_copper(struct e1000_hw *hw);
72 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
73 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
74 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
75 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
76 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
77 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
78 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
79 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
80 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
81 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
82 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
83 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
84 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
85 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
H A D80003es2lan.c39 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
40 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
41 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
42 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
43 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
44 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
46 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
48 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
50 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
54 * @hw: pointer to the HW structure
56 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) e1000_init_phy_params_80003es2lan() argument
58 struct e1000_phy_info *phy = &hw->phy; e1000_init_phy_params_80003es2lan()
61 if (hw->phy.media_type != e1000_media_type_copper) { e1000_init_phy_params_80003es2lan()
75 ret_val = e1000e_get_phy_id(hw); e1000_init_phy_params_80003es2lan()
86 * @hw: pointer to the HW structure
88 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) e1000_init_nvm_params_80003es2lan() argument
90 struct e1000_nvm_info *nvm = &hw->nvm; e1000_init_nvm_params_80003es2lan()
131 * @hw: pointer to the HW structure
133 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) e1000_init_mac_params_80003es2lan() argument
135 struct e1000_mac_info *mac = &hw->mac; e1000_init_mac_params_80003es2lan()
138 switch (hw->adapter->pdev->device) { e1000_init_mac_params_80003es2lan()
140 hw->phy.media_type = e1000_media_type_internal_serdes; e1000_init_mac_params_80003es2lan()
146 hw->phy.media_type = e1000_media_type_copper; e1000_init_mac_params_80003es2lan()
165 hw->mac.ops.set_lan_id(hw); e1000_init_mac_params_80003es2lan()
172 struct e1000_hw *hw = &adapter->hw; e1000_get_variants_80003es2lan() local
175 rc = e1000_init_mac_params_80003es2lan(hw); e1000_get_variants_80003es2lan()
179 rc = e1000_init_nvm_params_80003es2lan(hw); e1000_get_variants_80003es2lan()
183 rc = e1000_init_phy_params_80003es2lan(hw); e1000_get_variants_80003es2lan()
192 * @hw: pointer to the HW structure
196 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) e1000_acquire_phy_80003es2lan() argument
200 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; e1000_acquire_phy_80003es2lan()
201 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); e1000_acquire_phy_80003es2lan()
206 * @hw: pointer to the HW structure
210 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) e1000_release_phy_80003es2lan() argument
214 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; e1000_release_phy_80003es2lan()
215 e1000_release_swfw_sync_80003es2lan(hw, mask); e1000_release_phy_80003es2lan()
220 * @hw: pointer to the HW structure
225 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) e1000_acquire_mac_csr_80003es2lan() argument
231 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); e1000_acquire_mac_csr_80003es2lan()
236 * @hw: pointer to the HW structure
240 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) e1000_release_mac_csr_80003es2lan() argument
246 e1000_release_swfw_sync_80003es2lan(hw, mask); e1000_release_mac_csr_80003es2lan()
251 * @hw: pointer to the HW structure
255 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) e1000_acquire_nvm_80003es2lan() argument
259 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); e1000_acquire_nvm_80003es2lan()
263 ret_val = e1000e_acquire_nvm(hw); e1000_acquire_nvm_80003es2lan()
266 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); e1000_acquire_nvm_80003es2lan()
273 * @hw: pointer to the HW structure
277 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) e1000_release_nvm_80003es2lan() argument
279 e1000e_release_nvm(hw); e1000_release_nvm_80003es2lan()
280 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); e1000_release_nvm_80003es2lan()
285 * @hw: pointer to the HW structure
291 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) e1000_acquire_swfw_sync_80003es2lan() argument
300 if (e1000e_get_hw_semaphore(hw)) e1000_acquire_swfw_sync_80003es2lan()
310 e1000e_put_hw_semaphore(hw); e1000_acquire_swfw_sync_80003es2lan()
323 e1000e_put_hw_semaphore(hw); e1000_acquire_swfw_sync_80003es2lan()
330 * @hw: pointer to the HW structure
336 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) e1000_release_swfw_sync_80003es2lan() argument
340 while (e1000e_get_hw_semaphore(hw) != 0) e1000_release_swfw_sync_80003es2lan()
347 e1000e_put_hw_semaphore(hw); e1000_release_swfw_sync_80003es2lan()
352 * @hw: pointer to the HW structure
358 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, e1000_read_phy_reg_gg82563_80003es2lan() argument
365 ret_val = e1000_acquire_phy_80003es2lan(hw); e1000_read_phy_reg_gg82563_80003es2lan()
380 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); e1000_read_phy_reg_gg82563_80003es2lan()
382 e1000_release_phy_80003es2lan(hw); e1000_read_phy_reg_gg82563_80003es2lan()
386 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { e1000_read_phy_reg_gg82563_80003es2lan()
394 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); e1000_read_phy_reg_gg82563_80003es2lan()
397 e1000_release_phy_80003es2lan(hw); e1000_read_phy_reg_gg82563_80003es2lan()
403 ret_val = e1000e_read_phy_reg_mdic(hw, e1000_read_phy_reg_gg82563_80003es2lan()
409 ret_val = e1000e_read_phy_reg_mdic(hw, e1000_read_phy_reg_gg82563_80003es2lan()
414 e1000_release_phy_80003es2lan(hw); e1000_read_phy_reg_gg82563_80003es2lan()
421 * @hw: pointer to the HW structure
427 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, e1000_write_phy_reg_gg82563_80003es2lan() argument
434 ret_val = e1000_acquire_phy_80003es2lan(hw); e1000_write_phy_reg_gg82563_80003es2lan()
449 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); e1000_write_phy_reg_gg82563_80003es2lan()
451 e1000_release_phy_80003es2lan(hw); e1000_write_phy_reg_gg82563_80003es2lan()
455 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { e1000_write_phy_reg_gg82563_80003es2lan()
463 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); e1000_write_phy_reg_gg82563_80003es2lan()
466 e1000_release_phy_80003es2lan(hw); e1000_write_phy_reg_gg82563_80003es2lan()
472 ret_val = e1000e_write_phy_reg_mdic(hw, e1000_write_phy_reg_gg82563_80003es2lan()
478 ret_val = e1000e_write_phy_reg_mdic(hw, e1000_write_phy_reg_gg82563_80003es2lan()
483 e1000_release_phy_80003es2lan(hw); e1000_write_phy_reg_gg82563_80003es2lan()
490 * @hw: pointer to the HW structure
497 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, e1000_write_nvm_80003es2lan() argument
500 return e1000e_write_nvm_spi(hw, offset, words, data); e1000_write_nvm_80003es2lan()
505 * @hw: pointer to the HW structure
510 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) e1000_get_cfg_done_80003es2lan() argument
515 if (hw->bus.func == 1) e1000_get_cfg_done_80003es2lan()
534 * @hw: pointer to the HW structure
539 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) e1000_phy_force_speed_duplex_80003es2lan() argument
548 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_phy_force_speed_duplex_80003es2lan()
553 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); e1000_phy_force_speed_duplex_80003es2lan()
559 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); e1000_phy_force_speed_duplex_80003es2lan()
563 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); e1000_phy_force_speed_duplex_80003es2lan()
568 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); e1000_phy_force_speed_duplex_80003es2lan()
574 if (hw->phy.autoneg_wait_to_complete) { e1000_phy_force_speed_duplex_80003es2lan()
577 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000_phy_force_speed_duplex_80003es2lan()
586 ret_val = e1000e_phy_reset_dsp(hw); e1000_phy_force_speed_duplex_80003es2lan()
592 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000_phy_force_speed_duplex_80003es2lan()
598 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); e1000_phy_force_speed_duplex_80003es2lan()
606 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) e1000_phy_force_speed_duplex_80003es2lan()
615 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); e1000_phy_force_speed_duplex_80003es2lan()
622 * @hw: pointer to the HW structure
627 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) e1000_get_cable_length_80003es2lan() argument
629 struct e1000_phy_info *phy = &hw->phy; e1000_get_cable_length_80003es2lan()
633 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); e1000_get_cable_length_80003es2lan()
652 * @hw: pointer to the HW structure
658 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, e1000_get_link_up_info_80003es2lan() argument
663 if (hw->phy.media_type == e1000_media_type_copper) { e1000_get_link_up_info_80003es2lan()
664 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); e1000_get_link_up_info_80003es2lan()
665 hw->phy.ops.cfg_on_link_up(hw); e1000_get_link_up_info_80003es2lan()
667 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, e1000_get_link_up_info_80003es2lan()
677 * @hw: pointer to the HW structure
681 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) e1000_reset_hw_80003es2lan() argument
690 ret_val = e1000e_disable_pcie_master(hw); e1000_reset_hw_80003es2lan()
705 ret_val = e1000_acquire_phy_80003es2lan(hw); e1000_reset_hw_80003es2lan()
711 e1000_release_phy_80003es2lan(hw); e1000_reset_hw_80003es2lan()
715 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, e1000_reset_hw_80003es2lan()
720 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, e1000_reset_hw_80003es2lan()
723 ret_val = e1000e_get_auto_rd_done(hw); e1000_reset_hw_80003es2lan()
732 return e1000_check_alt_mac_addr_generic(hw); e1000_reset_hw_80003es2lan()
737 * @hw: pointer to the HW structure
739 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
741 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) e1000_init_hw_80003es2lan() argument
743 struct e1000_mac_info *mac = &hw->mac; e1000_init_hw_80003es2lan()
749 e1000_initialize_hw_bits_80003es2lan(hw); e1000_init_hw_80003es2lan()
752 ret_val = mac->ops.id_led_init(hw); e1000_init_hw_80003es2lan()
759 mac->ops.clear_vfta(hw); e1000_init_hw_80003es2lan()
762 e1000e_init_rx_addrs(hw, mac->rar_entry_count); e1000_init_hw_80003es2lan()
767 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); e1000_init_hw_80003es2lan()
770 ret_val = mac->ops.setup_link(hw); e1000_init_hw_80003es2lan()
775 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, e1000_init_hw_80003es2lan()
778 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, e1000_init_hw_80003es2lan()
810 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); e1000_init_hw_80003es2lan()
812 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); e1000_init_hw_80003es2lan()
815 hw->dev_spec.e80003es2lan.mdic_wa_enable = true; e1000_init_hw_80003es2lan()
818 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> e1000_init_hw_80003es2lan()
823 hw->dev_spec.e80003es2lan.mdic_wa_enable = false; e1000_init_hw_80003es2lan()
831 e1000_clear_hw_cntrs_80003es2lan(hw); e1000_init_hw_80003es2lan()
837 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
838 * @hw: pointer to the HW structure
842 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) e1000_initialize_hw_bits_80003es2lan() argument
859 if (hw->phy.media_type != e1000_media_type_copper) e1000_initialize_hw_bits_80003es2lan()
881 * @hw: pointer to the HW structure
885 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) e1000_copper_link_setup_gg82563_80003es2lan() argument
887 struct e1000_phy_info *phy = &hw->phy; e1000_copper_link_setup_gg82563_80003es2lan()
892 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); e1000_copper_link_setup_gg82563_80003es2lan()
900 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); e1000_copper_link_setup_gg82563_80003es2lan()
911 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); e1000_copper_link_setup_gg82563_80003es2lan()
940 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); e1000_copper_link_setup_gg82563_80003es2lan()
945 ret_val = hw->phy.ops.commit(hw); e1000_copper_link_setup_gg82563_80003es2lan()
955 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); e1000_copper_link_setup_gg82563_80003es2lan()
960 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); e1000_copper_link_setup_gg82563_80003es2lan()
964 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); e1000_copper_link_setup_gg82563_80003es2lan()
968 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); e1000_copper_link_setup_gg82563_80003es2lan()
973 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); e1000_copper_link_setup_gg82563_80003es2lan()
981 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); e1000_copper_link_setup_gg82563_80003es2lan()
989 if (!hw->mac.ops.check_mng_mode(hw)) { e1000_copper_link_setup_gg82563_80003es2lan()
992 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); e1000_copper_link_setup_gg82563_80003es2lan()
996 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); e1000_copper_link_setup_gg82563_80003es2lan()
1001 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); e1000_copper_link_setup_gg82563_80003es2lan()
1009 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); e1000_copper_link_setup_gg82563_80003es2lan()
1014 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); e1000_copper_link_setup_gg82563_80003es2lan()
1023 * @hw: pointer to the HW structure
1028 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) e1000_setup_copper_link_80003es2lan() argument
1043 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), e1000_setup_copper_link_80003es2lan()
1047 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), e1000_setup_copper_link_80003es2lan()
1052 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), e1000_setup_copper_link_80003es2lan()
1057 e1000_read_kmrn_reg_80003es2lan(hw, e1000_setup_copper_link_80003es2lan()
1064 e1000_write_kmrn_reg_80003es2lan(hw, e1000_setup_copper_link_80003es2lan()
1070 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); e1000_setup_copper_link_80003es2lan()
1074 return e1000e_setup_copper_link(hw); e1000_setup_copper_link_80003es2lan()
1079 * @hw: pointer to the HW structure
1085 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) e1000_cfg_on_link_up_80003es2lan() argument
1091 if (hw->phy.media_type == e1000_media_type_copper) { e1000_cfg_on_link_up_80003es2lan()
1092 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, e1000_cfg_on_link_up_80003es2lan()
1098 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); e1000_cfg_on_link_up_80003es2lan()
1100 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); e1000_cfg_on_link_up_80003es2lan()
1108 * @hw: pointer to the HW structure
1114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) e1000_cfg_kmrn_10_100_80003es2lan() argument
1123 e1000_write_kmrn_reg_80003es2lan(hw, e1000_cfg_kmrn_10_100_80003es2lan()
1136 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); e1000_cfg_kmrn_10_100_80003es2lan()
1140 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2); e1000_cfg_kmrn_10_100_80003es2lan()
1151 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); e1000_cfg_kmrn_10_100_80003es2lan()
1156 * @hw: pointer to the HW structure
1161 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) e1000_cfg_kmrn_1000_80003es2lan() argument
1170 e1000_write_kmrn_reg_80003es2lan(hw, e1000_cfg_kmrn_1000_80003es2lan()
1183 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); e1000_cfg_kmrn_1000_80003es2lan()
1187 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2); e1000_cfg_kmrn_1000_80003es2lan()
1195 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); e1000_cfg_kmrn_1000_80003es2lan()
1200 * @hw: pointer to the HW structure
1208 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, e1000_read_kmrn_reg_80003es2lan() argument
1214 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); e1000_read_kmrn_reg_80003es2lan()
1228 e1000_release_mac_csr_80003es2lan(hw); e1000_read_kmrn_reg_80003es2lan()
1235 * @hw: pointer to the HW structure
1243 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, e1000_write_kmrn_reg_80003es2lan() argument
1249 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); e1000_write_kmrn_reg_80003es2lan()
1260 e1000_release_mac_csr_80003es2lan(hw); e1000_write_kmrn_reg_80003es2lan()
1267 * @hw: pointer to the HW structure
1269 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) e1000_read_mac_addr_80003es2lan() argument
1277 ret_val = e1000_check_alt_mac_addr_generic(hw); e1000_read_mac_addr_80003es2lan()
1281 return e1000_read_mac_addr_generic(hw); e1000_read_mac_addr_80003es2lan()
1286 * @hw: pointer to the HW structure
1291 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) e1000_power_down_phy_copper_80003es2lan() argument
1294 if (!(hw->mac.ops.check_mng_mode(hw) || e1000_power_down_phy_copper_80003es2lan()
1295 hw->phy.ops.check_reset_block(hw))) e1000_power_down_phy_copper_80003es2lan()
1296 e1000_power_down_phy_copper(hw); e1000_power_down_phy_copper_80003es2lan()
1301 * @hw: pointer to the HW structure
1305 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) e1000_clear_hw_cntrs_80003es2lan() argument
1307 e1000e_clear_hw_cntrs_base(hw); e1000_clear_hw_cntrs_80003es2lan()
H A Dphy.c24 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
25 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
28 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
55 * @hw: pointer to the HW structure
61 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) e1000e_check_reset_block_generic() argument
72 * @hw: pointer to the HW structure
77 s32 e1000e_get_phy_id(struct e1000_hw *hw) e1000e_get_phy_id() argument
79 struct e1000_phy_info *phy = &hw->phy; e1000e_get_phy_id()
88 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); e1000e_get_phy_id()
94 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); e1000e_get_phy_id()
112 * @hw: pointer to the HW structure
116 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) e1000e_phy_reset_dsp() argument
120 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); e1000e_phy_reset_dsp()
124 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); e1000e_phy_reset_dsp()
129 * @hw: pointer to the HW structure
136 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_phy_reg_mdic() argument
138 struct e1000_phy_info *phy = &hw->phy; e1000e_read_phy_reg_mdic()
185 if (hw->mac.type == e1000_pch2lan) e1000e_read_phy_reg_mdic()
193 * @hw: pointer to the HW structure
199 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_phy_reg_mdic() argument
201 struct e1000_phy_info *phy = &hw->phy; e1000e_write_phy_reg_mdic()
248 if (hw->mac.type == e1000_pch2lan) e1000e_write_phy_reg_mdic()
256 * @hw: pointer to the HW structure
264 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_phy_reg_m88() argument
268 ret_val = hw->phy.ops.acquire(hw); e1000e_read_phy_reg_m88()
272 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, e1000e_read_phy_reg_m88()
275 hw->phy.ops.release(hw); e1000e_read_phy_reg_m88()
282 * @hw: pointer to the HW structure
289 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_phy_reg_m88() argument
293 ret_val = hw->phy.ops.acquire(hw); e1000e_write_phy_reg_m88()
297 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, e1000e_write_phy_reg_m88()
300 hw->phy.ops.release(hw); e1000e_write_phy_reg_m88()
307 * @hw: pointer to the HW structure
314 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) e1000_set_page_igp() argument
318 hw->phy.addr = 1; e1000_set_page_igp()
320 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); e1000_set_page_igp()
325 * @hw: pointer to the HW structure
334 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, __e1000e_read_phy_reg_igp() argument
340 if (!hw->phy.ops.acquire) __e1000e_read_phy_reg_igp()
343 ret_val = hw->phy.ops.acquire(hw); __e1000e_read_phy_reg_igp()
349 ret_val = e1000e_write_phy_reg_mdic(hw, __e1000e_read_phy_reg_igp()
353 ret_val = e1000e_read_phy_reg_mdic(hw, __e1000e_read_phy_reg_igp()
357 hw->phy.ops.release(hw); __e1000e_read_phy_reg_igp()
364 * @hw: pointer to the HW structure
372 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_phy_reg_igp() argument
374 return __e1000e_read_phy_reg_igp(hw, offset, data, false); e1000e_read_phy_reg_igp()
379 * @hw: pointer to the HW structure
386 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_phy_reg_igp_locked() argument
388 return __e1000e_read_phy_reg_igp(hw, offset, data, true); e1000e_read_phy_reg_igp_locked()
393 * @hw: pointer to the HW structure
401 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, __e1000e_write_phy_reg_igp() argument
407 if (!hw->phy.ops.acquire) __e1000e_write_phy_reg_igp()
410 ret_val = hw->phy.ops.acquire(hw); __e1000e_write_phy_reg_igp()
416 ret_val = e1000e_write_phy_reg_mdic(hw, __e1000e_write_phy_reg_igp()
420 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & __e1000e_write_phy_reg_igp()
423 hw->phy.ops.release(hw); __e1000e_write_phy_reg_igp()
430 * @hw: pointer to the HW structure
437 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_phy_reg_igp() argument
439 return __e1000e_write_phy_reg_igp(hw, offset, data, false); e1000e_write_phy_reg_igp()
444 * @hw: pointer to the HW structure
451 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_phy_reg_igp_locked() argument
453 return __e1000e_write_phy_reg_igp(hw, offset, data, true); e1000e_write_phy_reg_igp_locked()
458 * @hw: pointer to the HW structure
467 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, __e1000_read_kmrn_reg() argument
475 if (!hw->phy.ops.acquire) __e1000_read_kmrn_reg()
478 ret_val = hw->phy.ops.acquire(hw); __e1000_read_kmrn_reg()
494 hw->phy.ops.release(hw); __e1000_read_kmrn_reg()
501 * @hw: pointer to the HW structure
509 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_kmrn_reg() argument
511 return __e1000_read_kmrn_reg(hw, offset, data, false); e1000e_read_kmrn_reg()
516 * @hw: pointer to the HW structure
524 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_kmrn_reg_locked() argument
526 return __e1000_read_kmrn_reg(hw, offset, data, true); e1000e_read_kmrn_reg_locked()
531 * @hw: pointer to the HW structure
540 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, __e1000_write_kmrn_reg() argument
548 if (!hw->phy.ops.acquire) __e1000_write_kmrn_reg()
551 ret_val = hw->phy.ops.acquire(hw); __e1000_write_kmrn_reg()
564 hw->phy.ops.release(hw); __e1000_write_kmrn_reg()
571 * @hw: pointer to the HW structure
578 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_kmrn_reg() argument
580 return __e1000_write_kmrn_reg(hw, offset, data, false); e1000e_write_kmrn_reg()
585 * @hw: pointer to the HW structure
592 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_kmrn_reg_locked() argument
594 return __e1000_write_kmrn_reg(hw, offset, data, true); e1000e_write_kmrn_reg_locked()
599 * @hw: pointer to the HW structure
603 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) e1000_set_master_slave_mode() argument
609 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); e1000_set_master_slave_mode()
614 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? e1000_set_master_slave_mode()
618 switch (hw->phy.ms_type) { e1000_set_master_slave_mode()
633 return e1e_wphy(hw, MII_CTRL1000, phy_data); e1000_set_master_slave_mode()
638 * @hw: pointer to the HW structure
642 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) e1000_copper_link_setup_82577() argument
648 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); e1000_copper_link_setup_82577()
657 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); e1000_copper_link_setup_82577()
662 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); e1000_copper_link_setup_82577()
671 switch (hw->phy.mdix) { e1000_copper_link_setup_82577()
682 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); e1000_copper_link_setup_82577()
686 return e1000_set_master_slave_mode(hw); e1000_copper_link_setup_82577()
691 * @hw: pointer to the HW structure
696 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) e1000e_copper_link_setup_m88() argument
698 struct e1000_phy_info *phy = &hw->phy; e1000e_copper_link_setup_m88()
703 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000e_copper_link_setup_m88()
751 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, e1000e_copper_link_setup_m88()
756 ret_val = phy->ops.commit(hw); e1000e_copper_link_setup_m88()
766 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000e_copper_link_setup_m88()
776 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); e1000e_copper_link_setup_m88()
793 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); e1000e_copper_link_setup_m88()
800 ret_val = e1e_wphy(hw, 29, 0x0003); e1000e_copper_link_setup_m88()
805 ret_val = e1e_wphy(hw, 30, 0x0000); e1000e_copper_link_setup_m88()
812 ret_val = phy->ops.commit(hw); e1000e_copper_link_setup_m88()
820 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); e1000e_copper_link_setup_m88()
827 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); e1000e_copper_link_setup_m88()
837 * @hw: pointer to the HW structure
842 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) e1000e_copper_link_setup_igp() argument
844 struct e1000_phy_info *phy = &hw->phy; e1000e_copper_link_setup_igp()
848 ret_val = e1000_phy_hw_reset(hw); e1000e_copper_link_setup_igp()
860 if (hw->phy.ops.set_d0_lplu_state) { e1000e_copper_link_setup_igp()
861 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); e1000e_copper_link_setup_igp()
868 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); e1000e_copper_link_setup_igp()
886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); e1000e_copper_link_setup_igp()
891 if (hw->mac.autoneg) { e1000e_copper_link_setup_igp()
898 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000e_copper_link_setup_igp()
904 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000e_copper_link_setup_igp()
910 ret_val = e1e_rphy(hw, MII_CTRL1000, &data); e1000e_copper_link_setup_igp()
915 ret_val = e1e_wphy(hw, MII_CTRL1000, data); e1000e_copper_link_setup_igp()
920 ret_val = e1000_set_master_slave_mode(hw); e1000e_copper_link_setup_igp()
928 * @hw: pointer to the HW structure
935 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) e1000_phy_setup_autoneg() argument
937 struct e1000_phy_info *phy = &hw->phy; e1000_phy_setup_autoneg()
945 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); e1000_phy_setup_autoneg()
951 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); e1000_phy_setup_autoneg()
1025 switch (hw->fc.current_mode) { e1000_phy_setup_autoneg()
1041 * hw's ability to send PAUSE frames. e1000_phy_setup_autoneg()
1065 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); e1000_phy_setup_autoneg()
1072 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); e1000_phy_setup_autoneg()
1079 * @hw: pointer to the HW structure
1086 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) e1000_copper_link_autoneg() argument
1088 struct e1000_phy_info *phy = &hw->phy; e1000_copper_link_autoneg()
1104 ret_val = e1000_phy_setup_autoneg(hw); e1000_copper_link_autoneg()
1114 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); e1000_copper_link_autoneg()
1119 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); e1000_copper_link_autoneg()
1127 ret_val = e1000_wait_autoneg(hw); e1000_copper_link_autoneg()
1134 hw->mac.get_link_status = true; e1000_copper_link_autoneg()
1141 * @hw: pointer to the HW structure
1148 s32 e1000e_setup_copper_link(struct e1000_hw *hw) e1000e_setup_copper_link() argument
1153 if (hw->mac.autoneg) { e1000e_setup_copper_link()
1157 ret_val = e1000_copper_link_autoneg(hw); e1000e_setup_copper_link()
1165 ret_val = hw->phy.ops.force_speed_duplex(hw); e1000e_setup_copper_link()
1175 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, e1000e_setup_copper_link()
1182 hw->mac.ops.config_collision_dist(hw); e1000e_setup_copper_link()
1183 ret_val = e1000e_config_fc_after_link_up(hw); e1000e_setup_copper_link()
1193 * @hw: pointer to the HW structure
1199 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) e1000e_phy_force_speed_duplex_igp() argument
1201 struct e1000_phy_info *phy = &hw->phy; e1000e_phy_force_speed_duplex_igp()
1206 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); e1000e_phy_force_speed_duplex_igp()
1210 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); e1000e_phy_force_speed_duplex_igp()
1212 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); e1000e_phy_force_speed_duplex_igp()
1219 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); e1000e_phy_force_speed_duplex_igp()
1226 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); e1000e_phy_force_speed_duplex_igp()
1237 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000e_phy_force_speed_duplex_igp()
1246 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000e_phy_force_speed_duplex_igp()
1255 * @hw: pointer to the HW structure
1263 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) e1000e_phy_force_speed_duplex_m88() argument
1265 struct e1000_phy_info *phy = &hw->phy; e1000e_phy_force_speed_duplex_m88()
1273 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000e_phy_force_speed_duplex_m88()
1278 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000e_phy_force_speed_duplex_m88()
1284 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); e1000e_phy_force_speed_duplex_m88()
1288 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); e1000e_phy_force_speed_duplex_m88()
1290 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); e1000e_phy_force_speed_duplex_m88()
1295 if (hw->phy.ops.commit) { e1000e_phy_force_speed_duplex_m88()
1296 ret_val = hw->phy.ops.commit(hw); e1000e_phy_force_speed_duplex_m88()
1304 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000e_phy_force_speed_duplex_m88()
1310 if (hw->phy.type != e1000_phy_m88) { e1000e_phy_force_speed_duplex_m88()
1316 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, e1000e_phy_force_speed_duplex_m88()
1320 ret_val = e1000e_phy_reset_dsp(hw); e1000e_phy_force_speed_duplex_m88()
1327 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000e_phy_force_speed_duplex_m88()
1333 if (hw->phy.type != e1000_phy_m88) e1000e_phy_force_speed_duplex_m88()
1336 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); e1000e_phy_force_speed_duplex_m88()
1345 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); e1000e_phy_force_speed_duplex_m88()
1352 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000e_phy_force_speed_duplex_m88()
1357 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000e_phy_force_speed_duplex_m88()
1364 * @hw: pointer to the HW structure
1370 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) e1000_phy_force_speed_duplex_ife() argument
1372 struct e1000_phy_info *phy = &hw->phy; e1000_phy_force_speed_duplex_ife()
1377 ret_val = e1e_rphy(hw, MII_BMCR, &data); e1000_phy_force_speed_duplex_ife()
1381 e1000e_phy_force_speed_duplex_setup(hw, &data); e1000_phy_force_speed_duplex_ife()
1383 ret_val = e1e_wphy(hw, MII_BMCR, data); e1000_phy_force_speed_duplex_ife()
1388 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); e1000_phy_force_speed_duplex_ife()
1395 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); e1000_phy_force_speed_duplex_ife()
1406 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000_phy_force_speed_duplex_ife()
1415 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000_phy_force_speed_duplex_ife()
1426 * @hw: pointer to the HW structure
1436 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) e1000e_phy_force_speed_duplex_setup() argument
1438 struct e1000_mac_info *mac = &hw->mac; e1000e_phy_force_speed_duplex_setup()
1442 hw->fc.current_mode = e1000_fc_none; e1000e_phy_force_speed_duplex_setup()
1478 hw->mac.ops.config_collision_dist(hw); e1000e_phy_force_speed_duplex_setup()
1485 * @hw: pointer to the HW structure
1497 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) e1000e_set_d3_lplu_state() argument
1499 struct e1000_phy_info *phy = &hw->phy; e1000e_set_d3_lplu_state()
1503 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); e1000e_set_d3_lplu_state()
1509 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); e1000e_set_d3_lplu_state()
1518 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000e_set_d3_lplu_state()
1524 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000e_set_d3_lplu_state()
1529 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000e_set_d3_lplu_state()
1535 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000e_set_d3_lplu_state()
1544 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); e1000e_set_d3_lplu_state()
1549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); e1000e_set_d3_lplu_state()
1554 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); e1000e_set_d3_lplu_state()
1562 * @hw: pointer to the HW structure
1568 s32 e1000e_check_downshift(struct e1000_hw *hw) e1000e_check_downshift() argument
1570 struct e1000_phy_info *phy = &hw->phy; e1000e_check_downshift()
1593 ret_val = e1e_rphy(hw, offset, &phy_data); e1000e_check_downshift()
1603 * @hw: pointer to the HW structure
1609 s32 e1000_check_polarity_m88(struct e1000_hw *hw) e1000_check_polarity_m88() argument
1611 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_m88()
1615 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); e1000_check_polarity_m88()
1627 * @hw: pointer to the HW structure
1634 s32 e1000_check_polarity_igp(struct e1000_hw *hw) e1000_check_polarity_igp() argument
1636 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_igp()
1643 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); e1000_check_polarity_igp()
1659 ret_val = e1e_rphy(hw, offset, &data); e1000_check_polarity_igp()
1671 * @hw: pointer to the HW structure
1675 s32 e1000_check_polarity_ife(struct e1000_hw *hw) e1000_check_polarity_ife() argument
1677 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_ife()
1691 ret_val = e1e_rphy(hw, offset, &phy_data); e1000_check_polarity_ife()
1703 * @hw: pointer to the HW structure
1708 static s32 e1000_wait_autoneg(struct e1000_hw *hw) e1000_wait_autoneg() argument
1715 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); e1000_wait_autoneg()
1718 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); e1000_wait_autoneg()
1734 * @hw: pointer to the HW structure
1741 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, e1000e_phy_has_link_generic() argument
1752 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); e1000e_phy_has_link_generic()
1763 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); e1000e_phy_has_link_generic()
1781 * @hw: pointer to the HW structure
1794 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) e1000e_get_cable_length_m88() argument
1796 struct e1000_phy_info *phy = &hw->phy; e1000e_get_cable_length_m88()
1800 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); e1000e_get_cable_length_m88()
1820 * @hw: pointer to the HW structure
1829 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) e1000e_get_cable_length_igp_2() argument
1831 struct e1000_phy_info *phy = &hw->phy; e1000e_get_cable_length_igp_2()
1845 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); e1000e_get_cable_length_igp_2()
1889 * @hw: pointer to the HW structure
1897 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) e1000e_get_phy_info_m88() argument
1899 struct e1000_phy_info *phy = &hw->phy; e1000e_get_phy_info_m88()
1909 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); e1000e_get_phy_info_m88()
1918 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000e_get_phy_info_m88()
1925 ret_val = e1000_check_polarity_m88(hw); e1000e_get_phy_info_m88()
1929 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); e1000e_get_phy_info_m88()
1936 ret_val = hw->phy.ops.get_cable_length(hw); e1000e_get_phy_info_m88()
1940 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); e1000e_get_phy_info_m88()
1961 * @hw: pointer to the HW structure
1968 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) e1000e_get_phy_info_igp() argument
1970 struct e1000_phy_info *phy = &hw->phy; e1000e_get_phy_info_igp()
1975 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); e1000e_get_phy_info_igp()
1986 ret_val = e1000_check_polarity_igp(hw); e1000e_get_phy_info_igp()
1990 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); e1000e_get_phy_info_igp()
1998 ret_val = phy->ops.get_cable_length(hw); e1000e_get_phy_info_igp()
2002 ret_val = e1e_rphy(hw, MII_STAT1000, &data); e1000e_get_phy_info_igp()
2022 * @hw: pointer to the HW structure
2026 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) e1000_get_phy_info_ife() argument
2028 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_info_ife()
2033 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); e1000_get_phy_info_ife()
2042 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); e1000_get_phy_info_ife()
2048 ret_val = e1000_check_polarity_ife(hw); e1000_get_phy_info_ife()
2058 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); e1000_get_phy_info_ife()
2074 * @hw: pointer to the HW structure
2079 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) e1000e_phy_sw_reset() argument
2084 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); e1000e_phy_sw_reset()
2089 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); e1000e_phy_sw_reset()
2100 * @hw: pointer to the HW structure
2107 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) e1000e_phy_hw_reset_generic() argument
2109 struct e1000_phy_info *phy = &hw->phy; e1000e_phy_hw_reset_generic()
2114 ret_val = phy->ops.check_reset_block(hw); e1000e_phy_hw_reset_generic()
2119 ret_val = phy->ops.acquire(hw); e1000e_phy_hw_reset_generic()
2134 phy->ops.release(hw); e1000e_phy_hw_reset_generic()
2136 return phy->ops.get_cfg_done(hw); e1000e_phy_hw_reset_generic()
2141 * @hw: pointer to the HW structure
2146 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) e1000e_get_cfg_done_generic() argument
2155 * @hw: pointer to the HW structure
2159 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) e1000e_phy_init_script_igp3() argument
2165 e1e_wphy(hw, 0x2F5B, 0x9018); e1000e_phy_init_script_igp3()
2167 e1e_wphy(hw, 0x2F52, 0x0000); e1000e_phy_init_script_igp3()
2169 e1e_wphy(hw, 0x2FB1, 0x8B24); e1000e_phy_init_script_igp3()
2171 e1e_wphy(hw, 0x2FB2, 0xF8F0); e1000e_phy_init_script_igp3()
2173 e1e_wphy(hw, 0x2010, 0x10B0); e1000e_phy_init_script_igp3()
2175 e1e_wphy(hw, 0x2011, 0x0000); e1000e_phy_init_script_igp3()
2177 e1e_wphy(hw, 0x20DD, 0x249A); e1000e_phy_init_script_igp3()
2179 e1e_wphy(hw, 0x20DE, 0x00D3); e1000e_phy_init_script_igp3()
2181 e1e_wphy(hw, 0x28B4, 0x04CE); e1000e_phy_init_script_igp3()
2183 e1e_wphy(hw, 0x2F70, 0x29E4); e1000e_phy_init_script_igp3()
2185 e1e_wphy(hw, 0x0000, 0x0140); e1000e_phy_init_script_igp3()
2187 e1e_wphy(hw, 0x1F30, 0x1606); e1000e_phy_init_script_igp3()
2189 e1e_wphy(hw, 0x1F31, 0xB814); e1000e_phy_init_script_igp3()
2191 e1e_wphy(hw, 0x1F35, 0x002A); e1000e_phy_init_script_igp3()
2193 e1e_wphy(hw, 0x1F3E, 0x0067); e1000e_phy_init_script_igp3()
2195 e1e_wphy(hw, 0x1F54, 0x0065); e1000e_phy_init_script_igp3()
2197 e1e_wphy(hw, 0x1F55, 0x002A); e1000e_phy_init_script_igp3()
2199 e1e_wphy(hw, 0x1F56, 0x002A); e1000e_phy_init_script_igp3()
2201 e1e_wphy(hw, 0x1F72, 0x3FB0); e1000e_phy_init_script_igp3()
2203 e1e_wphy(hw, 0x1F76, 0xC0FF); e1000e_phy_init_script_igp3()
2205 e1e_wphy(hw, 0x1F77, 0x1DEC); e1000e_phy_init_script_igp3()
2207 e1e_wphy(hw, 0x1F78, 0xF9EF); e1000e_phy_init_script_igp3()
2209 e1e_wphy(hw, 0x1F79, 0x0210); e1000e_phy_init_script_igp3()
2211 e1e_wphy(hw, 0x1895, 0x0003); e1000e_phy_init_script_igp3()
2213 e1e_wphy(hw, 0x1796, 0x0008); e1000e_phy_init_script_igp3()
2215 e1e_wphy(hw, 0x1798, 0xD008); e1000e_phy_init_script_igp3()
2219 e1e_wphy(hw, 0x1898, 0xD918); e1000e_phy_init_script_igp3()
2221 e1e_wphy(hw, 0x187A, 0x0800); e1000e_phy_init_script_igp3()
2225 e1e_wphy(hw, 0x0019, 0x008D); e1000e_phy_init_script_igp3()
2227 e1e_wphy(hw, 0x001B, 0x2080); e1000e_phy_init_script_igp3()
2229 e1e_wphy(hw, 0x0014, 0x0045); e1000e_phy_init_script_igp3()
2231 e1e_wphy(hw, 0x0000, 0x1340); e1000e_phy_init_script_igp3()
2292 * @hw: pointer to the HW structure
2298 s32 e1000e_determine_phy_address(struct e1000_hw *hw) e1000e_determine_phy_address() argument
2304 hw->phy.id = phy_type; e1000e_determine_phy_address()
2307 hw->phy.addr = phy_addr; e1000e_determine_phy_address()
2311 e1000e_get_phy_id(hw); e1000e_determine_phy_address()
2312 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); e1000e_determine_phy_address()
2346 * @hw: pointer to the HW structure
2353 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_phy_reg_bm() argument
2358 ret_val = hw->phy.ops.acquire(hw); e1000e_write_phy_reg_bm()
2364 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, e1000e_write_phy_reg_bm()
2369 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); e1000e_write_phy_reg_bm()
2378 if (hw->phy.addr == 1) { e1000e_write_phy_reg_bm()
2387 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, e1000e_write_phy_reg_bm()
2393 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, e1000e_write_phy_reg_bm()
2397 hw->phy.ops.release(hw); e1000e_write_phy_reg_bm()
2403 * @hw: pointer to the HW structure
2411 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_phy_reg_bm() argument
2416 ret_val = hw->phy.ops.acquire(hw); e1000e_read_phy_reg_bm()
2422 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, e1000e_read_phy_reg_bm()
2427 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); e1000e_read_phy_reg_bm()
2436 if (hw->phy.addr == 1) { e1000e_read_phy_reg_bm()
2445 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, e1000e_read_phy_reg_bm()
2451 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, e1000e_read_phy_reg_bm()
2454 hw->phy.ops.release(hw); e1000e_read_phy_reg_bm()
2460 * @hw: pointer to the HW structure
2468 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) e1000e_read_phy_reg_bm2() argument
2473 ret_val = hw->phy.ops.acquire(hw); e1000e_read_phy_reg_bm2()
2479 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, e1000e_read_phy_reg_bm2()
2484 hw->phy.addr = 1; e1000e_read_phy_reg_bm2()
2488 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, e1000e_read_phy_reg_bm2()
2495 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, e1000e_read_phy_reg_bm2()
2498 hw->phy.ops.release(hw); e1000e_read_phy_reg_bm2()
2504 * @hw: pointer to the HW structure
2511 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) e1000e_write_phy_reg_bm2() argument
2516 ret_val = hw->phy.ops.acquire(hw); e1000e_write_phy_reg_bm2()
2522 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, e1000e_write_phy_reg_bm2()
2527 hw->phy.addr = 1; e1000e_write_phy_reg_bm2()
2531 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, e1000e_write_phy_reg_bm2()
2538 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, e1000e_write_phy_reg_bm2()
2542 hw->phy.ops.release(hw); e1000e_write_phy_reg_bm2()
2548 * @hw: pointer to the HW structure
2554 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) e1000_enable_phy_wakeup_reg_access_bm() argument
2560 hw->phy.addr = 1; e1000_enable_phy_wakeup_reg_access_bm()
2563 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); e1000_enable_phy_wakeup_reg_access_bm()
2569 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); e1000_enable_phy_wakeup_reg_access_bm()
2583 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); e1000_enable_phy_wakeup_reg_access_bm()
2593 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); e1000_enable_phy_wakeup_reg_access_bm()
2598 * @hw: pointer to the HW structure
2607 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) e1000_disable_phy_wakeup_reg_access_bm() argument
2612 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); e1000_disable_phy_wakeup_reg_access_bm()
2619 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); e1000_disable_phy_wakeup_reg_access_bm()
2629 * @hw: pointer to the HW structure
2652 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, e1000_access_phy_wakeup_reg_bm() argument
2661 if ((hw->mac.type == e1000_pchlan) && e1000_access_phy_wakeup_reg_bm()
2668 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); e1000_access_phy_wakeup_reg_bm()
2678 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); e1000_access_phy_wakeup_reg_bm()
2686 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, e1000_access_phy_wakeup_reg_bm()
2690 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, e1000_access_phy_wakeup_reg_bm()
2700 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); e1000_access_phy_wakeup_reg_bm()
2707 * @hw: pointer to the HW structure
2713 void e1000_power_up_phy_copper(struct e1000_hw *hw) e1000_power_up_phy_copper() argument
2718 e1e_rphy(hw, MII_BMCR, &mii_reg); e1000_power_up_phy_copper()
2720 e1e_wphy(hw, MII_BMCR, mii_reg); e1000_power_up_phy_copper()
2725 * @hw: pointer to the HW structure
2731 void e1000_power_down_phy_copper(struct e1000_hw *hw) e1000_power_down_phy_copper() argument
2736 e1e_rphy(hw, MII_BMCR, &mii_reg); e1000_power_down_phy_copper()
2738 e1e_wphy(hw, MII_BMCR, mii_reg); e1000_power_down_phy_copper()
2744 * @hw: pointer to the HW structure
2753 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, __e1000_read_phy_reg_hv() argument
2759 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); __e1000_read_phy_reg_hv()
2762 ret_val = hw->phy.ops.acquire(hw); __e1000_read_phy_reg_hv()
2769 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, __e1000_read_phy_reg_hv()
2775 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, __e1000_read_phy_reg_hv()
2786 ret_val = e1000_set_page_igp(hw, __e1000_read_phy_reg_hv()
2789 hw->phy.addr = phy_addr; __e1000_read_phy_reg_hv()
2799 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); __e1000_read_phy_reg_hv()
2802 hw->phy.ops.release(hw); __e1000_read_phy_reg_hv()
2809 * @hw: pointer to the HW structure
2817 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) e1000_read_phy_reg_hv() argument
2819 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); e1000_read_phy_reg_hv()
2824 * @hw: pointer to the HW structure
2831 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) e1000_read_phy_reg_hv_locked() argument
2833 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); e1000_read_phy_reg_hv_locked()
2838 * @hw: pointer to the HW structure
2845 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) e1000_read_phy_reg_page_hv() argument
2847 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); e1000_read_phy_reg_page_hv()
2852 * @hw: pointer to the HW structure
2860 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, __e1000_write_phy_reg_hv() argument
2866 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); __e1000_write_phy_reg_hv()
2869 ret_val = hw->phy.ops.acquire(hw); __e1000_write_phy_reg_hv()
2876 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, __e1000_write_phy_reg_hv()
2882 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, __e1000_write_phy_reg_hv()
2894 if ((hw->phy.type == e1000_phy_82578) && __e1000_write_phy_reg_hv()
2895 (hw->phy.revision >= 1) && __e1000_write_phy_reg_hv()
2896 (hw->phy.addr == 2) && __e1000_write_phy_reg_hv()
2900 ret_val = e1000_access_phy_debug_regs_hv(hw, __e1000_write_phy_reg_hv()
2909 ret_val = e1000_set_page_igp(hw, __e1000_write_phy_reg_hv()
2912 hw->phy.addr = phy_addr; __e1000_write_phy_reg_hv()
2922 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, __e1000_write_phy_reg_hv()
2927 hw->phy.ops.release(hw); __e1000_write_phy_reg_hv()
2934 * @hw: pointer to the HW structure
2941 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) e1000_write_phy_reg_hv() argument
2943 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); e1000_write_phy_reg_hv()
2948 * @hw: pointer to the HW structure
2955 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) e1000_write_phy_reg_hv_locked() argument
2957 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); e1000_write_phy_reg_hv_locked()
2962 * @hw: pointer to the HW structure
2969 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) e1000_write_phy_reg_page_hv() argument
2971 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); e1000_write_phy_reg_page_hv()
2990 * @hw: pointer to the HW structure
3000 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, e1000_access_phy_debug_regs_hv() argument
3008 addr_reg = ((hw->phy.type == e1000_phy_82578) ? e1000_access_phy_debug_regs_hv()
3013 hw->phy.addr = 2; e1000_access_phy_debug_regs_hv()
3016 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); e1000_access_phy_debug_regs_hv()
3024 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); e1000_access_phy_debug_regs_hv()
3026 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); e1000_access_phy_debug_regs_hv()
3036 * @hw: pointer to the HW structure
3045 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) e1000_link_stall_workaround_hv() argument
3050 if (hw->phy.type != e1000_phy_82578) e1000_link_stall_workaround_hv()
3054 e1e_rphy(hw, MII_BMCR, &data); e1000_link_stall_workaround_hv()
3059 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); e1000_link_stall_workaround_hv()
3073 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, e1000_link_stall_workaround_hv()
3079 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); e1000_link_stall_workaround_hv()
3084 * @hw: pointer to the HW structure
3090 s32 e1000_check_polarity_82577(struct e1000_hw *hw) e1000_check_polarity_82577() argument
3092 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_82577()
3096 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); e1000_check_polarity_82577()
3108 * @hw: pointer to the HW structure
3112 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) e1000_phy_force_speed_duplex_82577() argument
3114 struct e1000_phy_info *phy = &hw->phy; e1000_phy_force_speed_duplex_82577()
3119 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); e1000_phy_force_speed_duplex_82577()
3123 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); e1000_phy_force_speed_duplex_82577()
3125 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); e1000_phy_force_speed_duplex_82577()
3134 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000_phy_force_speed_duplex_82577()
3143 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, e1000_phy_force_speed_duplex_82577()
3152 * @hw: pointer to the HW structure
3159 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) e1000_get_phy_info_82577() argument
3161 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_info_82577()
3166 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); e1000_get_phy_info_82577()
3177 ret_val = e1000_check_polarity_82577(hw); e1000_get_phy_info_82577()
3181 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); e1000_get_phy_info_82577()
3189 ret_val = hw->phy.ops.get_cable_length(hw); e1000_get_phy_info_82577()
3193 ret_val = e1e_rphy(hw, MII_STAT1000, &data); e1000_get_phy_info_82577()
3213 * @hw: pointer to the HW structure
3218 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) e1000_get_cable_length_82577() argument
3220 struct e1000_phy_info *phy = &hw->phy; e1000_get_cable_length_82577()
3224 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); e1000_get_cable_length_82577()
H A Dich8lan.c115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) __er16flash() argument
161 return readw(hw->flash_address + reg); __er16flash()
164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) __er32flash() argument
166 return readl(hw->flash_address + reg); __er32flash()
169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) __ew16flash() argument
171 writew(val, hw->flash_address + reg); __ew16flash()
174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) __ew32flash() argument
176 writel(val, hw->flash_address + reg); __ew32flash()
179 #define er16flash(reg) __er16flash(hw, (reg))
180 #define er32flash(reg) __er32flash(hw, (reg))
181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
186 * @hw: pointer to the HW structure
192 * Assumes the sw/fw/hw semaphore is already acquired.
194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) e1000_phy_is_accessible_pchlan() argument
203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); e1000_phy_is_accessible_pchlan()
208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); e1000_phy_is_accessible_pchlan()
217 if (hw->phy.id) { e1000_phy_is_accessible_pchlan()
218 if (hw->phy.id == phy_id) e1000_phy_is_accessible_pchlan()
221 hw->phy.id = phy_id; e1000_phy_is_accessible_pchlan()
222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); e1000_phy_is_accessible_pchlan()
229 if (hw->mac.type < e1000_pch_lpt) { e1000_phy_is_accessible_pchlan()
230 hw->phy.ops.release(hw); e1000_phy_is_accessible_pchlan()
231 ret_val = e1000_set_mdio_slow_mode_hv(hw); e1000_phy_is_accessible_pchlan()
233 ret_val = e1000e_get_phy_id(hw); e1000_phy_is_accessible_pchlan()
234 hw->phy.ops.acquire(hw); e1000_phy_is_accessible_pchlan()
240 if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) { e1000_phy_is_accessible_pchlan()
244 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); e1000_phy_is_accessible_pchlan()
246 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); e1000_phy_is_accessible_pchlan()
260 * @hw: pointer to the HW structure
265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) e1000_toggle_lanphypc_pch_lpt() argument
286 if (hw->mac.type < e1000_pch_lpt) { e1000_toggle_lanphypc_pch_lpt()
301 * @hw: pointer to the HW structure
306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) e1000_init_phy_workarounds_pchlan() argument
308 struct e1000_adapter *adapter = hw->adapter; e1000_init_phy_workarounds_pchlan()
315 e1000_gate_hw_phy_config_ich8lan(hw, true); e1000_init_phy_workarounds_pchlan()
320 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; e1000_init_phy_workarounds_pchlan()
321 e1000_disable_ulp_lpt_lp(hw, true); e1000_init_phy_workarounds_pchlan()
323 ret_val = hw->phy.ops.acquire(hw); e1000_init_phy_workarounds_pchlan()
333 switch (hw->mac.type) { e1000_init_phy_workarounds_pchlan()
336 if (e1000_phy_is_accessible_pchlan(hw)) e1000_init_phy_workarounds_pchlan()
354 if (e1000_phy_is_accessible_pchlan(hw)) e1000_init_phy_workarounds_pchlan()
359 if ((hw->mac.type == e1000_pchlan) && e1000_init_phy_workarounds_pchlan()
363 if (hw->phy.ops.check_reset_block(hw)) { e1000_init_phy_workarounds_pchlan()
370 e1000_toggle_lanphypc_pch_lpt(hw); e1000_init_phy_workarounds_pchlan()
371 if (hw->mac.type >= e1000_pch_lpt) { e1000_init_phy_workarounds_pchlan()
372 if (e1000_phy_is_accessible_pchlan(hw)) e1000_init_phy_workarounds_pchlan()
382 if (e1000_phy_is_accessible_pchlan(hw)) e1000_init_phy_workarounds_pchlan()
392 hw->phy.ops.release(hw); e1000_init_phy_workarounds_pchlan()
396 if (hw->phy.ops.check_reset_block(hw)) { e1000_init_phy_workarounds_pchlan()
406 ret_val = e1000e_phy_hw_reset_generic(hw); e1000_init_phy_workarounds_pchlan()
416 ret_val = hw->phy.ops.check_reset_block(hw); e1000_init_phy_workarounds_pchlan()
423 if ((hw->mac.type == e1000_pch2lan) && e1000_init_phy_workarounds_pchlan()
426 e1000_gate_hw_phy_config_ich8lan(hw, false); e1000_init_phy_workarounds_pchlan()
434 * @hw: pointer to the HW structure
438 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) e1000_init_phy_params_pchlan() argument
440 struct e1000_phy_info *phy = &hw->phy; e1000_init_phy_params_pchlan()
461 ret_val = e1000_init_phy_workarounds_pchlan(hw); e1000_init_phy_params_pchlan()
466 switch (hw->mac.type) { e1000_init_phy_params_pchlan()
468 ret_val = e1000e_get_phy_id(hw); e1000_init_phy_params_pchlan()
480 ret_val = e1000_set_mdio_slow_mode_hv(hw); e1000_init_phy_params_pchlan()
483 ret_val = e1000e_get_phy_id(hw); e1000_init_phy_params_pchlan()
517 * @hw: pointer to the HW structure
521 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) e1000_init_phy_params_ich8lan() argument
523 struct e1000_phy_info *phy = &hw->phy; e1000_init_phy_params_ich8lan()
536 ret_val = e1000e_determine_phy_address(hw); e1000_init_phy_params_ich8lan()
540 ret_val = e1000e_determine_phy_address(hw); e1000_init_phy_params_ich8lan()
551 ret_val = e1000e_get_phy_id(hw); e1000_init_phy_params_ich8lan()
595 * @hw: pointer to the HW structure
600 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) e1000_init_nvm_params_ich8lan() argument
602 struct e1000_nvm_info *nvm = &hw->nvm; e1000_init_nvm_params_ich8lan()
603 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_init_nvm_params_ich8lan()
610 if (hw->mac.type == e1000_pch_spt) { e1000_init_nvm_params_ich8lan()
624 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; e1000_init_nvm_params_ich8lan()
627 if (!hw->flash_address) { e1000_init_nvm_params_ich8lan()
668 * @hw: pointer to the HW structure
673 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) e1000_init_mac_params_ich8lan() argument
675 struct e1000_mac_info *mac = &hw->mac; e1000_init_mac_params_ich8lan()
678 hw->phy.media_type = e1000_media_type_copper; e1000_init_mac_params_ich8lan()
745 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); e1000_init_mac_params_ich8lan()
752 * @hw: pointer to the HW structure
759 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, __e1000_access_emi_reg_locked() argument
764 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); __e1000_access_emi_reg_locked()
769 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); __e1000_access_emi_reg_locked()
771 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); __e1000_access_emi_reg_locked()
778 * @hw: pointer to the HW structure
784 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) e1000_read_emi_reg_locked() argument
786 return __e1000_access_emi_reg_locked(hw, addr, data, true); e1000_read_emi_reg_locked()
791 * @hw: pointer to the HW structure
797 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) e1000_write_emi_reg_locked() argument
799 return __e1000_access_emi_reg_locked(hw, addr, &data, false); e1000_write_emi_reg_locked()
804 * @hw: pointer to the HW structure
816 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) e1000_set_eee_pchlan() argument
818 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_set_eee_pchlan()
822 switch (hw->phy.type) { e1000_set_eee_pchlan()
837 ret_val = hw->phy.ops.acquire(hw); e1000_set_eee_pchlan()
841 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); e1000_set_eee_pchlan()
851 ret_val = e1000_read_emi_reg_locked(hw, lpa, e1000_set_eee_pchlan()
857 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); e1000_set_eee_pchlan()
868 e1e_rphy_locked(hw, MII_LPA, &data); e1000_set_eee_pchlan()
881 if (hw->phy.type == e1000_phy_82579) { e1000_set_eee_pchlan()
882 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, e1000_set_eee_pchlan()
888 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, e1000_set_eee_pchlan()
893 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); e1000_set_eee_pchlan()
897 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); e1000_set_eee_pchlan()
899 hw->phy.ops.release(hw); e1000_set_eee_pchlan()
906 * @hw: pointer to the HW structure
915 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) e1000_k1_workaround_lpt_lp() argument
923 ret_val = hw->phy.ops.acquire(hw); e1000_k1_workaround_lpt_lp()
928 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, e1000_k1_workaround_lpt_lp()
934 e1000e_write_kmrn_reg_locked(hw, e1000_k1_workaround_lpt_lp()
946 e1000e_write_kmrn_reg_locked(hw, e1000_k1_workaround_lpt_lp()
950 hw->phy.ops.release(hw); e1000_k1_workaround_lpt_lp()
955 if ((hw->phy.revision > 5) || !link || e1000_k1_workaround_lpt_lp()
960 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg); e1000_k1_workaround_lpt_lp()
982 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); e1000_k1_workaround_lpt_lp()
995 * @hw: pointer to the HW structure
1009 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) e1000_platform_pm_pch_lpt() argument
1022 if (!hw->adapter->max_frame_size) { e1000_platform_pm_pch_lpt()
1027 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); e1000_platform_pm_pch_lpt()
1045 value = (rxa > hw->adapter->max_frame_size) ? e1000_platform_pm_pch_lpt()
1046 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : e1000_platform_pm_pch_lpt()
1060 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, e1000_platform_pm_pch_lpt()
1062 pci_read_config_word(hw->adapter->pdev, e1000_platform_pm_pch_lpt()
1079 * @hw: pointer to the HW structure
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) e1000_enable_ulp_lpt_lp() argument
1094 if ((hw->mac.type < e1000_pch_lpt) || e1000_enable_ulp_lpt_lp()
1095 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || e1000_enable_ulp_lpt_lp()
1096 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || e1000_enable_ulp_lpt_lp()
1097 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || e1000_enable_ulp_lpt_lp()
1098 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || e1000_enable_ulp_lpt_lp()
1099 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) e1000_enable_ulp_lpt_lp()
1130 ret_val = hw->phy.ops.acquire(hw); e1000_enable_ulp_lpt_lp()
1135 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); e1000_enable_ulp_lpt_lp()
1139 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); e1000_enable_ulp_lpt_lp()
1149 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { e1000_enable_ulp_lpt_lp()
1150 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, e1000_enable_ulp_lpt_lp()
1158 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, e1000_enable_ulp_lpt_lp()
1168 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); e1000_enable_ulp_lpt_lp()
1186 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); e1000_enable_ulp_lpt_lp()
1195 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); e1000_enable_ulp_lpt_lp()
1197 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && e1000_enable_ulp_lpt_lp()
1199 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, e1000_enable_ulp_lpt_lp()
1206 hw->phy.ops.release(hw); e1000_enable_ulp_lpt_lp()
1211 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; e1000_enable_ulp_lpt_lp()
1218 * @hw: pointer to the HW structure
1231 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) e1000_disable_ulp_lpt_lp() argument
1238 if ((hw->mac.type < e1000_pch_lpt) || e1000_disable_ulp_lpt_lp()
1239 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || e1000_disable_ulp_lpt_lp()
1240 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || e1000_disable_ulp_lpt_lp()
1241 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || e1000_disable_ulp_lpt_lp()
1242 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || e1000_disable_ulp_lpt_lp()
1243 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) e1000_disable_ulp_lpt_lp()
1280 ret_val = hw->phy.ops.acquire(hw); e1000_disable_ulp_lpt_lp()
1286 e1000_toggle_lanphypc_pch_lpt(hw); e1000_disable_ulp_lpt_lp()
1289 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); e1000_disable_ulp_lpt_lp()
1300 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, e1000_disable_ulp_lpt_lp()
1306 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); e1000_disable_ulp_lpt_lp()
1316 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); e1000_disable_ulp_lpt_lp()
1320 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); e1000_disable_ulp_lpt_lp()
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); e1000_disable_ulp_lpt_lp()
1332 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); e1000_disable_ulp_lpt_lp()
1336 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); e1000_disable_ulp_lpt_lp()
1344 hw->phy.ops.release(hw); e1000_disable_ulp_lpt_lp()
1346 e1000_phy_hw_reset(hw); e1000_disable_ulp_lpt_lp()
1353 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; e1000_disable_ulp_lpt_lp()
1360 * @hw: pointer to the HW structure
1366 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) e1000_check_for_copper_link_ich8lan() argument
1368 struct e1000_mac_info *mac = &hw->mac; e1000_check_for_copper_link_ich8lan()
1386 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); e1000_check_for_copper_link_ich8lan()
1390 if (hw->mac.type == e1000_pchlan) { e1000_check_for_copper_link_ich8lan()
1391 ret_val = e1000_k1_gig_workaround_hv(hw, link); e1000_check_for_copper_link_ich8lan()
1400 if (((hw->mac.type == e1000_pch2lan) || e1000_check_for_copper_link_ich8lan()
1401 (hw->mac.type == e1000_pch_lpt) || e1000_check_for_copper_link_ich8lan()
1402 (hw->mac.type == e1000_pch_spt)) && link) { e1000_check_for_copper_link_ich8lan()
1405 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); e1000_check_for_copper_link_ich8lan()
1413 } else if (hw->mac.type == e1000_pch_spt && e1000_check_for_copper_link_ich8lan()
1426 ret_val = hw->phy.ops.acquire(hw); e1000_check_for_copper_link_ich8lan()
1430 if (hw->mac.type == e1000_pch2lan) e1000_check_for_copper_link_ich8lan()
1434 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); e1000_check_for_copper_link_ich8lan()
1436 hw->phy.ops.release(hw); e1000_check_for_copper_link_ich8lan()
1441 if (hw->mac.type == e1000_pch_spt) { e1000_check_for_copper_link_ich8lan()
1446 ret_val = hw->phy.ops.acquire(hw); e1000_check_for_copper_link_ich8lan()
1450 ret_val = e1e_rphy_locked(hw, e1000_check_for_copper_link_ich8lan()
1454 hw->phy.ops.release(hw); e1000_check_for_copper_link_ich8lan()
1463 e1e_wphy_locked(hw, e1000_check_for_copper_link_ich8lan()
1467 hw->phy.ops.release(hw); e1000_check_for_copper_link_ich8lan()
1479 if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) { e1000_check_for_copper_link_ich8lan()
1489 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || e1000_check_for_copper_link_ich8lan()
1490 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || e1000_check_for_copper_link_ich8lan()
1491 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || e1000_check_for_copper_link_ich8lan()
1492 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { e1000_check_for_copper_link_ich8lan()
1493 ret_val = e1000_k1_workaround_lpt_lp(hw, link); e1000_check_for_copper_link_ich8lan()
1497 if ((hw->mac.type == e1000_pch_lpt) || e1000_check_for_copper_link_ich8lan()
1498 (hw->mac.type == e1000_pch_spt)) { e1000_check_for_copper_link_ich8lan()
1502 ret_val = e1000_platform_pm_pch_lpt(hw, link); e1000_check_for_copper_link_ich8lan()
1508 hw->dev_spec.ich8lan.eee_lp_ability = 0; e1000_check_for_copper_link_ich8lan()
1511 if (hw->mac.type == e1000_pch_spt) { e1000_check_for_copper_link_ich8lan()
1528 switch (hw->mac.type) { e1000_check_for_copper_link_ich8lan()
1530 ret_val = e1000_k1_workaround_lv(hw); e1000_check_for_copper_link_ich8lan()
1535 if (hw->phy.type == e1000_phy_82578) { e1000_check_for_copper_link_ich8lan()
1536 ret_val = e1000_link_stall_workaround_hv(hw); e1000_check_for_copper_link_ich8lan()
1546 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); e1000_check_for_copper_link_ich8lan()
1552 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); e1000_check_for_copper_link_ich8lan()
1561 e1000e_check_downshift(hw); e1000_check_for_copper_link_ich8lan()
1564 if (hw->phy.type > e1000_phy_82579) { e1000_check_for_copper_link_ich8lan()
1565 ret_val = e1000_set_eee_pchlan(hw); e1000_check_for_copper_link_ich8lan()
1580 mac->ops.config_collision_dist(hw); e1000_check_for_copper_link_ich8lan()
1587 ret_val = e1000e_config_fc_after_link_up(hw); e1000_check_for_copper_link_ich8lan()
1596 struct e1000_hw *hw = &adapter->hw; e1000_get_variants_ich8lan() local
1599 rc = e1000_init_mac_params_ich8lan(hw); e1000_get_variants_ich8lan()
1603 rc = e1000_init_nvm_params_ich8lan(hw); e1000_get_variants_ich8lan()
1607 switch (hw->mac.type) { e1000_get_variants_ich8lan()
1611 rc = e1000_init_phy_params_ich8lan(hw); e1000_get_variants_ich8lan()
1617 rc = e1000_init_phy_params_pchlan(hw); e1000_get_variants_ich8lan()
1628 if ((adapter->hw.phy.type == e1000_phy_ife) || e1000_get_variants_ich8lan()
1629 ((adapter->hw.mac.type >= e1000_pch2lan) && e1000_get_variants_ich8lan()
1634 hw->mac.ops.blink_led = NULL; e1000_get_variants_ich8lan()
1637 if ((adapter->hw.mac.type == e1000_ich8lan) && e1000_get_variants_ich8lan()
1638 (adapter->hw.phy.type != e1000_phy_ife)) e1000_get_variants_ich8lan()
1642 if ((adapter->hw.mac.type == e1000_pch2lan) && e1000_get_variants_ich8lan()
1653 * @hw: pointer to the HW structure
1657 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) e1000_acquire_nvm_ich8lan() argument
1666 * @hw: pointer to the HW structure
1670 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) e1000_release_nvm_ich8lan() argument
1677 * @hw: pointer to the HW structure
1682 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) e1000_acquire_swflag_ich8lan() argument
1688 &hw->adapter->state)) { e1000_acquire_swflag_ich8lan()
1733 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); e1000_acquire_swflag_ich8lan()
1740 * @hw: pointer to the HW structure
1745 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) e1000_release_swflag_ich8lan() argument
1755 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); e1000_release_swflag_ich8lan()
1758 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); e1000_release_swflag_ich8lan()
1763 * @hw: pointer to the HW structure
1769 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) e1000_check_mng_mode_ich8lan() argument
1781 * @hw: pointer to the HW structure
1787 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) e1000_check_mng_mode_pchlan() argument
1798 * @hw: pointer to the HW structure
1807 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) e1000_rar_set_pch2lan() argument
1835 if (index < (u32)(hw->mac.rar_entry_count)) { e1000_rar_set_pch2lan()
1838 ret_val = e1000_acquire_swflag_ich8lan(hw); e1000_rar_set_pch2lan()
1847 e1000_release_swflag_ich8lan(hw); e1000_rar_set_pch2lan()
1865 * @hw: pointer to the HW structure
1873 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) e1000_rar_get_count_pch_lpt() argument
1884 num_entries = hw->mac.rar_entry_count; e1000_rar_get_count_pch_lpt()
1901 * @hw: pointer to the HW structure
1910 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) e1000_rar_set_pch_lpt() argument
1938 if (index < hw->mac.rar_entry_count) { e1000_rar_set_pch_lpt()
1949 ret_val = e1000_acquire_swflag_ich8lan(hw); e1000_rar_set_pch_lpt()
1959 e1000_release_swflag_ich8lan(hw); e1000_rar_set_pch_lpt()
1975 * @hw: pointer to the HW structure
1981 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) e1000_check_reset_block_ich8lan() argument
1994 * @hw: pointer to the HW structure
1999 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) e1000_write_smbus_addr() argument
2009 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); e1000_write_smbus_addr()
2017 if (hw->phy.type == e1000_phy_i217) { e1000_write_smbus_addr()
2030 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); e1000_write_smbus_addr()
2035 * @hw: pointer to the HW structure
2040 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) e1000_sw_lcd_config_ich8lan() argument
2042 struct e1000_phy_info *phy = &hw->phy; e1000_sw_lcd_config_ich8lan()
2053 switch (hw->mac.type) { e1000_sw_lcd_config_ich8lan()
2058 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || e1000_sw_lcd_config_ich8lan()
2059 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { e1000_sw_lcd_config_ich8lan()
2074 ret_val = hw->phy.ops.acquire(hw); e1000_sw_lcd_config_ich8lan()
2086 if ((hw->mac.type < e1000_pch2lan) && e1000_sw_lcd_config_ich8lan()
2099 if (((hw->mac.type == e1000_pchlan) && e1000_sw_lcd_config_ich8lan()
2101 (hw->mac.type > e1000_pchlan)) { e1000_sw_lcd_config_ich8lan()
2107 ret_val = e1000_write_smbus_addr(hw); e1000_sw_lcd_config_ich8lan()
2112 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, e1000_sw_lcd_config_ich8lan()
2124 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data); e1000_sw_lcd_config_ich8lan()
2128 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), e1000_sw_lcd_config_ich8lan()
2142 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); e1000_sw_lcd_config_ich8lan()
2148 hw->phy.ops.release(hw); e1000_sw_lcd_config_ich8lan()
2154 * @hw: pointer to the HW structure
2162 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) e1000_k1_gig_workaround_hv() argument
2166 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; e1000_k1_gig_workaround_hv()
2168 if (hw->mac.type != e1000_pchlan) e1000_k1_gig_workaround_hv()
2172 ret_val = hw->phy.ops.acquire(hw); e1000_k1_gig_workaround_hv()
2178 if (hw->phy.type == e1000_phy_82578) { e1000_k1_gig_workaround_hv()
2179 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, e1000_k1_gig_workaround_hv()
2194 if (hw->phy.type == e1000_phy_82577) { e1000_k1_gig_workaround_hv()
2195 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); e1000_k1_gig_workaround_hv()
2210 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); e1000_k1_gig_workaround_hv()
2216 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); e1000_k1_gig_workaround_hv()
2221 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); e1000_k1_gig_workaround_hv()
2224 hw->phy.ops.release(hw); e1000_k1_gig_workaround_hv()
2231 * @hw: pointer to the HW structure
2239 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) e1000_configure_k1_ich8lan() argument
2247 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, e1000_configure_k1_ich8lan()
2257 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, e1000_configure_k1_ich8lan()
2283 * @hw: pointer to the HW structure
2290 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) e1000_oem_bits_config_ich8lan() argument
2296 if (hw->mac.type < e1000_pchlan) e1000_oem_bits_config_ich8lan()
2299 ret_val = hw->phy.ops.acquire(hw); e1000_oem_bits_config_ich8lan()
2303 if (hw->mac.type == e1000_pchlan) { e1000_oem_bits_config_ich8lan()
2315 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); e1000_oem_bits_config_ich8lan()
2338 if ((d0_state || (hw->mac.type != e1000_pchlan)) && e1000_oem_bits_config_ich8lan()
2339 !hw->phy.ops.check_reset_block(hw)) e1000_oem_bits_config_ich8lan()
2342 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); e1000_oem_bits_config_ich8lan()
2345 hw->phy.ops.release(hw); e1000_oem_bits_config_ich8lan()
2352 * @hw: pointer to the HW structure
2354 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) e1000_set_mdio_slow_mode_hv() argument
2359 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); e1000_set_mdio_slow_mode_hv()
2365 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); e1000_set_mdio_slow_mode_hv()
2374 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) e1000_hv_phy_workarounds_ich8lan() argument
2379 if (hw->mac.type != e1000_pchlan) e1000_hv_phy_workarounds_ich8lan()
2383 if (hw->phy.type == e1000_phy_82577) { e1000_hv_phy_workarounds_ich8lan()
2384 ret_val = e1000_set_mdio_slow_mode_hv(hw); e1000_hv_phy_workarounds_ich8lan()
2389 if (((hw->phy.type == e1000_phy_82577) && e1000_hv_phy_workarounds_ich8lan()
2390 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || e1000_hv_phy_workarounds_ich8lan()
2391 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { e1000_hv_phy_workarounds_ich8lan()
2393 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); e1000_hv_phy_workarounds_ich8lan()
2398 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); e1000_hv_phy_workarounds_ich8lan()
2403 if (hw->phy.type == e1000_phy_82578) { e1000_hv_phy_workarounds_ich8lan()
2407 if (hw->phy.revision < 2) { e1000_hv_phy_workarounds_ich8lan()
2408 e1000e_phy_sw_reset(hw); e1000_hv_phy_workarounds_ich8lan()
2409 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); e1000_hv_phy_workarounds_ich8lan()
2414 ret_val = hw->phy.ops.acquire(hw); e1000_hv_phy_workarounds_ich8lan()
2418 hw->phy.addr = 1; e1000_hv_phy_workarounds_ich8lan()
2419 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); e1000_hv_phy_workarounds_ich8lan()
2420 hw->phy.ops.release(hw); e1000_hv_phy_workarounds_ich8lan()
2427 ret_val = e1000_k1_gig_workaround_hv(hw, true); e1000_hv_phy_workarounds_ich8lan()
2432 ret_val = hw->phy.ops.acquire(hw); e1000_hv_phy_workarounds_ich8lan()
2435 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); e1000_hv_phy_workarounds_ich8lan()
2438 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); e1000_hv_phy_workarounds_ich8lan()
2443 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); e1000_hv_phy_workarounds_ich8lan()
2445 hw->phy.ops.release(hw); e1000_hv_phy_workarounds_ich8lan()
2452 * @hw: pointer to the HW structure
2454 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) e1000_copy_rx_addrs_to_phy_ich8lan() argument
2460 ret_val = hw->phy.ops.acquire(hw); e1000_copy_rx_addrs_to_phy_ich8lan()
2463 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); e1000_copy_rx_addrs_to_phy_ich8lan()
2468 for (i = 0; i < (hw->mac.rar_entry_count); i++) { e1000_copy_rx_addrs_to_phy_ich8lan()
2470 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), e1000_copy_rx_addrs_to_phy_ich8lan()
2472 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), e1000_copy_rx_addrs_to_phy_ich8lan()
2476 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), e1000_copy_rx_addrs_to_phy_ich8lan()
2478 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), e1000_copy_rx_addrs_to_phy_ich8lan()
2483 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); e1000_copy_rx_addrs_to_phy_ich8lan()
2486 hw->phy.ops.release(hw); e1000_copy_rx_addrs_to_phy_ich8lan()
2492 * @hw: pointer to the HW structure
2495 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) e1000_lv_jumbo_workaround_ich8lan() argument
2502 if (hw->mac.type < e1000_pch2lan) e1000_lv_jumbo_workaround_ich8lan()
2506 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); e1000_lv_jumbo_workaround_ich8lan()
2507 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); e1000_lv_jumbo_workaround_ich8lan()
2515 for (i = 0; i < hw->mac.rar_entry_count; i++) { e1000_lv_jumbo_workaround_ich8lan()
2534 e1000_copy_rx_addrs_to_phy_ich8lan(hw); e1000_lv_jumbo_workaround_ich8lan()
2546 ret_val = e1000e_read_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2551 ret_val = e1000e_write_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2556 ret_val = e1000e_read_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2563 ret_val = e1000e_write_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2570 e1e_rphy(hw, PHY_REG(769, 23), &data); e1000_lv_jumbo_workaround_ich8lan()
2573 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); e1000_lv_jumbo_workaround_ich8lan()
2576 e1e_rphy(hw, PHY_REG(769, 16), &data); e1000_lv_jumbo_workaround_ich8lan()
2578 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); e1000_lv_jumbo_workaround_ich8lan()
2581 e1e_rphy(hw, PHY_REG(776, 20), &data); e1000_lv_jumbo_workaround_ich8lan()
2584 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); e1000_lv_jumbo_workaround_ich8lan()
2587 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); e1000_lv_jumbo_workaround_ich8lan()
2590 e1e_rphy(hw, HV_PM_CTRL, &data); e1000_lv_jumbo_workaround_ich8lan()
2591 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); e1000_lv_jumbo_workaround_ich8lan()
2604 ret_val = e1000e_read_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2609 ret_val = e1000e_write_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2614 ret_val = e1000e_read_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2621 ret_val = e1000e_write_kmrn_reg(hw, e1000_lv_jumbo_workaround_ich8lan()
2628 e1e_rphy(hw, PHY_REG(769, 23), &data); e1000_lv_jumbo_workaround_ich8lan()
2630 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); e1000_lv_jumbo_workaround_ich8lan()
2633 e1e_rphy(hw, PHY_REG(769, 16), &data); e1000_lv_jumbo_workaround_ich8lan()
2635 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); e1000_lv_jumbo_workaround_ich8lan()
2638 e1e_rphy(hw, PHY_REG(776, 20), &data); e1000_lv_jumbo_workaround_ich8lan()
2641 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); e1000_lv_jumbo_workaround_ich8lan()
2644 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); e1000_lv_jumbo_workaround_ich8lan()
2647 e1e_rphy(hw, HV_PM_CTRL, &data); e1000_lv_jumbo_workaround_ich8lan()
2648 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); e1000_lv_jumbo_workaround_ich8lan()
2654 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); e1000_lv_jumbo_workaround_ich8lan()
2661 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) e1000_lv_phy_workarounds_ich8lan() argument
2665 if (hw->mac.type != e1000_pch2lan) e1000_lv_phy_workarounds_ich8lan()
2669 ret_val = e1000_set_mdio_slow_mode_hv(hw); e1000_lv_phy_workarounds_ich8lan()
2673 ret_val = hw->phy.ops.acquire(hw); e1000_lv_phy_workarounds_ich8lan()
2677 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); e1000_lv_phy_workarounds_ich8lan()
2681 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); e1000_lv_phy_workarounds_ich8lan()
2683 hw->phy.ops.release(hw); e1000_lv_phy_workarounds_ich8lan()
2690 * @hw: pointer to the HW structure
2695 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) e1000_k1_workaround_lv() argument
2700 if (hw->mac.type != e1000_pch2lan) e1000_k1_workaround_lv()
2704 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); e1000_k1_workaround_lv()
2715 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); e1000_k1_workaround_lv()
2719 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); e1000_k1_workaround_lv()
2737 * @hw: pointer to the HW structure
2743 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) e1000_gate_hw_phy_config_ich8lan() argument
2747 if (hw->mac.type < e1000_pch2lan) e1000_gate_hw_phy_config_ich8lan()
2762 * @hw: pointer to the HW structure
2767 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) e1000_lan_init_done_ich8lan() argument
2793 * @hw: pointer to the HW structure
2795 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) e1000_post_phy_reset_ich8lan() argument
2800 if (hw->phy.ops.check_reset_block(hw)) e1000_post_phy_reset_ich8lan()
2807 switch (hw->mac.type) { e1000_post_phy_reset_ich8lan()
2809 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); e1000_post_phy_reset_ich8lan()
2814 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); e1000_post_phy_reset_ich8lan()
2823 if (hw->mac.type >= e1000_pchlan) { e1000_post_phy_reset_ich8lan()
2824 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg); e1000_post_phy_reset_ich8lan()
2826 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); e1000_post_phy_reset_ich8lan()
2830 ret_val = e1000_sw_lcd_config_ich8lan(hw); e1000_post_phy_reset_ich8lan()
2835 ret_val = e1000_oem_bits_config_ich8lan(hw, true); e1000_post_phy_reset_ich8lan()
2837 if (hw->mac.type == e1000_pch2lan) { e1000_post_phy_reset_ich8lan()
2841 e1000_gate_hw_phy_config_ich8lan(hw, false); e1000_post_phy_reset_ich8lan()
2845 ret_val = hw->phy.ops.acquire(hw); e1000_post_phy_reset_ich8lan()
2848 ret_val = e1000_write_emi_reg_locked(hw, e1000_post_phy_reset_ich8lan()
2851 hw->phy.ops.release(hw); e1000_post_phy_reset_ich8lan()
2859 * @hw: pointer to the HW structure
2865 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) e1000_phy_hw_reset_ich8lan() argument
2870 if ((hw->mac.type == e1000_pch2lan) && e1000_phy_hw_reset_ich8lan()
2872 e1000_gate_hw_phy_config_ich8lan(hw, true); e1000_phy_hw_reset_ich8lan()
2874 ret_val = e1000e_phy_hw_reset_generic(hw); e1000_phy_hw_reset_ich8lan()
2878 return e1000_post_phy_reset_ich8lan(hw); e1000_phy_hw_reset_ich8lan()
2883 * @hw: pointer to the HW structure
2889 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2892 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) e1000_set_lplu_state_pchlan() argument
2897 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); e1000_set_lplu_state_pchlan()
2906 if (!hw->phy.ops.check_reset_block(hw)) e1000_set_lplu_state_pchlan()
2909 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); e1000_set_lplu_state_pchlan()
2914 * @hw: pointer to the HW structure
2925 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) e1000_set_d0_lplu_state_ich8lan() argument
2927 struct e1000_phy_info *phy = &hw->phy; e1000_set_d0_lplu_state_ich8lan()
2947 if (hw->mac.type == e1000_ich8lan) e1000_set_d0_lplu_state_ich8lan()
2948 e1000e_gig_downshift_workaround_ich8lan(hw); e1000_set_d0_lplu_state_ich8lan()
2951 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); e1000_set_d0_lplu_state_ich8lan()
2955 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); e1000_set_d0_lplu_state_ich8lan()
2971 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d0_lplu_state_ich8lan()
2977 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d0_lplu_state_ich8lan()
2982 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d0_lplu_state_ich8lan()
2988 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d0_lplu_state_ich8lan()
3000 * @hw: pointer to the HW structure
3011 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) e1000_set_d3_lplu_state_ich8lan() argument
3013 struct e1000_phy_info *phy = &hw->phy; e1000_set_d3_lplu_state_ich8lan()
3033 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state_ich8lan()
3039 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state_ich8lan()
3044 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state_ich8lan()
3050 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state_ich8lan()
3067 if (hw->mac.type == e1000_ich8lan) e1000_set_d3_lplu_state_ich8lan()
3068 e1000e_gig_downshift_workaround_ich8lan(hw); e1000_set_d3_lplu_state_ich8lan()
3071 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); e1000_set_d3_lplu_state_ich8lan()
3076 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); e1000_set_d3_lplu_state_ich8lan()
3084 * @hw: pointer to the HW structure
3090 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) e1000_valid_nvm_bank_detect_ich8lan() argument
3093 struct e1000_nvm_info *nvm = &hw->nvm; e1000_valid_nvm_bank_detect_ich8lan()
3099 switch (hw->mac.type) { e1000_valid_nvm_bank_detect_ich8lan()
3133 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, e1000_valid_nvm_bank_detect_ich8lan()
3144 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + e1000_valid_nvm_bank_detect_ich8lan()
3162 * @hw: pointer to the HW structure
3169 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, e1000_read_nvm_spt() argument
3172 struct e1000_nvm_info *nvm = &hw->nvm; e1000_read_nvm_spt()
3173 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_read_nvm_spt()
3188 nvm->ops.acquire(hw); e1000_read_nvm_spt()
3190 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); e1000_read_nvm_spt()
3210 e1000_read_flash_dword_ich8lan(hw, e1000_read_nvm_spt()
3225 e1000_read_flash_dword_ich8lan(hw, e1000_read_nvm_spt()
3244 nvm->ops.release(hw); e1000_read_nvm_spt()
3255 * @hw: pointer to the HW structure
3262 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, e1000_read_nvm_ich8lan() argument
3265 struct e1000_nvm_info *nvm = &hw->nvm; e1000_read_nvm_ich8lan()
3266 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_read_nvm_ich8lan()
3279 nvm->ops.acquire(hw); e1000_read_nvm_ich8lan()
3281 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); e1000_read_nvm_ich8lan()
3295 ret_val = e1000_read_flash_word_ich8lan(hw, e1000_read_nvm_ich8lan()
3304 nvm->ops.release(hw); e1000_read_nvm_ich8lan()
3315 * @hw: pointer to the HW structure
3320 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) e1000_flash_cycle_init_ich8lan() argument
3333 /* Clear FCERR and DAEL in hw status by writing 1 */ e1000_flash_cycle_init_ich8lan()
3336 if (hw->mac.type == e1000_pch_spt) e1000_flash_cycle_init_ich8lan()
3355 if (hw->mac.type == e1000_pch_spt) e1000_flash_cycle_init_ich8lan()
3379 if (hw->mac.type == e1000_pch_spt) e1000_flash_cycle_init_ich8lan()
3394 * @hw: pointer to the HW structure
3399 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) e1000_flash_cycle_ich8lan() argument
3406 if (hw->mac.type == e1000_pch_spt) e1000_flash_cycle_ich8lan()
3412 if (hw->mac.type == e1000_pch_spt) e1000_flash_cycle_ich8lan()
3433 * @hw: pointer to the HW structure
3440 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, e1000_read_flash_dword_ich8lan() argument
3445 return e1000_read_flash_data32_ich8lan(hw, offset, data); e1000_read_flash_dword_ich8lan()
3450 * @hw: pointer to the HW structure
3457 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, e1000_read_flash_word_ich8lan() argument
3463 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); e1000_read_flash_word_ich8lan()
3468 * @hw: pointer to the HW structure
3474 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, e1000_read_flash_byte_ich8lan() argument
3483 if (hw->mac.type == e1000_pch_spt) e1000_read_flash_byte_ich8lan()
3486 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); e1000_read_flash_byte_ich8lan()
3498 * @hw: pointer to the HW structure
3505 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, e1000_read_flash_data_ich8lan() argument
3519 hw->nvm.flash_base_addr); e1000_read_flash_data_ich8lan()
3524 ret_val = e1000_flash_cycle_init_ich8lan(hw); e1000_read_flash_data_ich8lan()
3537 e1000_flash_cycle_ich8lan(hw, e1000_read_flash_data_ich8lan()
3574 * @hw: pointer to the HW structure
3581 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, e1000_read_flash_data32_ich8lan() argument
3591 hw->mac.type != e1000_pch_spt) e1000_read_flash_data32_ich8lan()
3594 hw->nvm.flash_base_addr); e1000_read_flash_data32_ich8lan()
3599 ret_val = e1000_flash_cycle_init_ich8lan(hw); e1000_read_flash_data32_ich8lan()
3617 e1000_flash_cycle_ich8lan(hw, e1000_read_flash_data32_ich8lan()
3650 * @hw: pointer to the HW structure
3657 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, e1000_write_nvm_ich8lan() argument
3660 struct e1000_nvm_info *nvm = &hw->nvm; e1000_write_nvm_ich8lan()
3661 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_write_nvm_ich8lan()
3670 nvm->ops.acquire(hw); e1000_write_nvm_ich8lan()
3677 nvm->ops.release(hw); e1000_write_nvm_ich8lan()
3684 * @hw: pointer to the HW structure
3693 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) e1000_update_nvm_checksum_spt() argument
3695 struct e1000_nvm_info *nvm = &hw->nvm; e1000_update_nvm_checksum_spt()
3696 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_update_nvm_checksum_spt()
3701 ret_val = e1000e_update_nvm_checksum_generic(hw); e1000_update_nvm_checksum_spt()
3708 nvm->ops.acquire(hw); e1000_update_nvm_checksum_spt()
3714 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); e1000_update_nvm_checksum_spt()
3723 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); e1000_update_nvm_checksum_spt()
3729 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); e1000_update_nvm_checksum_spt()
3738 ret_val = e1000_read_flash_dword_ich8lan(hw, e1000_update_nvm_checksum_spt()
3771 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, e1000_update_nvm_checksum_spt()
3795 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); e1000_update_nvm_checksum_spt()
3801 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); e1000_update_nvm_checksum_spt()
3815 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); e1000_update_nvm_checksum_spt()
3821 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); e1000_update_nvm_checksum_spt()
3833 nvm->ops.release(hw); e1000_update_nvm_checksum_spt()
3839 nvm->ops.reload(hw); e1000_update_nvm_checksum_spt()
3852 * @hw: pointer to the HW structure
3861 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) e1000_update_nvm_checksum_ich8lan() argument
3863 struct e1000_nvm_info *nvm = &hw->nvm; e1000_update_nvm_checksum_ich8lan()
3864 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_update_nvm_checksum_ich8lan()
3869 ret_val = e1000e_update_nvm_checksum_generic(hw); e1000_update_nvm_checksum_ich8lan()
3876 nvm->ops.acquire(hw); e1000_update_nvm_checksum_ich8lan()
3882 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); e1000_update_nvm_checksum_ich8lan()
3891 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); e1000_update_nvm_checksum_ich8lan()
3897 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); e1000_update_nvm_checksum_ich8lan()
3905 ret_val = e1000_read_flash_word_ich8lan(hw, i + e1000_update_nvm_checksum_ich8lan()
3927 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, e1000_update_nvm_checksum_ich8lan()
3934 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, e1000_update_nvm_checksum_ich8lan()
3956 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); e1000_update_nvm_checksum_ich8lan()
3961 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, e1000_update_nvm_checksum_ich8lan()
3973 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); e1000_update_nvm_checksum_ich8lan()
3984 nvm->ops.release(hw); e1000_update_nvm_checksum_ich8lan()
3990 nvm->ops.reload(hw); e1000_update_nvm_checksum_ich8lan()
4003 * @hw: pointer to the HW structure
4009 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) e1000_validate_nvm_checksum_ich8lan() argument
4021 switch (hw->mac.type) { e1000_validate_nvm_checksum_ich8lan()
4033 ret_val = e1000_read_nvm(hw, word, 1, &data); e1000_validate_nvm_checksum_ich8lan()
4039 ret_val = e1000_write_nvm(hw, word, 1, &data); e1000_validate_nvm_checksum_ich8lan()
4042 ret_val = e1000e_update_nvm_checksum(hw); e1000_validate_nvm_checksum_ich8lan()
4047 return e1000e_validate_nvm_checksum_generic(hw); e1000_validate_nvm_checksum_ich8lan()
4052 * @hw: pointer to the HW structure
4060 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) e1000e_write_protect_nvm_ich8lan() argument
4062 struct e1000_nvm_info *nvm = &hw->nvm; e1000e_write_protect_nvm_ich8lan()
4067 nvm->ops.acquire(hw); e1000e_write_protect_nvm_ich8lan()
4087 nvm->ops.release(hw); e1000e_write_protect_nvm_ich8lan()
4092 * @hw: pointer to the HW structure
4099 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, e1000_write_flash_data_ich8lan() argument
4109 if (hw->mac.type == e1000_pch_spt) { e1000_write_flash_data_ich8lan()
4118 hw->nvm.flash_base_addr); e1000_write_flash_data_ich8lan()
4123 ret_val = e1000_flash_cycle_init_ich8lan(hw); e1000_write_flash_data_ich8lan()
4129 if (hw->mac.type == e1000_pch_spt) e1000_write_flash_data_ich8lan()
4141 if (hw->mac.type == e1000_pch_spt) e1000_write_flash_data_ich8lan()
4159 e1000_flash_cycle_ich8lan(hw, e1000_write_flash_data_ich8lan()
4184 * @hw: pointer to the HW structure
4190 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, e1000_write_flash_data32_ich8lan() argument
4199 if (hw->mac.type == e1000_pch_spt) { e1000_write_flash_data32_ich8lan()
4204 hw->nvm.flash_base_addr); e1000_write_flash_data32_ich8lan()
4208 ret_val = e1000_flash_cycle_init_ich8lan(hw); e1000_write_flash_data32_ich8lan()
4215 if (hw->mac.type == e1000_pch_spt) e1000_write_flash_data32_ich8lan()
4228 if (hw->mac.type == e1000_pch_spt) e1000_write_flash_data32_ich8lan()
4241 e1000_flash_cycle_ich8lan(hw, e1000_write_flash_data32_ich8lan()
4268 * @hw: pointer to the HW structure
4274 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, e1000_write_flash_byte_ich8lan() argument
4279 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); e1000_write_flash_byte_ich8lan()
4284 * @hw: pointer to the HW structure
4291 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, e1000_retry_write_flash_dword_ich8lan() argument
4299 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); e1000_retry_write_flash_dword_ich8lan()
4306 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); e1000_retry_write_flash_dword_ich8lan()
4318 * @hw: pointer to the HW structure
4325 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, e1000_retry_write_flash_byte_ich8lan() argument
4331 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); e1000_retry_write_flash_byte_ich8lan()
4338 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); e1000_retry_write_flash_byte_ich8lan()
4350 * @hw: pointer to the HW structure
4356 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) e1000_erase_flash_bank_ich8lan() argument
4358 struct e1000_nvm_info *nvm = &hw->nvm; e1000_erase_flash_bank_ich8lan()
4370 /* Determine HW Sector size: Read BERASE bits of hw flash status e1000_erase_flash_bank_ich8lan()
4405 flash_linear_addr = hw->nvm.flash_base_addr; e1000_erase_flash_bank_ich8lan()
4413 ret_val = e1000_flash_cycle_init_ich8lan(hw); e1000_erase_flash_bank_ich8lan()
4418 * Cycle field in hw flash control e1000_erase_flash_bank_ich8lan()
4420 if (hw->mac.type == e1000_pch_spt) e1000_erase_flash_bank_ich8lan()
4427 if (hw->mac.type == e1000_pch_spt) e1000_erase_flash_bank_ich8lan()
4440 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); e1000_erase_flash_bank_ich8lan()
4462 * @hw: pointer to the HW structure
4469 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) e1000_valid_led_default_ich8lan() argument
4473 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); e1000_valid_led_default_ich8lan()
4487 * @hw: pointer to the HW structure
4498 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) e1000_id_led_init_pchlan() argument
4500 struct e1000_mac_info *mac = &hw->mac; e1000_id_led_init_pchlan()
4507 ret_val = hw->nvm.ops.valid_led_default(hw, &data); e1000_id_led_init_pchlan()
4559 * @hw: pointer to the HW structure
4564 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) e1000_get_bus_info_ich8lan() argument
4566 struct e1000_bus_info *bus = &hw->bus; e1000_get_bus_info_ich8lan()
4569 ret_val = e1000e_get_bus_info_pcie(hw); e1000_get_bus_info_ich8lan()
4584 * @hw: pointer to the HW structure
4589 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) e1000_reset_hw_ich8lan() argument
4591 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_reset_hw_ich8lan()
4599 ret_val = e1000e_disable_pcie_master(hw); e1000_reset_hw_ich8lan()
4617 if (hw->mac.type == e1000_ich8lan) { e1000_reset_hw_ich8lan()
4624 if (hw->mac.type == e1000_pchlan) { e1000_reset_hw_ich8lan()
4626 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); e1000_reset_hw_ich8lan()
4638 if (!hw->phy.ops.check_reset_block(hw)) { e1000_reset_hw_ich8lan()
4648 if ((hw->mac.type == e1000_pch2lan) && e1000_reset_hw_ich8lan()
4650 e1000_gate_hw_phy_config_ich8lan(hw, true); e1000_reset_hw_ich8lan()
4652 ret_val = e1000_acquire_swflag_ich8lan(hw); e1000_reset_hw_ich8lan()
4659 if (hw->mac.type == e1000_pch2lan) { e1000_reset_hw_ich8lan()
4667 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); e1000_reset_hw_ich8lan()
4670 ret_val = hw->phy.ops.get_cfg_done(hw); e1000_reset_hw_ich8lan()
4674 ret_val = e1000_post_phy_reset_ich8lan(hw); e1000_reset_hw_ich8lan()
4683 if (hw->mac.type == e1000_pchlan) e1000_reset_hw_ich8lan()
4698 * @hw: pointer to the HW structure
4708 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) e1000_init_hw_ich8lan() argument
4710 struct e1000_mac_info *mac = &hw->mac; e1000_init_hw_ich8lan()
4715 e1000_initialize_hw_bits_ich8lan(hw); e1000_init_hw_ich8lan()
4718 ret_val = mac->ops.id_led_init(hw); e1000_init_hw_ich8lan()
4724 e1000e_init_rx_addrs(hw, mac->rar_entry_count); e1000_init_hw_ich8lan()
4729 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); e1000_init_hw_ich8lan()
4735 if (hw->phy.type == e1000_phy_82578) { e1000_init_hw_ich8lan()
4736 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); e1000_init_hw_ich8lan()
4738 e1e_wphy(hw, BM_PORT_GEN_CFG, i); e1000_init_hw_ich8lan()
4739 ret_val = e1000_phy_hw_reset_ich8lan(hw); e1000_init_hw_ich8lan()
4745 ret_val = mac->ops.setup_link(hw); e1000_init_hw_ich8lan()
4768 e1000e_set_pcie_no_snoop(hw, snoop); e1000_init_hw_ich8lan()
4779 e1000_clear_hw_cntrs_ich8lan(hw); e1000_init_hw_ich8lan()
4786 * @hw: pointer to the HW structure
4791 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) e1000_initialize_hw_bits_ich8lan() argument
4799 if (hw->mac.type >= e1000_pchlan) e1000_initialize_hw_bits_ich8lan()
4815 if (hw->mac.type == e1000_ich8lan) e1000_initialize_hw_bits_ich8lan()
4830 if (hw->mac.type == e1000_ich8lan) { e1000_initialize_hw_bits_ich8lan()
4845 if (hw->mac.type == e1000_ich8lan) e1000_initialize_hw_bits_ich8lan()
4850 if ((hw->mac.type == e1000_pch_lpt) || e1000_initialize_hw_bits_ich8lan()
4851 (hw->mac.type == e1000_pch_spt)) { e1000_initialize_hw_bits_ich8lan()
4864 * @hw: pointer to the HW structure
4872 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) e1000_setup_link_ich8lan() argument
4876 if (hw->phy.ops.check_reset_block(hw)) e1000_setup_link_ich8lan()
4883 if (hw->fc.requested_mode == e1000_fc_default) { e1000_setup_link_ich8lan()
4885 if (hw->mac.type == e1000_pchlan) e1000_setup_link_ich8lan()
4886 hw->fc.requested_mode = e1000_fc_rx_pause; e1000_setup_link_ich8lan()
4888 hw->fc.requested_mode = e1000_fc_full; e1000_setup_link_ich8lan()
4894 hw->fc.current_mode = hw->fc.requested_mode; e1000_setup_link_ich8lan()
4896 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); e1000_setup_link_ich8lan()
4899 ret_val = hw->mac.ops.setup_physical_interface(hw); e1000_setup_link_ich8lan()
4903 ew32(FCTTV, hw->fc.pause_time); e1000_setup_link_ich8lan()
4904 if ((hw->phy.type == e1000_phy_82578) || e1000_setup_link_ich8lan()
4905 (hw->phy.type == e1000_phy_82579) || e1000_setup_link_ich8lan()
4906 (hw->phy.type == e1000_phy_i217) || e1000_setup_link_ich8lan()
4907 (hw->phy.type == e1000_phy_82577)) { e1000_setup_link_ich8lan()
4908 ew32(FCRTV_PCH, hw->fc.refresh_time); e1000_setup_link_ich8lan()
4910 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), e1000_setup_link_ich8lan()
4911 hw->fc.pause_time); e1000_setup_link_ich8lan()
4916 return e1000e_set_fc_watermarks(hw); e1000_setup_link_ich8lan()
4921 * @hw: pointer to the HW structure
4927 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) e1000_setup_copper_link_ich8lan() argument
4942 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); e1000_setup_copper_link_ich8lan()
4945 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, e1000_setup_copper_link_ich8lan()
4950 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, e1000_setup_copper_link_ich8lan()
4955 switch (hw->phy.type) { e1000_setup_copper_link_ich8lan()
4957 ret_val = e1000e_copper_link_setup_igp(hw); e1000_setup_copper_link_ich8lan()
4963 ret_val = e1000e_copper_link_setup_m88(hw); e1000_setup_copper_link_ich8lan()
4969 ret_val = e1000_copper_link_setup_82577(hw); e1000_setup_copper_link_ich8lan()
4974 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data); e1000_setup_copper_link_ich8lan()
4980 switch (hw->phy.mdix) { e1000_setup_copper_link_ich8lan()
4992 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); e1000_setup_copper_link_ich8lan()
5000 return e1000e_setup_copper_link(hw); e1000_setup_copper_link_ich8lan()
5005 * @hw: pointer to the HW structure
5011 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) e1000_setup_copper_link_pch_lpt() argument
5021 ret_val = e1000_copper_link_setup_82577(hw); e1000_setup_copper_link_pch_lpt()
5025 return e1000e_setup_copper_link(hw); e1000_setup_copper_link_pch_lpt()
5030 * @hw: pointer to the HW structure
5038 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, e1000_get_link_up_info_ich8lan() argument
5043 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); e1000_get_link_up_info_ich8lan()
5047 if ((hw->mac.type == e1000_ich8lan) && e1000_get_link_up_info_ich8lan()
5048 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { e1000_get_link_up_info_ich8lan()
5049 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); e1000_get_link_up_info_ich8lan()
5057 * @hw: pointer to the HW structure
5070 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) e1000_kmrn_lock_loss_workaround_ich8lan() argument
5072 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_kmrn_lock_loss_workaround_ich8lan()
5085 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); e1000_kmrn_lock_loss_workaround_ich8lan()
5091 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); e1000_kmrn_lock_loss_workaround_ich8lan()
5095 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); e1000_kmrn_lock_loss_workaround_ich8lan()
5104 e1000_phy_hw_reset(hw); e1000_kmrn_lock_loss_workaround_ich8lan()
5116 e1000e_gig_downshift_workaround_ich8lan(hw); e1000_kmrn_lock_loss_workaround_ich8lan()
5124 * @hw: pointer to the HW structure
5130 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, e1000e_set_kmrn_lock_loss_workaround_ich8lan() argument
5133 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5135 if (hw->mac.type != e1000_ich8lan) { e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5145 * @hw: pointer to the HW structure
5153 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) e1000e_igp3_phy_powerdown_workaround_ich8lan() argument
5159 if (hw->phy.type != e1000_phy_igp_3) e1000e_igp3_phy_powerdown_workaround_ich8lan()
5173 if (hw->mac.type == e1000_ich8lan) e1000e_igp3_phy_powerdown_workaround_ich8lan()
5174 e1000e_gig_downshift_workaround_ich8lan(hw); e1000e_igp3_phy_powerdown_workaround_ich8lan()
5177 e1e_rphy(hw, IGP3_VR_CTRL, &data); e1000e_igp3_phy_powerdown_workaround_ich8lan()
5179 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); e1000e_igp3_phy_powerdown_workaround_ich8lan()
5182 e1e_rphy(hw, IGP3_VR_CTRL, &data); e1000e_igp3_phy_powerdown_workaround_ich8lan()
5196 * @hw: pointer to the HW structure
5204 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) e1000e_gig_downshift_workaround_ich8lan() argument
5209 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) e1000e_gig_downshift_workaround_ich8lan()
5212 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, e1000e_gig_downshift_workaround_ich8lan()
5217 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, e1000e_gig_downshift_workaround_ich8lan()
5222 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); e1000e_gig_downshift_workaround_ich8lan()
5227 * @hw: pointer to the HW structure
5239 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) e1000_suspend_workarounds_ich8lan() argument
5241 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; e1000_suspend_workarounds_ich8lan()
5248 if (hw->phy.type == e1000_phy_i217) { e1000_suspend_workarounds_ich8lan()
5249 u16 phy_reg, device_id = hw->adapter->pdev->device; e1000_suspend_workarounds_ich8lan()
5255 (hw->mac.type == e1000_pch_spt)) { e1000_suspend_workarounds_ich8lan()
5261 ret_val = hw->phy.ops.acquire(hw); e1000_suspend_workarounds_ich8lan()
5269 e1000_read_emi_reg_locked(hw, e1000_suspend_workarounds_ich8lan()
5283 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { e1000_suspend_workarounds_ich8lan()
5288 e1e_rphy_locked(hw, e1000_suspend_workarounds_ich8lan()
5291 e1e_wphy_locked(hw, e1000_suspend_workarounds_ich8lan()
5305 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); e1000_suspend_workarounds_ich8lan()
5307 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); e1000_suspend_workarounds_ich8lan()
5312 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); e1000_suspend_workarounds_ich8lan()
5314 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); e1000_suspend_workarounds_ich8lan()
5317 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); e1000_suspend_workarounds_ich8lan()
5319 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); e1000_suspend_workarounds_ich8lan()
5325 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); e1000_suspend_workarounds_ich8lan()
5327 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); e1000_suspend_workarounds_ich8lan()
5330 hw->phy.ops.release(hw); e1000_suspend_workarounds_ich8lan()
5335 if (hw->mac.type == e1000_ich8lan) e1000_suspend_workarounds_ich8lan()
5336 e1000e_gig_downshift_workaround_ich8lan(hw); e1000_suspend_workarounds_ich8lan()
5338 if (hw->mac.type >= e1000_pchlan) { e1000_suspend_workarounds_ich8lan()
5339 e1000_oem_bits_config_ich8lan(hw, false); e1000_suspend_workarounds_ich8lan()
5342 if (hw->mac.type == e1000_pchlan) e1000_suspend_workarounds_ich8lan()
5343 e1000e_phy_hw_reset_generic(hw); e1000_suspend_workarounds_ich8lan()
5345 ret_val = hw->phy.ops.acquire(hw); e1000_suspend_workarounds_ich8lan()
5348 e1000_write_smbus_addr(hw); e1000_suspend_workarounds_ich8lan()
5349 hw->phy.ops.release(hw); e1000_suspend_workarounds_ich8lan()
5355 * @hw: pointer to the HW structure
5363 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) e1000_resume_workarounds_pchlan() argument
5367 if (hw->mac.type < e1000_pch2lan) e1000_resume_workarounds_pchlan()
5370 ret_val = e1000_init_phy_workarounds_pchlan(hw); e1000_resume_workarounds_pchlan()
5381 if (hw->phy.type == e1000_phy_i217) { e1000_resume_workarounds_pchlan()
5384 ret_val = hw->phy.ops.acquire(hw); e1000_resume_workarounds_pchlan()
5391 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); e1000_resume_workarounds_pchlan()
5393 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); e1000_resume_workarounds_pchlan()
5399 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); e1000_resume_workarounds_pchlan()
5403 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); e1000_resume_workarounds_pchlan()
5406 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); e1000_resume_workarounds_pchlan()
5409 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); e1000_resume_workarounds_pchlan()
5413 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); e1000_resume_workarounds_pchlan()
5417 hw->phy.ops.release(hw); e1000_resume_workarounds_pchlan()
5423 * @hw: pointer to the HW structure
5427 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) e1000_cleanup_led_ich8lan() argument
5429 if (hw->phy.type == e1000_phy_ife) e1000_cleanup_led_ich8lan()
5430 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); e1000_cleanup_led_ich8lan()
5432 ew32(LEDCTL, hw->mac.ledctl_default); e1000_cleanup_led_ich8lan()
5438 * @hw: pointer to the HW structure
5442 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) e1000_led_on_ich8lan() argument
5444 if (hw->phy.type == e1000_phy_ife) e1000_led_on_ich8lan()
5445 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, e1000_led_on_ich8lan()
5448 ew32(LEDCTL, hw->mac.ledctl_mode2); e1000_led_on_ich8lan()
5454 * @hw: pointer to the HW structure
5458 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) e1000_led_off_ich8lan() argument
5460 if (hw->phy.type == e1000_phy_ife) e1000_led_off_ich8lan()
5461 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, e1000_led_off_ich8lan()
5465 ew32(LEDCTL, hw->mac.ledctl_mode1); e1000_led_off_ich8lan()
5471 * @hw: pointer to the HW structure
5475 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) e1000_setup_led_pchlan() argument
5477 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); e1000_setup_led_pchlan()
5482 * @hw: pointer to the HW structure
5486 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) e1000_cleanup_led_pchlan() argument
5488 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); e1000_cleanup_led_pchlan()
5493 * @hw: pointer to the HW structure
5497 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) e1000_led_on_pchlan() argument
5499 u16 data = (u16)hw->mac.ledctl_mode2; e1000_led_on_pchlan()
5518 return e1e_wphy(hw, HV_LED_CONFIG, data); e1000_led_on_pchlan()
5523 * @hw: pointer to the HW structure
5527 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) e1000_led_off_pchlan() argument
5529 u16 data = (u16)hw->mac.ledctl_mode1; e1000_led_off_pchlan()
5548 return e1e_wphy(hw, HV_LED_CONFIG, data); e1000_led_off_pchlan()
5553 * @hw: pointer to the HW structure
5563 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) e1000_get_cfg_done_ich8lan() argument
5569 e1000e_get_cfg_done_generic(hw); e1000_get_cfg_done_ich8lan()
5572 if (hw->mac.type >= e1000_ich10lan) { e1000_get_cfg_done_ich8lan()
5573 e1000_lan_init_done_ich8lan(hw); e1000_get_cfg_done_ich8lan()
5575 ret_val = e1000e_get_auto_rd_done(hw); e1000_get_cfg_done_ich8lan()
5594 if (hw->mac.type <= e1000_ich9lan) { e1000_get_cfg_done_ich8lan()
5596 (hw->phy.type == e1000_phy_igp_3)) { e1000_get_cfg_done_ich8lan()
5597 e1000e_phy_init_script_igp3(hw); e1000_get_cfg_done_ich8lan()
5600 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { e1000_get_cfg_done_ich8lan()
5612 * @hw: pointer to the HW structure
5617 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) e1000_power_down_phy_copper_ich8lan() argument
5620 if (!(hw->mac.ops.check_mng_mode(hw) || e1000_power_down_phy_copper_ich8lan()
5621 hw->phy.ops.check_reset_block(hw))) e1000_power_down_phy_copper_ich8lan()
5622 e1000_power_down_phy_copper(hw); e1000_power_down_phy_copper_ich8lan()
5627 * @hw: pointer to the HW structure
5632 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) e1000_clear_hw_cntrs_ich8lan() argument
5637 e1000e_clear_hw_cntrs_base(hw); e1000_clear_hw_cntrs_ich8lan()
5654 if ((hw->phy.type == e1000_phy_82578) || e1000_clear_hw_cntrs_ich8lan()
5655 (hw->phy.type == e1000_phy_82579) || e1000_clear_hw_cntrs_ich8lan()
5656 (hw->phy.type == e1000_phy_i217) || e1000_clear_hw_cntrs_ich8lan()
5657 (hw->phy.type == e1000_phy_82577)) { e1000_clear_hw_cntrs_ich8lan()
5658 ret_val = hw->phy.ops.acquire(hw); e1000_clear_hw_cntrs_ich8lan()
5661 ret_val = hw->phy.ops.set_page(hw, e1000_clear_hw_cntrs_ich8lan()
5665 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5666 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5667 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5668 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5669 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5670 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5671 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5672 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5673 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5674 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5675 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5676 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5677 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5678 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); e1000_clear_hw_cntrs_ich8lan()
5680 hw->phy.ops.release(hw); e1000_clear_hw_cntrs_ich8lan()
H A Dnvm.h25 s32 e1000e_acquire_nvm(struct e1000_hw *hw);
27 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
28 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
29 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
31 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
32 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
33 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
34 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
35 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
36 void e1000e_release_nvm(struct e1000_hw *hw);
/linux-4.4.14/drivers/net/wireless/realtek/rtl818x/rtl8187/
H A Drfkill.h4 void rtl8187_rfkill_init(struct ieee80211_hw *hw);
5 void rtl8187_rfkill_poll(struct ieee80211_hw *hw);
6 void rtl8187_rfkill_exit(struct ieee80211_hw *hw);
/linux-4.4.14/drivers/media/platform/s5p-g2d/
H A DMakefile1 s5p-g2d-objs := g2d.o g2d-hw.o
/linux-4.4.14/drivers/net/ethernet/atheros/alx/
H A DMakefile2 alx-objs := main.o ethtool.o hw.o
H A Dhw.c39 #include "hw.h"
46 static int alx_wait_mdio_idle(struct alx_hw *hw) alx_wait_mdio_idle() argument
52 val = alx_read_mem32(hw, ALX_MDIO); alx_wait_mdio_idle()
61 static int alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev, alx_read_phy_core() argument
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? alx_read_phy_core()
77 alx_write_mem32(hw, ALX_MDIO_EXTN, val); alx_read_phy_core()
88 alx_write_mem32(hw, ALX_MDIO, val); alx_read_phy_core()
90 err = alx_wait_mdio_idle(hw); alx_read_phy_core()
93 val = alx_read_mem32(hw, ALX_MDIO); alx_read_phy_core()
98 static int alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev, alx_write_phy_core() argument
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? alx_write_phy_core()
111 alx_write_mem32(hw, ALX_MDIO_EXTN, val); alx_write_phy_core()
124 alx_write_mem32(hw, ALX_MDIO, val); alx_write_phy_core()
126 return alx_wait_mdio_idle(hw); alx_write_phy_core()
129 static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) __alx_read_phy_reg() argument
131 return alx_read_phy_core(hw, false, 0, reg, phy_data); __alx_read_phy_reg()
134 static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) __alx_write_phy_reg() argument
136 return alx_write_phy_core(hw, false, 0, reg, phy_data); __alx_write_phy_reg()
139 static int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) __alx_read_phy_ext() argument
141 return alx_read_phy_core(hw, true, dev, reg, pdata); __alx_read_phy_ext()
144 static int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) __alx_write_phy_ext() argument
146 return alx_write_phy_core(hw, true, dev, reg, data); __alx_write_phy_ext()
149 static int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) __alx_read_phy_dbg() argument
153 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); __alx_read_phy_dbg()
157 return __alx_read_phy_reg(hw, ALX_MII_DBG_DATA, pdata); __alx_read_phy_dbg()
160 static int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) __alx_write_phy_dbg() argument
164 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); __alx_write_phy_dbg()
168 return __alx_write_phy_reg(hw, ALX_MII_DBG_DATA, data); __alx_write_phy_dbg()
171 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) alx_read_phy_reg() argument
175 spin_lock(&hw->mdio_lock); alx_read_phy_reg()
176 err = __alx_read_phy_reg(hw, reg, phy_data); alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); alx_read_phy_reg()
182 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) alx_write_phy_reg() argument
186 spin_lock(&hw->mdio_lock); alx_write_phy_reg()
187 err = __alx_write_phy_reg(hw, reg, phy_data); alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); alx_write_phy_reg()
193 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) alx_read_phy_ext() argument
197 spin_lock(&hw->mdio_lock); alx_read_phy_ext()
198 err = __alx_read_phy_ext(hw, dev, reg, pdata); alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); alx_read_phy_ext()
204 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) alx_write_phy_ext() argument
208 spin_lock(&hw->mdio_lock); alx_write_phy_ext()
209 err = __alx_write_phy_ext(hw, dev, reg, data); alx_write_phy_ext()
210 spin_unlock(&hw->mdio_lock); alx_write_phy_ext()
215 static int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) alx_read_phy_dbg() argument
219 spin_lock(&hw->mdio_lock); alx_read_phy_dbg()
220 err = __alx_read_phy_dbg(hw, reg, pdata); alx_read_phy_dbg()
221 spin_unlock(&hw->mdio_lock); alx_read_phy_dbg()
226 static int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) alx_write_phy_dbg() argument
230 spin_lock(&hw->mdio_lock); alx_write_phy_dbg()
231 err = __alx_write_phy_dbg(hw, reg, data); alx_write_phy_dbg()
232 spin_unlock(&hw->mdio_lock); alx_write_phy_dbg()
237 static u16 alx_get_phy_config(struct alx_hw *hw) alx_get_phy_config() argument
242 val = alx_read_mem32(hw, ALX_PHY_CTRL); alx_get_phy_config()
247 val = alx_read_mem32(hw, ALX_DRV); alx_get_phy_config()
252 alx_read_phy_reg(hw, ALX_MII_DBG_ADDR, &phy_val); alx_get_phy_config()
259 static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val) alx_wait_reg() argument
265 read = alx_read_mem32(hw, reg); alx_wait_reg()
277 static bool alx_read_macaddr(struct alx_hw *hw, u8 *addr) alx_read_macaddr() argument
281 mac0 = alx_read_mem32(hw, ALX_STAD0); alx_read_macaddr()
282 mac1 = alx_read_mem32(hw, ALX_STAD1); alx_read_macaddr()
291 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr) alx_get_perm_macaddr() argument
296 if (alx_read_macaddr(hw, addr)) alx_get_perm_macaddr()
300 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val)) alx_get_perm_macaddr()
302 alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START); alx_get_perm_macaddr()
303 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_START, NULL)) alx_get_perm_macaddr()
305 if (alx_read_macaddr(hw, addr)) alx_get_perm_macaddr()
309 val = alx_read_mem32(hw, ALX_EFLD); alx_get_perm_macaddr()
311 if (!alx_wait_reg(hw, ALX_EFLD, alx_get_perm_macaddr()
314 alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START); alx_get_perm_macaddr()
315 if (!alx_wait_reg(hw, ALX_EFLD, ALX_EFLD_START, NULL)) alx_get_perm_macaddr()
317 if (alx_read_macaddr(hw, addr)) alx_get_perm_macaddr()
324 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr) alx_set_macaddr() argument
330 alx_write_mem32(hw, ALX_STAD0, val); alx_set_macaddr()
332 alx_write_mem32(hw, ALX_STAD1, val); alx_set_macaddr()
335 static void alx_reset_osc(struct alx_hw *hw, u8 rev) alx_reset_osc() argument
339 /* clear Internal OSC settings, switching OSC by hw itself */ alx_reset_osc()
340 val = alx_read_mem32(hw, ALX_MISC3); alx_reset_osc()
341 alx_write_mem32(hw, ALX_MISC3, alx_reset_osc()
348 val = alx_read_mem32(hw, ALX_MISC); alx_reset_osc()
356 alx_write_mem32(hw, ALX_MISC, val); alx_reset_osc()
357 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); alx_reset_osc()
358 /* hw will automatically dis OSC after cab. */ alx_reset_osc()
359 val2 = alx_read_mem32(hw, ALX_MSIC2); alx_reset_osc()
361 alx_write_mem32(hw, ALX_MSIC2, val2); alx_reset_osc()
362 alx_write_mem32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START); alx_reset_osc()
369 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN); alx_reset_osc()
370 alx_write_mem32(hw, ALX_MISC, val); alx_reset_osc()
376 static int alx_stop_mac(struct alx_hw *hw) alx_stop_mac() argument
381 rxq = alx_read_mem32(hw, ALX_RXQ0); alx_stop_mac()
382 alx_write_mem32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN); alx_stop_mac()
383 txq = alx_read_mem32(hw, ALX_TXQ0); alx_stop_mac()
384 alx_write_mem32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN); alx_stop_mac()
388 hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN); alx_stop_mac()
389 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_stop_mac()
392 val = alx_read_mem32(hw, ALX_MAC_STS); alx_stop_mac()
401 int alx_reset_mac(struct alx_hw *hw) alx_reset_mac() argument
409 rev = alx_hw_revision(hw); alx_reset_mac()
410 a_cr = alx_is_rev_a(rev) && alx_hw_with_cr(hw); alx_reset_mac()
413 alx_write_mem32(hw, ALX_MSIX_MASK, 0xFFFFFFFF); alx_reset_mac()
414 alx_write_mem32(hw, ALX_IMR, 0); alx_reset_mac()
415 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); alx_reset_mac()
417 ret = alx_stop_mac(hw); alx_reset_mac()
422 alx_write_mem32(hw, ALX_RFD_PIDX, 1); alx_reset_mac()
426 pmctrl = alx_read_mem32(hw, ALX_PMCTRL); alx_reset_mac()
428 alx_write_mem32(hw, ALX_PMCTRL, alx_reset_mac()
434 val = alx_read_mem32(hw, ALX_MASTER); alx_reset_mac()
435 alx_write_mem32(hw, ALX_MASTER, alx_reset_mac()
441 val = alx_read_mem32(hw, ALX_RFD_PIDX); alx_reset_mac()
447 val = alx_read_mem32(hw, ALX_MASTER); alx_reset_mac()
457 alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS); alx_reset_mac()
460 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); alx_reset_mac()
463 alx_reset_osc(hw, rev); alx_reset_mac()
465 /* clear Internal OSC settings, switching OSC by hw itself, alx_reset_mac()
468 val = alx_read_mem32(hw, ALX_MISC3); alx_reset_mac()
469 alx_write_mem32(hw, ALX_MISC3, alx_reset_mac()
472 val = alx_read_mem32(hw, ALX_MISC); alx_reset_mac()
476 alx_write_mem32(hw, ALX_MISC, val); alx_reset_mac()
480 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_reset_mac()
482 val = alx_read_mem32(hw, ALX_SERDES); alx_reset_mac()
483 alx_write_mem32(hw, ALX_SERDES, alx_reset_mac()
490 void alx_reset_phy(struct alx_hw *hw) alx_reset_phy() argument
497 val = alx_read_mem32(hw, ALX_PHY_CTRL); alx_reset_phy()
504 alx_write_mem32(hw, ALX_PHY_CTRL, val); alx_reset_phy()
506 alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT); alx_reset_phy()
512 alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF); alx_reset_phy()
513 alx_write_phy_dbg(hw, ALX_MIIDBG_SYSMODCTRL, alx_reset_phy()
515 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS, alx_reset_phy()
519 val = alx_read_mem32(hw, ALX_LPI_CTRL); alx_reset_phy()
520 alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN); alx_reset_phy()
521 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_LOCAL_EEEADV, 0); alx_reset_phy()
524 alx_write_phy_dbg(hw, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF); alx_reset_phy()
525 alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF); alx_reset_phy()
526 alx_write_phy_dbg(hw, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF); alx_reset_phy()
527 alx_write_phy_dbg(hw, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF); alx_reset_phy()
528 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val); alx_reset_phy()
529 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, alx_reset_phy()
532 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78, alx_reset_phy()
534 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10, alx_reset_phy()
537 if (hw->lnk_patch) { alx_reset_phy()
539 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3, alx_reset_phy()
541 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3, alx_reset_phy()
544 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val); alx_reset_phy()
545 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, alx_reset_phy()
548 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5, alx_reset_phy()
550 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5, alx_reset_phy()
555 alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP | ALX_IER_LINK_DOWN); alx_reset_phy()
560 void alx_reset_pcie(struct alx_hw *hw) alx_reset_pcie() argument
562 u8 rev = alx_hw_revision(hw); alx_reset_pcie()
567 pci_read_config_word(hw->pdev, PCI_COMMAND, &val16); alx_reset_pcie()
570 pci_write_config_word(hw->pdev, PCI_COMMAND, val16); alx_reset_pcie()
574 val = alx_read_mem32(hw, ALX_WOL0); alx_reset_pcie()
575 alx_write_mem32(hw, ALX_WOL0, 0); alx_reset_pcie()
577 val = alx_read_mem32(hw, ALX_PDLL_TRNS1); alx_reset_pcie()
578 alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN); alx_reset_pcie()
581 val = alx_read_mem32(hw, ALX_UE_SVRT); alx_reset_pcie()
583 alx_write_mem32(hw, ALX_UE_SVRT, val); alx_reset_pcie()
586 val = alx_read_mem32(hw, ALX_MASTER); alx_reset_pcie()
587 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) { alx_reset_pcie()
590 alx_write_mem32(hw, ALX_MASTER, alx_reset_pcie()
596 alx_write_mem32(hw, ALX_MASTER, alx_reset_pcie()
602 alx_enable_aspm(hw, true, true); alx_reset_pcie()
607 void alx_start_mac(struct alx_hw *hw) alx_start_mac() argument
611 rxq = alx_read_mem32(hw, ALX_RXQ0); alx_start_mac()
612 alx_write_mem32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN); alx_start_mac()
613 txq = alx_read_mem32(hw, ALX_TXQ0); alx_start_mac()
614 alx_write_mem32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN); alx_start_mac()
616 mac = hw->rx_ctrl; alx_start_mac()
617 if (hw->duplex == DUPLEX_FULL) alx_start_mac()
622 hw->link_speed == SPEED_1000 ? ALX_MAC_CTRL_SPEED_1000 : alx_start_mac()
625 hw->rx_ctrl = mac; alx_start_mac()
626 alx_write_mem32(hw, ALX_MAC_CTRL, mac); alx_start_mac()
629 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc) alx_cfg_mac_flowcontrol() argument
632 hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN; alx_cfg_mac_flowcontrol()
634 hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN; alx_cfg_mac_flowcontrol()
637 hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN; alx_cfg_mac_flowcontrol()
639 hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN; alx_cfg_mac_flowcontrol()
641 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_cfg_mac_flowcontrol()
644 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en) alx_enable_aspm() argument
647 u8 rev = alx_hw_revision(hw); alx_enable_aspm()
649 pmctrl = alx_read_mem32(hw, ALX_PMCTRL); alx_enable_aspm()
668 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) alx_enable_aspm()
676 alx_write_mem32(hw, ALX_PMCTRL, pmctrl); alx_enable_aspm()
680 static u32 ethadv_to_hw_cfg(struct alx_hw *hw, u32 ethadv_cfg) ethadv_to_hw_cfg() argument
722 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl) alx_setup_speed_duplex() argument
728 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0); alx_setup_speed_duplex()
729 val = alx_read_mem32(hw, ALX_DRV); alx_setup_speed_duplex()
746 if (alx_hw_giga(hw)) alx_setup_speed_duplex()
751 if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) || alx_setup_speed_duplex()
752 alx_write_phy_reg(hw, MII_CTRL1000, giga) || alx_setup_speed_duplex()
753 alx_write_phy_reg(hw, MII_BMCR, cr)) alx_setup_speed_duplex()
764 err = alx_write_phy_reg(hw, MII_BMCR, cr); alx_setup_speed_duplex()
768 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED); alx_setup_speed_duplex()
769 val |= ethadv_to_hw_cfg(hw, ethadv); alx_setup_speed_duplex()
772 alx_write_mem32(hw, ALX_DRV, val); alx_setup_speed_duplex()
778 void alx_post_phy_link(struct alx_hw *hw) alx_post_phy_link() argument
781 u8 revid = alx_hw_revision(hw); alx_post_phy_link()
788 if (hw->link_speed != SPEED_UNKNOWN) { alx_post_phy_link()
789 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6, alx_post_phy_link()
792 alx_read_phy_dbg(hw, ALX_MIIDBG_AGC, &phy_val); alx_post_phy_link()
795 if ((hw->link_speed == SPEED_1000 && alx_post_phy_link()
798 (hw->link_speed == SPEED_100 && alx_post_phy_link()
801 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT, alx_post_phy_link()
803 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, alx_post_phy_link()
805 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, alx_post_phy_link()
808 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT, alx_post_phy_link()
810 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, alx_post_phy_link()
812 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, alx_post_phy_link()
817 if (adj_th && hw->lnk_patch) { alx_post_phy_link()
818 if (hw->link_speed == SPEED_100) { alx_post_phy_link()
819 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB, alx_post_phy_link()
821 } else if (hw->link_speed == SPEED_1000) { alx_post_phy_link()
826 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, alx_post_phy_link()
830 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, alx_post_phy_link()
835 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, alx_post_phy_link()
837 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE, alx_post_phy_link()
840 if (adj_th && hw->lnk_patch) { alx_post_phy_link()
841 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB, alx_post_phy_link()
843 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, &phy_val); alx_post_phy_link()
846 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, phy_val); alx_post_phy_link()
851 bool alx_phy_configured(struct alx_hw *hw) alx_phy_configured() argument
855 cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg); alx_phy_configured()
857 hw_cfg = alx_get_phy_config(hw); alx_phy_configured()
865 int alx_read_phy_link(struct alx_hw *hw) alx_read_phy_link() argument
867 struct pci_dev *pdev = hw->pdev; alx_read_phy_link()
871 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr); alx_read_phy_link()
875 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr); alx_read_phy_link()
880 hw->link_speed = SPEED_UNKNOWN; alx_read_phy_link()
881 hw->duplex = DUPLEX_UNKNOWN; alx_read_phy_link()
886 err = alx_read_phy_reg(hw, ALX_MII_GIGA_PSSR, &giga); alx_read_phy_link()
895 hw->link_speed = SPEED_1000; alx_read_phy_link()
898 hw->link_speed = SPEED_100; alx_read_phy_link()
901 hw->link_speed = SPEED_10; alx_read_phy_link()
907 hw->duplex = (giga & ALX_GIGA_PSSR_DPLX) ? DUPLEX_FULL : DUPLEX_HALF; alx_read_phy_link()
915 int alx_clear_phy_intr(struct alx_hw *hw) alx_clear_phy_intr() argument
920 return alx_read_phy_reg(hw, ALX_MII_ISR, &isr); alx_clear_phy_intr()
923 void alx_disable_rss(struct alx_hw *hw) alx_disable_rss() argument
925 u32 ctrl = alx_read_mem32(hw, ALX_RXQ0); alx_disable_rss()
928 alx_write_mem32(hw, ALX_RXQ0, ctrl); alx_disable_rss()
931 void alx_configure_basic(struct alx_hw *hw) alx_configure_basic() argument
935 u8 chip_rev = alx_hw_revision(hw); alx_configure_basic()
937 alx_set_macaddr(hw, hw->mac_addr); alx_configure_basic()
939 alx_write_mem32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL); alx_configure_basic()
943 alx_write_mem32(hw, ALX_IDLE_DECISN_TIMER, alx_configure_basic()
946 alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL); alx_configure_basic()
948 val = alx_read_mem32(hw, ALX_MASTER); alx_configure_basic()
952 alx_write_mem32(hw, ALX_MASTER, val); alx_configure_basic()
953 alx_write_mem32(hw, ALX_IRQ_MODU_TIMER, alx_configure_basic()
954 (hw->imt >> 1) << ALX_IRQ_MODU_TIMER1_SHIFT); alx_configure_basic()
956 alx_write_mem32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO); alx_configure_basic()
958 alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd); alx_configure_basic()
959 alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt); alx_configure_basic()
961 raw_mtu = hw->mtu + ETH_HLEN; alx_configure_basic()
962 alx_write_mem32(hw, ALX_MTU, raw_mtu + 8); alx_configure_basic()
964 hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE; alx_configure_basic()
970 alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN); alx_configure_basic()
972 max_payload = pcie_get_readrq(hw->pdev) >> 8; alx_configure_basic()
978 pcie_set_readrq(hw->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN); alx_configure_basic()
984 alx_write_mem32(hw, ALX_TXQ0, val); alx_configure_basic()
989 alx_write_mem32(hw, ALX_HQTPD, val); alx_configure_basic()
992 val = alx_read_mem32(hw, ALX_SRAM5); alx_configure_basic()
1001 alx_write_mem32(hw, ALX_RXQ2, alx_configure_basic()
1010 if (alx_hw_giga(hw)) alx_configure_basic()
1014 alx_write_mem32(hw, ALX_RXQ0, val); alx_configure_basic()
1016 val = alx_read_mem32(hw, ALX_DMA); alx_configure_basic()
1022 (hw->dma_chnl - 1) << ALX_DMA_RCHNL_SEL_SHIFT; alx_configure_basic()
1023 alx_write_mem32(hw, ALX_DMA, val); alx_configure_basic()
1031 alx_write_mem32(hw, ALX_WRR, val); alx_configure_basic()
1034 bool alx_get_phy_info(struct alx_hw *hw) alx_get_phy_info() argument
1038 if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) || alx_get_phy_info()
1039 alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1])) alx_get_phy_info()
1046 if (alx_read_phy_ext(hw, 3, MDIO_DEVS1, &devs1) || alx_get_phy_info()
1047 alx_read_phy_ext(hw, 3, MDIO_DEVS2, &devs2)) alx_get_phy_info()
1049 hw->mdio.mmds = devs1 | devs2 << 16; alx_get_phy_info()
1054 void alx_update_hw_stats(struct alx_hw *hw) alx_update_hw_stats() argument
1057 hw->stats.rx_ok += alx_read_mem32(hw, ALX_MIB_RX_OK); alx_update_hw_stats()
1058 hw->stats.rx_bcast += alx_read_mem32(hw, ALX_MIB_RX_BCAST); alx_update_hw_stats()
1059 hw->stats.rx_mcast += alx_read_mem32(hw, ALX_MIB_RX_MCAST); alx_update_hw_stats()
1060 hw->stats.rx_pause += alx_read_mem32(hw, ALX_MIB_RX_PAUSE); alx_update_hw_stats()
1061 hw->stats.rx_ctrl += alx_read_mem32(hw, ALX_MIB_RX_CTRL); alx_update_hw_stats()
1062 hw->stats.rx_fcs_err += alx_read_mem32(hw, ALX_MIB_RX_FCS_ERR); alx_update_hw_stats()
1063 hw->stats.rx_len_err += alx_read_mem32(hw, ALX_MIB_RX_LEN_ERR); alx_update_hw_stats()
1064 hw->stats.rx_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BYTE_CNT); alx_update_hw_stats()
1065 hw->stats.rx_runt += alx_read_mem32(hw, ALX_MIB_RX_RUNT); alx_update_hw_stats()
1066 hw->stats.rx_frag += alx_read_mem32(hw, ALX_MIB_RX_FRAG); alx_update_hw_stats()
1067 hw->stats.rx_sz_64B += alx_read_mem32(hw, ALX_MIB_RX_SZ_64B); alx_update_hw_stats()
1068 hw->stats.rx_sz_127B += alx_read_mem32(hw, ALX_MIB_RX_SZ_127B); alx_update_hw_stats()
1069 hw->stats.rx_sz_255B += alx_read_mem32(hw, ALX_MIB_RX_SZ_255B); alx_update_hw_stats()
1070 hw->stats.rx_sz_511B += alx_read_mem32(hw, ALX_MIB_RX_SZ_511B); alx_update_hw_stats()
1071 hw->stats.rx_sz_1023B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1023B); alx_update_hw_stats()
1072 hw->stats.rx_sz_1518B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1518B); alx_update_hw_stats()
1073 hw->stats.rx_sz_max += alx_read_mem32(hw, ALX_MIB_RX_SZ_MAX); alx_update_hw_stats()
1074 hw->stats.rx_ov_sz += alx_read_mem32(hw, ALX_MIB_RX_OV_SZ); alx_update_hw_stats()
1075 hw->stats.rx_ov_rxf += alx_read_mem32(hw, ALX_MIB_RX_OV_RXF); alx_update_hw_stats()
1076 hw->stats.rx_ov_rrd += alx_read_mem32(hw, ALX_MIB_RX_OV_RRD); alx_update_hw_stats()
1077 hw->stats.rx_align_err += alx_read_mem32(hw, ALX_MIB_RX_ALIGN_ERR); alx_update_hw_stats()
1078 hw->stats.rx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BCCNT); alx_update_hw_stats()
1079 hw->stats.rx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_MCCNT); alx_update_hw_stats()
1080 hw->stats.rx_err_addr += alx_read_mem32(hw, ALX_MIB_RX_ERRADDR); alx_update_hw_stats()
1083 hw->stats.tx_ok += alx_read_mem32(hw, ALX_MIB_TX_OK); alx_update_hw_stats()
1084 hw->stats.tx_bcast += alx_read_mem32(hw, ALX_MIB_TX_BCAST); alx_update_hw_stats()
1085 hw->stats.tx_mcast += alx_read_mem32(hw, ALX_MIB_TX_MCAST); alx_update_hw_stats()
1086 hw->stats.tx_pause += alx_read_mem32(hw, ALX_MIB_TX_PAUSE); alx_update_hw_stats()
1087 hw->stats.tx_exc_defer += alx_read_mem32(hw, ALX_MIB_TX_EXC_DEFER); alx_update_hw_stats()
1088 hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL); alx_update_hw_stats()
1089 hw->stats.tx_defer += alx_read_mem32(hw, ALX_MIB_TX_DEFER); alx_update_hw_stats()
1090 hw->stats.tx_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BYTE_CNT); alx_update_hw_stats()
1091 hw->stats.tx_sz_64B += alx_read_mem32(hw, ALX_MIB_TX_SZ_64B); alx_update_hw_stats()
1092 hw->stats.tx_sz_127B += alx_read_mem32(hw, ALX_MIB_TX_SZ_127B); alx_update_hw_stats()
1093 hw->stats.tx_sz_255B += alx_read_mem32(hw, ALX_MIB_TX_SZ_255B); alx_update_hw_stats()
1094 hw->stats.tx_sz_511B += alx_read_mem32(hw, ALX_MIB_TX_SZ_511B); alx_update_hw_stats()
1095 hw->stats.tx_sz_1023B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1023B); alx_update_hw_stats()
1096 hw->stats.tx_sz_1518B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1518B); alx_update_hw_stats()
1097 hw->stats.tx_sz_max += alx_read_mem32(hw, ALX_MIB_TX_SZ_MAX); alx_update_hw_stats()
1098 hw->stats.tx_single_col += alx_read_mem32(hw, ALX_MIB_TX_SINGLE_COL); alx_update_hw_stats()
1099 hw->stats.tx_multi_col += alx_read_mem32(hw, ALX_MIB_TX_MULTI_COL); alx_update_hw_stats()
1100 hw->stats.tx_late_col += alx_read_mem32(hw, ALX_MIB_TX_LATE_COL); alx_update_hw_stats()
1101 hw->stats.tx_abort_col += alx_read_mem32(hw, ALX_MIB_TX_ABORT_COL); alx_update_hw_stats()
1102 hw->stats.tx_underrun += alx_read_mem32(hw, ALX_MIB_TX_UNDERRUN); alx_update_hw_stats()
1103 hw->stats.tx_trd_eop += alx_read_mem32(hw, ALX_MIB_TX_TRD_EOP); alx_update_hw_stats()
1104 hw->stats.tx_len_err += alx_read_mem32(hw, ALX_MIB_TX_LEN_ERR); alx_update_hw_stats()
1105 hw->stats.tx_trunc += alx_read_mem32(hw, ALX_MIB_TX_TRUNC); alx_update_hw_stats()
1106 hw->stats.tx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BCCNT); alx_update_hw_stats()
1107 hw->stats.tx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_MCCNT); alx_update_hw_stats()
1109 hw->stats.update += alx_read_mem32(hw, ALX_MIB_UPDATE); alx_update_hw_stats()
H A Dmain.c49 #include "hw.h"
60 dma_unmap_single(&alx->hw.pdev->dev, alx_free_txbuf()
92 dma = dma_map_single(&alx->hw.pdev->dev, alx_refill_rx_ring()
95 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) { alx_refill_rx_ring()
124 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur); alx_refill_rx_ring()
147 hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX); alx_clean_tx_irq()
211 dma_unmap_single(&alx->hw.pdev->dev, alx_clean_rx_irq()
268 struct alx_hw *hw = &alx->hw; alx_poll() local
284 alx_write_mem32(hw, ALX_IMR, alx->int_mask); alx_poll()
287 alx_post_write(hw); alx_poll()
294 struct alx_hw *hw = &alx->hw; alx_intr_handle() local
300 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS); alx_intr_handle()
304 netif_warn(alx, hw, alx->dev, alx_intr_handle()
331 alx_write_mem32(hw, ALX_IMR, alx->int_mask); alx_intr_handle()
333 alx_write_mem32(hw, ALX_ISR, 0); alx_intr_handle()
344 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR)); alx_intr_msi()
350 struct alx_hw *hw = &alx->hw; alx_intr_legacy() local
353 intr = alx_read_mem32(hw, ALX_ISR); alx_intr_legacy()
363 struct alx_hw *hw = &alx->hw; alx_init_ring_ptrs() local
369 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi); alx_init_ring_ptrs()
370 alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma); alx_init_ring_ptrs()
371 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz); alx_init_ring_ptrs()
372 alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma); alx_init_ring_ptrs()
373 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz); alx_init_ring_ptrs()
374 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size); alx_init_ring_ptrs()
378 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi); alx_init_ring_ptrs()
379 alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma); alx_init_ring_ptrs()
380 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz); alx_init_ring_ptrs()
383 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR); alx_init_ring_ptrs()
417 dma_unmap_single(&alx->hw.pdev->dev, alx_free_rxring_buf()
451 static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash) alx_add_mc_addr() argument
465 struct alx_hw *hw = &alx->hw; __alx_set_rx_mode() local
471 alx_add_mc_addr(hw, ha->addr, mc_hash); __alx_set_rx_mode()
473 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]); __alx_set_rx_mode()
474 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]); __alx_set_rx_mode()
477 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN); __alx_set_rx_mode()
479 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN; __alx_set_rx_mode()
481 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN; __alx_set_rx_mode()
483 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); __alx_set_rx_mode()
494 struct alx_hw *hw = &alx->hw; alx_set_mac_address() local
504 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len); alx_set_mac_address()
505 alx_set_macaddr(hw, hw->mac_addr); alx_set_mac_address()
533 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev, alx_alloc_descriptors()
596 dma_free_coherent(&alx->hw.pdev->dev, alx_free_rings()
604 struct alx_hw *hw = &alx->hw; alx_config_vector_mapping() local
606 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0); alx_config_vector_mapping()
607 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0); alx_config_vector_mapping()
608 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0); alx_config_vector_mapping()
613 struct alx_hw *hw = &alx->hw; alx_irq_enable() local
616 alx_write_mem32(hw, ALX_ISR, 0); alx_irq_enable()
617 alx_write_mem32(hw, ALX_IMR, alx->int_mask); alx_irq_enable()
618 alx_post_write(hw); alx_irq_enable()
623 struct alx_hw *hw = &alx->hw; alx_irq_disable() local
625 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); alx_irq_disable()
626 alx_write_mem32(hw, ALX_IMR, 0); alx_irq_disable()
627 alx_post_write(hw); alx_irq_disable()
629 synchronize_irq(alx->hw.pdev->irq); alx_irq_disable()
634 struct pci_dev *pdev = alx->hw.pdev; alx_request_irq()
635 struct alx_hw *hw = &alx->hw; alx_request_irq() local
639 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT; alx_request_irq()
641 if (!pci_enable_msi(alx->hw.pdev)) { alx_request_irq()
644 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, alx_request_irq()
651 pci_disable_msi(alx->hw.pdev); alx_request_irq()
654 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0); alx_request_irq()
665 struct pci_dev *pdev = alx->hw.pdev; alx_free_irq()
670 pci_disable_msi(alx->hw.pdev); alx_free_irq()
677 struct alx_hw *hw = &alx->hw; alx_identify_hw() local
678 int rev = alx_hw_revision(hw); alx_identify_hw()
683 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2; alx_identify_hw()
690 struct pci_dev *pdev = alx->hw.pdev; alx_init_sw()
691 struct alx_hw *hw = &alx->hw; alx_init_sw() local
700 alx->hw.lnk_patch = alx_init_sw()
706 hw->smb_timer = 400; alx_init_sw()
707 hw->mtu = alx->dev->mtu; alx_init_sw()
708 alx->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8); alx_init_sw()
711 hw->imt = 200; alx_init_sw()
713 hw->dma_chnl = hw->max_dma_chnl; alx_init_sw()
714 hw->ith_tpd = alx->tx_ringsz / 3; alx_init_sw()
715 hw->link_speed = SPEED_UNKNOWN; alx_init_sw()
716 hw->duplex = DUPLEX_UNKNOWN; alx_init_sw()
717 hw->adv_cfg = ADVERTISED_Autoneg | alx_init_sw()
723 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX; alx_init_sw()
725 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN | alx_init_sw()
759 struct alx_hw *hw = &alx->hw; alx_halt() local
762 hw->link_speed = SPEED_UNKNOWN; alx_halt()
763 hw->duplex = DUPLEX_UNKNOWN; alx_halt()
765 alx_reset_mac(hw); alx_halt()
768 alx_enable_aspm(hw, false, false); alx_halt()
775 struct alx_hw *hw = &alx->hw; alx_configure() local
777 alx_configure_basic(hw); alx_configure()
778 alx_disable_rss(hw); alx_configure()
781 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); alx_configure()
791 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); alx_activate()
819 alx->hw.mtu = mtu; alx_change_mtu()
853 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); __alx_open()
875 static const char *alx_speed_desc(struct alx_hw *hw) alx_speed_desc() argument
877 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) { alx_speed_desc()
895 struct alx_hw *hw = &alx->hw; alx_check_link() local
904 alx_clear_phy_intr(hw); alx_check_link()
906 old_speed = hw->link_speed; alx_check_link()
907 old_duplex = hw->duplex; alx_check_link()
908 err = alx_read_phy_link(hw); alx_check_link()
914 alx_write_mem32(hw, ALX_IMR, alx->int_mask); alx_check_link()
917 if (old_speed == hw->link_speed) alx_check_link()
920 if (hw->link_speed != SPEED_UNKNOWN) { alx_check_link()
922 "NIC Up: %s\n", alx_speed_desc(hw)); alx_check_link()
923 alx_post_phy_link(hw); alx_check_link()
924 alx_enable_aspm(hw, true, true); alx_check_link()
925 alx_start_mac(hw); alx_check_link()
933 err = alx_reset_mac(hw); alx_check_link()
943 alx_enable_aspm(hw, false, true); alx_check_link()
944 alx_post_phy_link(hw); alx_check_link()
1015 dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen, alx_map_tx_skb()
1017 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) alx_map_tx_skb()
1038 dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0, alx_map_tx_skb()
1040 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) alx_map_tx_skb()
1094 alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx); alx_start_xmit()
1117 struct alx_hw *hw = &alx->hw; alx_mdio_read() local
1121 if (prtad != hw->mdio.prtad) alx_mdio_read()
1125 err = alx_read_phy_reg(hw, addr, &val); alx_mdio_read()
1127 err = alx_read_phy_ext(hw, devad, addr, &val); alx_mdio_read()
1138 struct alx_hw *hw = &alx->hw; alx_mdio_write() local
1140 if (prtad != hw->mdio.prtad) alx_mdio_write()
1144 return alx_write_phy_reg(hw, addr, val); alx_mdio_write()
1146 return alx_write_phy_ext(hw, devad, addr, val); alx_mdio_write()
1156 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd); alx_ioctl()
1175 struct alx_hw_stats *hw_stats = &alx->hw.stats; alx_get_stats64()
1179 alx_update_hw_stats(&alx->hw); alx_get_stats64()
1241 struct alx_hw *hw; alx_probe() local
1289 spin_lock_init(&alx->hw.mdio_lock); alx_probe()
1293 alx->hw.pdev = pdev; alx_probe()
1296 hw = &alx->hw; alx_probe()
1299 hw->hw_addr = pci_ioremap_bar(pdev, 0); alx_probe()
1300 if (!hw->hw_addr) { alx_probe()
1320 alx_reset_pcie(hw); alx_probe()
1322 phy_configured = alx_phy_configured(hw); alx_probe()
1325 alx_reset_phy(hw); alx_probe()
1327 err = alx_reset_mac(hw); alx_probe()
1335 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl); alx_probe()
1346 if (alx_get_perm_macaddr(hw, hw->perm_addr)) { alx_probe()
1350 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len); alx_probe()
1353 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN); alx_probe()
1354 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN); alx_probe()
1355 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN); alx_probe()
1357 hw->mdio.prtad = 0; alx_probe()
1358 hw->mdio.mmds = 0; alx_probe()
1359 hw->mdio.dev = netdev; alx_probe()
1360 hw->mdio.mode_support = MDIO_SUPPORTS_C45 | alx_probe()
1363 hw->mdio.mdio_read = alx_mdio_read; alx_probe()
1364 hw->mdio.mdio_write = alx_mdio_write; alx_probe()
1366 if (!alx_get_phy_info(hw)) { alx_probe()
1389 iounmap(hw->hw_addr); alx_probe()
1402 struct alx_hw *hw = &alx->hw; alx_remove() local
1408 alx_set_macaddr(hw, hw->perm_addr); alx_remove()
1411 iounmap(hw->hw_addr); alx_remove()
1438 struct alx_hw *hw = &alx->hw; alx_resume() local
1440 alx_reset_phy(hw); alx_resume()
1484 struct alx_hw *hw = &alx->hw; alx_pci_error_slot_reset() local
1498 alx_reset_pcie(hw); alx_pci_error_slot_reset()
1499 if (!alx_reset_mac(hw)) alx_pci_error_slot_reset()
H A Dethtool.c47 #include "hw.h"
51 * See hw.h
109 static u32 alx_get_supported_speeds(struct alx_hw *hw) alx_get_supported_speeds() argument
116 if (alx_hw_giga(hw)) alx_get_supported_speeds()
131 struct alx_hw *hw = &alx->hw; alx_get_settings() local
137 if (alx_hw_giga(hw)) alx_get_settings()
139 ecmd->supported |= alx_get_supported_speeds(hw); alx_get_settings()
142 if (hw->adv_cfg & ADVERTISED_Autoneg) alx_get_settings()
143 ecmd->advertising |= hw->adv_cfg; alx_get_settings()
148 if (hw->adv_cfg & ADVERTISED_Autoneg) alx_get_settings()
154 if (hw->flowctrl & ALX_FC_ANEG && hw->adv_cfg & ADVERTISED_Autoneg) { alx_get_settings()
155 if (hw->flowctrl & ALX_FC_RX) { alx_get_settings()
158 if (!(hw->flowctrl & ALX_FC_TX)) alx_get_settings()
160 } else if (hw->flowctrl & ALX_FC_TX) { alx_get_settings()
165 ethtool_cmd_speed_set(ecmd, hw->link_speed); alx_get_settings()
166 ecmd->duplex = hw->duplex; alx_get_settings()
174 struct alx_hw *hw = &alx->hw; alx_set_settings() local
180 if (ecmd->advertising & ~alx_get_supported_speeds(hw)) alx_set_settings()
191 hw->adv_cfg = adv_cfg; alx_set_settings()
192 return alx_setup_speed_duplex(hw, adv_cfg, hw->flowctrl); alx_set_settings()
199 struct alx_hw *hw = &alx->hw; alx_get_pauseparam() local
201 pause->autoneg = !!(hw->flowctrl & ALX_FC_ANEG && alx_get_pauseparam()
202 hw->adv_cfg & ADVERTISED_Autoneg); alx_get_pauseparam()
203 pause->tx_pause = !!(hw->flowctrl & ALX_FC_TX); alx_get_pauseparam()
204 pause->rx_pause = !!(hw->flowctrl & ALX_FC_RX); alx_get_pauseparam()
212 struct alx_hw *hw = &alx->hw; alx_set_pauseparam() local
227 if (hw->adv_cfg & ADVERTISED_Autoneg) { alx_set_pauseparam()
228 if (!((fc ^ hw->flowctrl) & ALX_FC_ANEG)) alx_set_pauseparam()
230 if (fc & hw->flowctrl & ALX_FC_ANEG && alx_set_pauseparam()
231 (fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX)) alx_set_pauseparam()
236 err = alx_setup_speed_duplex(hw, hw->adv_cfg, fc); alx_set_pauseparam()
242 if ((fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX)) alx_set_pauseparam()
243 alx_cfg_mac_flowcontrol(hw, fc); alx_set_pauseparam()
245 hw->flowctrl = fc; alx_set_pauseparam()
268 struct alx_hw *hw = &alx->hw; alx_get_ethtool_stats() local
272 alx_update_hw_stats(hw); alx_get_ethtool_stats()
273 BUILD_BUG_ON(sizeof(hw->stats) - offsetof(struct alx_hw_stats, rx_ok) < alx_get_ethtool_stats()
275 memcpy(data, &hw->stats.rx_ok, ALX_NUM_STATS * sizeof(u64)); alx_get_ethtool_stats()
/linux-4.4.14/drivers/clk/sirf/
H A Dclk-atlas6.c24 .hw = {
32 .hw = {
40 .hw = {
55 .hw = {
72 &clk_pll1.hw,
73 &clk_pll2.hw,
74 &clk_pll3.hw,
75 &clk_mem.hw,
76 &clk_sys.hw,
77 &clk_security.hw,
78 &clk_dsp.hw,
79 &clk_gps.hw,
80 &clk_mf.hw,
81 &clk_io.hw,
82 &clk_cpu.hw,
83 &clk_uart0.hw,
84 &clk_uart1.hw,
85 &clk_uart2.hw,
86 &clk_tsc.hw,
87 &clk_i2c0.hw,
88 &clk_i2c1.hw,
89 &clk_spi0.hw,
90 &clk_spi1.hw,
91 &clk_pwmc.hw,
92 &clk_efuse.hw,
93 &clk_pulse.hw,
94 &clk_dmac0.hw,
95 &clk_dmac1.hw,
96 &clk_nand.hw,
97 &clk_audio.hw,
98 &clk_usp0.hw,
99 &clk_usp1.hw,
100 &clk_usp2.hw,
101 &clk_vip.hw,
102 &clk_gfx.hw,
103 &clk_gfx2d.hw,
104 &clk_lcd.hw,
105 &clk_vpp.hw,
106 &clk_mmc01.hw,
107 &clk_mmc23.hw,
108 &clk_mmc45.hw,
110 &clk_usb0.hw,
111 &clk_usb1.hw,
112 &clk_cphif.hw,
H A Dclk-prima2.c24 .hw = {
32 .hw = {
40 .hw = {
54 .hw = {
71 &clk_pll1.hw,
72 &clk_pll2.hw,
73 &clk_pll3.hw,
74 &clk_mem.hw,
75 &clk_sys.hw,
76 &clk_security.hw,
77 &clk_dsp.hw,
78 &clk_gps.hw,
79 &clk_mf.hw,
80 &clk_io.hw,
81 &clk_cpu.hw,
82 &clk_uart0.hw,
83 &clk_uart1.hw,
84 &clk_uart2.hw,
85 &clk_tsc.hw,
86 &clk_i2c0.hw,
87 &clk_i2c1.hw,
88 &clk_spi0.hw,
89 &clk_spi1.hw,
90 &clk_pwmc.hw,
91 &clk_efuse.hw,
92 &clk_pulse.hw,
93 &clk_dmac0.hw,
94 &clk_dmac1.hw,
95 &clk_nand.hw,
96 &clk_audio.hw,
97 &clk_usp0.hw,
98 &clk_usp1.hw,
99 &clk_usp2.hw,
100 &clk_vip.hw,
101 &clk_gfx.hw,
102 &clk_mm.hw,
103 &clk_lcd.hw,
104 &clk_vpp.hw,
105 &clk_mmc01.hw,
106 &clk_mmc23.hw,
107 &clk_mmc45.hw,
109 &clk_usb0.hw,
110 &clk_usb1.hw,
111 &clk_cphif.hw,
/linux-4.4.14/drivers/isdn/hardware/mISDN/
H A DmISDNinfineon.c282 struct inf_hw *hw = dev_id; diva_irq() local
285 spin_lock(&hw->lock); diva_irq()
286 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); diva_irq()
288 spin_unlock(&hw->lock); diva_irq()
291 hw->irqcnt++; diva_irq()
292 mISDNipac_irq(&hw->ipac, irqloops); diva_irq()
293 spin_unlock(&hw->lock); diva_irq()
300 struct inf_hw *hw = dev_id; diva20x_irq() local
303 spin_lock(&hw->lock); diva20x_irq()
304 val = readb(hw->cfg.p); diva20x_irq()
306 spin_unlock(&hw->lock); diva20x_irq()
309 hw->irqcnt++; diva20x_irq()
310 mISDNipac_irq(&hw->ipac, irqloops); diva20x_irq()
311 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */ diva20x_irq()
312 spin_unlock(&hw->lock); diva20x_irq()
319 struct inf_hw *hw = dev_id; tiger_irq() local
322 spin_lock(&hw->lock); tiger_irq()
323 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); tiger_irq()
325 spin_unlock(&hw->lock); tiger_irq()
328 hw->irqcnt++; tiger_irq()
329 mISDNipac_irq(&hw->ipac, irqloops); tiger_irq()
330 spin_unlock(&hw->lock); tiger_irq()
337 struct inf_hw *hw = dev_id; elsa_irq() local
340 spin_lock(&hw->lock); elsa_irq()
341 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); elsa_irq()
343 spin_unlock(&hw->lock); elsa_irq()
346 hw->irqcnt++; elsa_irq()
347 mISDNipac_irq(&hw->ipac, irqloops); elsa_irq()
348 spin_unlock(&hw->lock); elsa_irq()
355 struct inf_hw *hw = dev_id; niccy_irq() local
358 spin_lock(&hw->lock); niccy_irq()
359 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); niccy_irq()
361 spin_unlock(&hw->lock); niccy_irq()
364 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); niccy_irq()
365 hw->irqcnt++; niccy_irq()
366 mISDNipac_irq(&hw->ipac, irqloops); niccy_irq()
367 spin_unlock(&hw->lock); niccy_irq()
374 struct inf_hw *hw = dev_id; gazel_irq() local
377 spin_lock(&hw->lock); gazel_irq()
378 ret = mISDNipac_irq(&hw->ipac, irqloops); gazel_irq()
379 spin_unlock(&hw->lock); gazel_irq()
386 struct inf_hw *hw = dev_id; ipac_irq() local
389 spin_lock(&hw->lock); ipac_irq()
390 val = hw->ipac.read_reg(hw, IPAC_ISTA); ipac_irq()
392 spin_unlock(&hw->lock); ipac_irq()
395 hw->irqcnt++; ipac_irq()
396 mISDNipac_irq(&hw->ipac, irqloops); ipac_irq()
397 spin_unlock(&hw->lock); ipac_irq()
402 enable_hwirq(struct inf_hw *hw) enable_hwirq() argument
407 switch (hw->ci->typ) { enable_hwirq()
410 writel(PITA_INT0_ENABLE, hw->cfg.p); enable_hwirq()
414 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); enable_hwirq()
417 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); enable_hwirq()
420 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); enable_hwirq()
423 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); enable_hwirq()
425 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); enable_hwirq()
428 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); enable_hwirq()
430 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); enable_hwirq()
434 (u32)hw->cfg.start + GAZEL_INCSR); enable_hwirq()
438 (u32)hw->cfg.start + GAZEL_INCSR); enable_hwirq()
446 disable_hwirq(struct inf_hw *hw) disable_hwirq() argument
451 switch (hw->ci->typ) { disable_hwirq()
454 writel(0, hw->cfg.p); disable_hwirq()
458 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); disable_hwirq()
461 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); disable_hwirq()
464 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); disable_hwirq()
467 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); disable_hwirq()
469 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); disable_hwirq()
472 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); disable_hwirq()
474 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); disable_hwirq()
478 outb(0, (u32)hw->cfg.start + GAZEL_INCSR); disable_hwirq()
486 ipac_chip_reset(struct inf_hw *hw) ipac_chip_reset() argument
488 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20); ipac_chip_reset()
490 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00); ipac_chip_reset()
492 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf); ipac_chip_reset()
493 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0); ipac_chip_reset()
497 reset_inf(struct inf_hw *hw) reset_inf() argument
503 pr_notice("%s: resetting card\n", hw->name); reset_inf()
504 switch (hw->ci->typ) { reset_inf()
507 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL); reset_inf()
509 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL); reset_inf()
512 outb(9, (u32)hw->cfg.start + 0x69); reset_inf()
514 (u32)hw->cfg.start + DIVA_PCI_CTRL); reset_inf()
518 hw->cfg.p + PITA_MISC_REG); reset_inf()
520 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG); reset_inf()
525 hw->cfg.p + PITA_MISC_REG); reset_inf()
528 hw->cfg.p + PITA_MISC_REG); reset_inf()
533 ipac_chip_reset(hw); reset_inf()
534 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); reset_inf()
535 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); reset_inf()
536 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12); reset_inf()
540 ipac_chip_reset(hw); reset_inf()
541 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00); reset_inf()
542 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c); reset_inf()
543 hw->ipac.write_reg(hw, IPAC_ATX, 0xff); reset_inf()
548 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); reset_inf()
550 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); reset_inf()
552 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); reset_inf()
554 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); reset_inf()
558 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); reset_inf()
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); reset_inf()
563 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); reset_inf()
565 hw->ipac.isac.adf2 = 0x87; reset_inf()
566 hw->ipac.hscx[0].slot = 0x1f; reset_inf()
567 hw->ipac.hscx[1].slot = 0x23; reset_inf()
570 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); reset_inf()
572 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); reset_inf()
575 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); reset_inf()
577 ipac_chip_reset(hw); reset_inf()
578 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); reset_inf()
579 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); reset_inf()
580 hw->ipac.conf = 0x01; /* IOM off */ reset_inf()
585 enable_hwirq(hw); reset_inf()
589 inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg) inf_ctrl() argument
595 reset_inf(hw); inf_ctrl()
599 hw->name, __func__, cmd, arg); inf_ctrl()
607 init_irq(struct inf_hw *hw) init_irq() argument
612 if (!hw->ci->irqfunc) init_irq()
614 ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw); init_irq()
616 pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq); init_irq()
620 spin_lock_irqsave(&hw->lock, flags); init_irq()
621 reset_inf(hw); init_irq()
622 ret = hw->ipac.init(&hw->ipac); init_irq()
624 spin_unlock_irqrestore(&hw->lock, flags); init_irq()
626 hw->name, ret); init_irq()
629 spin_unlock_irqrestore(&hw->lock, flags); init_irq()
632 pr_notice("%s: IRQ %d count %d\n", hw->name, init_irq()
633 hw->irq, hw->irqcnt); init_irq()
634 if (!hw->irqcnt) { init_irq()
636 hw->name, hw->irq, 3 - cnt); init_irq()
640 free_irq(hw->irq, hw); init_irq()
645 release_io(struct inf_hw *hw) release_io() argument
647 if (hw->cfg.mode) { release_io()
648 if (hw->cfg.p) { release_io()
649 release_mem_region(hw->cfg.start, hw->cfg.size); release_io()
650 iounmap(hw->cfg.p); release_io()
652 release_region(hw->cfg.start, hw->cfg.size); release_io()
653 hw->cfg.mode = AM_NONE; release_io()
655 if (hw->addr.mode) { release_io()
656 if (hw->addr.p) { release_io()
657 release_mem_region(hw->addr.start, hw->addr.size); release_io()
658 iounmap(hw->addr.p); release_io()
660 release_region(hw->addr.start, hw->addr.size); release_io()
661 hw->addr.mode = AM_NONE; release_io()
666 setup_io(struct inf_hw *hw) setup_io() argument
670 if (hw->ci->cfg_mode) { setup_io()
671 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar); setup_io()
672 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar); setup_io()
673 if (hw->ci->cfg_mode == AM_MEMIO) { setup_io()
674 if (!request_mem_region(hw->cfg.start, hw->cfg.size, setup_io()
675 hw->name)) setup_io()
678 if (!request_region(hw->cfg.start, hw->cfg.size, setup_io()
679 hw->name)) setup_io()
684 "already in use\n", hw->name, setup_io()
685 (ulong)hw->cfg.start, (ulong)hw->cfg.size); setup_io()
688 if (hw->ci->cfg_mode == AM_MEMIO) setup_io()
689 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size); setup_io()
690 hw->cfg.mode = hw->ci->cfg_mode; setup_io()
693 hw->name, (ulong)hw->cfg.start, setup_io()
694 (ulong)hw->cfg.size, hw->ci->cfg_mode); setup_io()
697 if (hw->ci->addr_mode) { setup_io()
698 hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar); setup_io()
699 hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar); setup_io()
700 if (hw->ci->addr_mode == AM_MEMIO) { setup_io()
701 if (!request_mem_region(hw->addr.start, hw->addr.size, setup_io()
702 hw->name)) setup_io()
705 if (!request_region(hw->addr.start, hw->addr.size, setup_io()
706 hw->name)) setup_io()
711 "already in use\n", hw->name, setup_io()
712 (ulong)hw->addr.start, (ulong)hw->addr.size); setup_io()
715 if (hw->ci->addr_mode == AM_MEMIO) setup_io()
716 hw->addr.p = ioremap(hw->addr.start, hw->addr.size); setup_io()
717 hw->addr.mode = hw->ci->addr_mode; setup_io()
720 hw->name, (ulong)hw->addr.start, setup_io()
721 (ulong)hw->addr.size, hw->ci->addr_mode); setup_io()
725 switch (hw->ci->typ) { setup_io()
728 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; setup_io()
729 hw->isac.mode = hw->cfg.mode; setup_io()
730 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE; setup_io()
731 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT; setup_io()
732 hw->hscx.mode = hw->cfg.mode; setup_io()
733 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; setup_io()
734 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; setup_io()
737 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
738 hw->ipac.isac.off = 0x80; setup_io()
739 hw->isac.mode = hw->addr.mode; setup_io()
740 hw->isac.a.p = hw->addr.p; setup_io()
741 hw->hscx.mode = hw->addr.mode; setup_io()
742 hw->hscx.a.p = hw->addr.p; setup_io()
745 hw->ipac.type = IPAC_TYPE_IPACX; setup_io()
746 hw->isac.mode = hw->addr.mode; setup_io()
747 hw->isac.a.p = hw->addr.p; setup_io()
748 hw->hscx.mode = hw->addr.mode; setup_io()
749 hw->hscx.a.p = hw->addr.p; setup_io()
753 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
754 hw->ipac.isac.off = 0x80; setup_io()
755 hw->isac.mode = hw->cfg.mode; setup_io()
756 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; setup_io()
757 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; setup_io()
758 hw->hscx.mode = hw->cfg.mode; setup_io()
759 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; setup_io()
760 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; setup_io()
761 outb(0xff, (ulong)hw->cfg.start); setup_io()
763 outb(0x00, (ulong)hw->cfg.start); setup_io()
765 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL); setup_io()
769 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
770 hw->ipac.isac.off = 0x80; setup_io()
771 hw->isac.a.io.ale = (u32)hw->addr.start; setup_io()
772 hw->isac.a.io.port = (u32)hw->addr.start + 1; setup_io()
773 hw->isac.mode = hw->addr.mode; setup_io()
774 hw->hscx.a.io.ale = (u32)hw->addr.start; setup_io()
775 hw->hscx.a.io.port = (u32)hw->addr.start + 1; setup_io()
776 hw->hscx.mode = hw->addr.mode; setup_io()
779 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; setup_io()
780 hw->isac.mode = hw->addr.mode; setup_io()
781 hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE; setup_io()
782 hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT; setup_io()
783 hw->hscx.mode = hw->addr.mode; setup_io()
784 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE; setup_io()
785 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT; setup_io()
788 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
789 hw->ipac.isac.off = 0x80; setup_io()
790 hw->isac.a.io.ale = (u32)hw->addr.start; setup_io()
791 hw->isac.a.io.port = hw->isac.a.io.ale + 4; setup_io()
792 hw->isac.mode = hw->addr.mode; setup_io()
793 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io()
794 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
795 hw->hscx.mode = hw->addr.mode; setup_io()
798 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
799 hw->ipac.isac.off = 0x80; setup_io()
800 hw->isac.a.io.ale = (u32)hw->addr.start + 0x08; setup_io()
801 hw->isac.a.io.port = hw->isac.a.io.ale + 4; setup_io()
802 hw->isac.mode = hw->addr.mode; setup_io()
803 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io()
804 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
805 hw->hscx.mode = hw->addr.mode; setup_io()
808 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
809 hw->ipac.isac.off = 0x80; setup_io()
810 hw->isac.a.io.ale = (u32)hw->addr.start + 0x10; setup_io()
811 hw->isac.a.io.port = hw->isac.a.io.ale + 4; setup_io()
812 hw->isac.mode = hw->addr.mode; setup_io()
813 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io()
814 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
815 hw->hscx.mode = hw->addr.mode; setup_io()
818 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
819 hw->ipac.isac.off = 0x80; setup_io()
820 hw->isac.a.io.ale = (u32)hw->addr.start + 0x20; setup_io()
821 hw->isac.a.io.port = hw->isac.a.io.ale + 4; setup_io()
822 hw->isac.mode = hw->addr.mode; setup_io()
823 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io()
824 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
825 hw->hscx.mode = hw->addr.mode; setup_io()
828 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; setup_io()
829 hw->ipac.isac.off = 0x80; setup_io()
830 hw->isac.mode = hw->addr.mode; setup_io()
831 hw->isac.a.io.port = (u32)hw->addr.start; setup_io()
832 hw->hscx.mode = hw->addr.mode; setup_io()
833 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
836 hw->ipac.type = IPAC_TYPE_IPAC; setup_io()
837 hw->ipac.isac.off = 0x80; setup_io()
838 hw->isac.mode = hw->addr.mode; setup_io()
839 hw->isac.a.io.ale = (u32)hw->addr.start; setup_io()
840 hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT; setup_io()
841 hw->hscx.mode = hw->addr.mode; setup_io()
842 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io()
843 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
848 switch (hw->isac.mode) { setup_io()
850 ASSIGN_FUNC_IPAC(MIO, hw->ipac); setup_io()
853 ASSIGN_FUNC_IPAC(IND, hw->ipac); setup_io()
856 ASSIGN_FUNC_IPAC(IO, hw->ipac); setup_io()
H A Dhfcsusb.c55 static void hfcsusb_ph_command(struct hfcsusb *hw, u_char command);
56 static void release_hw(struct hfcsusb *hw);
57 static void reset_hfcsusb(struct hfcsusb *hw);
58 static void setPortMode(struct hfcsusb *hw);
59 static void hfcsusb_start_endpoint(struct hfcsusb *hw, int channel);
60 static void hfcsusb_stop_endpoint(struct hfcsusb *hw, int channel);
63 static void hfcsusb_ph_info(struct hfcsusb *hw);
67 ctrl_start_transfer(struct hfcsusb *hw) ctrl_start_transfer() argument
70 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); ctrl_start_transfer()
72 if (hw->ctrl_cnt) { ctrl_start_transfer()
73 hw->ctrl_urb->pipe = hw->ctrl_out_pipe; ctrl_start_transfer()
74 hw->ctrl_urb->setup_packet = (u_char *)&hw->ctrl_write; ctrl_start_transfer()
75 hw->ctrl_urb->transfer_buffer = NULL; ctrl_start_transfer()
76 hw->ctrl_urb->transfer_buffer_length = 0; ctrl_start_transfer()
77 hw->ctrl_write.wIndex = ctrl_start_transfer()
78 cpu_to_le16(hw->ctrl_buff[hw->ctrl_out_idx].hfcs_reg); ctrl_start_transfer()
79 hw->ctrl_write.wValue = ctrl_start_transfer()
80 cpu_to_le16(hw->ctrl_buff[hw->ctrl_out_idx].reg_val); ctrl_start_transfer()
82 usb_submit_urb(hw->ctrl_urb, GFP_ATOMIC); ctrl_start_transfer()
90 static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) write_reg() argument
96 hw->name, __func__, reg, val); write_reg()
98 spin_lock(&hw->ctrl_lock); write_reg()
99 if (hw->ctrl_cnt >= HFC_CTRL_BUFSIZE) { write_reg()
100 spin_unlock(&hw->ctrl_lock); write_reg()
103 buf = &hw->ctrl_buff[hw->ctrl_in_idx]; write_reg()
106 if (++hw->ctrl_in_idx >= HFC_CTRL_BUFSIZE) write_reg()
107 hw->ctrl_in_idx = 0; write_reg()
108 if (++hw->ctrl_cnt == 1) write_reg()
109 ctrl_start_transfer(hw); write_reg()
110 spin_unlock(&hw->ctrl_lock); write_reg()
119 struct hfcsusb *hw = (struct hfcsusb *) urb->context; ctrl_complete() local
122 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); ctrl_complete()
124 urb->dev = hw->dev; ctrl_complete()
125 if (hw->ctrl_cnt) { ctrl_complete()
126 hw->ctrl_cnt--; /* decrement actual count */ ctrl_complete()
127 if (++hw->ctrl_out_idx >= HFC_CTRL_BUFSIZE) ctrl_complete()
128 hw->ctrl_out_idx = 0; /* pointer wrap */ ctrl_complete()
130 ctrl_start_transfer(hw); /* start next transfer */ ctrl_complete()
136 set_led_bit(struct hfcsusb *hw, signed short led_bits, int set_on) set_led_bit() argument
140 hw->led_state &= ~abs(led_bits); set_led_bit()
142 hw->led_state |= led_bits; set_led_bit()
145 hw->led_state |= abs(led_bits); set_led_bit()
147 hw->led_state &= ~led_bits; set_led_bit()
153 handle_led(struct hfcsusb *hw, int event) handle_led() argument
156 hfcsusb_idtab[hw->vend_idx].driver_info; handle_led()
161 tmpled = hw->led_state; handle_led()
165 set_led_bit(hw, driver_info->led_bits[0], 1); handle_led()
166 set_led_bit(hw, driver_info->led_bits[1], 0); handle_led()
167 set_led_bit(hw, driver_info->led_bits[2], 0); handle_led()
168 set_led_bit(hw, driver_info->led_bits[3], 0); handle_led()
171 set_led_bit(hw, driver_info->led_bits[0], 0); handle_led()
172 set_led_bit(hw, driver_info->led_bits[1], 0); handle_led()
173 set_led_bit(hw, driver_info->led_bits[2], 0); handle_led()
174 set_led_bit(hw, driver_info->led_bits[3], 0); handle_led()
177 set_led_bit(hw, driver_info->led_bits[1], 1); handle_led()
180 set_led_bit(hw, driver_info->led_bits[1], 0); handle_led()
183 set_led_bit(hw, driver_info->led_bits[2], 1); handle_led()
186 set_led_bit(hw, driver_info->led_bits[2], 0); handle_led()
189 set_led_bit(hw, driver_info->led_bits[3], 1); handle_led()
192 set_led_bit(hw, driver_info->led_bits[3], 0); handle_led()
196 if (hw->led_state != tmpled) { handle_led()
199 hw->name, __func__, handle_led()
200 HFCUSB_P_DATA, hw->led_state); handle_led()
202 write_reg(hw, HFCUSB_P_DATA, hw->led_state); handle_led()
213 struct hfcsusb *hw = bch->hw; hfcusb_l2l1B() local
219 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); hfcusb_l2l1B()
223 spin_lock_irqsave(&hw->lock, flags); hfcusb_l2l1B()
225 spin_unlock_irqrestore(&hw->lock, flags); hfcusb_l2l1B()
228 hw->name, __func__, ret); hfcusb_l2l1B()
234 hfcsusb_start_endpoint(hw, bch->nr - 1); hfcusb_l2l1B()
259 hfcsusb_ph_info(struct hfcsusb *hw) hfcsusb_ph_info() argument
262 struct dchannel *dch = &hw->dch; hfcsusb_ph_info()
267 phi->dch.ch.protocol = hw->protocol; hfcsusb_ph_info()
272 phi->bch[i].protocol = hw->bch[i].ch.protocol; hfcsusb_ph_info()
273 phi->bch[i].Flags = hw->bch[i].Flags; hfcsusb_ph_info()
290 struct hfcsusb *hw = dch->hw; hfcusb_l2l1D() local
298 hw->name, __func__); hfcusb_l2l1D()
300 spin_lock_irqsave(&hw->lock, flags); hfcusb_l2l1D()
302 spin_unlock_irqrestore(&hw->lock, flags); hfcusb_l2l1D()
312 hw->name, __func__, hfcusb_l2l1D()
313 (hw->protocol == ISDN_P_NT_S0) ? "NT" : "TE"); hfcusb_l2l1D()
315 if (hw->protocol == ISDN_P_NT_S0) { hfcusb_l2l1D()
322 hfcsusb_ph_command(hw, hfcusb_l2l1D()
328 hfcsusb_ph_command(hw, HFC_L1_ACTIVATE_TE); hfcusb_l2l1D()
336 hw->name, __func__); hfcusb_l2l1D()
339 if (hw->protocol == ISDN_P_NT_S0) { hfcusb_l2l1D()
340 hfcsusb_ph_command(hw, HFC_L1_DEACTIVATE_NT); hfcusb_l2l1D()
341 spin_lock_irqsave(&hw->lock, flags); hfcusb_l2l1D()
353 spin_unlock_irqrestore(&hw->lock, flags); hfcusb_l2l1D()
363 hfcsusb_ph_info(hw); hfcusb_l2l1D()
377 struct hfcsusb *hw = dch->hw; hfc_l1callback() local
381 hw->name, __func__, cmd); hfc_l1callback()
416 hw->name, __func__, cmd); hfc_l1callback()
419 hfcsusb_ph_info(hw); hfc_l1callback()
424 open_dchannel(struct hfcsusb *hw, struct mISDNchannel *ch, open_dchannel() argument
431 hw->name, __func__, hw->dch.dev.id, rq->adr.channel, open_dchannel()
436 test_and_clear_bit(FLG_ACTIVE, &hw->dch.Flags); open_dchannel()
437 test_and_clear_bit(FLG_ACTIVE, &hw->ech.Flags); open_dchannel()
438 hfcsusb_start_endpoint(hw, HFC_CHAN_D); open_dchannel()
442 if (hw->fifos[HFCUSB_PCM_RX].pipe) { open_dchannel()
443 hfcsusb_start_endpoint(hw, HFC_CHAN_E); open_dchannel()
444 set_bit(FLG_ACTIVE, &hw->ech.Flags); open_dchannel()
445 _queue_data(&hw->ech.dev.D, PH_ACTIVATE_IND, open_dchannel()
451 if (!hw->initdone) { open_dchannel()
452 hw->protocol = rq->protocol; open_dchannel()
454 err = create_l1(&hw->dch, hfc_l1callback); open_dchannel()
458 setPortMode(hw); open_dchannel()
460 hw->initdone = 1; open_dchannel()
466 if (((ch->protocol == ISDN_P_NT_S0) && (hw->dch.state == 3)) || open_dchannel()
467 ((ch->protocol == ISDN_P_TE_S0) && (hw->dch.state == 7))) open_dchannel()
473 hw->name, __func__); open_dchannel()
478 open_bchannel(struct hfcsusb *hw, struct channel_req *rq) open_bchannel() argument
489 hw->name, __func__, rq->adr.channel); open_bchannel()
491 bch = &hw->bch[rq->adr.channel - 1]; open_bchannel()
499 hw->name, __func__); open_bchannel()
504 channel_ctrl(struct hfcsusb *hw, struct mISDN_ctrl_req *cq) channel_ctrl() argument
510 hw->name, __func__, (cq->op), (cq->channel)); channel_ctrl()
519 hw->name, __func__, cq->op); channel_ctrl()
534 struct hfcsusb *hw = dch->hw; hfc_dctrl() local
540 hw->name, __func__, cmd, arg); hfc_dctrl()
546 err = open_dchannel(hw, ch, rq); hfc_dctrl()
548 err = open_bchannel(hw, rq); hfc_dctrl()
550 hw->open++; hfc_dctrl()
553 hw->open--; hfc_dctrl()
557 hw->name, __func__, hw->dch.dev.id, hfc_dctrl()
558 __builtin_return_address(0), hw->open); hfc_dctrl()
559 if (!hw->open) { hfc_dctrl()
560 hfcsusb_stop_endpoint(hw, HFC_CHAN_D); hfc_dctrl()
561 if (hw->fifos[HFCUSB_PCM_RX].pipe) hfc_dctrl()
562 hfcsusb_stop_endpoint(hw, HFC_CHAN_E); hfc_dctrl()
563 handle_led(hw, LED_POWER_ON); hfc_dctrl()
568 err = channel_ctrl(hw, arg); hfc_dctrl()
573 hw->name, __func__, cmd); hfc_dctrl()
585 struct hfcsusb *hw = dch->hw; ph_state_te() local
589 printk(KERN_DEBUG "%s: %s: %s\n", hw->name, __func__, ph_state_te()
593 hw->name, __func__, dch->state); ph_state_te()
615 handle_led(hw, LED_S0_ON); ph_state_te()
617 handle_led(hw, LED_S0_OFF); ph_state_te()
626 struct hfcsusb *hw = dch->hw; ph_state_nt() local
631 hw->name, __func__, ph_state_nt()
636 hw->name, __func__, dch->state); ph_state_nt()
643 hw->nt_timer = 0; ph_state_nt()
644 hw->timers &= ~NT_ACTIVATION_TIMER; ph_state_nt()
645 handle_led(hw, LED_S0_OFF); ph_state_nt()
649 if (hw->nt_timer < 0) { ph_state_nt()
650 hw->nt_timer = 0; ph_state_nt()
651 hw->timers &= ~NT_ACTIVATION_TIMER; ph_state_nt()
652 hfcsusb_ph_command(dch->hw, HFC_L1_DEACTIVATE_NT); ph_state_nt()
654 hw->timers |= NT_ACTIVATION_TIMER; ph_state_nt()
655 hw->nt_timer = NT_T1_COUNT; ph_state_nt()
657 write_reg(hw, HFCUSB_STATES, 2 | HFCUSB_NT_G2_G3); ph_state_nt()
661 hw->nt_timer = 0; ph_state_nt()
662 hw->timers &= ~NT_ACTIVATION_TIMER; ph_state_nt()
666 handle_led(hw, LED_S0_ON); ph_state_nt()
669 hw->nt_timer = 0; ph_state_nt()
670 hw->timers &= ~NT_ACTIVATION_TIMER; ph_state_nt()
675 hfcsusb_ph_info(hw); ph_state_nt()
681 struct hfcsusb *hw = dch->hw; ph_state() local
683 if (hw->protocol == ISDN_P_NT_S0) ph_state()
685 else if (hw->protocol == ISDN_P_TE_S0) ph_state()
695 struct hfcsusb *hw = bch->hw; hfcsusb_setup_bch() local
700 hw->name, __func__, bch->state, protocol, hfcsusb_setup_bch()
731 hw->name, __func__, protocol); hfcsusb_setup_bch()
736 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 0 : 2); hfcsusb_setup_bch()
737 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); hfcsusb_setup_bch()
738 write_reg(hw, HFCUSB_INC_RES_F, 2); hfcsusb_setup_bch()
739 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 1 : 3); hfcsusb_setup_bch()
740 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); hfcsusb_setup_bch()
741 write_reg(hw, HFCUSB_INC_RES_F, 2); hfcsusb_setup_bch()
743 sctrl = 0x40 + ((hw->protocol == ISDN_P_TE_S0) ? 0x00 : 0x04); hfcsusb_setup_bch()
745 if (test_bit(FLG_ACTIVE, &hw->bch[0].Flags)) { hfcsusb_setup_bch()
749 if (test_bit(FLG_ACTIVE, &hw->bch[1].Flags)) { hfcsusb_setup_bch()
753 write_reg(hw, HFCUSB_SCTRL, sctrl); hfcsusb_setup_bch()
754 write_reg(hw, HFCUSB_SCTRL_R, sctrl_r); hfcsusb_setup_bch()
757 handle_led(hw, (bch->nr == 1) ? LED_B1_ON : LED_B2_ON); hfcsusb_setup_bch()
759 handle_led(hw, (bch->nr == 1) ? LED_B1_OFF : hfcsusb_setup_bch()
762 hfcsusb_ph_info(hw); hfcsusb_setup_bch()
767 hfcsusb_ph_command(struct hfcsusb *hw, u_char command) hfcsusb_ph_command() argument
771 hw->name, __func__, command); hfcsusb_ph_command()
776 write_reg(hw, HFCUSB_STATES, 0x14); hfcsusb_ph_command()
778 write_reg(hw, HFCUSB_STATES, 0x04); hfcsusb_ph_command()
782 write_reg(hw, HFCUSB_STATES, 0x10); hfcsusb_ph_command()
783 write_reg(hw, HFCUSB_STATES, 0x03); hfcsusb_ph_command()
787 if (hw->dch.state == 3) hfcsusb_ph_command()
788 _queue_data(&hw->dch.dev.D, PH_ACTIVATE_IND, hfcsusb_ph_command()
791 write_reg(hw, HFCUSB_STATES, HFCUSB_ACTIVATE | hfcsusb_ph_command()
796 write_reg(hw, HFCUSB_STATES, hfcsusb_ph_command()
816 struct hfcsusb *hw = fifo->hw; hfcsusb_rx_frame() local
826 hw->name, __func__, fifon, len, hfcsusb_rx_frame()
834 hw->name, __func__); hfcsusb_rx_frame()
838 spin_lock(&hw->lock); hfcsusb_rx_frame()
847 spin_unlock(&hw->lock); hfcsusb_rx_frame()
856 hw->name, fifo->bch->nr, len); hfcsusb_rx_frame()
857 spin_unlock(&hw->lock); hfcsusb_rx_frame()
880 hw->name, __func__); hfcsusb_rx_frame()
881 spin_unlock(&hw->lock); hfcsusb_rx_frame()
889 hw->name, __func__, fifon); hfcsusb_rx_frame()
891 spin_unlock(&hw->lock); hfcsusb_rx_frame()
906 hw->name, __func__, fifon, hfcsusb_rx_frame()
925 &hw->dch); hfcsusb_rx_frame()
931 hw->name, fifon, rx_skb->len); hfcsusb_rx_frame()
945 spin_unlock(&hw->lock); hfcsusb_rx_frame()
976 struct hfcsusb *hw = fifo->hw; rx_iso_complete() local
986 spin_lock(&hw->lock); rx_iso_complete()
990 spin_unlock(&hw->lock); rx_iso_complete()
993 spin_unlock(&hw->lock); rx_iso_complete()
1003 hw->name, __func__, status, fifon); rx_iso_complete()
1023 hw->name, __func__, k, iso_status); rx_iso_complete()
1031 hw->name, __func__, urb->start_frame, rx_iso_complete()
1046 hw->threshold_mask = buf[1]; rx_iso_complete()
1065 if ((s0_state) && (hw->initdone) && rx_iso_complete()
1066 (s0_state != hw->dch.state)) { rx_iso_complete()
1067 hw->dch.state = s0_state; rx_iso_complete()
1068 schedule_event(&hw->dch, FLG_PHCHANGE); rx_iso_complete()
1071 fill_isoc_urb(urb, fifo->hw->dev, fifo->pipe, rx_iso_complete()
1080 hw->name, __func__, errcode); rx_iso_complete()
1086 hw->name, __func__, status, fifon); rx_iso_complete()
1097 struct hfcsusb *hw = fifo->hw; rx_int_complete() local
1100 spin_lock(&hw->lock); rx_int_complete()
1104 spin_unlock(&hw->lock); rx_int_complete()
1107 spin_unlock(&hw->lock); rx_int_complete()
1114 hw->name, __func__, fifon, urb->status); rx_int_complete()
1126 hw->name, __func__, len); rx_int_complete()
1134 hw->threshold_mask = buf[1]; rx_int_complete()
1137 if (hw->initdone && ((buf[0] >> 4) != hw->dch.state)) { rx_int_complete()
1138 hw->dch.state = (buf[0] >> 4); rx_int_complete()
1139 schedule_event(&hw->dch, FLG_PHCHANGE); rx_int_complete()
1158 hw->name, __func__); rx_int_complete()
1168 struct hfcsusb *hw = fifo->hw; tx_iso_complete() local
1176 spin_lock(&hw->lock); tx_iso_complete()
1180 spin_unlock(&hw->lock); tx_iso_complete()
1197 hw->name, __func__); tx_iso_complete()
1198 spin_unlock(&hw->lock); tx_iso_complete()
1215 hw->name, __func__, status, fifon); tx_iso_complete()
1223 threshbit = (hw->threshold_mask & (1 << fifon)); tx_iso_complete()
1231 fill_isoc_urb(urb, fifo->hw->dev, fifo->pipe, tx_iso_complete()
1246 hw->name, __func__, k, errcode); tx_iso_complete()
1302 hw->name, __func__, tx_iso_complete()
1334 hw->name, __func__, tx_iso_complete()
1357 hw->name, __func__, errcode); tx_iso_complete()
1365 if ((fifon == HFCUSB_D_TX) && (hw->protocol == ISDN_P_NT_S0) tx_iso_complete()
1366 && (hw->timers & NT_ACTIVATION_TIMER)) { tx_iso_complete()
1367 if ((--hw->nt_timer) < 0) tx_iso_complete()
1368 schedule_event(&hw->dch, FLG_PHCHANGE); tx_iso_complete()
1375 hw->name, __func__, tx_iso_complete()
1378 spin_unlock(&hw->lock); tx_iso_complete()
1389 struct hfcsusb *hw = fifo->hw; start_isoc_chain() local
1394 hw->name, __func__, fifo->fifonum); start_isoc_chain()
1404 hw->name, __func__, fifo->fifonum); start_isoc_chain()
1414 fifo->hw->dev, fifo->pipe, start_isoc_chain()
1434 hw->name, __func__); start_isoc_chain()
1444 hw->name, __func__, start_isoc_chain()
1454 struct hfcsusb *hw = fifo->hw; stop_iso_gracefull() local
1459 spin_lock_irqsave(&hw->lock, flags); stop_iso_gracefull()
1462 hw->name, __func__, fifo->fifonum, i); stop_iso_gracefull()
1464 spin_unlock_irqrestore(&hw->lock, flags); stop_iso_gracefull()
1473 hw->name, __func__, fifo->fifonum, i); stop_iso_gracefull()
1480 struct hfcsusb *hw = fifo->hw; stop_int_gracefull() local
1484 spin_lock_irqsave(&hw->lock, flags); stop_int_gracefull()
1487 hw->name, __func__, fifo->fifonum); stop_int_gracefull()
1489 spin_unlock_irqrestore(&hw->lock, flags); stop_int_gracefull()
1496 hw->name, __func__, fifo->fifonum); stop_int_gracefull()
1503 struct hfcsusb *hw = fifo->hw; start_int_fifo() local
1508 hw->name, __func__, fifo->fifonum); start_int_fifo()
1515 usb_fill_int_urb(fifo->urb, fifo->hw->dev, fifo->pipe, start_int_fifo()
1523 hw->name, __func__, errcode); start_int_fifo()
1529 setPortMode(struct hfcsusb *hw) setPortMode() argument
1532 printk(KERN_DEBUG "%s: %s %s\n", hw->name, __func__, setPortMode()
1533 (hw->protocol == ISDN_P_TE_S0) ? "TE" : "NT"); setPortMode()
1535 if (hw->protocol == ISDN_P_TE_S0) { setPortMode()
1536 write_reg(hw, HFCUSB_SCTRL, 0x40); setPortMode()
1537 write_reg(hw, HFCUSB_SCTRL_E, 0x00); setPortMode()
1538 write_reg(hw, HFCUSB_CLKDEL, CLKDEL_TE); setPortMode()
1539 write_reg(hw, HFCUSB_STATES, 3 | 0x10); setPortMode()
1540 write_reg(hw, HFCUSB_STATES, 3); setPortMode()
1542 write_reg(hw, HFCUSB_SCTRL, 0x44); setPortMode()
1543 write_reg(hw, HFCUSB_SCTRL_E, 0x09); setPortMode()
1544 write_reg(hw, HFCUSB_CLKDEL, CLKDEL_NT); setPortMode()
1545 write_reg(hw, HFCUSB_STATES, 1 | 0x10); setPortMode()
1546 write_reg(hw, HFCUSB_STATES, 1); setPortMode()
1551 reset_hfcsusb(struct hfcsusb *hw) reset_hfcsusb() argument
1557 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); reset_hfcsusb()
1560 write_reg(hw, HFCUSB_CIRM, 8); reset_hfcsusb()
1563 write_reg(hw, HFCUSB_CIRM, 0x10); reset_hfcsusb()
1566 write_reg(hw, HFCUSB_USB_SIZE, (hw->packet_size / 8) | reset_hfcsusb()
1567 ((hw->packet_size / 8) << 4)); reset_hfcsusb()
1570 write_reg(hw, HFCUSB_USB_SIZE_I, hw->iso_packet_size); reset_hfcsusb()
1573 write_reg(hw, HFCUSB_MST_MODE1, 0); /* set default values */ reset_hfcsusb()
1574 write_reg(hw, HFCUSB_MST_MODE0, 1); /* enable master mode */ reset_hfcsusb()
1577 write_reg(hw, HFCUSB_F_THRES, reset_hfcsusb()
1580 fifo = hw->fifos; reset_hfcsusb()
1582 write_reg(hw, HFCUSB_FIFO, i); /* select the desired fifo */ reset_hfcsusb()
1588 write_reg(hw, HFCUSB_HDLC_PAR, ((i <= HFCUSB_B2_RX) ? 0 : 2)); reset_hfcsusb()
1592 write_reg(hw, HFCUSB_CON_HDLC, reset_hfcsusb()
1593 (hw->protocol == ISDN_P_NT_S0) ? 0x08 : 0x09); reset_hfcsusb()
1595 write_reg(hw, HFCUSB_CON_HDLC, 0x08); reset_hfcsusb()
1596 write_reg(hw, HFCUSB_INC_RES_F, 2); /* reset the fifo */ reset_hfcsusb()
1599 write_reg(hw, HFCUSB_SCTRL_R, 0); /* disable both B receivers */ reset_hfcsusb()
1600 handle_led(hw, LED_POWER_ON); reset_hfcsusb()
1605 hfcsusb_start_endpoint(struct hfcsusb *hw, int channel) hfcsusb_start_endpoint() argument
1608 if ((channel == HFC_CHAN_D) && (hw->fifos[HFCUSB_D_RX].active)) hfcsusb_start_endpoint()
1610 if ((channel == HFC_CHAN_B1) && (hw->fifos[HFCUSB_B1_RX].active)) hfcsusb_start_endpoint()
1612 if ((channel == HFC_CHAN_B2) && (hw->fifos[HFCUSB_B2_RX].active)) hfcsusb_start_endpoint()
1614 if ((channel == HFC_CHAN_E) && (hw->fifos[HFCUSB_PCM_RX].active)) hfcsusb_start_endpoint()
1618 if (hw->cfg_used == CNF_3INT3ISO || hw->cfg_used == CNF_4INT3ISO) hfcsusb_start_endpoint()
1619 start_int_fifo(hw->fifos + channel * 2 + 1); hfcsusb_start_endpoint()
1622 if (hw->cfg_used == CNF_3ISO3ISO || hw->cfg_used == CNF_4ISO3ISO) { hfcsusb_start_endpoint()
1625 start_isoc_chain(hw->fifos + HFCUSB_D_RX, hfcsusb_start_endpoint()
1631 start_isoc_chain(hw->fifos + HFCUSB_PCM_RX, hfcsusb_start_endpoint()
1637 start_isoc_chain(hw->fifos + HFCUSB_B1_RX, hfcsusb_start_endpoint()
1643 start_isoc_chain(hw->fifos + HFCUSB_B2_RX, hfcsusb_start_endpoint()
1654 start_isoc_chain(hw->fifos + HFCUSB_D_TX, hfcsusb_start_endpoint()
1659 start_isoc_chain(hw->fifos + HFCUSB_B1_TX, hfcsusb_start_endpoint()
1664 start_isoc_chain(hw->fifos + HFCUSB_B2_TX, hfcsusb_start_endpoint()
1673 hfcsusb_stop_endpoint(struct hfcsusb *hw, int channel) hfcsusb_stop_endpoint() argument
1676 if ((channel == HFC_CHAN_D) && (!hw->fifos[HFCUSB_D_RX].active)) hfcsusb_stop_endpoint()
1678 if ((channel == HFC_CHAN_B1) && (!hw->fifos[HFCUSB_B1_RX].active)) hfcsusb_stop_endpoint()
1680 if ((channel == HFC_CHAN_B2) && (!hw->fifos[HFCUSB_B2_RX].active)) hfcsusb_stop_endpoint()
1682 if ((channel == HFC_CHAN_E) && (!hw->fifos[HFCUSB_PCM_RX].active)) hfcsusb_stop_endpoint()
1686 if (hw->cfg_used == CNF_3INT3ISO || hw->cfg_used == CNF_4INT3ISO) hfcsusb_stop_endpoint()
1687 stop_int_gracefull(hw->fifos + channel * 2 + 1); hfcsusb_stop_endpoint()
1690 if (hw->cfg_used == CNF_3ISO3ISO || hw->cfg_used == CNF_4ISO3ISO) hfcsusb_stop_endpoint()
1691 stop_iso_gracefull(hw->fifos + channel * 2 + 1); hfcsusb_stop_endpoint()
1695 stop_iso_gracefull(hw->fifos + channel * 2); hfcsusb_stop_endpoint()
1701 setup_hfcsusb(struct hfcsusb *hw) setup_hfcsusb() argument
1706 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); setup_hfcsusb()
1709 if (read_reg_atomic(hw, HFCUSB_CHIP_ID, &b) != 1) { setup_hfcsusb()
1711 hw->name, __func__); setup_hfcsusb()
1716 hw->name, __func__, b); setup_hfcsusb()
1721 (void) usb_set_interface(hw->dev, hw->if_used, hw->alt_used); setup_hfcsusb()
1723 hw->led_state = 0; setup_hfcsusb()
1726 hw->ctrl_read.bRequestType = 0xc0; setup_hfcsusb()
1727 hw->ctrl_read.bRequest = 1; setup_hfcsusb()
1728 hw->ctrl_read.wLength = cpu_to_le16(1); setup_hfcsusb()
1729 hw->ctrl_write.bRequestType = 0x40; setup_hfcsusb()
1730 hw->ctrl_write.bRequest = 0; setup_hfcsusb()
1731 hw->ctrl_write.wLength = 0; setup_hfcsusb()
1732 usb_fill_control_urb(hw->ctrl_urb, hw->dev, hw->ctrl_out_pipe, setup_hfcsusb()
1733 (u_char *)&hw->ctrl_write, NULL, 0, setup_hfcsusb()
1734 (usb_complete_t)ctrl_complete, hw); setup_hfcsusb()
1736 reset_hfcsusb(hw); setup_hfcsusb()
1741 release_hw(struct hfcsusb *hw) release_hw() argument
1744 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); release_hw()
1751 hfcsusb_stop_endpoint(hw, HFC_CHAN_D); release_hw()
1752 hfcsusb_stop_endpoint(hw, HFC_CHAN_B1); release_hw()
1753 hfcsusb_stop_endpoint(hw, HFC_CHAN_B2); release_hw()
1754 if (hw->fifos[HFCUSB_PCM_RX].pipe) release_hw()
1755 hfcsusb_stop_endpoint(hw, HFC_CHAN_E); release_hw()
1756 if (hw->protocol == ISDN_P_TE_S0) release_hw()
1757 l1_event(hw->dch.l1, CLOSE_CHANNEL); release_hw()
1759 mISDN_unregister_device(&hw->dch.dev); release_hw()
1760 mISDN_freebchannel(&hw->bch[1]); release_hw()
1761 mISDN_freebchannel(&hw->bch[0]); release_hw()
1762 mISDN_freedchannel(&hw->dch); release_hw()
1764 if (hw->ctrl_urb) { release_hw()
1765 usb_kill_urb(hw->ctrl_urb); release_hw()
1766 usb_free_urb(hw->ctrl_urb); release_hw()
1767 hw->ctrl_urb = NULL; release_hw()
1770 if (hw->intf) release_hw()
1771 usb_set_intfdata(hw->intf, NULL); release_hw()
1772 list_del(&hw->list); release_hw()
1773 kfree(hw); release_hw()
1774 hw = NULL; release_hw()
1780 struct hfcsusb *hw = bch->hw; deactivate_bchannel() local
1785 hw->name, __func__, bch->nr); deactivate_bchannel()
1787 spin_lock_irqsave(&hw->lock, flags); deactivate_bchannel()
1789 spin_unlock_irqrestore(&hw->lock, flags); deactivate_bchannel()
1791 hfcsusb_stop_endpoint(hw, bch->nr - 1); deactivate_bchannel()
1832 setup_instance(struct hfcsusb *hw, struct device *parent) setup_instance() argument
1838 printk(KERN_DEBUG "%s: %s\n", hw->name, __func__); setup_instance()
1840 spin_lock_init(&hw->ctrl_lock); setup_instance()
1841 spin_lock_init(&hw->lock); setup_instance()
1843 mISDN_initdchannel(&hw->dch, MAX_DFRAME_LEN_L1, ph_state); setup_instance()
1844 hw->dch.debug = debug & 0xFFFF; setup_instance()
1845 hw->dch.hw = hw; setup_instance()
1846 hw->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); setup_instance()
1847 hw->dch.dev.D.send = hfcusb_l2l1D; setup_instance()
1848 hw->dch.dev.D.ctrl = hfc_dctrl; setup_instance()
1851 if (hw->fifos[HFCUSB_PCM_RX].pipe) setup_instance()
1852 mISDN_initdchannel(&hw->ech, MAX_DFRAME_LEN_L1, NULL); setup_instance()
1854 hw->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | setup_instance()
1856 hw->dch.dev.nrbchan = 2; setup_instance()
1858 hw->bch[i].nr = i + 1; setup_instance()
1859 set_channelmap(i + 1, hw->dch.dev.channelmap); setup_instance()
1860 hw->bch[i].debug = debug; setup_instance()
1861 mISDN_initbchannel(&hw->bch[i], MAX_DATA_MEM, poll >> 1); setup_instance()
1862 hw->bch[i].hw = hw; setup_instance()
1863 hw->bch[i].ch.send = hfcusb_l2l1B; setup_instance()
1864 hw->bch[i].ch.ctrl = hfc_bctrl; setup_instance()
1865 hw->bch[i].ch.nr = i + 1; setup_instance()
1866 list_add(&hw->bch[i].ch.list, &hw->dch.dev.bchannels); setup_instance()
1869 hw->fifos[HFCUSB_B1_TX].bch = &hw->bch[0]; setup_instance()
1870 hw->fifos[HFCUSB_B1_RX].bch = &hw->bch[0]; setup_instance()
1871 hw->fifos[HFCUSB_B2_TX].bch = &hw->bch[1]; setup_instance()
1872 hw->fifos[HFCUSB_B2_RX].bch = &hw->bch[1]; setup_instance()
1873 hw->fifos[HFCUSB_D_TX].dch = &hw->dch; setup_instance()
1874 hw->fifos[HFCUSB_D_RX].dch = &hw->dch; setup_instance()
1875 hw->fifos[HFCUSB_PCM_RX].ech = &hw->ech; setup_instance()
1876 hw->fifos[HFCUSB_PCM_TX].ech = &hw->ech; setup_instance()
1878 err = setup_hfcsusb(hw); setup_instance()
1882 snprintf(hw->name, MISDN_MAX_IDLEN - 1, "%s.%d", DRIVER_NAME, setup_instance()
1885 DRIVER_NAME, hw->name); setup_instance()
1887 err = mISDN_register_device(&hw->dch.dev, parent, hw->name); setup_instance()
1893 list_add_tail(&hw->list, &HFClist); setup_instance()
1898 mISDN_freebchannel(&hw->bch[1]); setup_instance()
1899 mISDN_freebchannel(&hw->bch[0]); setup_instance()
1900 mISDN_freedchannel(&hw->dch); setup_instance()
1901 kfree(hw); setup_instance()
1908 struct hfcsusb *hw; hfcsusb_probe() local
2012 hw = kzalloc(sizeof(struct hfcsusb), GFP_KERNEL); hfcsusb_probe()
2013 if (!hw) hfcsusb_probe()
2015 snprintf(hw->name, MISDN_MAX_IDLEN - 1, "%s", DRIVER_NAME); hfcsusb_probe()
2028 f = &hw->fifos[idx & 7]; hfcsusb_probe()
2068 f->hw = hw; hfcsusb_probe()
2075 hw->dev = dev; /* save device */ hfcsusb_probe()
2076 hw->if_used = ifnum; /* save used interface */ hfcsusb_probe()
2077 hw->alt_used = alt_used; /* and alternate config */ hfcsusb_probe()
2078 hw->ctrl_paksize = dev->descriptor.bMaxPacketSize0; /* control size */ hfcsusb_probe()
2079 hw->cfg_used = vcf[16]; /* store used config */ hfcsusb_probe()
2080 hw->vend_idx = vend_idx; /* store found vendor */ hfcsusb_probe()
2081 hw->packet_size = packet_size; hfcsusb_probe()
2082 hw->iso_packet_size = iso_packet_size; hfcsusb_probe()
2085 hw->ctrl_in_pipe = usb_rcvctrlpipe(hw->dev, 0); hfcsusb_probe()
2086 hw->ctrl_out_pipe = usb_sndctrlpipe(hw->dev, 0); hfcsusb_probe()
2091 hw->ctrl_urb = usb_alloc_urb(0, GFP_KERNEL); hfcsusb_probe()
2092 if (!hw->ctrl_urb) { hfcsusb_probe()
2095 kfree(hw); hfcsusb_probe()
2100 hw->name, __func__, driver_info->vend_name, hfcsusb_probe()
2103 if (setup_instance(hw, dev->dev.parent)) hfcsusb_probe()
2106 hw->intf = intf; hfcsusb_probe()
2107 usb_set_intfdata(hw->intf, hw); hfcsusb_probe()
2115 struct hfcsusb *hw = usb_get_intfdata(intf); hfcsusb_disconnect() local
2119 printk(KERN_INFO "%s: device disconnected\n", hw->name); hfcsusb_disconnect()
2121 handle_led(hw, LED_POWER_OFF); hfcsusb_disconnect()
2122 release_hw(hw); hfcsusb_disconnect()
2124 list_for_each_entry_safe(hw, next, &HFClist, list) hfcsusb_disconnect()
H A Diohelper.h40 struct hws *hw = p; \
41 return inb(hw->ap.port + off); \
44 struct hws *hw = p; \
45 outb(val, hw->ap.port + off); \
48 struct hws *hw = p; \
49 insb(hw->ap.port + off, dp, size); \
52 struct hws *hw = p; \
53 outsb(hw->ap.port + off, dp, size); \
58 struct hws *hw = p; \
59 outb(off, hw->ap.ale); \
60 return inb(hw->ap.port); \
63 struct hws *hw = p; \
64 outb(off, hw->ap.ale); \
65 outb(val, hw->ap.port); \
68 struct hws *hw = p; \
69 outb(off, hw->ap.ale); \
70 insb(hw->ap.port, dp, size); \
73 struct hws *hw = p; \
74 outb(off, hw->ap.ale); \
75 outsb(hw->ap.port, dp, size); \
80 struct hws *hw = p; \
81 return readb(((typ *)hw->adr) + off); \
84 struct hws *hw = p; \
85 writeb(val, ((typ *)hw->adr) + off); \
88 struct hws *hw = p; \
90 *dp++ = readb(((typ *)hw->adr) + off); \
93 struct hws *hw = p; \
95 writeb(*dp++, ((typ *)hw->adr) + off); \
H A Dhfcpci.c145 struct hfcPCI_hw hw; member in struct:hfc_pci
155 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE; enable_hwirq()
156 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2); enable_hwirq()
162 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE); disable_hwirq()
163 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2); disable_hwirq()
174 del_timer(&hc->hw.timer); release_io_hfcpci()
175 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle); release_io_hfcpci()
176 iounmap(hc->hw.pci_io); release_io_hfcpci()
185 if (hc->hw.protocol == ISDN_P_NT_S0) { hfcpci_setmode()
186 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */ hfcpci_setmode()
187 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */ hfcpci_setmode()
188 hc->hw.states = 1; /* G1 */ hfcpci_setmode()
190 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */ hfcpci_setmode()
191 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */ hfcpci_setmode()
192 hc->hw.states = 2; /* F2 */ hfcpci_setmode()
194 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel); hfcpci_setmode()
195 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states); hfcpci_setmode()
197 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */ hfcpci_setmode()
198 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl); hfcpci_setmode()
222 hc->hw.cirm = HFCPCI_RESET; /* Reset On */ reset_hfcpci()
223 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); reset_hfcpci()
226 hc->hw.cirm = 0; /* Reset Off */ reset_hfcpci()
227 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); reset_hfcpci()
239 hc->hw.fifo_en = 0x30; /* only D fifos enabled */ reset_hfcpci()
241 hc->hw.bswapped = 0; /* no exchange */ reset_hfcpci()
242 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER; reset_hfcpci()
243 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */ reset_hfcpci()
244 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ reset_hfcpci()
245 hc->hw.sctrl_r = 0; reset_hfcpci()
246 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */ reset_hfcpci()
247 hc->hw.mst_m = 0; reset_hfcpci()
249 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */ reset_hfcpci()
251 hc->hw.mst_m |= HFCPCI_F0_NEGATIV; reset_hfcpci()
252 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); reset_hfcpci()
253 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm); reset_hfcpci()
254 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e); reset_hfcpci()
255 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt); reset_hfcpci()
257 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC | reset_hfcpci()
259 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); reset_hfcpci()
267 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); reset_hfcpci()
268 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r); reset_hfcpci()
281 hc->hw.conn = 0x09; reset_hfcpci()
283 hc->hw.conn = 0x36; /* set data flow directions */ reset_hfcpci()
296 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); reset_hfcpci()
306 hc->hw.timer.expires = jiffies + 75; hfcpci_Timer()
309 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80); hfcpci_Timer()
310 * add_timer(&hc->hw.timer); hfcpci_Timer()
341 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2; hfcpci_clear_fifo_rx()
342 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX; hfcpci_clear_fifo_rx()
344 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1; hfcpci_clear_fifo_rx()
345 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX; hfcpci_clear_fifo_rx()
348 hc->hw.fifo_en ^= fifo_state; hfcpci_clear_fifo_rx()
349 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); hfcpci_clear_fifo_rx()
350 hc->hw.last_bfifo_cnt[fifo] = 0; hfcpci_clear_fifo_rx()
357 hc->hw.fifo_en |= fifo_state; hfcpci_clear_fifo_rx()
358 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); hfcpci_clear_fifo_rx()
370 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2; hfcpci_clear_fifo_tx()
371 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX; hfcpci_clear_fifo_tx()
373 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1; hfcpci_clear_fifo_tx()
374 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX; hfcpci_clear_fifo_tx()
377 hc->hw.fifo_en ^= fifo_state; hfcpci_clear_fifo_tx()
378 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); hfcpci_clear_fifo_tx()
391 hc->hw.fifo_en |= fifo_state; hfcpci_clear_fifo_tx()
392 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); hfcpci_clear_fifo_tx()
474 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx; receive_dmsg()
613 struct hfc_pci *hc = bch->hw; main_rec_hfcpci()
620 if ((bch->nr & 2) && (!hc->hw.bswapped)) { main_rec_hfcpci()
621 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2; main_rec_hfcpci()
622 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2; main_rec_hfcpci()
623 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2; main_rec_hfcpci()
626 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1; main_rec_hfcpci()
627 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1; main_rec_hfcpci()
628 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1; main_rec_hfcpci()
652 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) { main_rec_hfcpci()
656 hc->hw.last_bfifo_cnt[real_fifo] = rcnt; main_rec_hfcpci()
691 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx; hfcpci_fill_dfifo()
754 struct hfc_pci *hc = bch->hw; hfcpci_fill_fifo()
772 if ((bch->nr & 2) && (!hc->hw.bswapped)) { hfcpci_fill_fifo()
773 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2; hfcpci_fill_fifo()
774 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2; hfcpci_fill_fifo()
776 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1; hfcpci_fill_fifo()
777 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1; hfcpci_fill_fifo()
953 struct hfc_pci *hc = dch->hw; handle_nt_timer3()
956 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; handle_nt_timer3()
957 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); handle_nt_timer3()
958 hc->hw.nt_timer = 0; handle_nt_timer3()
961 hc->hw.mst_m |= HFCPCI_MASTER; handle_nt_timer3()
962 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); handle_nt_timer3()
970 struct hfc_pci *hc = dch->hw; ph_state_nt()
977 if (hc->hw.nt_timer < 0) { ph_state_nt()
978 hc->hw.nt_timer = 0; ph_state_nt()
981 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; ph_state_nt()
982 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); ph_state_nt()
989 } else if (hc->hw.nt_timer == 0) { ph_state_nt()
990 hc->hw.int_m1 |= HFCPCI_INTS_TIMER; ph_state_nt()
991 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); ph_state_nt()
992 hc->hw.nt_timer = NT_T1_COUNT; ph_state_nt()
993 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER; ph_state_nt()
994 hc->hw.ctmt |= HFCPCI_TIM3_125; ph_state_nt()
995 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | ph_state_nt()
1006 hc->hw.nt_timer = 0; ph_state_nt()
1009 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; ph_state_nt()
1010 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); ph_state_nt()
1012 hc->hw.mst_m &= ~HFCPCI_MASTER; ph_state_nt()
1013 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); ph_state_nt()
1019 hc->hw.nt_timer = 0; ph_state_nt()
1022 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; ph_state_nt()
1023 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); ph_state_nt()
1033 hc->hw.int_m1 |= HFCPCI_INTS_TIMER; ph_state_nt()
1034 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); ph_state_nt()
1035 hc->hw.nt_timer = NT_T3_COUNT; ph_state_nt()
1036 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER; ph_state_nt()
1037 hc->hw.ctmt |= HFCPCI_TIM3_125; ph_state_nt()
1038 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | ph_state_nt()
1048 struct hfc_pci *hc = dch->hw; ph_state()
1050 if (hc->hw.protocol == ISDN_P_NT_S0) { ph_state()
1052 hc->hw.nt_timer < 0) ph_state()
1066 struct hfc_pci *hc = dch->hw; hfc_l1callback()
1072 hc->hw.mst_m |= HFCPCI_MASTER; hfc_l1callback()
1073 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); hfc_l1callback()
1081 hc->hw.mst_m |= HFCPCI_MASTER; hfc_l1callback()
1082 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); hfc_l1callback()
1088 hc->hw.mst_m &= ~HFCPCI_MASTER; hfc_l1callback()
1089 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); hfc_l1callback()
1146 hfcpci_fill_dfifo(dch->hw); tx_dirq()
1151 hfcpci_fill_dfifo(dch->hw); tx_dirq()
1164 if (!(hc->hw.int_m2 & 0x08)) { hfcpci_int()
1183 val &= hc->hw.int_m1; hfcpci_int()
1194 if (hc->hw.protocol == ISDN_P_NT_S0) { hfcpci_int()
1195 if ((--hc->hw.nt_timer) < 0) hfcpci_int()
1199 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER); hfcpci_int()
1202 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1); hfcpci_int()
1216 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1); hfcpci_int()
1254 struct hfc_pci *hc = bch->hw; mode_hfcpci()
1277 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1278 hc->hw.sctrl_e &= ~0x80; mode_hfcpci()
1282 hc->hw.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcpci()
1283 hc->hw.sctrl_e |= 0x80; mode_hfcpci()
1285 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1286 hc->hw.sctrl_e &= ~0x80; mode_hfcpci()
1290 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1291 hc->hw.sctrl_e &= ~0x80; mode_hfcpci()
1302 hc->hw.sctrl &= ~SCTRL_B2_ENA; mode_hfcpci()
1303 hc->hw.sctrl_r &= ~SCTRL_B2_ENA; mode_hfcpci()
1305 hc->hw.sctrl &= ~SCTRL_B1_ENA; mode_hfcpci()
1306 hc->hw.sctrl_r &= ~SCTRL_B1_ENA; mode_hfcpci()
1309 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2; mode_hfcpci()
1310 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS | mode_hfcpci()
1313 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1; mode_hfcpci()
1314 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS | mode_hfcpci()
1319 hc->hw.cirm &= 0x7f; mode_hfcpci()
1321 hc->hw.cirm &= 0xbf; mode_hfcpci()
1334 hc->hw.sctrl |= SCTRL_B2_ENA; mode_hfcpci()
1335 hc->hw.sctrl_r |= SCTRL_B2_ENA; mode_hfcpci()
1337 hc->hw.cirm |= 0x80; mode_hfcpci()
1340 hc->hw.sctrl |= SCTRL_B1_ENA; mode_hfcpci()
1341 hc->hw.sctrl_r |= SCTRL_B1_ENA; mode_hfcpci()
1343 hc->hw.cirm |= 0x40; mode_hfcpci()
1347 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2; mode_hfcpci()
1349 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS | mode_hfcpci()
1351 hc->hw.ctmt |= 2; mode_hfcpci()
1352 hc->hw.conn &= ~0x18; mode_hfcpci()
1354 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1; mode_hfcpci()
1356 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS | mode_hfcpci()
1358 hc->hw.ctmt |= 1; mode_hfcpci()
1359 hc->hw.conn &= ~0x03; mode_hfcpci()
1369 hc->hw.sctrl |= SCTRL_B2_ENA; mode_hfcpci()
1370 hc->hw.sctrl_r |= SCTRL_B2_ENA; mode_hfcpci()
1372 hc->hw.sctrl |= SCTRL_B1_ENA; mode_hfcpci()
1373 hc->hw.sctrl_r |= SCTRL_B1_ENA; mode_hfcpci()
1376 hc->hw.last_bfifo_cnt[1] = 0; mode_hfcpci()
1377 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2; mode_hfcpci()
1378 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS | mode_hfcpci()
1380 hc->hw.ctmt &= ~2; mode_hfcpci()
1381 hc->hw.conn &= ~0x18; mode_hfcpci()
1383 hc->hw.last_bfifo_cnt[0] = 0; mode_hfcpci()
1384 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1; mode_hfcpci()
1385 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS | mode_hfcpci()
1387 hc->hw.ctmt &= ~1; mode_hfcpci()
1388 hc->hw.conn &= ~0x03; mode_hfcpci()
1411 hc->hw.conn &= 0xc7; mode_hfcpci()
1412 hc->hw.conn |= 0x08; mode_hfcpci()
1420 hc->hw.conn &= 0xf8; mode_hfcpci()
1421 hc->hw.conn |= 0x01; mode_hfcpci()
1430 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e); mode_hfcpci()
1431 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); mode_hfcpci()
1432 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); mode_hfcpci()
1433 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl); mode_hfcpci()
1434 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r); mode_hfcpci()
1435 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt); mode_hfcpci()
1436 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); mode_hfcpci()
1438 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); mode_hfcpci()
1446 struct hfc_pci *hc = bch->hw; set_hfcpci_rxtest()
1463 hc->hw.sctrl_r |= SCTRL_B2_ENA; set_hfcpci_rxtest()
1464 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX; set_hfcpci_rxtest()
1466 hc->hw.int_m1 |= HFCPCI_INTS_B2REC; set_hfcpci_rxtest()
1467 hc->hw.ctmt |= 2; set_hfcpci_rxtest()
1468 hc->hw.conn &= ~0x18; set_hfcpci_rxtest()
1470 hc->hw.cirm |= 0x80; set_hfcpci_rxtest()
1473 hc->hw.sctrl_r |= SCTRL_B1_ENA; set_hfcpci_rxtest()
1474 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX; set_hfcpci_rxtest()
1476 hc->hw.int_m1 |= HFCPCI_INTS_B1REC; set_hfcpci_rxtest()
1477 hc->hw.ctmt |= 1; set_hfcpci_rxtest()
1478 hc->hw.conn &= ~0x03; set_hfcpci_rxtest()
1480 hc->hw.cirm |= 0x40; set_hfcpci_rxtest()
1488 hc->hw.sctrl_r |= SCTRL_B2_ENA; set_hfcpci_rxtest()
1489 hc->hw.last_bfifo_cnt[1] = 0; set_hfcpci_rxtest()
1490 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX; set_hfcpci_rxtest()
1491 hc->hw.int_m1 |= HFCPCI_INTS_B2REC; set_hfcpci_rxtest()
1492 hc->hw.ctmt &= ~2; set_hfcpci_rxtest()
1493 hc->hw.conn &= ~0x18; set_hfcpci_rxtest()
1495 hc->hw.sctrl_r |= SCTRL_B1_ENA; set_hfcpci_rxtest()
1496 hc->hw.last_bfifo_cnt[0] = 0; set_hfcpci_rxtest()
1497 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX; set_hfcpci_rxtest()
1498 hc->hw.int_m1 |= HFCPCI_INTS_B1REC; set_hfcpci_rxtest()
1499 hc->hw.ctmt &= ~1; set_hfcpci_rxtest()
1500 hc->hw.conn &= ~0x03; set_hfcpci_rxtest()
1507 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); set_hfcpci_rxtest()
1508 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); set_hfcpci_rxtest()
1509 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r); set_hfcpci_rxtest()
1510 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt); set_hfcpci_rxtest()
1511 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); set_hfcpci_rxtest()
1513 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); set_hfcpci_rxtest()
1521 struct hfc_pci *hc = bch->hw; deactivate_bchannel()
1542 struct hfc_pci *hc = bch->hw; hfc_bctrl()
1591 struct hfc_pci *hc = dch->hw; hfcpci_l2l1D()
1603 hfcpci_fill_dfifo(dch->hw); hfcpci_l2l1D()
1612 if (hc->hw.protocol == ISDN_P_NT_S0) { hfcpci_l2l1D()
1615 hc->hw.mst_m |= HFCPCI_MASTER; hfcpci_l2l1D()
1616 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); hfcpci_l2l1D()
1633 if (hc->hw.protocol == ISDN_P_NT_S0) { hfcpci_l2l1D()
1653 hc->hw.mst_m &= ~HFCPCI_MASTER; hfcpci_l2l1D()
1654 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); hfcpci_l2l1D()
1674 struct hfc_pci *hc = bch->hw; hfcpci_l2l1B()
1764 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; init_card()
1765 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); init_card()
1767 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); init_card()
1816 hc->hw.conn = (hc->hw.conn & ~7) | 6; channel_ctrl()
1817 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); channel_ctrl()
1828 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30; channel_ctrl()
1829 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); channel_ctrl()
1832 hc->hw.trm |= 0x80; /* enable IOM-loop */ channel_ctrl()
1834 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09; channel_ctrl()
1835 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); channel_ctrl()
1836 hc->hw.trm &= 0x7f; /* disable IOM-loop */ channel_ctrl()
1838 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm); channel_ctrl()
1866 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36; channel_ctrl()
1867 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); channel_ctrl()
1868 hc->hw.trm |= 0x80; channel_ctrl()
1869 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm); channel_ctrl()
1872 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09; channel_ctrl()
1873 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); channel_ctrl()
1874 hc->hw.trm &= 0x7f; /* disable IOM-loop */ channel_ctrl()
1909 hc->hw.protocol = rq->protocol; open_dchannel()
1916 if (hc->hw.protocol == ISDN_P_TE_S0) open_dchannel()
1923 hc->hw.protocol = rq->protocol; open_dchannel()
1967 struct hfc_pci *hc = dch->hw; hfc_dctrl()
2008 hc->hw.cirm = 0; setup_hw()
2015 hc->hw.pci_io = setup_hw()
2018 if (!hc->hw.pci_io) { setup_hw()
2025 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle); setup_hw()
2032 hc->hw.fifos = buffer; setup_hw()
2033 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle); setup_hw()
2034 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256); setup_hw()
2037 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos, setup_hw()
2038 (u_long) hc->hw.dmahandle, hc->irq, HZ); setup_hw()
2041 hc->hw.int_m2 = 0; setup_hw()
2043 hc->hw.int_m1 = 0; setup_hw()
2044 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); setup_hw()
2047 hc->hw.timer.function = (void *) hfcpci_Timer; setup_hw()
2048 hc->hw.timer.data = (long) hc; setup_hw()
2049 init_timer(&hc->hw.timer); setup_hw()
2060 hc->hw.int_m2 = 0; /* interrupt output off ! */ release_card()
2069 if (hc->hw.protocol == ISDN_P_TE_S0) release_card()
2092 card->dch.hw = card; setup_card()
2104 card->bch[i].hw = card; setup_card()
2278 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) { _hfcpci_softirq()
2280 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1); _hfcpci_softirq()
2285 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2); _hfcpci_softirq()
/linux-4.4.14/drivers/scsi/csiostor/
H A Dcsio_isr.c47 struct csio_hw *hw = (struct csio_hw *) dev_id; csio_nondata_isr() local
51 if (unlikely(!hw)) csio_nondata_isr()
54 if (unlikely(pci_channel_offline(hw->pdev))) { csio_nondata_isr()
55 CSIO_INC_STATS(hw, n_pcich_offline); csio_nondata_isr()
59 spin_lock_irqsave(&hw->lock, flags); csio_nondata_isr()
60 csio_hw_slow_intr_handler(hw); csio_nondata_isr()
61 rv = csio_mb_isr_handler(hw); csio_nondata_isr()
63 if (rv == 0 && !(hw->flags & CSIO_HWF_FWEVT_PENDING)) { csio_nondata_isr()
64 hw->flags |= CSIO_HWF_FWEVT_PENDING; csio_nondata_isr()
65 spin_unlock_irqrestore(&hw->lock, flags); csio_nondata_isr()
66 schedule_work(&hw->evtq_work); csio_nondata_isr()
69 spin_unlock_irqrestore(&hw->lock, flags); csio_nondata_isr()
75 * @hw: HW module.
81 csio_fwevt_handler(struct csio_hw *hw) csio_fwevt_handler() argument
86 rv = csio_fwevtq_handler(hw); csio_fwevt_handler()
88 spin_lock_irqsave(&hw->lock, flags); csio_fwevt_handler()
89 if (rv == 0 && !(hw->flags & CSIO_HWF_FWEVT_PENDING)) { csio_fwevt_handler()
90 hw->flags |= CSIO_HWF_FWEVT_PENDING; csio_fwevt_handler()
91 spin_unlock_irqrestore(&hw->lock, flags); csio_fwevt_handler()
92 schedule_work(&hw->evtq_work); csio_fwevt_handler()
95 spin_unlock_irqrestore(&hw->lock, flags); csio_fwevt_handler()
110 struct csio_hw *hw = (struct csio_hw *) dev_id; csio_fwevt_isr() local
112 if (unlikely(!hw)) csio_fwevt_isr()
115 if (unlikely(pci_channel_offline(hw->pdev))) { csio_fwevt_isr()
116 CSIO_INC_STATS(hw, n_pcich_offline); csio_fwevt_isr()
120 csio_fwevt_handler(hw); csio_fwevt_isr()
131 csio_fwevt_intx_handler(struct csio_hw *hw, void *wr, uint32_t len, csio_fwevt_intx_handler() argument
134 csio_fwevt_handler(hw); csio_fwevt_intx_handler()
139 * @hw: HW module.
146 csio_process_scsi_cmpl(struct csio_hw *hw, void *wr, uint32_t len, csio_process_scsi_cmpl() argument
155 ioreq = csio_scsi_cmpl_handler(hw, wr, len, flb, NULL, &scsiwr); csio_process_scsi_cmpl()
162 csio_dbg(hw, "%s cmpl recvd ioreq:%p status:%d\n", csio_process_scsi_cmpl()
166 spin_lock_irqsave(&hw->lock, flags); csio_process_scsi_cmpl()
188 spin_unlock_irqrestore(&hw->lock, flags); csio_process_scsi_cmpl()
191 csio_put_scsi_ioreq_lock(hw, csio_process_scsi_cmpl()
192 csio_hw_to_scsim(hw), ioreq); csio_process_scsi_cmpl()
194 spin_lock_irqsave(&hw->lock, flags); csio_process_scsi_cmpl()
196 spin_unlock_irqrestore(&hw->lock, flags); csio_process_scsi_cmpl()
214 struct csio_hw *hw = (struct csio_hw *)iq->owner; csio_scsi_isr_handler() local
221 scm = csio_hw_to_scsim(hw); csio_scsi_isr_handler()
223 if (unlikely(csio_wr_process_iq(hw, iq, csio_process_scsi_cmpl, csio_scsi_isr_handler()
231 ioreq->io_cbfn(hw, ioreq); csio_scsi_isr_handler()
234 csio_put_scsi_ddp_list_lock(hw, scm, &ioreq->gen_list, csio_scsi_isr_handler()
240 csio_put_scsi_ioreq_list_lock(hw, scm, &cbfn_q, csio_scsi_isr_handler()
259 struct csio_hw *hw; csio_scsi_isr() local
264 hw = (struct csio_hw *)iq->owner; csio_scsi_isr()
266 if (unlikely(pci_channel_offline(hw->pdev))) { csio_scsi_isr()
267 CSIO_INC_STATS(hw, n_pcich_offline); csio_scsi_isr()
285 csio_scsi_intx_handler(struct csio_hw *hw, void *wr, uint32_t len, csio_scsi_intx_handler() argument
304 struct csio_hw *hw = (struct csio_hw *) dev_id; csio_fcoe_isr() local
310 if (unlikely(!hw)) csio_fcoe_isr()
313 if (unlikely(pci_channel_offline(hw->pdev))) { csio_fcoe_isr()
314 CSIO_INC_STATS(hw, n_pcich_offline); csio_fcoe_isr()
319 if (hw->intr_mode == CSIO_IM_INTX) csio_fcoe_isr()
320 csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI_A)); csio_fcoe_isr()
326 if (csio_hw_slow_intr_handler(hw)) csio_fcoe_isr()
330 intx_q = csio_get_q(hw, hw->intr_iq_idx); csio_fcoe_isr()
335 if (likely(csio_wr_process_iq(hw, intx_q, NULL, NULL) == 0)) csio_fcoe_isr()
338 spin_lock_irqsave(&hw->lock, flags); csio_fcoe_isr()
339 rv = csio_mb_isr_handler(hw); csio_fcoe_isr()
340 if (rv == 0 && !(hw->flags & CSIO_HWF_FWEVT_PENDING)) { csio_fcoe_isr()
341 hw->flags |= CSIO_HWF_FWEVT_PENDING; csio_fcoe_isr()
342 spin_unlock_irqrestore(&hw->lock, flags); csio_fcoe_isr()
343 schedule_work(&hw->evtq_work); csio_fcoe_isr()
346 spin_unlock_irqrestore(&hw->lock, flags); csio_fcoe_isr()
352 csio_add_msix_desc(struct csio_hw *hw) csio_add_msix_desc() argument
355 struct csio_msix_entries *entryp = &hw->msix_entries[0]; csio_add_msix_desc()
358 int cnt = hw->num_sqsets + k; csio_add_msix_desc()
363 CSIO_PCI_BUS(hw), CSIO_PCI_DEV(hw), CSIO_PCI_FUNC(hw)); csio_add_msix_desc()
368 CSIO_PCI_BUS(hw), CSIO_PCI_DEV(hw), CSIO_PCI_FUNC(hw)); csio_add_msix_desc()
375 CSIO_PCI_BUS(hw), CSIO_PCI_DEV(hw), csio_add_msix_desc()
376 CSIO_PCI_FUNC(hw), i - CSIO_EXTRA_VECS); csio_add_msix_desc()
381 csio_request_irqs(struct csio_hw *hw) csio_request_irqs() argument
384 struct csio_msix_entries *entryp = &hw->msix_entries[0]; csio_request_irqs()
387 if (hw->intr_mode != CSIO_IM_MSIX) { csio_request_irqs()
388 rv = request_irq(hw->pdev->irq, csio_fcoe_isr, csio_request_irqs()
389 (hw->intr_mode == CSIO_IM_MSI) ? csio_request_irqs()
391 KBUILD_MODNAME, hw); csio_request_irqs()
393 if (hw->intr_mode == CSIO_IM_MSI) csio_request_irqs()
394 pci_disable_msi(hw->pdev); csio_request_irqs()
395 csio_err(hw, "Failed to allocate interrupt line.\n"); csio_request_irqs()
403 csio_add_msix_desc(hw); csio_request_irqs()
406 entryp[k].desc, hw); csio_request_irqs()
408 csio_err(hw, "IRQ request failed for vec %d err:%d\n", csio_request_irqs()
413 entryp[k++].dev_id = (void *)hw; csio_request_irqs()
416 entryp[k].desc, hw); csio_request_irqs()
418 csio_err(hw, "IRQ request failed for vec %d err:%d\n", csio_request_irqs()
423 entryp[k++].dev_id = (void *)hw; csio_request_irqs()
426 for (i = 0; i < hw->num_pports; i++) { csio_request_irqs()
427 info = &hw->scsi_cpu_info[i]; csio_request_irqs()
429 struct csio_scsi_qset *sqset = &hw->sqset[i][j]; csio_request_irqs()
430 struct csio_q *q = hw->wrm.q_arr[sqset->iq_idx]; csio_request_irqs()
435 csio_err(hw, csio_request_irqs()
447 hw->flags |= CSIO_HWF_HOST_INTR_ENABLED; csio_request_irqs()
453 entryp = &hw->msix_entries[i]; csio_request_irqs()
456 pci_disable_msix(hw->pdev); csio_request_irqs()
462 csio_disable_msix(struct csio_hw *hw, bool free) csio_disable_msix() argument
466 int cnt = hw->num_sqsets + CSIO_EXTRA_VECS; csio_disable_msix()
470 entryp = &hw->msix_entries[i]; csio_disable_msix()
474 pci_disable_msix(hw->pdev); csio_disable_msix()
479 csio_reduce_sqsets(struct csio_hw *hw, int cnt) csio_reduce_sqsets() argument
484 while (cnt < hw->num_sqsets) { csio_reduce_sqsets()
485 for (i = 0; i < hw->num_pports; i++) { csio_reduce_sqsets()
486 info = &hw->scsi_cpu_info[i]; csio_reduce_sqsets()
489 hw->num_sqsets--; csio_reduce_sqsets()
490 if (hw->num_sqsets <= cnt) csio_reduce_sqsets()
496 csio_dbg(hw, "Reduced sqsets to %d\n", hw->num_sqsets); csio_reduce_sqsets()
500 csio_enable_msix(struct csio_hw *hw) csio_enable_msix() argument
508 min = hw->num_pports + extra; csio_enable_msix()
509 cnt = hw->num_sqsets + extra; csio_enable_msix()
512 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS || !csio_is_hw_master(hw)) csio_enable_msix()
513 cnt = min_t(uint8_t, hw->cfg_niq, cnt); csio_enable_msix()
522 csio_dbg(hw, "FW supp #niq:%d, trying %d msix's\n", hw->cfg_niq, cnt); csio_enable_msix()
524 cnt = pci_enable_msix_range(hw->pdev, entries, min, cnt); csio_enable_msix()
530 if (cnt < (hw->num_sqsets + extra)) { csio_enable_msix()
531 csio_dbg(hw, "Reducing sqsets to %d\n", cnt - extra); csio_enable_msix()
532 csio_reduce_sqsets(hw, cnt - extra); csio_enable_msix()
537 entryp = &hw->msix_entries[i]; csio_enable_msix()
543 csio_set_nondata_intr_idx(hw, entries[k].entry); csio_enable_msix()
544 csio_set_mb_intr_idx(csio_hw_to_mbm(hw), entries[k++].entry); csio_enable_msix()
545 csio_set_fwevt_intr_idx(hw, entries[k++].entry); csio_enable_msix()
547 for (i = 0; i < hw->num_pports; i++) { csio_enable_msix()
548 info = &hw->scsi_cpu_info[i]; csio_enable_msix()
550 for (j = 0; j < hw->num_scsi_msix_cpus; j++) { csio_enable_msix()
552 hw->sqset[i][j].intr_idx = entries[n].entry; csio_enable_msix()
563 csio_intr_enable(struct csio_hw *hw) csio_intr_enable() argument
565 hw->intr_mode = CSIO_IM_NONE; csio_intr_enable()
566 hw->flags &= ~CSIO_HWF_HOST_INTR_ENABLED; csio_intr_enable()
569 if ((csio_msi == 2) && !csio_enable_msix(hw)) csio_intr_enable()
570 hw->intr_mode = CSIO_IM_MSIX; csio_intr_enable()
573 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS || csio_intr_enable()
574 !csio_is_hw_master(hw)) { csio_intr_enable()
577 if (hw->cfg_niq < (hw->num_sqsets + extra)) { csio_intr_enable()
578 csio_dbg(hw, "Reducing sqsets to %d\n", csio_intr_enable()
579 hw->cfg_niq - extra); csio_intr_enable()
580 csio_reduce_sqsets(hw, hw->cfg_niq - extra); csio_intr_enable()
584 if ((csio_msi == 1) && !pci_enable_msi(hw->pdev)) csio_intr_enable()
585 hw->intr_mode = CSIO_IM_MSI; csio_intr_enable()
587 hw->intr_mode = CSIO_IM_INTX; csio_intr_enable()
590 csio_dbg(hw, "Using %s interrupt mode.\n", csio_intr_enable()
591 (hw->intr_mode == CSIO_IM_MSIX) ? "MSIX" : csio_intr_enable()
592 ((hw->intr_mode == CSIO_IM_MSI) ? "MSI" : "INTx")); csio_intr_enable()
596 csio_intr_disable(struct csio_hw *hw, bool free) csio_intr_disable() argument
598 csio_hw_intr_disable(hw); csio_intr_disable()
600 switch (hw->intr_mode) { csio_intr_disable()
602 csio_disable_msix(hw, free); csio_intr_disable()
606 free_irq(hw->pdev->irq, hw); csio_intr_disable()
607 pci_disable_msi(hw->pdev); csio_intr_disable()
611 free_irq(hw->pdev->irq, hw); csio_intr_disable()
616 hw->intr_mode = CSIO_IM_NONE; csio_intr_disable()
617 hw->flags &= ~CSIO_HWF_HOST_INTR_ENABLED; csio_intr_disable()
H A Dcsio_init.c69 struct csio_hw *hw = file->private_data - mem; csio_mem_read() local
84 ret = hw->chip_ops->chip_mc_read(hw, 0, pos, csio_mem_read()
87 ret = hw->chip_ops->chip_edc_read(hw, mem, pos, csio_mem_read()
113 void csio_add_debugfs_mem(struct csio_hw *hw, const char *name, csio_add_debugfs_mem() argument
116 debugfs_create_file_size(name, S_IRUSR, hw->debugfs_root, csio_add_debugfs_mem()
117 (void *)hw + idx, &csio_mem_debugfs_fops, csio_add_debugfs_mem()
121 static int csio_setup_debugfs(struct csio_hw *hw) csio_setup_debugfs() argument
125 if (IS_ERR_OR_NULL(hw->debugfs_root)) csio_setup_debugfs()
128 i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A); csio_setup_debugfs()
130 csio_add_debugfs_mem(hw, "edc0", MEM_EDC0, 5); csio_setup_debugfs()
132 csio_add_debugfs_mem(hw, "edc1", MEM_EDC1, 5); csio_setup_debugfs()
134 hw->chip_ops->chip_dfs_create_ext_mem(hw); csio_setup_debugfs()
139 * csio_dfs_create - Creates and sets up per-hw debugfs.
143 csio_dfs_create(struct csio_hw *hw) csio_dfs_create() argument
146 hw->debugfs_root = debugfs_create_dir(pci_name(hw->pdev), csio_dfs_create()
148 csio_setup_debugfs(hw); csio_dfs_create()
155 * csio_dfs_destroy - Destroys per-hw debugfs.
158 csio_dfs_destroy(struct csio_hw *hw) csio_dfs_destroy() argument
160 if (hw->debugfs_root) csio_dfs_destroy()
161 debugfs_remove_recursive(hw->debugfs_root); csio_dfs_destroy()
248 * @hw: HW module.
252 csio_hw_init_workers(struct csio_hw *hw) csio_hw_init_workers() argument
254 INIT_WORK(&hw->evtq_work, csio_evtq_worker); csio_hw_init_workers()
258 csio_hw_exit_workers(struct csio_hw *hw) csio_hw_exit_workers() argument
260 cancel_work_sync(&hw->evtq_work); csio_hw_exit_workers()
265 csio_create_queues(struct csio_hw *hw) csio_create_queues() argument
268 struct csio_mgmtm *mgmtm = csio_hw_to_mgmtm(hw); csio_create_queues()
272 if (hw->flags & CSIO_HWF_Q_FW_ALLOCED) csio_create_queues()
275 if (hw->intr_mode != CSIO_IM_MSIX) { csio_create_queues()
276 rv = csio_wr_iq_create(hw, NULL, hw->intr_iq_idx, csio_create_queues()
277 0, hw->pport[0].portid, false, NULL); csio_create_queues()
279 csio_err(hw, " Forward Interrupt IQ failed!: %d\n", rv); csio_create_queues()
285 rv = csio_wr_iq_create(hw, NULL, hw->fwevt_iq_idx, csio_create_queues()
286 csio_get_fwevt_intr_idx(hw), csio_create_queues()
287 hw->pport[0].portid, true, NULL); csio_create_queues()
289 csio_err(hw, "FW event IQ config failed!: %d\n", rv); csio_create_queues()
294 rv = csio_wr_eq_create(hw, NULL, mgmtm->eq_idx, csio_create_queues()
295 mgmtm->iq_idx, hw->pport[0].portid, NULL); csio_create_queues()
298 csio_err(hw, "Mgmt EQ create failed!: %d\n", rv); csio_create_queues()
303 for (i = 0; i < hw->num_pports; i++) { csio_create_queues()
304 info = &hw->scsi_cpu_info[i]; csio_create_queues()
307 struct csio_scsi_qset *sqset = &hw->sqset[i][j]; csio_create_queues()
309 rv = csio_wr_iq_create(hw, NULL, sqset->iq_idx, csio_create_queues()
312 csio_err(hw, csio_create_queues()
317 rv = csio_wr_eq_create(hw, NULL, sqset->eq_idx, csio_create_queues()
320 csio_err(hw, csio_create_queues()
328 hw->flags |= CSIO_HWF_Q_FW_ALLOCED; csio_create_queues()
331 csio_wr_destroy_queues(hw, true); csio_create_queues()
337 * @hw: HW module.
342 csio_config_queues(struct csio_hw *hw) csio_config_queues() argument
347 struct csio_mgmtm *mgmtm = csio_hw_to_mgmtm(hw); csio_config_queues()
351 if (hw->flags & CSIO_HWF_Q_MEM_ALLOCED) csio_config_queues()
352 return csio_create_queues(hw); csio_config_queues()
355 hw->num_scsi_msix_cpus = num_online_cpus(); csio_config_queues()
356 hw->num_sqsets = num_online_cpus() * hw->num_pports; csio_config_queues()
358 if (hw->num_sqsets > CSIO_MAX_SCSI_QSETS) { csio_config_queues()
359 hw->num_sqsets = CSIO_MAX_SCSI_QSETS; csio_config_queues()
360 hw->num_scsi_msix_cpus = CSIO_MAX_SCSI_CPU; csio_config_queues()
364 for (i = 0; i < hw->num_pports; i++) csio_config_queues()
365 hw->scsi_cpu_info[i].max_cpus = hw->num_scsi_msix_cpus; csio_config_queues()
367 csio_dbg(hw, "nsqsets:%d scpus:%d\n", csio_config_queues()
368 hw->num_sqsets, hw->num_scsi_msix_cpus); csio_config_queues()
370 csio_intr_enable(hw); csio_config_queues()
372 if (hw->intr_mode != CSIO_IM_MSIX) { csio_config_queues()
375 hw->intr_iq_idx = csio_wr_alloc_q(hw, CSIO_INTR_IQSIZE, csio_config_queues()
377 (void *)hw, 0, 0, NULL); csio_config_queues()
378 if (hw->intr_iq_idx == -1) { csio_config_queues()
379 csio_err(hw, csio_config_queues()
386 hw->fwevt_iq_idx = csio_wr_alloc_q(hw, CSIO_FWEVT_IQSIZE, csio_config_queues()
388 CSIO_INGRESS, (void *)hw, csio_config_queues()
391 if (hw->fwevt_iq_idx == -1) { csio_config_queues()
392 csio_err(hw, "FW evt queue creation failed\n"); csio_config_queues()
397 mgmtm->eq_idx = csio_wr_alloc_q(hw, CSIO_MGMT_EQSIZE, csio_config_queues()
399 CSIO_EGRESS, (void *)hw, 0, 0, NULL); csio_config_queues()
401 csio_err(hw, "Failed to alloc egress queue for mgmt module\n"); csio_config_queues()
406 mgmtm->iq_idx = hw->fwevt_iq_idx; csio_config_queues()
409 for (i = 0; i < hw->num_pports; i++) { csio_config_queues()
410 info = &hw->scsi_cpu_info[i]; csio_config_queues()
412 for (j = 0; j < hw->num_scsi_msix_cpus; j++) { csio_config_queues()
413 sqset = &hw->sqset[i][j]; csio_config_queues()
417 orig = &hw->sqset[i][k]; csio_config_queues()
423 idx = csio_wr_alloc_q(hw, csio_scsi_eqsize, 0, csio_config_queues()
424 CSIO_EGRESS, (void *)hw, 0, 0, csio_config_queues()
427 csio_err(hw, "EQ creation failed for idx:%d\n", csio_config_queues()
434 idx = csio_wr_alloc_q(hw, CSIO_SCSI_IQSIZE, csio_config_queues()
436 (void *)hw, 0, 0, csio_config_queues()
439 csio_err(hw, "IQ creation failed for idx:%d\n", csio_config_queues()
447 hw->flags |= CSIO_HWF_Q_MEM_ALLOCED; csio_config_queues()
449 rv = csio_create_queues(hw); csio_config_queues()
457 rv = csio_request_irqs(hw); csio_config_queues()
464 csio_intr_disable(hw, false); csio_config_queues()
470 csio_resource_alloc(struct csio_hw *hw) csio_resource_alloc() argument
472 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_resource_alloc()
478 hw->mb_mempool = mempool_create_kmalloc_pool(CSIO_MIN_MEMPOOL_SZ, csio_resource_alloc()
480 if (!hw->mb_mempool) csio_resource_alloc()
483 hw->rnode_mempool = mempool_create_kmalloc_pool(CSIO_MIN_MEMPOOL_SZ, csio_resource_alloc()
485 if (!hw->rnode_mempool) csio_resource_alloc()
488 hw->scsi_pci_pool = pci_pool_create("csio_scsi_pci_pool", hw->pdev, csio_resource_alloc()
490 if (!hw->scsi_pci_pool) csio_resource_alloc()
496 mempool_destroy(hw->rnode_mempool); csio_resource_alloc()
497 hw->rnode_mempool = NULL; csio_resource_alloc()
499 mempool_destroy(hw->mb_mempool); csio_resource_alloc()
500 hw->mb_mempool = NULL; csio_resource_alloc()
506 csio_resource_free(struct csio_hw *hw) csio_resource_free() argument
508 pci_pool_destroy(hw->scsi_pci_pool); csio_resource_free()
509 hw->scsi_pci_pool = NULL; csio_resource_free()
510 mempool_destroy(hw->rnode_mempool); csio_resource_free()
511 hw->rnode_mempool = NULL; csio_resource_free()
512 mempool_destroy(hw->mb_mempool); csio_resource_free()
513 hw->mb_mempool = NULL; csio_resource_free()
525 struct csio_hw *hw; csio_hw_alloc() local
527 hw = kzalloc(sizeof(struct csio_hw), GFP_KERNEL); csio_hw_alloc()
528 if (!hw) csio_hw_alloc()
531 hw->pdev = pdev; csio_hw_alloc()
532 strncpy(hw->drv_version, CSIO_DRV_VERSION, 32); csio_hw_alloc()
535 if (csio_resource_alloc(hw)) csio_hw_alloc()
539 hw->regstart = ioremap_nocache(pci_resource_start(pdev, 0), csio_hw_alloc()
541 if (!hw->regstart) { csio_hw_alloc()
542 csio_err(hw, "Could not map BAR 0, regstart = %p\n", csio_hw_alloc()
543 hw->regstart); csio_hw_alloc()
547 csio_hw_init_workers(hw); csio_hw_alloc()
549 if (csio_hw_init(hw)) csio_hw_alloc()
552 csio_dfs_create(hw); csio_hw_alloc()
554 csio_dbg(hw, "hw:%p\n", hw); csio_hw_alloc()
556 return hw; csio_hw_alloc()
559 csio_hw_exit_workers(hw); csio_hw_alloc()
560 iounmap(hw->regstart); csio_hw_alloc()
562 csio_resource_free(hw); csio_hw_alloc()
564 kfree(hw); csio_hw_alloc()
571 * @hw: The HW module
573 * Disable interrupts, uninit the HW module, free resources, free hw.
576 csio_hw_free(struct csio_hw *hw) csio_hw_free() argument
578 csio_intr_disable(hw, true); csio_hw_free()
579 csio_hw_exit_workers(hw); csio_hw_free()
580 csio_hw_exit(hw); csio_hw_free()
581 iounmap(hw->regstart); csio_hw_free()
582 csio_dfs_destroy(hw); csio_hw_free()
583 csio_resource_free(hw); csio_hw_free()
584 kfree(hw); csio_hw_free()
589 * @hw: The HW module.
600 csio_shost_init(struct csio_hw *hw, struct device *dev, csio_shost_init() argument
610 * hw->pdev is the physical port's PCI dev structure, csio_shost_init()
613 if (dev == &hw->pdev->dev) csio_shost_init()
636 hw->fres_info.max_ssns); csio_shost_init()
638 if (dev == &hw->pdev->dev) csio_shost_init()
644 if (!hw->rln) csio_shost_init()
645 hw->rln = ln; csio_shost_init()
648 if (csio_lnode_init(ln, hw, pln)) csio_shost_init()
673 struct csio_hw *hw = csio_lnode_to_hw(ln); csio_shost_exit() local
684 spin_lock_irq(&hw->lock); csio_shost_exit()
685 csio_evtq_flush(hw); csio_shost_exit()
686 spin_unlock_irq(&hw->lock); csio_shost_exit()
693 csio_lnode_alloc(struct csio_hw *hw) csio_lnode_alloc() argument
695 return csio_shost_init(hw, &hw->pdev->dev, false, NULL); csio_lnode_alloc()
699 csio_lnodes_block_request(struct csio_hw *hw) csio_lnodes_block_request() argument
708 lnode_list = kzalloc((sizeof(struct csio_lnode *) * hw->num_lns), csio_lnodes_block_request()
711 csio_err(hw, "Failed to allocate lnodes_list"); csio_lnodes_block_request()
715 spin_lock_irq(&hw->lock); csio_lnodes_block_request()
717 list_for_each(cur_ln, &hw->sln_head) { csio_lnodes_block_request()
725 spin_unlock_irq(&hw->lock); csio_lnodes_block_request()
728 csio_dbg(hw, "Blocking IOs on lnode: %p\n", lnode_list[ii]); csio_lnodes_block_request()
738 csio_lnodes_unblock_request(struct csio_hw *hw) csio_lnodes_unblock_request() argument
747 lnode_list = kzalloc((sizeof(struct csio_lnode *) * hw->num_lns), csio_lnodes_unblock_request()
750 csio_err(hw, "Failed to allocate lnodes_list"); csio_lnodes_unblock_request()
754 spin_lock_irq(&hw->lock); csio_lnodes_unblock_request()
756 list_for_each(cur_ln, &hw->sln_head) { csio_lnodes_unblock_request()
764 spin_unlock_irq(&hw->lock); csio_lnodes_unblock_request()
767 csio_dbg(hw, "unblocking IOs on lnode: %p\n", lnode_list[ii]); csio_lnodes_unblock_request()
776 csio_lnodes_block_by_port(struct csio_hw *hw, uint8_t portid) csio_lnodes_block_by_port() argument
785 lnode_list = kzalloc((sizeof(struct csio_lnode *) * hw->num_lns), csio_lnodes_block_by_port()
788 csio_err(hw, "Failed to allocate lnodes_list"); csio_lnodes_block_by_port()
792 spin_lock_irq(&hw->lock); csio_lnodes_block_by_port()
794 list_for_each(cur_ln, &hw->sln_head) { csio_lnodes_block_by_port()
805 spin_unlock_irq(&hw->lock); csio_lnodes_block_by_port()
808 csio_dbg(hw, "Blocking IOs on lnode: %p\n", lnode_list[ii]); csio_lnodes_block_by_port()
817 csio_lnodes_unblock_by_port(struct csio_hw *hw, uint8_t portid) csio_lnodes_unblock_by_port() argument
826 lnode_list = kzalloc((sizeof(struct csio_lnode *) * hw->num_lns), csio_lnodes_unblock_by_port()
829 csio_err(hw, "Failed to allocate lnodes_list"); csio_lnodes_unblock_by_port()
833 spin_lock_irq(&hw->lock); csio_lnodes_unblock_by_port()
835 list_for_each(cur_ln, &hw->sln_head) { csio_lnodes_unblock_by_port()
845 spin_unlock_irq(&hw->lock); csio_lnodes_unblock_by_port()
848 csio_dbg(hw, "unblocking IOs on lnode: %p\n", lnode_list[ii]); csio_lnodes_unblock_by_port()
857 csio_lnodes_exit(struct csio_hw *hw, bool npiv) csio_lnodes_exit() argument
865 lnode_list = kzalloc((sizeof(struct csio_lnode *) * hw->num_lns), csio_lnodes_exit()
868 csio_err(hw, "lnodes_exit: Failed to allocate lnodes_list.\n"); csio_lnodes_exit()
873 spin_lock_irq(&hw->lock); csio_lnodes_exit()
874 list_for_each(cur_ln, &hw->sln_head) { csio_lnodes_exit()
881 spin_unlock_irq(&hw->lock); csio_lnodes_exit()
885 csio_dbg(hw, "Deleting child lnode: %p\n", lnode_list[ii]); csio_lnodes_exit()
896 spin_lock_irq(&hw->lock); csio_lnodes_exit()
898 list_for_each(cur_ln, &hw->sln_head) { csio_lnodes_exit()
902 spin_unlock_irq(&hw->lock); csio_lnodes_exit()
906 csio_dbg(hw, "Deleting parent lnode: %p\n", lnode_list[ii]); csio_lnodes_exit()
952 struct csio_hw *hw; csio_probe_one() local
963 hw = csio_hw_alloc(pdev); csio_probe_one()
964 if (!hw) { csio_probe_one()
969 pci_set_drvdata(pdev, hw); csio_probe_one()
971 if (csio_hw_start(hw) != 0) { csio_probe_one()
977 sprintf(hw->fwrev_str, "%u.%u.%u.%u\n", csio_probe_one()
978 FW_HDR_FW_VER_MAJOR_G(hw->fwrev), csio_probe_one()
979 FW_HDR_FW_VER_MINOR_G(hw->fwrev), csio_probe_one()
980 FW_HDR_FW_VER_MICRO_G(hw->fwrev), csio_probe_one()
981 FW_HDR_FW_VER_BUILD_G(hw->fwrev)); csio_probe_one()
983 for (i = 0; i < hw->num_pports; i++) { csio_probe_one()
984 ln = csio_shost_init(hw, &pdev->dev, true, NULL); csio_probe_one()
990 ln->portid = hw->pport[i].portid; csio_probe_one()
992 spin_lock_irq(&hw->lock); csio_probe_one()
995 spin_unlock_irq(&hw->lock); csio_probe_one()
1009 csio_lnodes_block_request(hw); csio_probe_one()
1010 spin_lock_irq(&hw->lock); csio_probe_one()
1011 csio_hw_stop(hw); csio_probe_one()
1012 spin_unlock_irq(&hw->lock); csio_probe_one()
1013 csio_lnodes_unblock_request(hw); csio_probe_one()
1014 csio_lnodes_exit(hw, 0); csio_probe_one()
1015 csio_hw_free(hw); csio_probe_one()
1031 struct csio_hw *hw = pci_get_drvdata(pdev); csio_remove_one() local
1034 csio_lnodes_block_request(hw); csio_remove_one()
1035 spin_lock_irq(&hw->lock); csio_remove_one()
1041 csio_hw_stop(hw); csio_remove_one()
1042 spin_unlock_irq(&hw->lock); csio_remove_one()
1043 csio_lnodes_unblock_request(hw); csio_remove_one()
1045 csio_lnodes_exit(hw, 0); csio_remove_one()
1046 csio_hw_free(hw); csio_remove_one()
1058 struct csio_hw *hw = pci_get_drvdata(pdev); csio_pci_error_detected() local
1060 csio_lnodes_block_request(hw); csio_pci_error_detected()
1061 spin_lock_irq(&hw->lock); csio_pci_error_detected()
1067 csio_post_event(&hw->sm, CSIO_HWE_PCIERR_DETECTED); csio_pci_error_detected()
1068 spin_unlock_irq(&hw->lock); csio_pci_error_detected()
1069 csio_lnodes_unblock_request(hw); csio_pci_error_detected()
1070 csio_lnodes_exit(hw, 0); csio_pci_error_detected()
1071 csio_intr_disable(hw, true); csio_pci_error_detected()
1085 struct csio_hw *hw = pci_get_drvdata(pdev); csio_pci_slot_reset() local
1101 spin_lock_irq(&hw->lock); csio_pci_slot_reset()
1102 csio_post_event(&hw->sm, CSIO_HWE_PCIERR_SLOT_RESET); csio_pci_slot_reset()
1103 ready = csio_is_hw_ready(hw); csio_pci_slot_reset()
1104 spin_unlock_irq(&hw->lock); csio_pci_slot_reset()
1122 struct csio_hw *hw = pci_get_drvdata(pdev); csio_pci_resume() local
1129 for (i = 0; i < hw->num_pports; i++) { csio_pci_resume()
1130 ln = csio_shost_init(hw, &pdev->dev, true, NULL); csio_pci_resume()
1136 ln->portid = hw->pport[i].portid; csio_pci_resume()
1138 spin_lock_irq(&hw->lock); csio_pci_resume()
1141 spin_unlock_irq(&hw->lock); csio_pci_resume()
1155 csio_lnodes_block_request(hw); csio_pci_resume()
1156 spin_lock_irq(&hw->lock); csio_pci_resume()
1157 csio_hw_stop(hw); csio_pci_resume()
1158 spin_unlock_irq(&hw->lock); csio_pci_resume()
1159 csio_lnodes_unblock_request(hw); csio_pci_resume()
1160 csio_lnodes_exit(hw, 0); csio_pci_resume()
1161 csio_hw_free(hw); csio_pci_resume()
H A Dcsio_hw.c102 static void csio_hw_initialize(struct csio_hw *hw);
103 static void csio_evtq_stop(struct csio_hw *hw);
104 static void csio_evtq_start(struct csio_hw *hw);
106 int csio_is_hw_ready(struct csio_hw *hw) csio_is_hw_ready() argument
108 return csio_match_state(hw, csio_hws_ready); csio_is_hw_ready()
111 int csio_is_hw_removing(struct csio_hw *hw) csio_is_hw_removing() argument
113 return csio_match_state(hw, csio_hws_removing); csio_is_hw_removing()
119 * @hw: the HW module
133 csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, csio_hw_wait_op_done_val() argument
138 val = csio_rd_reg32(hw, reg); csio_hw_wait_op_done_val()
155 * @hw: the adapter
163 csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr, csio_hw_tp_wr_bits_indirect() argument
166 csio_wr_reg32(hw, addr, TP_PIO_ADDR_A); csio_hw_tp_wr_bits_indirect()
167 val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask; csio_hw_tp_wr_bits_indirect()
168 csio_wr_reg32(hw, val, TP_PIO_DATA_A); csio_hw_tp_wr_bits_indirect()
172 csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask, csio_set_reg_field() argument
175 uint32_t val = csio_rd_reg32(hw, reg) & ~mask; csio_set_reg_field()
177 csio_wr_reg32(hw, val | value, reg); csio_set_reg_field()
179 csio_rd_reg32(hw, reg); csio_set_reg_field()
184 csio_memory_write(struct csio_hw *hw, int mtype, u32 addr, u32 len, u32 *buf) csio_memory_write() argument
186 return hw->chip_ops->chip_memory_rw(hw, MEMWIN_CSIOSTOR, mtype, csio_memory_write()
203 * @hw: hw to read
212 csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data) csio_hw_seeprom_read() argument
216 uint32_t base = hw->params.pci.vpd_cap_addr; csio_hw_seeprom_read()
221 pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr); csio_hw_seeprom_read()
225 pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val); csio_hw_seeprom_read()
229 csio_err(hw, "reading EEPROM address 0x%x failed\n", addr); csio_hw_seeprom_read()
233 pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data); csio_hw_seeprom_read()
297 * @hw: HW module
303 csio_hw_get_vpd_params(struct csio_hw *hw, struct csio_vpd *p) csio_hw_get_vpd_params() argument
311 if (csio_is_valid_vpd(hw)) csio_hw_get_vpd_params()
314 ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD, csio_hw_get_vpd_params()
315 &hw->params.pci.vpd_cap_addr); csio_hw_get_vpd_params()
327 ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd)); csio_hw_get_vpd_params()
331 ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i)); csio_hw_get_vpd_params()
339 hw->flags &= (~CSIO_HWF_VPD_VALID); csio_hw_get_vpd_params()
346 csio_err(hw, "missing VPD keyword " name "\n"); \ csio_hw_get_vpd_params()
357 csio_err(hw, "corrupted VPD EEPROM, actual csum %u\n", csum); csio_hw_get_vpd_params()
373 csio_valid_vpd_copied(hw); csio_hw_get_vpd_params()
381 * @hw: the HW module
392 csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont, csio_hw_sf1_read() argument
399 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) csio_hw_sf1_read()
402 csio_wr_reg32(hw, SF_LOCK_V(lock) | SF_CONT_V(cont) | csio_hw_sf1_read()
404 ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, csio_hw_sf1_read()
407 *valp = csio_rd_reg32(hw, SF_DATA_A); csio_hw_sf1_read()
413 * @hw: the HW module
424 csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont, csio_hw_sf1_write() argument
429 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) csio_hw_sf1_write()
432 csio_wr_reg32(hw, val, SF_DATA_A); csio_hw_sf1_write()
433 csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | csio_hw_sf1_write()
436 return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, csio_hw_sf1_write()
442 * @hw: the HW module
449 csio_hw_flash_wait_op(struct csio_hw *hw, int32_t attempts, int32_t delay) csio_hw_flash_wait_op() argument
455 ret = csio_hw_sf1_write(hw, 1, 1, 1, SF_RD_STATUS); csio_hw_flash_wait_op()
459 ret = csio_hw_sf1_read(hw, 1, 0, 1, &status); csio_hw_flash_wait_op()
474 * @hw: the HW module
486 csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords, csio_hw_read_flash() argument
491 if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3)) csio_hw_read_flash()
496 ret = csio_hw_sf1_write(hw, 4, 1, 0, addr); csio_hw_read_flash()
500 ret = csio_hw_sf1_read(hw, 1, 1, 0, data); csio_hw_read_flash()
505 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data); csio_hw_read_flash()
507 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ csio_hw_read_flash()
518 * @hw: the hw
527 csio_hw_write_flash(struct csio_hw *hw, uint32_t addr, csio_hw_write_flash() argument
534 if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE) csio_hw_write_flash()
539 ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); csio_hw_write_flash()
543 ret = csio_hw_sf1_write(hw, 4, 1, 1, val); csio_hw_write_flash()
552 ret = csio_hw_sf1_write(hw, c, c != left, 1, val); csio_hw_write_flash()
556 ret = csio_hw_flash_wait_op(hw, 8, 1); csio_hw_write_flash()
560 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ csio_hw_write_flash()
563 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); csio_hw_write_flash()
568 csio_err(hw, csio_hw_write_flash()
577 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ csio_hw_write_flash()
583 * @hw: the HW module
590 csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end) csio_hw_flash_erase_sectors() argument
596 ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); csio_hw_flash_erase_sectors()
600 ret = csio_hw_sf1_write(hw, 4, 0, 1, csio_hw_flash_erase_sectors()
605 ret = csio_hw_flash_wait_op(hw, 14, 500); csio_hw_flash_erase_sectors()
613 csio_err(hw, "erase of flash sector %d failed, error %d\n", csio_hw_flash_erase_sectors()
615 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ csio_hw_flash_erase_sectors()
620 csio_hw_print_fw_version(struct csio_hw *hw, char *str) csio_hw_print_fw_version() argument
622 csio_info(hw, "%s: %u.%u.%u.%u\n", str, csio_hw_print_fw_version()
623 FW_HDR_FW_VER_MAJOR_G(hw->fwrev), csio_hw_print_fw_version()
624 FW_HDR_FW_VER_MINOR_G(hw->fwrev), csio_hw_print_fw_version()
625 FW_HDR_FW_VER_MICRO_G(hw->fwrev), csio_hw_print_fw_version()
626 FW_HDR_FW_VER_BUILD_G(hw->fwrev)); csio_hw_print_fw_version()
631 * @hw: HW module
637 csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers) csio_hw_get_fw_version() argument
639 return csio_hw_read_flash(hw, FLASH_FW_START + csio_hw_get_fw_version()
646 * @hw: HW module
652 csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers) csio_hw_get_tp_version() argument
654 return csio_hw_read_flash(hw, FLASH_FW_START + csio_hw_get_tp_version()
661 * @hw: HW module
668 csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size) csio_hw_fw_dload() argument
679 if ((!hw->params.sf_size) || (!hw->params.sf_nsec)) { csio_hw_fw_dload()
680 csio_err(hw, "Serial Flash data invalid\n"); csio_hw_fw_dload()
685 csio_err(hw, "FW image has no data\n"); csio_hw_fw_dload()
690 csio_err(hw, "FW image size not multiple of 512 bytes\n"); csio_hw_fw_dload()
695 csio_err(hw, "FW image size differs from size in FW header\n"); csio_hw_fw_dload()
700 csio_err(hw, "FW image too large, max is %u bytes\n", csio_hw_fw_dload()
709 csio_err(hw, "corrupted firmware image, checksum %#x\n", csum); csio_hw_fw_dload()
713 sf_sec_size = hw->params.sf_size / hw->params.sf_nsec; csio_hw_fw_dload()
716 csio_dbg(hw, "Erasing sectors... start:%d end:%d\n", csio_hw_fw_dload()
719 ret = csio_hw_flash_erase_sectors(hw, FLASH_FW_START_SEC, csio_hw_fw_dload()
722 csio_err(hw, "Flash Erase failed\n"); csio_hw_fw_dload()
733 ret = csio_hw_write_flash(hw, FLASH_FW_START, SF_PAGE_SIZE, first_page); csio_hw_fw_dload()
737 csio_dbg(hw, "Writing Flash .. start:%d end:%d\n", csio_hw_fw_dload()
744 ret = csio_hw_write_flash(hw, addr, SF_PAGE_SIZE, fw_data); csio_hw_fw_dload()
749 ret = csio_hw_write_flash(hw, csio_hw_fw_dload()
757 csio_err(hw, "firmware download failed, error %d\n", ret); csio_hw_fw_dload()
762 csio_hw_get_flash_params(struct csio_hw *hw) csio_hw_get_flash_params() argument
767 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID); csio_hw_get_flash_params()
769 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info); csio_hw_get_flash_params()
770 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ csio_hw_get_flash_params()
778 hw->params.sf_nsec = 1 << (info - 16); csio_hw_get_flash_params()
780 hw->params.sf_nsec = 64; csio_hw_get_flash_params()
783 hw->params.sf_size = 1 << info; csio_hw_get_flash_params()
793 csio_hw_dev_ready(struct csio_hw *hw) csio_hw_dev_ready() argument
798 while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) && csio_hw_dev_ready()
804 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt); csio_hw_dev_ready()
808 hw->pfn = SOURCEPF_G(reg); csio_hw_dev_ready()
815 * @hw: HW module
821 csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state) csio_do_hello() argument
832 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_do_hello()
835 CSIO_INC_STATS(hw, n_err_nomem); csio_do_hello()
840 csio_mb_hello(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, csio_do_hello()
841 hw->pfn, CSIO_MASTER_MAY, NULL); csio_do_hello()
843 rv = csio_mb_issue(hw, mbp); csio_do_hello()
845 csio_err(hw, "failed to issue HELLO cmd. ret:%d.\n", rv); csio_do_hello()
849 csio_mb_process_hello_rsp(hw, mbp, &retval, state, &mpfn); csio_do_hello()
851 csio_err(hw, "HELLO cmd failed with ret: %d\n", retval); csio_do_hello()
857 if (hw->pfn == mpfn) { csio_do_hello()
858 hw->flags |= CSIO_HWF_MASTER; csio_do_hello()
885 spin_unlock_irq(&hw->lock); csio_do_hello()
887 spin_lock_irq(&hw->lock); csio_do_hello()
896 pcie_fw = csio_rd_reg32(hw, PCIE_FW_A); csio_do_hello()
930 hw->flags &= ~CSIO_HWF_MASTER; csio_do_hello()
948 if (hw->pfn == mpfn) csio_do_hello()
949 csio_info(hw, "PF: %d, Coming up as MASTER, HW state: %s\n", csio_do_hello()
950 hw->pfn, state_str); csio_do_hello()
952 csio_info(hw, csio_do_hello()
954 hw->pfn, mpfn, state_str); csio_do_hello()
957 mempool_free(mbp, hw->mb_mempool); csio_do_hello()
964 * @hw: HW module
968 csio_do_bye(struct csio_hw *hw) csio_do_bye() argument
973 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_do_bye()
975 CSIO_INC_STATS(hw, n_err_nomem); csio_do_bye()
979 csio_mb_bye(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); csio_do_bye()
981 if (csio_mb_issue(hw, mbp)) { csio_do_bye()
982 csio_err(hw, "Issue of BYE command failed\n"); csio_do_bye()
983 mempool_free(mbp, hw->mb_mempool); csio_do_bye()
989 mempool_free(mbp, hw->mb_mempool); csio_do_bye()
993 mempool_free(mbp, hw->mb_mempool); csio_do_bye()
1000 * @hw: HW module
1008 csio_do_reset(struct csio_hw *hw, bool fw_rst) csio_do_reset() argument
1015 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A); csio_do_reset()
1020 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_do_reset()
1022 CSIO_INC_STATS(hw, n_err_nomem); csio_do_reset()
1026 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, csio_do_reset()
1029 if (csio_mb_issue(hw, mbp)) { csio_do_reset()
1030 csio_err(hw, "Issue of RESET command failed.n"); csio_do_reset()
1031 mempool_free(mbp, hw->mb_mempool); csio_do_reset()
1037 csio_err(hw, "RESET cmd failed with ret:0x%x.\n", retval); csio_do_reset()
1038 mempool_free(mbp, hw->mb_mempool); csio_do_reset()
1042 mempool_free(mbp, hw->mb_mempool); csio_do_reset()
1048 csio_hw_validate_caps(struct csio_hw *hw, struct csio_mb *mbp) csio_hw_validate_caps() argument
1056 csio_err(hw, "No FCoE Initiator capability in the firmware.\n"); csio_hw_validate_caps()
1061 csio_err(hw, "No FCoE Control Offload capability\n"); csio_hw_validate_caps()
1070 * @hw: the HW module
1085 csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force) csio_hw_fw_halt() argument
1096 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_hw_fw_halt()
1098 CSIO_INC_STATS(hw, n_err_nomem); csio_hw_fw_halt()
1102 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, csio_hw_fw_halt()
1106 if (csio_mb_issue(hw, mbp)) { csio_hw_fw_halt()
1107 csio_err(hw, "Issue of RESET command failed!\n"); csio_hw_fw_halt()
1108 mempool_free(mbp, hw->mb_mempool); csio_hw_fw_halt()
1113 mempool_free(mbp, hw->mb_mempool); csio_hw_fw_halt()
1130 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); csio_hw_fw_halt()
1131 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, csio_hw_fw_halt()
1144 * @hw: the HW module
1164 csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset) csio_hw_fw_restart() argument
1172 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0); csio_hw_fw_restart()
1182 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0); csio_hw_fw_restart()
1184 if (csio_do_reset(hw, true) == 0) csio_hw_fw_restart()
1188 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A); csio_hw_fw_restart()
1193 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0); csio_hw_fw_restart()
1195 if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F)) csio_hw_fw_restart()
1207 * @hw: the HW module
1227 csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox, csio_hw_fw_upgrade() argument
1233 ret = csio_hw_fw_halt(hw, mbox, force); csio_hw_fw_upgrade()
1237 ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size); csio_hw_fw_upgrade()
1250 return csio_hw_fw_restart(hw, mbox, reset); csio_hw_fw_upgrade()
1255 * @hw: HW module
1259 csio_get_device_params(struct csio_hw *hw) csio_get_device_params() argument
1261 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_get_device_params()
1269 hw->pport[i].portid = -1; csio_get_device_params()
1271 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_get_device_params()
1273 CSIO_INC_STATS(hw, n_err_nomem); csio_get_device_params()
1291 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, csio_get_device_params()
1293 if (csio_mb_issue(hw, mbp)) { csio_get_device_params()
1294 csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n"); csio_get_device_params()
1295 mempool_free(mbp, hw->mb_mempool); csio_get_device_params()
1299 csio_mb_process_read_params_rsp(hw, mbp, &retval, csio_get_device_params()
1302 csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n", csio_get_device_params()
1304 mempool_free(mbp, hw->mb_mempool); csio_get_device_params()
1309 hw->port_vec = param[0]; csio_get_device_params()
1310 hw->vpd.cclk = param[1]; csio_get_device_params()
1315 if ((hw->flags & CSIO_HWF_USING_SOFT_PARAMS) || csio_get_device_params()
1316 !csio_is_hw_master(hw)) { csio_get_device_params()
1317 hw->cfg_niq = param[5] - param[4] + 1; csio_get_device_params()
1318 hw->cfg_neq = param[3] - param[2] + 1; csio_get_device_params()
1319 csio_dbg(hw, "Using fwconfig max niqs %d neqs %d\n", csio_get_device_params()
1320 hw->cfg_niq, hw->cfg_neq); csio_get_device_params()
1323 hw->port_vec &= csio_port_mask; csio_get_device_params()
1325 hw->num_pports = hweight32(hw->port_vec); csio_get_device_params()
1327 csio_dbg(hw, "Port vector: 0x%x, #ports: %d\n", csio_get_device_params()
1328 hw->port_vec, hw->num_pports); csio_get_device_params()
1330 for (i = 0; i < hw->num_pports; i++) { csio_get_device_params()
1331 while ((hw->port_vec & (1 << j)) == 0) csio_get_device_params()
1333 hw->pport[i].portid = j++; csio_get_device_params()
1334 csio_dbg(hw, "Found Port:%d\n", hw->pport[i].portid); csio_get_device_params()
1336 mempool_free(mbp, hw->mb_mempool); csio_get_device_params()
1344 * @hw: HW module
1348 csio_config_device_caps(struct csio_hw *hw) csio_config_device_caps() argument
1354 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_config_device_caps()
1356 CSIO_INC_STATS(hw, n_err_nomem); csio_config_device_caps()
1361 csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, 0, 0, 0, 0, NULL); csio_config_device_caps()
1363 if (csio_mb_issue(hw, mbp)) { csio_config_device_caps()
1364 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(r) failed!\n"); csio_config_device_caps()
1370 csio_err(hw, "FW_CAPS_CONFIG_CMD(r) returned %d!\n", retval); csio_config_device_caps()
1375 rv = csio_hw_validate_caps(hw, mbp); csio_config_device_caps()
1380 if (hw->fw_state == CSIO_DEV_STATE_INIT) { csio_config_device_caps()
1386 csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, true, true, csio_config_device_caps()
1389 if (csio_mb_issue(hw, mbp)) { csio_config_device_caps()
1390 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(w) failed!\n"); csio_config_device_caps()
1396 csio_err(hw, "FW_CAPS_CONFIG_CMD(w) returned %d!\n", retval); csio_config_device_caps()
1402 mempool_free(mbp, hw->mb_mempool); csio_config_device_caps()
1408 * @hw: HW module.
1412 csio_enable_ports(struct csio_hw *hw) csio_enable_ports() argument
1419 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_enable_ports()
1421 CSIO_INC_STATS(hw, n_err_nomem); csio_enable_ports()
1425 for (i = 0; i < hw->num_pports; i++) { csio_enable_ports()
1426 portid = hw->pport[i].portid; csio_enable_ports()
1429 csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, csio_enable_ports()
1432 if (csio_mb_issue(hw, mbp)) { csio_enable_ports()
1433 csio_err(hw, "failed to issue FW_PORT_CMD(r) port:%d\n", csio_enable_ports()
1435 mempool_free(mbp, hw->mb_mempool); csio_enable_ports()
1439 csio_mb_process_read_port_rsp(hw, mbp, &retval, csio_enable_ports()
1440 &hw->pport[i].pcap); csio_enable_ports()
1442 csio_err(hw, "FW_PORT_CMD(r) port:%d failed: 0x%x\n", csio_enable_ports()
1444 mempool_free(mbp, hw->mb_mempool); csio_enable_ports()
1449 csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, true, csio_enable_ports()
1450 (PAUSE_RX | PAUSE_TX), hw->pport[i].pcap, NULL); csio_enable_ports()
1452 if (csio_mb_issue(hw, mbp)) { csio_enable_ports()
1453 csio_err(hw, "failed to issue FW_PORT_CMD(w) port:%d\n", csio_enable_ports()
1455 mempool_free(mbp, hw->mb_mempool); csio_enable_ports()
1461 csio_err(hw, "FW_PORT_CMD(w) port:%d failed :0x%x\n", csio_enable_ports()
1463 mempool_free(mbp, hw->mb_mempool); csio_enable_ports()
1469 mempool_free(mbp, hw->mb_mempool); csio_enable_ports()
1476 * @hw: HW module
1480 csio_get_fcoe_resinfo(struct csio_hw *hw) csio_get_fcoe_resinfo() argument
1482 struct csio_fcoe_res_info *res_info = &hw->fres_info; csio_get_fcoe_resinfo()
1487 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_get_fcoe_resinfo()
1489 CSIO_INC_STATS(hw, n_err_nomem); csio_get_fcoe_resinfo()
1494 csio_fcoe_read_res_info_init_mb(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); csio_get_fcoe_resinfo()
1496 if (csio_mb_issue(hw, mbp)) { csio_get_fcoe_resinfo()
1497 csio_err(hw, "failed to issue FW_FCOE_RES_INFO_CMD\n"); csio_get_fcoe_resinfo()
1498 mempool_free(mbp, hw->mb_mempool); csio_get_fcoe_resinfo()
1505 csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n", csio_get_fcoe_resinfo()
1507 mempool_free(mbp, hw->mb_mempool); csio_get_fcoe_resinfo()
1524 csio_dbg(hw, "max ssns:%d max xchgs:%d\n", res_info->max_ssns, csio_get_fcoe_resinfo()
1526 mempool_free(mbp, hw->mb_mempool); csio_get_fcoe_resinfo()
1532 csio_hw_check_fwconfig(struct csio_hw *hw, u32 *param) csio_hw_check_fwconfig() argument
1538 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_hw_check_fwconfig()
1540 CSIO_INC_STATS(hw, n_err_nomem); csio_hw_check_fwconfig()
1551 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, csio_hw_check_fwconfig()
1553 if (csio_mb_issue(hw, mbp)) { csio_hw_check_fwconfig()
1554 csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n"); csio_hw_check_fwconfig()
1555 mempool_free(mbp, hw->mb_mempool); csio_hw_check_fwconfig()
1559 csio_mb_process_read_params_rsp(hw, mbp, &retval, csio_hw_check_fwconfig()
1562 csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n", csio_hw_check_fwconfig()
1564 mempool_free(mbp, hw->mb_mempool); csio_hw_check_fwconfig()
1568 mempool_free(mbp, hw->mb_mempool); csio_hw_check_fwconfig()
1575 csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path) csio_hw_flash_config() argument
1579 struct pci_dev *pci_dev = hw->pdev; csio_hw_flash_config()
1586 csio_err(hw, "could not find config file %s, err: %d\n", csio_hw_flash_config()
1601 if (csio_hw_check_fwconfig(hw, fw_cfg_param) != 0) { csio_hw_flash_config()
1609 ret = csio_memory_write(hw, mtype, maddr, csio_hw_flash_config()
1623 ret = csio_memory_write(hw, mtype, maddr + size, 4, &last.word); csio_hw_flash_config()
1626 csio_info(hw, "config file upgraded to %s\n", csio_hw_flash_config()
1654 csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param) csio_hw_use_fwconfig() argument
1668 rv = csio_do_reset(hw, true); csio_hw_use_fwconfig()
1678 spin_unlock_irq(&hw->lock); csio_hw_use_fwconfig()
1679 rv = csio_hw_flash_config(hw, fw_cfg_param, path); csio_hw_use_fwconfig()
1680 spin_lock_irq(&hw->lock); csio_hw_use_fwconfig()
1688 maddr = hw->chip_ops->chip_flash_cfg_addr(hw); csio_hw_use_fwconfig()
1695 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_hw_use_fwconfig()
1697 CSIO_INC_STATS(hw, n_err_nomem); csio_hw_use_fwconfig()
1707 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1); csio_hw_use_fwconfig()
1718 if (csio_mb_issue(hw, mbp)) { csio_hw_use_fwconfig()
1731 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1); csio_hw_use_fwconfig()
1737 if (csio_mb_issue(hw, mbp)) { csio_hw_use_fwconfig()
1761 if (csio_mb_issue(hw, mbp)) { csio_hw_use_fwconfig()
1768 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv); csio_hw_use_fwconfig()
1772 mempool_free(mbp, hw->mb_mempool); csio_hw_use_fwconfig()
1774 csio_warn(hw, csio_hw_use_fwconfig()
1780 rv = csio_hw_validate_caps(hw, mbp); csio_hw_use_fwconfig()
1788 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; csio_hw_use_fwconfig()
1791 rv = csio_get_device_params(hw); csio_hw_use_fwconfig()
1796 csio_wr_sge_init(hw); csio_hw_use_fwconfig()
1803 csio_post_event(&hw->sm, CSIO_HWE_INIT); csio_hw_use_fwconfig()
1805 csio_info(hw, "Successfully configure using Firmware " csio_hw_use_fwconfig()
1815 mempool_free(mbp, hw->mb_mempool); csio_hw_use_fwconfig()
1816 hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS; csio_hw_use_fwconfig()
1817 csio_warn(hw, "Configuration file error %d\n", rv); csio_hw_use_fwconfig()
1844 static int csio_should_install_fs_fw(struct csio_hw *hw, int card_fw_usable, csio_should_install_fs_fw() argument
1862 csio_err(hw, "firmware on card (%u.%u.%u.%u) is %s, " csio_should_install_fs_fw()
1900 static int csio_hw_prep_fw(struct csio_hw *hw, struct fw_info *fw_info, csio_hw_prep_fw() argument
1912 ret = csio_hw_read_flash(hw, FLASH_FW_START, csio_hw_prep_fw()
1918 csio_err(hw, csio_hw_prep_fw()
1938 csio_should_install_fs_fw(hw, card_fw_usable, csio_hw_prep_fw()
1941 ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data, csio_hw_prep_fw()
1944 csio_err(hw, csio_hw_prep_fw()
1962 csio_err(hw, "Cannot find a usable firmware: " csio_hw_prep_fw()
1978 hw->fwrev = be32_to_cpu(card_fw->fw_ver); csio_hw_prep_fw()
1979 hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); csio_hw_prep_fw()
1992 csio_hw_flash_fw(struct csio_hw *hw, int *reset) csio_hw_flash_fw() argument
1998 struct pci_dev *pci_dev = hw->pdev; csio_hw_flash_fw()
2006 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id)); csio_hw_flash_fw()
2008 csio_err(hw, csio_hw_flash_fw()
2010 CHELSIO_CHIP_VERSION(hw->chip_id)); csio_hw_flash_fw()
2015 csio_err(hw, "could not find firmware image %s, err: %d\n", csio_hw_flash_fw()
2028 ret = csio_hw_prep_fw(hw, fw_info, fw_data, fw_size, card_fw, csio_hw_flash_fw()
2029 hw->fw_state, reset); csio_hw_flash_fw()
2040 * @hw - HW module
2044 csio_hw_configure(struct csio_hw *hw) csio_hw_configure() argument
2050 rv = csio_hw_dev_ready(hw); csio_hw_configure()
2052 CSIO_INC_STATS(hw, n_err_fatal); csio_hw_configure()
2053 csio_post_event(&hw->sm, CSIO_HWE_FATAL); csio_hw_configure()
2058 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A); csio_hw_configure()
2061 rv = csio_hw_get_flash_params(hw); csio_hw_configure()
2063 csio_err(hw, "Failed to get serial flash params rv:%d\n", rv); csio_hw_configure()
2064 csio_post_event(&hw->sm, CSIO_HWE_FATAL); csio_hw_configure()
2069 if (pci_is_pcie(hw->pdev)) csio_hw_configure()
2070 pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2, csio_hw_configure()
2073 hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR); csio_hw_configure()
2075 rv = csio_hw_get_fw_version(hw, &hw->fwrev); csio_hw_configure()
2079 csio_hw_print_fw_version(hw, "Firmware revision"); csio_hw_configure()
2081 rv = csio_do_hello(hw, &hw->fw_state); csio_hw_configure()
2083 CSIO_INC_STATS(hw, n_err_fatal); csio_hw_configure()
2084 csio_post_event(&hw->sm, CSIO_HWE_FATAL); csio_hw_configure()
2089 rv = csio_hw_get_vpd_params(hw, &hw->vpd); csio_hw_configure()
2093 csio_hw_get_fw_version(hw, &hw->fwrev); csio_hw_configure()
2094 csio_hw_get_tp_version(hw, &hw->tp_vers); csio_hw_configure()
2095 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { csio_hw_configure()
2098 spin_unlock_irq(&hw->lock); csio_hw_configure()
2099 rv = csio_hw_flash_fw(hw, &reset); csio_hw_configure()
2100 spin_lock_irq(&hw->lock); csio_hw_configure()
2108 rv = csio_hw_check_fwconfig(hw, param); csio_hw_configure()
2110 csio_info(hw, "Firmware doesn't support " csio_hw_configure()
2119 rv = csio_hw_use_fwconfig(hw, reset, param); csio_hw_configure()
2121 csio_info(hw, "Could not initialize " csio_hw_configure()
2126 csio_info(hw, "Could not initialize " csio_hw_configure()
2132 if (hw->fw_state == CSIO_DEV_STATE_INIT) { csio_hw_configure()
2134 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; csio_hw_configure()
2137 rv = csio_get_device_params(hw); csio_hw_configure()
2142 rv = csio_config_device_caps(hw); csio_hw_configure()
2147 csio_wr_sge_init(hw); csio_hw_configure()
2150 csio_post_event(&hw->sm, CSIO_HWE_INIT); csio_hw_configure()
2161 * @hw - HW module
2165 csio_hw_initialize(struct csio_hw *hw) csio_hw_initialize() argument
2172 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { csio_hw_initialize()
2173 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_hw_initialize()
2177 csio_mb_initialize(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); csio_hw_initialize()
2179 if (csio_mb_issue(hw, mbp)) { csio_hw_initialize()
2180 csio_err(hw, "Issue of FW_INITIALIZE_CMD failed!\n"); csio_hw_initialize()
2186 csio_err(hw, "FW_INITIALIZE_CMD returned 0x%x!\n", csio_hw_initialize()
2191 mempool_free(mbp, hw->mb_mempool); csio_hw_initialize()
2194 rv = csio_get_fcoe_resinfo(hw); csio_hw_initialize()
2196 csio_err(hw, "Failed to read fcoe resource info: %d\n", rv); csio_hw_initialize()
2200 spin_unlock_irq(&hw->lock); csio_hw_initialize()
2201 rv = csio_config_queues(hw); csio_hw_initialize()
2202 spin_lock_irq(&hw->lock); csio_hw_initialize()
2205 csio_err(hw, "Config of queues failed!: %d\n", rv); csio_hw_initialize()
2209 for (i = 0; i < hw->num_pports; i++) csio_hw_initialize()
2210 hw->pport[i].mod_type = FW_PORT_MOD_TYPE_NA; csio_hw_initialize()
2212 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { csio_hw_initialize()
2213 rv = csio_enable_ports(hw); csio_hw_initialize()
2215 csio_err(hw, "Failed to enable ports: %d\n", rv); csio_hw_initialize()
2220 csio_post_event(&hw->sm, CSIO_HWE_INIT_DONE); csio_hw_initialize()
2224 mempool_free(mbp, hw->mb_mempool); csio_hw_initialize()
2233 * @hw: Pointer to HW module.
2238 csio_hw_intr_enable(struct csio_hw *hw) csio_hw_intr_enable() argument
2240 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw)); csio_hw_intr_enable()
2241 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A)); csio_hw_intr_enable()
2242 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A); csio_hw_intr_enable()
2248 if (hw->intr_mode == CSIO_IM_MSIX) csio_hw_intr_enable()
2249 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A), csio_hw_intr_enable()
2251 else if (hw->intr_mode == CSIO_IM_MSI) csio_hw_intr_enable()
2252 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A), csio_hw_intr_enable()
2255 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A)); csio_hw_intr_enable()
2258 csio_mb_intr_enable(hw); csio_hw_intr_enable()
2261 if (csio_is_hw_master(hw)) { csio_hw_intr_enable()
2266 csio_wr_reg32(hw, pl, PL_INT_ENABLE_A); csio_hw_intr_enable()
2268 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F | csio_hw_intr_enable()
2277 csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf); csio_hw_intr_enable()
2280 hw->flags |= CSIO_HWF_HW_INTR_ENABLED; csio_hw_intr_enable()
2286 * @hw: Pointer to HW module.
2291 csio_hw_intr_disable(struct csio_hw *hw) csio_hw_intr_disable() argument
2293 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A)); csio_hw_intr_disable()
2295 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED)) csio_hw_intr_disable()
2298 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED; csio_hw_intr_disable()
2300 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A)); csio_hw_intr_disable()
2301 if (csio_is_hw_master(hw)) csio_hw_intr_disable()
2302 csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0); csio_hw_intr_disable()
2305 csio_mb_intr_disable(hw); csio_hw_intr_disable()
2310 csio_hw_fatal_err(struct csio_hw *hw) csio_hw_fatal_err() argument
2312 csio_set_reg_field(hw, SGE_CONTROL_A, GLOBALENABLE_F, 0); csio_hw_fatal_err()
2313 csio_hw_intr_disable(hw); csio_hw_fatal_err()
2316 csio_fatal(hw, "HW Fatal error encountered!\n"); csio_hw_fatal_err()
2324 * @hw - HW module
2329 csio_hws_uninit(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_uninit() argument
2331 hw->prev_evt = hw->cur_evt; csio_hws_uninit()
2332 hw->cur_evt = evt; csio_hws_uninit()
2333 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_uninit()
2337 csio_set_state(&hw->sm, csio_hws_configuring); csio_hws_uninit()
2338 csio_hw_configure(hw); csio_hws_uninit()
2342 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_uninit()
2349 * @hw - HW module
2354 csio_hws_configuring(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_configuring() argument
2356 hw->prev_evt = hw->cur_evt; csio_hws_configuring()
2357 hw->cur_evt = evt; csio_hws_configuring()
2358 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_configuring()
2362 csio_set_state(&hw->sm, csio_hws_initializing); csio_hws_configuring()
2363 csio_hw_initialize(hw); csio_hws_configuring()
2367 csio_set_state(&hw->sm, csio_hws_ready); csio_hws_configuring()
2369 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY); csio_hws_configuring()
2373 csio_set_state(&hw->sm, csio_hws_uninit); csio_hws_configuring()
2377 csio_do_bye(hw); csio_hws_configuring()
2380 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_configuring()
2387 * @hw - HW module
2392 csio_hws_initializing(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_initializing() argument
2394 hw->prev_evt = hw->cur_evt; csio_hws_initializing()
2395 hw->cur_evt = evt; csio_hws_initializing()
2396 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_initializing()
2400 csio_set_state(&hw->sm, csio_hws_ready); csio_hws_initializing()
2403 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY); csio_hws_initializing()
2406 csio_hw_intr_enable(hw); csio_hws_initializing()
2410 csio_set_state(&hw->sm, csio_hws_uninit); csio_hws_initializing()
2414 csio_do_bye(hw); csio_hws_initializing()
2418 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_initializing()
2425 * @hw - HW module
2430 csio_hws_ready(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_ready() argument
2433 hw->evtflag = evt; csio_hws_ready()
2435 hw->prev_evt = hw->cur_evt; csio_hws_ready()
2436 hw->cur_evt = evt; csio_hws_ready()
2437 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_ready()
2445 csio_set_state(&hw->sm, csio_hws_quiescing); csio_hws_ready()
2449 csio_scsim_cleanup_io(csio_hw_to_scsim(hw), false); csio_hws_ready()
2451 csio_scsim_cleanup_io(csio_hw_to_scsim(hw), true); csio_hws_ready()
2453 csio_hw_intr_disable(hw); csio_hws_ready()
2454 csio_hw_mbm_cleanup(hw); csio_hws_ready()
2455 csio_evtq_stop(hw); csio_hws_ready()
2456 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWSTOP); csio_hws_ready()
2457 csio_evtq_flush(hw); csio_hws_ready()
2458 csio_mgmtm_cleanup(csio_hw_to_mgmtm(hw)); csio_hws_ready()
2459 csio_post_event(&hw->sm, CSIO_HWE_QUIESCED); csio_hws_ready()
2463 csio_set_state(&hw->sm, csio_hws_uninit); csio_hws_ready()
2467 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_ready()
2474 * @hw - HW module
2479 csio_hws_quiescing(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_quiescing() argument
2481 hw->prev_evt = hw->cur_evt; csio_hws_quiescing()
2482 hw->cur_evt = evt; csio_hws_quiescing()
2483 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_quiescing()
2487 switch (hw->evtflag) { csio_hws_quiescing()
2489 csio_set_state(&hw->sm, csio_hws_resetting); csio_hws_quiescing()
2494 csio_set_state(&hw->sm, csio_hws_resetting); csio_hws_quiescing()
2496 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWRESET); csio_hws_quiescing()
2497 csio_wr_destroy_queues(hw, false); csio_hws_quiescing()
2498 csio_do_reset(hw, false); csio_hws_quiescing()
2499 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET_DONE); csio_hws_quiescing()
2503 csio_set_state(&hw->sm, csio_hws_removing); csio_hws_quiescing()
2504 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREMOVE); csio_hws_quiescing()
2505 csio_wr_destroy_queues(hw, true); csio_hws_quiescing()
2507 csio_do_bye(hw); csio_hws_quiescing()
2511 csio_set_state(&hw->sm, csio_hws_quiesced); csio_hws_quiescing()
2515 csio_set_state(&hw->sm, csio_hws_pcierr); csio_hws_quiescing()
2516 csio_wr_destroy_queues(hw, false); csio_hws_quiescing()
2520 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_quiescing()
2527 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_quiescing()
2534 * @hw - HW module
2539 csio_hws_quiesced(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_quiesced() argument
2541 hw->prev_evt = hw->cur_evt; csio_hws_quiesced()
2542 hw->cur_evt = evt; csio_hws_quiesced()
2543 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_quiesced()
2547 csio_set_state(&hw->sm, csio_hws_configuring); csio_hws_quiesced()
2548 csio_hw_configure(hw); csio_hws_quiesced()
2552 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_quiesced()
2559 * @hw - HW module
2564 csio_hws_resetting(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_resetting() argument
2566 hw->prev_evt = hw->cur_evt; csio_hws_resetting()
2567 hw->cur_evt = evt; csio_hws_resetting()
2568 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_resetting()
2572 csio_evtq_start(hw); csio_hws_resetting()
2573 csio_set_state(&hw->sm, csio_hws_configuring); csio_hws_resetting()
2574 csio_hw_configure(hw); csio_hws_resetting()
2578 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_resetting()
2585 * @hw - HW module
2590 csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_removing() argument
2592 hw->prev_evt = hw->cur_evt; csio_hws_removing()
2593 hw->cur_evt = evt; csio_hws_removing()
2594 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_removing()
2598 if (!csio_is_hw_master(hw)) csio_hws_removing()
2605 csio_err(hw, "Resetting HW and waiting 2 seconds...\n"); csio_hws_removing()
2606 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A); csio_hws_removing()
2612 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_removing()
2620 * @hw - HW module
2625 csio_hws_pcierr(struct csio_hw *hw, enum csio_hw_ev evt) csio_hws_pcierr() argument
2627 hw->prev_evt = hw->cur_evt; csio_hws_pcierr()
2628 hw->cur_evt = evt; csio_hws_pcierr()
2629 CSIO_INC_STATS(hw, n_evt_sm[evt]); csio_hws_pcierr()
2633 csio_evtq_start(hw); csio_hws_pcierr()
2634 csio_set_state(&hw->sm, csio_hws_configuring); csio_hws_pcierr()
2635 csio_hw_configure(hw); csio_hws_pcierr()
2639 CSIO_INC_STATS(hw, n_evt_unexp); csio_hws_pcierr()
2650 * @hw: HW instance
2662 csio_handle_intr_status(struct csio_hw *hw, unsigned int reg, csio_handle_intr_status() argument
2667 unsigned int status = csio_rd_reg32(hw, reg); csio_handle_intr_status()
2674 csio_fatal(hw, "Fatal %s (0x%x)\n", csio_handle_intr_status()
2677 csio_info(hw, "%s (0x%x)\n", csio_handle_intr_status()
2683 csio_wr_reg32(hw, status, reg); csio_handle_intr_status()
2690 static void csio_tp_intr_handler(struct csio_hw *hw) csio_tp_intr_handler() argument
2698 if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info)) csio_tp_intr_handler()
2699 csio_hw_fatal_err(hw); csio_tp_intr_handler()
2705 static void csio_sge_intr_handler(struct csio_hw *hw) csio_sge_intr_handler() argument
2735 v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) | csio_sge_intr_handler()
2736 ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32); csio_sge_intr_handler()
2738 csio_fatal(hw, "SGE parity error (%#llx)\n", csio_sge_intr_handler()
2740 csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF), csio_sge_intr_handler()
2742 csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A); csio_sge_intr_handler()
2745 v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info); csio_sge_intr_handler()
2747 if (csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info) || csio_sge_intr_handler()
2749 csio_hw_fatal_err(hw); csio_sge_intr_handler()
2760 static void csio_cim_intr_handler(struct csio_hw *hw) csio_cim_intr_handler() argument
2806 fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE_A, csio_cim_intr_handler()
2808 csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE_A, csio_cim_intr_handler()
2811 csio_hw_fatal_err(hw); csio_cim_intr_handler()
2817 static void csio_ulprx_intr_handler(struct csio_hw *hw) csio_ulprx_intr_handler() argument
2825 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info)) csio_ulprx_intr_handler()
2826 csio_hw_fatal_err(hw); csio_ulprx_intr_handler()
2832 static void csio_ulptx_intr_handler(struct csio_hw *hw) csio_ulptx_intr_handler() argument
2847 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info)) csio_ulptx_intr_handler()
2848 csio_hw_fatal_err(hw); csio_ulptx_intr_handler()
2854 static void csio_pmtx_intr_handler(struct csio_hw *hw) csio_pmtx_intr_handler() argument
2870 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info)) csio_pmtx_intr_handler()
2871 csio_hw_fatal_err(hw); csio_pmtx_intr_handler()
2877 static void csio_pmrx_intr_handler(struct csio_hw *hw) csio_pmrx_intr_handler() argument
2890 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info)) csio_pmrx_intr_handler()
2891 csio_hw_fatal_err(hw); csio_pmrx_intr_handler()
2897 static void csio_cplsw_intr_handler(struct csio_hw *hw) csio_cplsw_intr_handler() argument
2909 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info)) csio_cplsw_intr_handler()
2910 csio_hw_fatal_err(hw); csio_cplsw_intr_handler()
2916 static void csio_le_intr_handler(struct csio_hw *hw) csio_le_intr_handler() argument
2927 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A, le_intr_info)) csio_le_intr_handler()
2928 csio_hw_fatal_err(hw); csio_le_intr_handler()
2934 static void csio_mps_intr_handler(struct csio_hw *hw) csio_mps_intr_handler() argument
2980 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A, csio_mps_intr_handler()
2982 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A, csio_mps_intr_handler()
2984 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A, csio_mps_intr_handler()
2986 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A, csio_mps_intr_handler()
2988 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A, csio_mps_intr_handler()
2990 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A, csio_mps_intr_handler()
2992 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A, csio_mps_intr_handler()
2995 csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A); csio_mps_intr_handler()
2996 csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */ csio_mps_intr_handler()
2998 csio_hw_fatal_err(hw); csio_mps_intr_handler()
3007 static void csio_mem_intr_handler(struct csio_hw *hw, int idx) csio_mem_intr_handler() argument
3021 v = csio_rd_reg32(hw, addr) & MEM_INT_MASK; csio_mem_intr_handler()
3023 csio_fatal(hw, "%s FIFO parity error\n", name[idx]); csio_mem_intr_handler()
3025 uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr)); csio_mem_intr_handler()
3027 csio_wr_reg32(hw, ECC_CECNT_V(ECC_CECNT_M), cnt_addr); csio_mem_intr_handler()
3028 csio_warn(hw, "%u %s correctable ECC data error%s\n", csio_mem_intr_handler()
3032 csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]); csio_mem_intr_handler()
3034 csio_wr_reg32(hw, v, addr); csio_mem_intr_handler()
3036 csio_hw_fatal_err(hw); csio_mem_intr_handler()
3042 static void csio_ma_intr_handler(struct csio_hw *hw) csio_ma_intr_handler() argument
3044 uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A); csio_ma_intr_handler()
3047 csio_fatal(hw, "MA parity error, parity status %#x\n", csio_ma_intr_handler()
3048 csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A)); csio_ma_intr_handler()
3050 v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A); csio_ma_intr_handler()
3051 csio_fatal(hw, csio_ma_intr_handler()
3055 csio_wr_reg32(hw, status, MA_INT_CAUSE_A); csio_ma_intr_handler()
3056 csio_hw_fatal_err(hw); csio_ma_intr_handler()
3062 static void csio_smb_intr_handler(struct csio_hw *hw) csio_smb_intr_handler() argument
3071 if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info)) csio_smb_intr_handler()
3072 csio_hw_fatal_err(hw); csio_smb_intr_handler()
3078 static void csio_ncsi_intr_handler(struct csio_hw *hw) csio_ncsi_intr_handler() argument
3088 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info)) csio_ncsi_intr_handler()
3089 csio_hw_fatal_err(hw); csio_ncsi_intr_handler()
3095 static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) csio_xgmac_intr_handler() argument
3097 uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); csio_xgmac_intr_handler()
3104 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); csio_xgmac_intr_handler()
3106 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); csio_xgmac_intr_handler()
3107 csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)); csio_xgmac_intr_handler()
3108 csio_hw_fatal_err(hw); csio_xgmac_intr_handler()
3114 static void csio_pl_intr_handler(struct csio_hw *hw) csio_pl_intr_handler() argument
3122 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info)) csio_pl_intr_handler()
3123 csio_hw_fatal_err(hw); csio_pl_intr_handler()
3128 * @hw: HW module
3135 csio_hw_slow_intr_handler(struct csio_hw *hw) csio_hw_slow_intr_handler() argument
3137 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A); csio_hw_slow_intr_handler()
3140 CSIO_INC_STATS(hw, n_plint_unexp); csio_hw_slow_intr_handler()
3144 csio_dbg(hw, "Slow interrupt! cause: 0x%x\n", cause); csio_hw_slow_intr_handler()
3146 CSIO_INC_STATS(hw, n_plint_cnt); csio_hw_slow_intr_handler()
3149 csio_cim_intr_handler(hw); csio_hw_slow_intr_handler()
3152 csio_mps_intr_handler(hw); csio_hw_slow_intr_handler()
3155 csio_ncsi_intr_handler(hw); csio_hw_slow_intr_handler()
3158 csio_pl_intr_handler(hw); csio_hw_slow_intr_handler()
3161 csio_smb_intr_handler(hw); csio_hw_slow_intr_handler()
3164 csio_xgmac_intr_handler(hw, 0); csio_hw_slow_intr_handler()
3167 csio_xgmac_intr_handler(hw, 1); csio_hw_slow_intr_handler()
3170 csio_xgmac_intr_handler(hw, 2); csio_hw_slow_intr_handler()
3173 csio_xgmac_intr_handler(hw, 3); csio_hw_slow_intr_handler()
3176 hw->chip_ops->chip_pcie_intr_handler(hw); csio_hw_slow_intr_handler()
3179 csio_mem_intr_handler(hw, MEM_MC); csio_hw_slow_intr_handler()
3182 csio_mem_intr_handler(hw, MEM_EDC0); csio_hw_slow_intr_handler()
3185 csio_mem_intr_handler(hw, MEM_EDC1); csio_hw_slow_intr_handler()
3188 csio_le_intr_handler(hw); csio_hw_slow_intr_handler()
3191 csio_tp_intr_handler(hw); csio_hw_slow_intr_handler()
3194 csio_ma_intr_handler(hw); csio_hw_slow_intr_handler()
3197 csio_pmtx_intr_handler(hw); csio_hw_slow_intr_handler()
3200 csio_pmrx_intr_handler(hw); csio_hw_slow_intr_handler()
3203 csio_ulprx_intr_handler(hw); csio_hw_slow_intr_handler()
3206 csio_cplsw_intr_handler(hw); csio_hw_slow_intr_handler()
3209 csio_sge_intr_handler(hw); csio_hw_slow_intr_handler()
3212 csio_ulptx_intr_handler(hw); csio_hw_slow_intr_handler()
3215 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A); csio_hw_slow_intr_handler()
3216 csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */ csio_hw_slow_intr_handler()
3234 struct csio_hw *hw = (struct csio_hw *)data; csio_mberr_worker() local
3235 struct csio_mbm *mbm = &hw->mbm; csio_mberr_worker()
3242 spin_lock_irq(&hw->lock); csio_mberr_worker()
3244 spin_unlock_irq(&hw->lock); csio_mberr_worker()
3256 rv = csio_mb_issue(hw, mbp_next); csio_mberr_worker()
3262 spin_unlock_irq(&hw->lock); csio_mberr_worker()
3265 csio_mb_completions(hw, &cbfn_q); csio_mberr_worker()
3277 struct csio_hw *hw = (struct csio_hw *)data; csio_hw_mb_timer() local
3280 spin_lock_irq(&hw->lock); csio_hw_mb_timer()
3281 mbp = csio_mb_tmo_handler(hw); csio_hw_mb_timer()
3282 spin_unlock_irq(&hw->lock); csio_hw_mb_timer()
3286 mbp->mb_cbfn(hw, mbp); csio_hw_mb_timer()
3292 * @hw: HW module
3300 csio_hw_mbm_cleanup(struct csio_hw *hw) csio_hw_mbm_cleanup() argument
3304 csio_mb_cancel_all(hw, &cbfn_q); csio_hw_mbm_cleanup()
3306 spin_unlock_irq(&hw->lock); csio_hw_mbm_cleanup()
3307 csio_mb_completions(hw, &cbfn_q); csio_hw_mbm_cleanup()
3308 spin_lock_irq(&hw->lock); csio_hw_mbm_cleanup()
3315 csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type, void *evt_msg, csio_enqueue_evt() argument
3326 if (hw->flags & CSIO_HWF_FWEVT_STOP) csio_enqueue_evt()
3329 if (list_empty(&hw->evt_free_q)) { csio_enqueue_evt()
3330 csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n", csio_enqueue_evt()
3335 evt_entry = list_first_entry(&hw->evt_free_q, csio_enqueue_evt()
3342 list_add_tail(&evt_entry->list, &hw->evt_active_q); csio_enqueue_evt()
3344 CSIO_DEC_STATS(hw, n_evt_freeq); csio_enqueue_evt()
3345 CSIO_INC_STATS(hw, n_evt_activeq); csio_enqueue_evt()
3351 csio_enqueue_evt_lock(struct csio_hw *hw, enum csio_evt type, void *evt_msg, csio_enqueue_evt_lock() argument
3366 spin_lock_irqsave(&hw->lock, flags); csio_enqueue_evt_lock()
3367 if (hw->flags & CSIO_HWF_FWEVT_STOP) { csio_enqueue_evt_lock()
3372 if (list_empty(&hw->evt_free_q)) { csio_enqueue_evt_lock()
3373 csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n", csio_enqueue_evt_lock()
3379 evt_entry = list_first_entry(&hw->evt_free_q, csio_enqueue_evt_lock()
3398 list_add_tail(&evt_entry->list, &hw->evt_active_q); csio_enqueue_evt_lock()
3399 CSIO_DEC_STATS(hw, n_evt_freeq); csio_enqueue_evt_lock()
3400 CSIO_INC_STATS(hw, n_evt_activeq); csio_enqueue_evt_lock()
3402 spin_unlock_irqrestore(&hw->lock, flags); csio_enqueue_evt_lock()
3407 csio_free_evt(struct csio_hw *hw, struct csio_evt_msg *evt_entry) csio_free_evt() argument
3410 spin_lock_irq(&hw->lock); csio_free_evt()
3412 list_add_tail(&evt_entry->list, &hw->evt_free_q); csio_free_evt()
3413 CSIO_DEC_STATS(hw, n_evt_activeq); csio_free_evt()
3414 CSIO_INC_STATS(hw, n_evt_freeq); csio_free_evt()
3415 spin_unlock_irq(&hw->lock); csio_free_evt()
3420 csio_evtq_flush(struct csio_hw *hw) csio_evtq_flush() argument
3424 while (hw->flags & CSIO_HWF_FWEVT_PENDING && count--) { csio_evtq_flush()
3425 spin_unlock_irq(&hw->lock); csio_evtq_flush()
3427 spin_lock_irq(&hw->lock); csio_evtq_flush()
3430 CSIO_DB_ASSERT(!(hw->flags & CSIO_HWF_FWEVT_PENDING)); csio_evtq_flush()
3434 csio_evtq_stop(struct csio_hw *hw) csio_evtq_stop() argument
3436 hw->flags |= CSIO_HWF_FWEVT_STOP; csio_evtq_stop()
3440 csio_evtq_start(struct csio_hw *hw) csio_evtq_start() argument
3442 hw->flags &= ~CSIO_HWF_FWEVT_STOP; csio_evtq_start()
3446 csio_evtq_cleanup(struct csio_hw *hw) csio_evtq_cleanup() argument
3451 if (!list_empty(&hw->evt_active_q)) csio_evtq_cleanup()
3452 list_splice_tail_init(&hw->evt_active_q, &hw->evt_free_q); csio_evtq_cleanup()
3454 hw->stats.n_evt_activeq = 0; csio_evtq_cleanup()
3455 hw->flags &= ~CSIO_HWF_FWEVT_PENDING; csio_evtq_cleanup()
3458 list_for_each_safe(evt_entry, next_entry, &hw->evt_free_q) { csio_evtq_cleanup()
3460 CSIO_DEC_STATS(hw, n_evt_freeq); csio_evtq_cleanup()
3463 hw->stats.n_evt_freeq = 0; csio_evtq_cleanup()
3468 csio_process_fwevtq_entry(struct csio_hw *hw, void *wr, uint32_t len, csio_process_fwevtq_entry() argument
3478 CSIO_INC_STATS(hw, n_cpl_fw6_pld); csio_process_fwevtq_entry()
3480 CSIO_INC_STATS(hw, n_cpl_unexp); csio_process_fwevtq_entry()
3489 CSIO_INC_STATS(hw, n_cpl_fw6_msg); csio_process_fwevtq_entry()
3495 csio_warn(hw, "unexpected CPL %#x on FW event queue\n", op); csio_process_fwevtq_entry()
3496 CSIO_INC_STATS(hw, n_cpl_unexp); csio_process_fwevtq_entry()
3504 if (csio_enqueue_evt_lock(hw, CSIO_EVT_FW, msg, csio_process_fwevtq_entry()
3506 CSIO_INC_STATS(hw, n_evt_drop); csio_process_fwevtq_entry()
3512 struct csio_hw *hw = container_of(work, struct csio_hw, evtq_work); csio_evtq_worker() local
3521 csio_dbg(hw, "event worker thread active evts#%d\n", csio_evtq_worker()
3522 hw->stats.n_evt_activeq); csio_evtq_worker()
3524 spin_lock_irq(&hw->lock); csio_evtq_worker()
3525 while (!list_empty(&hw->evt_active_q)) { csio_evtq_worker()
3526 list_splice_tail_init(&hw->evt_active_q, &evt_q); csio_evtq_worker()
3527 spin_unlock_irq(&hw->lock); csio_evtq_worker()
3533 spin_lock_irq(&hw->lock); csio_evtq_worker()
3534 if (hw->flags & CSIO_HWF_FWEVT_STOP) csio_evtq_worker()
3536 spin_unlock_irq(&hw->lock); csio_evtq_worker()
3538 CSIO_INC_STATS(hw, n_evt_drop); csio_evtq_worker()
3549 rv = csio_mb_fwevt_handler(hw, csio_evtq_worker()
3554 csio_fcoe_fwevt_handler(hw, csio_evtq_worker()
3558 csio_fcoe_fwevt_handler(hw, csio_evtq_worker()
3561 csio_warn(hw, csio_evtq_worker()
3564 CSIO_INC_STATS(hw, n_evt_drop); csio_evtq_worker()
3569 csio_mberr_worker(hw); csio_evtq_worker()
3578 csio_warn(hw, "Unhandled event %x on evtq\n", csio_evtq_worker()
3580 CSIO_INC_STATS(hw, n_evt_unexp); csio_evtq_worker()
3584 csio_free_evt(hw, evt_msg); csio_evtq_worker()
3587 spin_lock_irq(&hw->lock); csio_evtq_worker()
3589 hw->flags &= ~CSIO_HWF_FWEVT_PENDING; csio_evtq_worker()
3590 spin_unlock_irq(&hw->lock); csio_evtq_worker()
3594 csio_fwevtq_handler(struct csio_hw *hw) csio_fwevtq_handler() argument
3598 if (csio_q_iqid(hw, hw->fwevt_iq_idx) == CSIO_MAX_QID) { csio_fwevtq_handler()
3599 CSIO_INC_STATS(hw, n_int_stray); csio_fwevtq_handler()
3603 rv = csio_wr_process_iq_idx(hw, hw->fwevt_iq_idx, csio_fwevtq_handler()
3649 csio_dbg(mgmtm->hw, "Mgmt timer invoked!\n"); csio_mgmt_tmo_handler()
3651 spin_lock_irq(&mgmtm->hw->lock); csio_mgmt_tmo_handler()
3664 io_req->io_cbfn(mgmtm->hw, io_req); csio_mgmt_tmo_handler()
3675 spin_unlock_irq(&mgmtm->hw->lock); csio_mgmt_tmo_handler()
3681 struct csio_hw *hw = mgmtm->hw; csio_mgmtm_cleanup() local
3689 spin_unlock_irq(&hw->lock); csio_mgmtm_cleanup()
3691 spin_lock_irq(&hw->lock); csio_mgmtm_cleanup()
3703 io_req->io_cbfn(mgmtm->hw, io_req); csio_mgmtm_cleanup()
3711 * @hw - HW module
3723 csio_mgmtm_init(struct csio_mgmtm *mgmtm, struct csio_hw *hw) csio_mgmtm_init() argument
3734 mgmtm->hw = hw; csio_mgmtm_init()
3735 /*mgmtm->iq_idx = hw->fwevt_iq_idx;*/ csio_mgmtm_init()
3758 * @hw: Pointer to HW module.
3765 csio_hw_start(struct csio_hw *hw) csio_hw_start() argument
3767 spin_lock_irq(&hw->lock); csio_hw_start()
3768 csio_post_event(&hw->sm, CSIO_HWE_CFG); csio_hw_start()
3769 spin_unlock_irq(&hw->lock); csio_hw_start()
3771 if (csio_is_hw_ready(hw)) csio_hw_start()
3778 csio_hw_stop(struct csio_hw *hw) csio_hw_stop() argument
3780 csio_post_event(&hw->sm, CSIO_HWE_PCI_REMOVE); csio_hw_stop()
3782 if (csio_is_hw_removing(hw)) csio_hw_stop()
3793 * @hw: HW module.
3798 csio_hw_reset(struct csio_hw *hw) csio_hw_reset() argument
3800 if (!csio_is_hw_master(hw)) csio_hw_reset()
3803 if (hw->rst_retries >= CSIO_MAX_RESET_RETRIES) { csio_hw_reset()
3804 csio_dbg(hw, "Max hw reset attempts reached.."); csio_hw_reset()
3808 hw->rst_retries++; csio_hw_reset()
3809 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET); csio_hw_reset()
3811 if (csio_is_hw_ready(hw)) { csio_hw_reset()
3812 hw->rst_retries = 0; csio_hw_reset()
3813 hw->stats.n_reset_start = jiffies_to_msecs(jiffies); csio_hw_reset()
3821 * @hw: HW module.
3824 csio_hw_get_device_id(struct csio_hw *hw) csio_hw_get_device_id() argument
3827 if (csio_is_dev_id_cached(hw)) csio_hw_get_device_id()
3831 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, csio_hw_get_device_id()
3832 &hw->params.pci.vendor_id); csio_hw_get_device_id()
3833 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, csio_hw_get_device_id()
3834 &hw->params.pci.device_id); csio_hw_get_device_id()
3836 csio_dev_id_cached(hw); csio_hw_get_device_id()
3837 hw->chip_id = (hw->params.pci.device_id & CSIO_HW_CHIP_MASK); csio_hw_get_device_id()
3842 * csio_hw_set_description - Set the model, description of the hw.
3843 * @hw: HW module.
3848 csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id) csio_hw_set_description() argument
3857 memcpy(hw->hw_ver, csio_hw_set_description()
3859 memcpy(hw->model_desc, csio_hw_set_description()
3864 memcpy(hw->model_desc, tempName, 32); csio_hw_set_description()
3871 * @hw: Pointer to HW module.
3876 csio_hw_init(struct csio_hw *hw) csio_hw_init() argument
3883 INIT_LIST_HEAD(&hw->sm.sm_list); csio_hw_init()
3884 csio_init_state(&hw->sm, csio_hws_uninit); csio_hw_init()
3885 spin_lock_init(&hw->lock); csio_hw_init()
3886 INIT_LIST_HEAD(&hw->sln_head); csio_hw_init()
3889 csio_hw_get_device_id(hw); csio_hw_init()
3891 strcpy(hw->name, CSIO_HW_NAME); csio_hw_init()
3894 hw->chip_ops = &t5_ops; csio_hw_init()
3898 ven_id = hw->params.pci.vendor_id; csio_hw_init()
3899 dev_id = hw->params.pci.device_id; csio_hw_init()
3901 csio_hw_set_description(hw, ven_id, dev_id); csio_hw_init()
3904 hw->params.log_level = (uint32_t) csio_dbg_level; csio_hw_init()
3906 csio_set_fwevt_intr_idx(hw, -1); csio_hw_init()
3907 csio_set_nondata_intr_idx(hw, -1); csio_hw_init()
3910 if (csio_mbm_init(csio_hw_to_mbm(hw), hw, csio_hw_mb_timer)) csio_hw_init()
3913 rv = csio_wrm_init(csio_hw_to_wrm(hw), hw); csio_hw_init()
3917 rv = csio_scsim_init(csio_hw_to_scsim(hw), hw); csio_hw_init()
3921 rv = csio_mgmtm_init(csio_hw_to_mgmtm(hw), hw); csio_hw_init()
3925 INIT_LIST_HEAD(&hw->evt_active_q); csio_hw_init()
3926 INIT_LIST_HEAD(&hw->evt_free_q); csio_hw_init()
3932 csio_err(hw, "Failed to initialize eventq"); csio_hw_init()
3936 list_add_tail(&evt_entry->list, &hw->evt_free_q); csio_hw_init()
3937 CSIO_INC_STATS(hw, n_evt_freeq); csio_hw_init()
3940 hw->dev_num = dev_num; csio_hw_init()
3946 csio_evtq_cleanup(hw); csio_hw_init()
3947 csio_mgmtm_exit(csio_hw_to_mgmtm(hw)); csio_hw_init()
3949 csio_scsim_exit(csio_hw_to_scsim(hw)); csio_hw_init()
3951 csio_wrm_exit(csio_hw_to_wrm(hw), hw); csio_hw_init() local
3953 csio_mbm_exit(csio_hw_to_mbm(hw)); csio_hw_init()
3960 * @hw: Pointer to HW module.
3964 csio_hw_exit(struct csio_hw *hw) csio_hw_exit() argument
3966 csio_evtq_cleanup(hw); csio_hw_exit()
3967 csio_mgmtm_exit(csio_hw_to_mgmtm(hw)); csio_hw_exit()
3968 csio_scsim_exit(csio_hw_to_scsim(hw)); csio_hw_exit()
3969 csio_wrm_exit(csio_hw_to_wrm(hw), hw); csio_hw_exit() local
3970 csio_mbm_exit(csio_hw_to_mbm(hw)); csio_hw_exit()
H A Dcsio_wr.c57 csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg) csio_get_flbuf_size() argument
59 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A + csio_get_flbuf_size()
72 csio_wr_qstat_pgsz(struct csio_hw *hw) csio_wr_qstat_pgsz() argument
74 return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64; csio_wr_qstat_pgsz()
79 csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq) csio_wr_ring_fldb() argument
87 csio_wr_reg32(hw, DBPRIO_F | QID_V(flq->un.fl.flid) | csio_wr_ring_fldb()
96 csio_wr_sge_intr_enable(struct csio_hw *hw, uint16_t iqid) csio_wr_sge_intr_enable() argument
98 csio_wr_reg32(hw, CIDXINC_V(0) | csio_wr_sge_intr_enable()
106 * @hw: HW module.
114 csio_wr_fill_fl(struct csio_hw *hw, struct csio_q *flq) csio_wr_fill_fl() argument
116 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_fill_fl()
126 buf->vaddr = pci_alloc_consistent(hw->pdev, buf->len, csio_wr_fill_fl()
129 csio_err(hw, "Could only fill %d buffers!\n", n + 1); csio_wr_fill_fl()
144 * @hw: HW module.
150 csio_wr_update_fl(struct csio_hw *hw, struct csio_q *flq, uint16_t n) csio_wr_update_fl() argument
163 * @hw: HW module
185 csio_wr_alloc_q(struct csio_hw *hw, uint32_t qsize, uint32_t wrsize, csio_wr_alloc_q() argument
189 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_alloc_q()
197 csio_err(hw, "No more free queues.\n"); csio_wr_alloc_q()
203 qsz = ALIGN(qsize, CSIO_QCREDIT_SZ) + csio_wr_qstat_pgsz(hw); csio_wr_alloc_q()
213 csio_err(hw, "Invalid Ingress queue WR size:%d\n", csio_wr_alloc_q()
226 qsz = ALIGN(qsize/wrsize, 8) * wrsize + csio_wr_qstat_pgsz(hw); csio_wr_alloc_q()
229 csio_err(hw, "Invalid queue type: 0x%x\n", type); csio_wr_alloc_q()
235 q->vstart = pci_zalloc_consistent(hw->pdev, qsz, &q->pstart); csio_wr_alloc_q()
237 csio_err(hw, csio_wr_alloc_q()
265 flq_idx = csio_wr_alloc_q(hw, nflb * sizeof(__be64), csio_wr_alloc_q()
269 csio_err(hw, csio_wr_alloc_q()
283 csio_err(hw, csio_wr_alloc_q()
294 if (csio_wr_fill_fl(hw, flq)) csio_wr_alloc_q()
310 csio_q_iqid(hw, ret_idx) = CSIO_MAX_QID; csio_wr_alloc_q()
313 q->credits = (qsz - csio_wr_qstat_pgsz(hw)) / CSIO_QCREDIT_SZ; csio_wr_alloc_q()
315 - csio_wr_qstat_pgsz(hw)); csio_wr_alloc_q()
316 csio_q_eqid(hw, ret_idx) = CSIO_MAX_QID; csio_wr_alloc_q()
318 q->credits = (qsz - csio_wr_qstat_pgsz(hw)) / sizeof(__be64); csio_wr_alloc_q()
320 - csio_wr_qstat_pgsz(hw)); csio_wr_alloc_q()
321 csio_q_flid(hw, ret_idx) = CSIO_MAX_QID; csio_wr_alloc_q()
329 * @hw: The HW module.
336 csio_wr_iq_create_rsp(struct csio_hw *hw, struct csio_mb *mbp, int iq_idx) csio_wr_iq_create_rsp() argument
345 csio_mb_iq_alloc_write_rsp(hw, mbp, &retval, &iqp); csio_wr_iq_create_rsp()
348 csio_err(hw, "IQ cmd returned 0x%x!\n", retval); csio_wr_iq_create_rsp()
349 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_create_rsp()
353 csio_q_iqid(hw, iq_idx) = iqp.iqid; csio_wr_iq_create_rsp()
354 csio_q_physiqid(hw, iq_idx) = iqp.physiqid; csio_wr_iq_create_rsp()
355 csio_q_pidx(hw, iq_idx) = csio_q_cidx(hw, iq_idx) = 0; csio_wr_iq_create_rsp()
356 csio_q_inc_idx(hw, iq_idx) = 0; csio_wr_iq_create_rsp()
359 iq_id = iqp.iqid - hw->wrm.fw_iq_start; csio_wr_iq_create_rsp()
363 csio_err(hw, csio_wr_iq_create_rsp()
366 CSIO_MAX_IQ, iq_id, iqp.iqid, hw->wrm.fw_iq_start); csio_wr_iq_create_rsp()
367 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_create_rsp()
370 csio_q_set_intr_map(hw, iq_idx, iq_id); csio_wr_iq_create_rsp()
380 csio_wr_sge_intr_enable(hw, iqp.physiqid); csio_wr_iq_create_rsp()
382 flq_idx = csio_q_iq_flq_idx(hw, iq_idx); csio_wr_iq_create_rsp()
384 struct csio_q *flq = hw->wrm.q_arr[flq_idx]; csio_wr_iq_create_rsp()
386 csio_q_flid(hw, flq_idx) = iqp.fl0id; csio_wr_iq_create_rsp()
387 csio_q_cidx(hw, flq_idx) = 0; csio_wr_iq_create_rsp()
388 csio_q_pidx(hw, flq_idx) = csio_q_credits(hw, flq_idx) - 8; csio_wr_iq_create_rsp()
389 csio_q_inc_idx(hw, flq_idx) = csio_q_credits(hw, flq_idx) - 8; csio_wr_iq_create_rsp()
392 csio_wr_ring_fldb(hw, flq); csio_wr_iq_create_rsp()
395 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_create_rsp()
402 * @hw: The HW module.
414 csio_wr_iq_create(struct csio_hw *hw, void *priv, int iq_idx, csio_wr_iq_create() argument
423 csio_q_portid(hw, iq_idx) = portid; csio_wr_iq_create()
425 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_wr_iq_create()
427 csio_err(hw, "IQ command out of memory!\n"); csio_wr_iq_create()
431 switch (hw->intr_mode) { csio_wr_iq_create()
435 if (hw->intr_iq_idx == iq_idx) csio_wr_iq_create()
440 csio_q_physiqid(hw, hw->intr_iq_idx); csio_wr_iq_create()
447 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_create()
452 iqp.pfn = hw->pfn; csio_wr_iq_create()
466 switch (csio_q_wr_sz(hw, iq_idx)) { csio_wr_iq_create()
477 iqp.iqsize = csio_q_size(hw, iq_idx) / csio_wr_iq_create()
478 csio_q_wr_sz(hw, iq_idx); csio_wr_iq_create()
479 iqp.iqaddr = csio_q_pstart(hw, iq_idx); csio_wr_iq_create()
481 flq_idx = csio_q_iq_flq_idx(hw, iq_idx); csio_wr_iq_create()
483 struct csio_q *flq = hw->wrm.q_arr[flq_idx]; csio_wr_iq_create()
489 iqp.fl0size = csio_q_size(hw, flq_idx) / CSIO_QCREDIT_SZ; csio_wr_iq_create()
490 iqp.fl0addr = csio_q_pstart(hw, flq_idx); csio_wr_iq_create()
493 csio_mb_iq_alloc_write(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &iqp, cbfn); csio_wr_iq_create()
495 if (csio_mb_issue(hw, mbp)) { csio_wr_iq_create()
496 csio_err(hw, "Issue of IQ cmd failed!\n"); csio_wr_iq_create()
497 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_create()
504 return csio_wr_iq_create_rsp(hw, mbp, iq_idx); csio_wr_iq_create()
509 * @hw: The HW module.
516 csio_wr_eq_cfg_rsp(struct csio_hw *hw, struct csio_mb *mbp, int eq_idx) csio_wr_eq_cfg_rsp() argument
523 csio_mb_eq_ofld_alloc_write_rsp(hw, mbp, &retval, &eqp); csio_wr_eq_cfg_rsp()
526 csio_err(hw, "EQ OFLD cmd returned 0x%x!\n", retval); csio_wr_eq_cfg_rsp()
527 mempool_free(mbp, hw->mb_mempool); csio_wr_eq_cfg_rsp()
531 csio_q_eqid(hw, eq_idx) = (uint16_t)eqp.eqid; csio_wr_eq_cfg_rsp()
532 csio_q_physeqid(hw, eq_idx) = (uint16_t)eqp.physeqid; csio_wr_eq_cfg_rsp()
533 csio_q_pidx(hw, eq_idx) = csio_q_cidx(hw, eq_idx) = 0; csio_wr_eq_cfg_rsp()
534 csio_q_inc_idx(hw, eq_idx) = 0; csio_wr_eq_cfg_rsp()
536 mempool_free(mbp, hw->mb_mempool); csio_wr_eq_cfg_rsp()
543 * @hw: HW module.
553 csio_wr_eq_create(struct csio_hw *hw, void *priv, int eq_idx, csio_wr_eq_create() argument
562 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_wr_eq_create()
564 csio_err(hw, "EQ command out of memory!\n"); csio_wr_eq_create()
568 eqp.pfn = hw->pfn; csio_wr_eq_create()
572 eqp.iqid = csio_q_iqid(hw, iq_idx); csio_wr_eq_create()
577 eqp.eqsize = csio_q_size(hw, eq_idx) / CSIO_QCREDIT_SZ; csio_wr_eq_create()
578 eqp.eqaddr = csio_q_pstart(hw, eq_idx); csio_wr_eq_create()
580 csio_mb_eq_ofld_alloc_write(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, csio_wr_eq_create()
583 if (csio_mb_issue(hw, mbp)) { csio_wr_eq_create()
584 csio_err(hw, "Issue of EQ OFLD cmd failed!\n"); csio_wr_eq_create()
585 mempool_free(mbp, hw->mb_mempool); csio_wr_eq_create()
592 return csio_wr_eq_cfg_rsp(hw, mbp, eq_idx); csio_wr_eq_create()
597 * @hw: The HW module.
604 csio_wr_iq_destroy_rsp(struct csio_hw *hw, struct csio_mb *mbp, int iq_idx) csio_wr_iq_destroy_rsp() argument
612 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_destroy_rsp()
619 * @hw: The HW module.
628 csio_wr_iq_destroy(struct csio_hw *hw, void *priv, int iq_idx, csio_wr_iq_destroy() argument
638 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_wr_iq_destroy()
642 iqp.pfn = hw->pfn; csio_wr_iq_destroy()
644 iqp.iqid = csio_q_iqid(hw, iq_idx); csio_wr_iq_destroy()
647 flq_idx = csio_q_iq_flq_idx(hw, iq_idx); csio_wr_iq_destroy()
649 iqp.fl0id = csio_q_flid(hw, flq_idx); csio_wr_iq_destroy()
655 csio_mb_iq_free(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &iqp, cbfn); csio_wr_iq_destroy()
657 rv = csio_mb_issue(hw, mbp); csio_wr_iq_destroy()
659 mempool_free(mbp, hw->mb_mempool); csio_wr_iq_destroy()
666 return csio_wr_iq_destroy_rsp(hw, mbp, iq_idx); csio_wr_iq_destroy()
671 * @hw: The HW module.
678 csio_wr_eq_destroy_rsp(struct csio_hw *hw, struct csio_mb *mbp, int eq_idx) csio_wr_eq_destroy_rsp() argument
686 mempool_free(mbp, hw->mb_mempool); csio_wr_eq_destroy_rsp()
693 * @hw: The HW module.
702 csio_wr_eq_destroy(struct csio_hw *hw, void *priv, int eq_idx, csio_wr_eq_destroy() argument
711 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); csio_wr_eq_destroy()
715 eqp.pfn = hw->pfn; csio_wr_eq_destroy()
717 eqp.eqid = csio_q_eqid(hw, eq_idx); csio_wr_eq_destroy()
719 csio_mb_eq_ofld_free(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &eqp, cbfn); csio_wr_eq_destroy()
721 rv = csio_mb_issue(hw, mbp); csio_wr_eq_destroy()
723 mempool_free(mbp, hw->mb_mempool); csio_wr_eq_destroy()
730 return csio_wr_eq_destroy_rsp(hw, mbp, eq_idx); csio_wr_eq_destroy()
735 * @hw: HW module
741 csio_wr_cleanup_eq_stpg(struct csio_hw *hw, int qidx) csio_wr_cleanup_eq_stpg() argument
743 struct csio_q *q = csio_hw_to_wrm(hw)->q_arr[qidx]; csio_wr_cleanup_eq_stpg()
751 * @hw: HW module
758 csio_wr_cleanup_iq_ftr(struct csio_hw *hw, int qidx) csio_wr_cleanup_iq_ftr() argument
760 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_cleanup_iq_ftr()
782 csio_wr_destroy_queues(struct csio_hw *hw, bool cmd) csio_wr_destroy_queues() argument
786 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_destroy_queues()
794 if (csio_q_eqid(hw, i) != CSIO_MAX_QID) { csio_wr_destroy_queues()
795 csio_wr_cleanup_eq_stpg(hw, i); csio_wr_destroy_queues()
797 csio_q_eqid(hw, i) = CSIO_MAX_QID; csio_wr_destroy_queues()
801 rv = csio_wr_eq_destroy(hw, NULL, i, NULL); csio_wr_destroy_queues()
805 csio_q_eqid(hw, i) = CSIO_MAX_QID; csio_wr_destroy_queues()
808 if (csio_q_iqid(hw, i) != CSIO_MAX_QID) { csio_wr_destroy_queues()
809 csio_wr_cleanup_iq_ftr(hw, i); csio_wr_destroy_queues()
811 csio_q_iqid(hw, i) = CSIO_MAX_QID; csio_wr_destroy_queues()
812 flq_idx = csio_q_iq_flq_idx(hw, i); csio_wr_destroy_queues()
814 csio_q_flid(hw, flq_idx) = csio_wr_destroy_queues()
819 rv = csio_wr_iq_destroy(hw, NULL, i, NULL); csio_wr_destroy_queues()
823 csio_q_iqid(hw, i) = CSIO_MAX_QID; csio_wr_destroy_queues()
824 flq_idx = csio_q_iq_flq_idx(hw, i); csio_wr_destroy_queues()
826 csio_q_flid(hw, flq_idx) = CSIO_MAX_QID; csio_wr_destroy_queues()
833 hw->flags &= ~CSIO_HWF_Q_FW_ALLOCED; csio_wr_destroy_queues()
840 * @hw: HW module.
857 csio_wr_get(struct csio_hw *hw, int qidx, uint32_t size, csio_wr_get() argument
860 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_get()
967 * @hw: HW module.
976 csio_wr_issue(struct csio_hw *hw, int qidx, bool prio) csio_wr_issue() argument
978 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_issue()
985 csio_wr_reg32(hw, DBPRIO_V(prio) | QID_V(q->un.eq.physeqid) | csio_wr_issue()
1006 * @hw: HW module.
1016 csio_wr_inval_flq_buf(struct csio_hw *hw, struct csio_q *flq) csio_wr_inval_flq_buf() argument
1027 * @hw: HW module.
1036 csio_wr_process_fl(struct csio_hw *hw, struct csio_q *q, csio_wr_process_fl() argument
1043 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_process_fl()
1049 struct csio_q *flq = hw->wrm.q_arr[q->un.iq.flq_idx]; csio_wr_process_fl()
1057 csio_wr_inval_flq_buf(hw, flq); csio_wr_process_fl()
1082 csio_wr_inval_flq_buf(hw, flq); csio_wr_process_fl()
1087 iq_handler(hw, wr, q->wr_sz - sizeof(struct csio_iqwr_footer), csio_wr_process_fl()
1093 csio_wr_inval_flq_buf(hw, flq); csio_wr_process_fl()
1113 * @hw: HW pointer
1123 csio_wr_process_iq(struct csio_hw *hw, struct csio_q *q, csio_wr_process_iq() argument
1129 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_process_iq()
1156 iq_handler(hw, wr, q->wr_sz - sizeof(*ftr), NULL, priv); csio_wr_process_iq()
1159 csio_wr_process_fl(hw, q, wr, csio_wr_process_iq()
1166 q_completed = hw->wrm.intr_map[qid]; csio_wr_process_iq()
1169 csio_q_physiqid(hw, hw->intr_iq_idx))) { csio_wr_process_iq()
1182 q_completed->un.iq.iq_intx_handler(hw, NULL, csio_wr_process_iq()
1187 csio_warn(hw, "Unknown resp type 0x%x received\n", csio_wr_process_iq()
1238 csio_wr_update_fl(hw, flq, (flq->credits - 8) - avail); csio_wr_process_iq()
1239 csio_wr_ring_fldb(hw, flq); csio_wr_process_iq()
1245 csio_wr_reg32(hw, CIDXINC_V(q->inc_idx) | csio_wr_process_iq()
1257 csio_wr_process_iq_idx(struct csio_hw *hw, int qidx, csio_wr_process_iq_idx() argument
1263 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_process_iq_idx()
1266 return csio_wr_process_iq(hw, iq, iq_handler, priv); csio_wr_process_iq_idx()
1304 csio_wr_fixup_host_params(struct csio_hw *hw) csio_wr_fixup_host_params() argument
1306 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_fixup_host_params()
1313 csio_wr_reg32(hw, HOSTPAGESIZEPF0_V(s_hps) | HOSTPAGESIZEPF1_V(s_hps) | csio_wr_fixup_host_params()
1322 csio_set_reg_field(hw, SGE_CONTROL_A, csio_wr_fixup_host_params()
1329 csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0_A); csio_wr_fixup_host_params()
1335 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) { csio_wr_fixup_host_params()
1336 csio_wr_reg32(hw, csio_wr_fixup_host_params()
1337 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2_A) + csio_wr_fixup_host_params()
1340 csio_wr_reg32(hw, csio_wr_fixup_host_params()
1341 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3_A) + csio_wr_fixup_host_params()
1346 csio_wr_reg32(hw, HPZ0_V(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ_A); csio_wr_fixup_host_params()
1349 csio_set_reg_field(hw, SGE_CONTROL_A, csio_wr_fixup_host_params()
1353 csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG_A, csio_wr_fixup_host_params()
1358 csio_init_intr_coalesce_parms(struct csio_hw *hw) csio_init_intr_coalesce_parms() argument
1360 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_init_intr_coalesce_parms()
1375 * @hw: HW module.
1380 csio_wr_get_sge(struct csio_hw *hw) csio_wr_get_sge() argument
1382 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_get_sge()
1389 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A); csio_wr_get_sge()
1413 csio_get_flbuf_size(hw, sge, i); csio_wr_get_sge()
1415 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A); csio_wr_get_sge()
1416 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A); csio_wr_get_sge()
1417 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A); csio_wr_get_sge()
1419 sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw, csio_wr_get_sge()
1421 sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw, csio_wr_get_sge()
1423 sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw, csio_wr_get_sge()
1425 sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw, csio_wr_get_sge()
1427 sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw, csio_wr_get_sge()
1429 sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw, csio_wr_get_sge()
1432 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A); csio_wr_get_sge()
1438 csio_init_intr_coalesce_parms(hw); csio_wr_get_sge()
1443 * @hw: HW module.
1449 csio_wr_set_sge(struct csio_hw *hw) csio_wr_set_sge() argument
1451 struct csio_wrm *wrm = csio_hw_to_wrm(hw); csio_wr_set_sge()
1459 csio_set_reg_field(hw, SGE_CONTROL_A, RXPKTCPLMODE_F, RXPKTCPLMODE_F); csio_wr_set_sge()
1461 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A); csio_wr_set_sge()
1469 csio_set_reg_field(hw, SGE_DBFIFO_STATUS_A, csio_wr_set_sge()
1472 csio_set_reg_field(hw, SGE_DBFIFO_STATUS2_A, csio_wr_set_sge()
1476 csio_set_reg_field(hw, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F, csio_wr_set_sge()
1481 CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1); csio_wr_set_sge()
1482 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1) csio_wr_set_sge()
1484 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1) csio_wr_set_sge()
1486 CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4); csio_wr_set_sge()
1487 CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5); csio_wr_set_sge()
1488 CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6); csio_wr_set_sge()
1489 CSIO_SET_FLBUF_SIZE(hw, 7, CSIO_SGE_FLBUF_SIZE7); csio_wr_set_sge()
1490 CSIO_SET_FLBUF_SIZE(hw, 8, CSIO_SGE_FLBUF_SIZE8); csio_wr_set_sge()
1493 csio_get_flbuf_size(hw, sge, i); csio_wr_set_sge()
1508 csio_wr_reg32(hw, THRESHOLD_0_V(sge->counter_val[0]) | csio_wr_set_sge()
1514 csio_wr_reg32(hw, csio_wr_set_sge()
1515 TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) | csio_wr_set_sge()
1516 TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])), csio_wr_set_sge()
1519 csio_wr_reg32(hw, csio_wr_set_sge()
1520 TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) | csio_wr_set_sge()
1521 TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])), csio_wr_set_sge()
1524 csio_wr_reg32(hw, csio_wr_set_sge()
1525 TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) | csio_wr_set_sge()
1526 TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])), csio_wr_set_sge()
1529 csio_init_intr_coalesce_parms(hw); csio_wr_set_sge()
1533 csio_wr_sge_init(struct csio_hw *hw) csio_wr_sge_init() argument
1551 if (csio_is_hw_master(hw)) { csio_wr_sge_init()
1552 if (hw->fw_state != CSIO_DEV_STATE_INIT) csio_wr_sge_init()
1553 csio_wr_fixup_host_params(hw); csio_wr_sge_init()
1555 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) csio_wr_sge_init()
1556 csio_wr_get_sge(hw); csio_wr_sge_init()
1558 csio_wr_set_sge(hw); csio_wr_sge_init()
1560 csio_wr_get_sge(hw); csio_wr_sge_init()
1566 * @hw: HW pointer
1571 csio_wrm_init(struct csio_wrm *wrm, struct csio_hw *hw) csio_wrm_init() argument
1576 csio_err(hw, "Num queues is not set\n"); csio_wrm_init()
1605 * @hw: HW module
1612 csio_wrm_exit(struct csio_wrm *wrm, struct csio_hw *hw) csio_wrm_exit() argument
1630 pci_free_consistent(hw->pdev, buf->len, csio_wrm_exit()
1636 pci_free_consistent(hw->pdev, q->size, csio_wrm_exit()
1642 hw->flags &= ~CSIO_HWF_Q_MEM_ALLOCED; csio_wrm_exit()
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
54 * @hw: pointer to the hardware structure
59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) ixgbe_out_i2c_byte_ack() argument
63 status = ixgbe_clock_out_i2c_byte(hw, byte); ixgbe_out_i2c_byte_ack()
66 return ixgbe_get_i2c_ack(hw); ixgbe_out_i2c_byte_ack()
71 * @hw: pointer to the hardware structure
76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) ixgbe_in_i2c_byte_ack() argument
80 status = ixgbe_clock_in_i2c_byte(hw, byte); ixgbe_in_i2c_byte_ack()
84 return ixgbe_clock_out_i2c_bit(hw, false); ixgbe_in_i2c_byte_ack()
104 * @hw: pointer to the hardware structure
112 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, ixgbe_read_i2c_combined_generic_int() argument
115 u32 swfw_mask = hw->phy.phy_semaphore_mask; ixgbe_read_i2c_combined_generic_int()
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) ixgbe_read_i2c_combined_generic_int()
130 ixgbe_i2c_start(hw); ixgbe_read_i2c_combined_generic_int()
132 if (ixgbe_out_i2c_byte_ack(hw, addr)) ixgbe_read_i2c_combined_generic_int()
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) ixgbe_read_i2c_combined_generic_int()
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) ixgbe_read_i2c_combined_generic_int()
141 if (ixgbe_out_i2c_byte_ack(hw, csum)) ixgbe_read_i2c_combined_generic_int()
144 ixgbe_i2c_start(hw); ixgbe_read_i2c_combined_generic_int()
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) ixgbe_read_i2c_combined_generic_int()
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) ixgbe_read_i2c_combined_generic_int()
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) ixgbe_read_i2c_combined_generic_int()
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) ixgbe_read_i2c_combined_generic_int()
158 if (ixgbe_clock_out_i2c_bit(hw, false)) ixgbe_read_i2c_combined_generic_int()
160 ixgbe_i2c_stop(hw); ixgbe_read_i2c_combined_generic_int()
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_read_i2c_combined_generic_int()
167 ixgbe_i2c_bus_clear(hw); ixgbe_read_i2c_combined_generic_int()
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_read_i2c_combined_generic_int()
172 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); ixgbe_read_i2c_combined_generic_int()
174 hw_dbg(hw, "I2C byte read combined error.\n"); ixgbe_read_i2c_combined_generic_int()
182 * @hw: pointer to the hardware structure
189 s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, ixgbe_read_i2c_combined_generic() argument
192 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); ixgbe_read_i2c_combined_generic()
197 * @hw: pointer to the hardware structure
204 s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, ixgbe_read_i2c_combined_generic_unlocked() argument
207 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); ixgbe_read_i2c_combined_generic_unlocked()
212 * @hw: pointer to the hardware structure
220 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, ixgbe_write_i2c_combined_generic_int() argument
223 u32 swfw_mask = hw->phy.phy_semaphore_mask; ixgbe_write_i2c_combined_generic_int()
235 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) ixgbe_write_i2c_combined_generic_int()
237 ixgbe_i2c_start(hw); ixgbe_write_i2c_combined_generic_int()
239 if (ixgbe_out_i2c_byte_ack(hw, addr)) ixgbe_write_i2c_combined_generic_int()
242 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) ixgbe_write_i2c_combined_generic_int()
245 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) ixgbe_write_i2c_combined_generic_int()
248 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) ixgbe_write_i2c_combined_generic_int()
251 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) ixgbe_write_i2c_combined_generic_int()
254 if (ixgbe_out_i2c_byte_ack(hw, csum)) ixgbe_write_i2c_combined_generic_int()
256 ixgbe_i2c_stop(hw); ixgbe_write_i2c_combined_generic_int()
258 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_write_i2c_combined_generic_int()
262 ixgbe_i2c_bus_clear(hw); ixgbe_write_i2c_combined_generic_int()
264 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_write_i2c_combined_generic_int()
267 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); ixgbe_write_i2c_combined_generic_int()
269 hw_dbg(hw, "I2C byte write combined error.\n"); ixgbe_write_i2c_combined_generic_int()
277 * @hw: pointer to the hardware structure
284 s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, ixgbe_write_i2c_combined_generic() argument
287 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); ixgbe_write_i2c_combined_generic()
292 * @hw: pointer to the hardware structure
299 s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, ixgbe_write_i2c_combined_generic_unlocked() argument
302 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); ixgbe_write_i2c_combined_generic_unlocked()
307 * @hw: pointer to hardware structure
311 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) ixgbe_identify_phy_generic() argument
316 if (!hw->phy.phy_semaphore_mask) { ixgbe_identify_phy_generic()
317 if (hw->bus.lan_id) ixgbe_identify_phy_generic()
318 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; ixgbe_identify_phy_generic()
320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; ixgbe_identify_phy_generic()
323 if (hw->phy.type == ixgbe_phy_unknown) { ixgbe_identify_phy_generic()
325 hw->phy.mdio.prtad = phy_addr; ixgbe_identify_phy_generic()
326 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { ixgbe_identify_phy_generic()
327 ixgbe_get_phy_id(hw); ixgbe_identify_phy_generic()
328 hw->phy.type = ixgbe_identify_phy_generic()
329 ixgbe_get_phy_type_from_id(hw->phy.id); ixgbe_identify_phy_generic()
331 if (hw->phy.type == ixgbe_phy_unknown) { ixgbe_identify_phy_generic()
332 hw->phy.ops.read_reg(hw, ixgbe_identify_phy_generic()
339 hw->phy.type = ixgbe_identify_phy_generic()
342 hw->phy.type = ixgbe_identify_phy_generic()
350 hw->phy.mdio.prtad = 0; ixgbe_identify_phy_generic()
358 * @hw: pointer to the hardware structure
365 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) ixgbe_check_reset_blocked() argument
370 if (hw->mac.type == ixgbe_mac_82598EB) ixgbe_check_reset_blocked()
373 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); ixgbe_check_reset_blocked()
375 hw_dbg(hw, "MNG_VETO bit detected.\n"); ixgbe_check_reset_blocked()
384 * @hw: pointer to hardware structure
387 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) ixgbe_get_phy_id() argument
393 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, ixgbe_get_phy_id()
397 hw->phy.id = (u32)(phy_id_high << 16); ixgbe_get_phy_id()
398 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, ixgbe_get_phy_id()
400 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); ixgbe_get_phy_id()
401 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); ixgbe_get_phy_id()
408 * @hw: pointer to hardware structure
442 * @hw: pointer to hardware structure
444 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) ixgbe_reset_phy_generic() argument
450 if (hw->phy.type == ixgbe_phy_unknown) ixgbe_reset_phy_generic()
451 status = ixgbe_identify_phy_generic(hw); ixgbe_reset_phy_generic()
453 if (status != 0 || hw->phy.type == ixgbe_phy_none) ixgbe_reset_phy_generic()
457 if (!hw->phy.reset_if_overtemp && ixgbe_reset_phy_generic()
458 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) ixgbe_reset_phy_generic()
462 if (ixgbe_check_reset_blocked(hw)) ixgbe_reset_phy_generic()
469 hw->phy.ops.write_reg(hw, MDIO_CTRL1, ixgbe_reset_phy_generic()
480 hw->phy.ops.read_reg(hw, MDIO_CTRL1, ixgbe_reset_phy_generic()
489 hw_dbg(hw, "PHY reset polling failed to complete.\n"); ixgbe_reset_phy_generic()
499 * @hw: pointer to hardware structure
503 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, ixgbe_read_phy_reg_mdi() argument
511 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | ixgbe_read_phy_reg_mdi()
514 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); ixgbe_read_phy_reg_mdi()
523 command = IXGBE_READ_REG(hw, IXGBE_MSCA); ixgbe_read_phy_reg_mdi()
530 hw_dbg(hw, "PHY address command did not complete.\n"); ixgbe_read_phy_reg_mdi()
539 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | ixgbe_read_phy_reg_mdi()
542 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); ixgbe_read_phy_reg_mdi()
551 command = IXGBE_READ_REG(hw, IXGBE_MSCA); ixgbe_read_phy_reg_mdi()
557 hw_dbg(hw, "PHY read command didn't complete\n"); ixgbe_read_phy_reg_mdi()
564 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); ixgbe_read_phy_reg_mdi()
574 * @hw: pointer to hardware structure
578 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_read_phy_reg_generic() argument
582 u32 gssr = hw->phy.phy_semaphore_mask; ixgbe_read_phy_reg_generic()
584 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { ixgbe_read_phy_reg_generic()
585 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, ixgbe_read_phy_reg_generic()
587 hw->mac.ops.release_swfw_sync(hw, gssr); ixgbe_read_phy_reg_generic()
598 * @hw: pointer to hardware structure
603 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_write_phy_reg_mdi() argument
609 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); ixgbe_write_phy_reg_mdi()
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | ixgbe_write_phy_reg_mdi()
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); ixgbe_write_phy_reg_mdi()
627 command = IXGBE_READ_REG(hw, IXGBE_MSCA); ixgbe_write_phy_reg_mdi()
633 hw_dbg(hw, "PHY address cmd didn't complete\n"); ixgbe_write_phy_reg_mdi()
643 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | ixgbe_write_phy_reg_mdi()
646 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); ixgbe_write_phy_reg_mdi()
655 command = IXGBE_READ_REG(hw, IXGBE_MSCA); ixgbe_write_phy_reg_mdi()
661 hw_dbg(hw, "PHY write cmd didn't complete\n"); ixgbe_write_phy_reg_mdi()
671 * @hw: pointer to hardware structure
676 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_write_phy_reg_generic() argument
680 u32 gssr = hw->phy.phy_semaphore_mask; ixgbe_write_phy_reg_generic()
682 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { ixgbe_write_phy_reg_generic()
683 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, ixgbe_write_phy_reg_generic()
685 hw->mac.ops.release_swfw_sync(hw, gssr); ixgbe_write_phy_reg_generic()
695 * @hw: pointer to hardware structure
699 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) ixgbe_setup_phy_link_generic() argument
706 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); ixgbe_setup_phy_link_generic()
710 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, ixgbe_setup_phy_link_generic()
715 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) ixgbe_setup_phy_link_generic()
718 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, ixgbe_setup_phy_link_generic()
725 hw->phy.ops.read_reg(hw, ixgbe_setup_phy_link_generic()
731 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) ixgbe_setup_phy_link_generic()
734 hw->phy.ops.write_reg(hw, ixgbe_setup_phy_link_generic()
742 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_phy_link_generic()
748 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) ixgbe_setup_phy_link_generic()
751 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_phy_link_generic()
757 if (ixgbe_check_reset_blocked(hw)) ixgbe_setup_phy_link_generic()
761 hw->phy.ops.read_reg(hw, MDIO_CTRL1, ixgbe_setup_phy_link_generic()
766 hw->phy.ops.write_reg(hw, MDIO_CTRL1, ixgbe_setup_phy_link_generic()
774 * @hw: pointer to hardware structure
777 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, ixgbe_setup_phy_link_speed_generic() argument
786 hw->phy.autoneg_advertised = 0; ixgbe_setup_phy_link_speed_generic()
789 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; ixgbe_setup_phy_link_speed_generic()
792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; ixgbe_setup_phy_link_speed_generic()
795 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; ixgbe_setup_phy_link_speed_generic()
798 hw->phy.ops.setup_link(hw); ixgbe_setup_phy_link_speed_generic()
805 * @hw: pointer to hardware structure
810 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) ixgbe_get_copper_speeds_supported() argument
815 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, ixgbe_get_copper_speeds_supported()
821 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; ixgbe_get_copper_speeds_supported()
823 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; ixgbe_get_copper_speeds_supported()
825 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; ixgbe_get_copper_speeds_supported()
827 switch (hw->mac.type) { ixgbe_get_copper_speeds_supported()
829 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; ixgbe_get_copper_speeds_supported()
830 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; ixgbe_get_copper_speeds_supported()
833 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; ixgbe_get_copper_speeds_supported()
844 * @hw: pointer to hardware structure
848 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ixgbe_get_copper_link_capabilities_generic() argument
855 if (!hw->phy.speeds_supported) ixgbe_get_copper_link_capabilities_generic()
856 status = ixgbe_get_copper_speeds_supported(hw); ixgbe_get_copper_link_capabilities_generic()
858 *speed = hw->phy.speeds_supported; ixgbe_get_copper_link_capabilities_generic()
864 * @hw: pointer to hardware structure
869 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ixgbe_check_phy_link_tnx() argument
890 status = hw->phy.ops.read_reg(hw, ixgbe_check_phy_link_tnx()
912 * @hw: pointer to hardware structure
919 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) ixgbe_setup_phy_link_tnx() argument
925 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); ixgbe_setup_phy_link_tnx()
929 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, ixgbe_setup_phy_link_tnx()
934 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) ixgbe_setup_phy_link_tnx()
937 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, ixgbe_setup_phy_link_tnx()
944 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, ixgbe_setup_phy_link_tnx()
949 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) ixgbe_setup_phy_link_tnx()
952 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, ixgbe_setup_phy_link_tnx()
959 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_phy_link_tnx()
965 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) ixgbe_setup_phy_link_tnx()
968 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_phy_link_tnx()
974 if (ixgbe_check_reset_blocked(hw)) ixgbe_setup_phy_link_tnx()
978 hw->phy.ops.read_reg(hw, MDIO_CTRL1, ixgbe_setup_phy_link_tnx()
983 hw->phy.ops.write_reg(hw, MDIO_CTRL1, ixgbe_setup_phy_link_tnx()
990 * @hw: pointer to hardware structure
993 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, ixgbe_get_phy_firmware_version_tnx() argument
998 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, ixgbe_get_phy_firmware_version_tnx()
1007 * @hw: pointer to hardware structure
1010 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, ixgbe_get_phy_firmware_version_generic() argument
1015 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, ixgbe_get_phy_firmware_version_generic()
1024 * @hw: pointer to hardware structure
1026 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) ixgbe_reset_phy_nl() argument
1036 if (ixgbe_check_reset_blocked(hw)) ixgbe_reset_phy_nl()
1039 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); ixgbe_reset_phy_nl()
1042 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, ixgbe_reset_phy_nl()
1046 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, ixgbe_reset_phy_nl()
1054 hw_dbg(hw, "PHY reset did not complete.\n"); ixgbe_reset_phy_nl()
1059 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, ixgbe_reset_phy_nl()
1064 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); ixgbe_reset_phy_nl()
1070 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); ixgbe_reset_phy_nl()
1079 hw_dbg(hw, "DELAY: %d MS\n", edata); ixgbe_reset_phy_nl()
1083 hw_dbg(hw, "DATA:\n"); ixgbe_reset_phy_nl()
1085 ret_val = hw->eeprom.ops.read(hw, data_offset++, ixgbe_reset_phy_nl()
1090 ret_val = hw->eeprom.ops.read(hw, data_offset, ixgbe_reset_phy_nl()
1094 hw->phy.ops.write_reg(hw, phy_offset, ixgbe_reset_phy_nl()
1096 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, ixgbe_reset_phy_nl()
1104 hw_dbg(hw, "CONTROL:\n"); ixgbe_reset_phy_nl()
1106 hw_dbg(hw, "EOL\n"); ixgbe_reset_phy_nl()
1109 hw_dbg(hw, "SOL\n"); ixgbe_reset_phy_nl()
1111 hw_dbg(hw, "Bad control value\n"); ixgbe_reset_phy_nl()
1116 hw_dbg(hw, "Bad control type\n"); ixgbe_reset_phy_nl()
1124 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); ixgbe_reset_phy_nl()
1130 * @hw: pointer to hardware structure
1134 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) ixgbe_identify_module_generic() argument
1136 switch (hw->mac.ops.get_media_type(hw)) { ixgbe_identify_module_generic()
1138 return ixgbe_identify_sfp_module_generic(hw); ixgbe_identify_module_generic()
1140 return ixgbe_identify_qsfp_module_generic(hw); ixgbe_identify_module_generic()
1142 hw->phy.sfp_type = ixgbe_sfp_type_not_present; ixgbe_identify_module_generic()
1151 * @hw: pointer to hardware structure
1155 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) ixgbe_identify_sfp_module_generic() argument
1157 struct ixgbe_adapter *adapter = hw->back; ixgbe_identify_sfp_module_generic()
1160 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; ixgbe_identify_sfp_module_generic()
1169 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { ixgbe_identify_sfp_module_generic()
1170 hw->phy.sfp_type = ixgbe_sfp_type_not_present; ixgbe_identify_sfp_module_generic()
1175 hw->mac.ops.set_lan_id(hw); ixgbe_identify_sfp_module_generic()
1177 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1185 hw->phy.type = ixgbe_phy_sfp_unsupported; ixgbe_identify_sfp_module_generic()
1188 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1195 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1201 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1224 if (hw->mac.type == ixgbe_mac_82598EB) { ixgbe_identify_sfp_module_generic()
1226 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; ixgbe_identify_sfp_module_generic()
1228 hw->phy.sfp_type = ixgbe_sfp_type_sr; ixgbe_identify_sfp_module_generic()
1230 hw->phy.sfp_type = ixgbe_sfp_type_lr; ixgbe_identify_sfp_module_generic()
1232 hw->phy.sfp_type = ixgbe_sfp_type_unknown; ixgbe_identify_sfp_module_generic()
1235 if (hw->bus.lan_id == 0) ixgbe_identify_sfp_module_generic()
1236 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1239 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1242 hw->phy.ops.read_i2c_eeprom( ixgbe_identify_sfp_module_generic()
1243 hw, IXGBE_SFF_CABLE_SPEC_COMP, ixgbe_identify_sfp_module_generic()
1247 if (hw->bus.lan_id == 0) ixgbe_identify_sfp_module_generic()
1248 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1251 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1254 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1260 if (hw->bus.lan_id == 0) ixgbe_identify_sfp_module_generic()
1261 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1264 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1267 if (hw->bus.lan_id == 0) ixgbe_identify_sfp_module_generic()
1268 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1271 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1274 if (hw->bus.lan_id == 0) ixgbe_identify_sfp_module_generic()
1275 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1278 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1281 if (hw->bus.lan_id == 0) ixgbe_identify_sfp_module_generic()
1282 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1285 hw->phy.sfp_type = ixgbe_identify_sfp_module_generic()
1288 hw->phy.sfp_type = ixgbe_sfp_type_unknown; ixgbe_identify_sfp_module_generic()
1292 if (hw->phy.sfp_type != stored_sfp_type) ixgbe_identify_sfp_module_generic()
1293 hw->phy.sfp_setup_needed = true; ixgbe_identify_sfp_module_generic()
1296 hw->phy.multispeed_fiber = false; ixgbe_identify_sfp_module_generic()
1301 hw->phy.multispeed_fiber = true; ixgbe_identify_sfp_module_generic()
1304 if (hw->phy.type != ixgbe_phy_nl) { ixgbe_identify_sfp_module_generic()
1305 hw->phy.id = identifier; ixgbe_identify_sfp_module_generic()
1306 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1313 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1320 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_sfp_module_generic()
1335 hw->phy.type = ixgbe_identify_sfp_module_generic()
1340 hw->phy.type = ixgbe_phy_sfp_ftl_active; ixgbe_identify_sfp_module_generic()
1342 hw->phy.type = ixgbe_phy_sfp_ftl; ixgbe_identify_sfp_module_generic()
1345 hw->phy.type = ixgbe_phy_sfp_avago; ixgbe_identify_sfp_module_generic()
1348 hw->phy.type = ixgbe_phy_sfp_intel; ixgbe_identify_sfp_module_generic()
1352 hw->phy.type = ixgbe_identify_sfp_module_generic()
1355 hw->phy.type = ixgbe_identify_sfp_module_generic()
1358 hw->phy.type = ixgbe_phy_sfp_unknown; ixgbe_identify_sfp_module_generic()
1370 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || ixgbe_identify_sfp_module_generic()
1371 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || ixgbe_identify_sfp_module_generic()
1372 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || ixgbe_identify_sfp_module_generic()
1373 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || ixgbe_identify_sfp_module_generic()
1374 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || ixgbe_identify_sfp_module_generic()
1375 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { ixgbe_identify_sfp_module_generic()
1376 hw->phy.type = ixgbe_phy_sfp_unsupported; ixgbe_identify_sfp_module_generic()
1381 if (hw->mac.type == ixgbe_mac_82598EB) ixgbe_identify_sfp_module_generic()
1384 hw->mac.ops.get_device_caps(hw, &enforce_sfp); ixgbe_identify_sfp_module_generic()
1386 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || ixgbe_identify_sfp_module_generic()
1387 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || ixgbe_identify_sfp_module_generic()
1388 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || ixgbe_identify_sfp_module_generic()
1389 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || ixgbe_identify_sfp_module_generic()
1390 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || ixgbe_identify_sfp_module_generic()
1391 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { ixgbe_identify_sfp_module_generic()
1393 if (hw->phy.type == ixgbe_phy_sfp_intel) ixgbe_identify_sfp_module_generic()
1395 if (hw->allow_unsupported_sfp) { ixgbe_identify_sfp_module_generic()
1399 hw_dbg(hw, "SFP+ module not supported\n"); ixgbe_identify_sfp_module_generic()
1400 hw->phy.type = ixgbe_phy_sfp_unsupported; ixgbe_identify_sfp_module_generic()
1406 hw->phy.sfp_type = ixgbe_sfp_type_not_present; ixgbe_identify_sfp_module_generic()
1407 if (hw->phy.type != ixgbe_phy_nl) { ixgbe_identify_sfp_module_generic()
1408 hw->phy.id = 0; ixgbe_identify_sfp_module_generic()
1409 hw->phy.type = ixgbe_phy_unknown; ixgbe_identify_sfp_module_generic()
1416 * @hw: pointer to hardware structure
1420 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) ixgbe_identify_qsfp_module_generic() argument
1422 struct ixgbe_adapter *adapter = hw->back; ixgbe_identify_qsfp_module_generic()
1425 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; ixgbe_identify_qsfp_module_generic()
1436 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { ixgbe_identify_qsfp_module_generic()
1437 hw->phy.sfp_type = ixgbe_sfp_type_not_present; ixgbe_identify_qsfp_module_generic()
1442 hw->mac.ops.set_lan_id(hw); ixgbe_identify_qsfp_module_generic()
1444 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, ixgbe_identify_qsfp_module_generic()
1451 hw->phy.type = ixgbe_phy_sfp_unsupported; ixgbe_identify_qsfp_module_generic()
1455 hw->phy.id = identifier; ixgbe_identify_qsfp_module_generic()
1457 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, ixgbe_identify_qsfp_module_generic()
1463 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, ixgbe_identify_qsfp_module_generic()
1470 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; ixgbe_identify_qsfp_module_generic()
1471 if (hw->bus.lan_id == 0) ixgbe_identify_qsfp_module_generic()
1472 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; ixgbe_identify_qsfp_module_generic()
1474 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; ixgbe_identify_qsfp_module_generic()
1477 if (hw->bus.lan_id == 0) ixgbe_identify_qsfp_module_generic()
1478 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; ixgbe_identify_qsfp_module_generic()
1480 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; ixgbe_identify_qsfp_module_generic()
1489 hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_qsfp_module_generic()
1493 hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_qsfp_module_generic()
1497 hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_qsfp_module_generic()
1510 hw->phy.type = ixgbe_phy_qsfp_active_unknown; ixgbe_identify_qsfp_module_generic()
1511 if (hw->bus.lan_id == 0) ixgbe_identify_qsfp_module_generic()
1512 hw->phy.sfp_type = ixgbe_identify_qsfp_module_generic()
1515 hw->phy.sfp_type = ixgbe_identify_qsfp_module_generic()
1519 hw->phy.type = ixgbe_phy_sfp_unsupported; ixgbe_identify_qsfp_module_generic()
1524 if (hw->phy.sfp_type != stored_sfp_type) ixgbe_identify_qsfp_module_generic()
1525 hw->phy.sfp_setup_needed = true; ixgbe_identify_qsfp_module_generic()
1528 hw->phy.multispeed_fiber = false; ixgbe_identify_qsfp_module_generic()
1533 hw->phy.multispeed_fiber = true; ixgbe_identify_qsfp_module_generic()
1538 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_qsfp_module_generic()
1545 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_qsfp_module_generic()
1552 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_identify_qsfp_module_generic()
1565 hw->phy.type = ixgbe_phy_qsfp_intel; ixgbe_identify_qsfp_module_generic()
1567 hw->phy.type = ixgbe_phy_qsfp_unknown; ixgbe_identify_qsfp_module_generic()
1569 hw->mac.ops.get_device_caps(hw, &enforce_sfp); ixgbe_identify_qsfp_module_generic()
1572 if (hw->phy.type == ixgbe_phy_qsfp_intel) ixgbe_identify_qsfp_module_generic()
1574 if (hw->allow_unsupported_sfp) { ixgbe_identify_qsfp_module_generic()
1578 hw_dbg(hw, "QSFP module not supported\n"); ixgbe_identify_qsfp_module_generic()
1579 hw->phy.type = ixgbe_phy_sfp_unsupported; ixgbe_identify_qsfp_module_generic()
1587 hw->phy.sfp_type = ixgbe_sfp_type_not_present; ixgbe_identify_qsfp_module_generic()
1588 hw->phy.id = 0; ixgbe_identify_qsfp_module_generic()
1589 hw->phy.type = ixgbe_phy_unknown; ixgbe_identify_qsfp_module_generic()
1596 * @hw: pointer to hardware structure
1603 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, ixgbe_get_sfp_init_sequence_offsets() argument
1608 u16 sfp_type = hw->phy.sfp_type; ixgbe_get_sfp_init_sequence_offsets()
1610 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) ixgbe_get_sfp_init_sequence_offsets()
1613 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) ixgbe_get_sfp_init_sequence_offsets()
1616 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && ixgbe_get_sfp_init_sequence_offsets()
1617 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) ixgbe_get_sfp_init_sequence_offsets()
1636 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { ixgbe_get_sfp_init_sequence_offsets()
1637 hw_err(hw, "eeprom read at %d failed\n", ixgbe_get_sfp_init_sequence_offsets()
1652 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) ixgbe_get_sfp_init_sequence_offsets()
1658 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) ixgbe_get_sfp_init_sequence_offsets()
1661 hw_dbg(hw, "SFP+ module not supported\n"); ixgbe_get_sfp_init_sequence_offsets()
1668 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) ixgbe_get_sfp_init_sequence_offsets()
1674 hw_dbg(hw, "No matching SFP+ module found\n"); ixgbe_get_sfp_init_sequence_offsets()
1681 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); ixgbe_get_sfp_init_sequence_offsets()
1687 * @hw: pointer to hardware structure
1693 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_eeprom_generic() argument
1696 return hw->phy.ops.read_i2c_byte(hw, byte_offset, ixgbe_read_i2c_eeprom_generic()
1703 * @hw: pointer to hardware structure
1709 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_sff8472_generic() argument
1712 return hw->phy.ops.read_i2c_byte(hw, byte_offset, ixgbe_read_i2c_sff8472_generic()
1719 * @hw: pointer to hardware structure
1725 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_write_i2c_eeprom_generic() argument
1728 return hw->phy.ops.write_i2c_byte(hw, byte_offset, ixgbe_write_i2c_eeprom_generic()
1735 * @hw: pointer to hardware structure
1739 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) ixgbe_is_sfp_probe() argument
1743 hw->phy.sfp_type == ixgbe_sfp_type_not_present) ixgbe_is_sfp_probe()
1750 * @hw: pointer to hardware structure
1758 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_byte_generic_int() argument
1764 u32 swfw_mask = hw->phy.phy_semaphore_mask; ixgbe_read_i2c_byte_generic_int()
1767 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) ixgbe_read_i2c_byte_generic_int()
1773 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) ixgbe_read_i2c_byte_generic_int()
1776 ixgbe_i2c_start(hw); ixgbe_read_i2c_byte_generic_int()
1779 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); ixgbe_read_i2c_byte_generic_int()
1783 status = ixgbe_get_i2c_ack(hw); ixgbe_read_i2c_byte_generic_int()
1787 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); ixgbe_read_i2c_byte_generic_int()
1791 status = ixgbe_get_i2c_ack(hw); ixgbe_read_i2c_byte_generic_int()
1795 ixgbe_i2c_start(hw); ixgbe_read_i2c_byte_generic_int()
1798 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); ixgbe_read_i2c_byte_generic_int()
1802 status = ixgbe_get_i2c_ack(hw); ixgbe_read_i2c_byte_generic_int()
1806 status = ixgbe_clock_in_i2c_byte(hw, data); ixgbe_read_i2c_byte_generic_int()
1810 status = ixgbe_clock_out_i2c_bit(hw, nack); ixgbe_read_i2c_byte_generic_int()
1814 ixgbe_i2c_stop(hw); ixgbe_read_i2c_byte_generic_int()
1816 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_read_i2c_byte_generic_int()
1820 ixgbe_i2c_bus_clear(hw); ixgbe_read_i2c_byte_generic_int()
1822 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_read_i2c_byte_generic_int()
1827 hw_dbg(hw, "I2C byte read error - Retrying.\n"); ixgbe_read_i2c_byte_generic_int()
1829 hw_dbg(hw, "I2C byte read error.\n"); ixgbe_read_i2c_byte_generic_int()
1838 * @hw: pointer to hardware structure
1845 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_byte_generic() argument
1848 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, ixgbe_read_i2c_byte_generic()
1854 * @hw: pointer to hardware structure
1861 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_byte_generic_unlocked() argument
1864 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, ixgbe_read_i2c_byte_generic_unlocked()
1870 * @hw: pointer to hardware structure
1878 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_write_i2c_byte_generic_int() argument
1884 u32 swfw_mask = hw->phy.phy_semaphore_mask; ixgbe_write_i2c_byte_generic_int()
1886 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) ixgbe_write_i2c_byte_generic_int()
1890 ixgbe_i2c_start(hw); ixgbe_write_i2c_byte_generic_int()
1892 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); ixgbe_write_i2c_byte_generic_int()
1896 status = ixgbe_get_i2c_ack(hw); ixgbe_write_i2c_byte_generic_int()
1900 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); ixgbe_write_i2c_byte_generic_int()
1904 status = ixgbe_get_i2c_ack(hw); ixgbe_write_i2c_byte_generic_int()
1908 status = ixgbe_clock_out_i2c_byte(hw, data); ixgbe_write_i2c_byte_generic_int()
1912 status = ixgbe_get_i2c_ack(hw); ixgbe_write_i2c_byte_generic_int()
1916 ixgbe_i2c_stop(hw); ixgbe_write_i2c_byte_generic_int()
1918 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_write_i2c_byte_generic_int()
1922 ixgbe_i2c_bus_clear(hw); ixgbe_write_i2c_byte_generic_int()
1925 hw_dbg(hw, "I2C byte write error - Retrying.\n"); ixgbe_write_i2c_byte_generic_int()
1927 hw_dbg(hw, "I2C byte write error.\n"); ixgbe_write_i2c_byte_generic_int()
1931 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_write_i2c_byte_generic_int()
1938 * @hw: pointer to hardware structure
1945 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_write_i2c_byte_generic() argument
1948 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, ixgbe_write_i2c_byte_generic()
1954 * @hw: pointer to hardware structure
1961 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_write_i2c_byte_generic_unlocked() argument
1964 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, ixgbe_write_i2c_byte_generic_unlocked()
1970 * @hw: pointer to hardware structure
1975 static void ixgbe_i2c_start(struct ixgbe_hw *hw) ixgbe_i2c_start() argument
1977 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_i2c_start()
1979 i2cctl |= IXGBE_I2C_BB_EN(hw); ixgbe_i2c_start()
1982 ixgbe_set_i2c_data(hw, &i2cctl, 1); ixgbe_i2c_start()
1983 ixgbe_raise_i2c_clk(hw, &i2cctl); ixgbe_i2c_start()
1988 ixgbe_set_i2c_data(hw, &i2cctl, 0); ixgbe_i2c_start()
1993 ixgbe_lower_i2c_clk(hw, &i2cctl); ixgbe_i2c_start()
2002 * @hw: pointer to hardware structure
2008 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) ixgbe_i2c_stop() argument
2010 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_i2c_stop()
2011 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); ixgbe_i2c_stop()
2012 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); ixgbe_i2c_stop()
2013 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw); ixgbe_i2c_stop()
2016 ixgbe_set_i2c_data(hw, &i2cctl, 0); ixgbe_i2c_stop()
2017 ixgbe_raise_i2c_clk(hw, &i2cctl); ixgbe_i2c_stop()
2022 ixgbe_set_i2c_data(hw, &i2cctl, 1); ixgbe_i2c_stop()
2030 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); ixgbe_i2c_stop()
2031 IXGBE_WRITE_FLUSH(hw); ixgbe_i2c_stop()
2037 * @hw: pointer to hardware structure
2042 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) ixgbe_clock_in_i2c_byte() argument
2049 ixgbe_clock_in_i2c_bit(hw, &bit); ixgbe_clock_in_i2c_byte()
2058 * @hw: pointer to hardware structure
2063 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) ixgbe_clock_out_i2c_byte() argument
2072 status = ixgbe_clock_out_i2c_bit(hw, bit); ixgbe_clock_out_i2c_byte()
2079 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_clock_out_i2c_byte()
2080 i2cctl |= IXGBE_I2C_DATA_OUT(hw); ixgbe_clock_out_i2c_byte()
2081 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw); ixgbe_clock_out_i2c_byte()
2082 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); ixgbe_clock_out_i2c_byte()
2083 IXGBE_WRITE_FLUSH(hw); ixgbe_clock_out_i2c_byte()
2090 * @hw: pointer to hardware structure
2094 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) ixgbe_get_i2c_ack() argument
2096 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); ixgbe_get_i2c_ack()
2099 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_get_i2c_ack()
2104 i2cctl |= IXGBE_I2C_DATA_OUT(hw); ixgbe_get_i2c_ack()
2106 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); ixgbe_get_i2c_ack()
2107 IXGBE_WRITE_FLUSH(hw); ixgbe_get_i2c_ack()
2109 ixgbe_raise_i2c_clk(hw, &i2cctl); ixgbe_get_i2c_ack()
2117 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_get_i2c_ack()
2118 ack = ixgbe_get_i2c_data(hw, &i2cctl); ixgbe_get_i2c_ack()
2126 hw_dbg(hw, "I2C ack was not received.\n"); ixgbe_get_i2c_ack()
2130 ixgbe_lower_i2c_clk(hw, &i2cctl); ixgbe_get_i2c_ack()
2140 * @hw: pointer to hardware structure
2145 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) ixgbe_clock_in_i2c_bit() argument
2147 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_clock_in_i2c_bit()
2148 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); ixgbe_clock_in_i2c_bit()
2151 i2cctl |= IXGBE_I2C_DATA_OUT(hw); ixgbe_clock_in_i2c_bit()
2153 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); ixgbe_clock_in_i2c_bit()
2154 IXGBE_WRITE_FLUSH(hw); ixgbe_clock_in_i2c_bit()
2156 ixgbe_raise_i2c_clk(hw, &i2cctl); ixgbe_clock_in_i2c_bit()
2161 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_clock_in_i2c_bit()
2162 *data = ixgbe_get_i2c_data(hw, &i2cctl); ixgbe_clock_in_i2c_bit()
2164 ixgbe_lower_i2c_clk(hw, &i2cctl); ixgbe_clock_in_i2c_bit()
2174 * @hw: pointer to hardware structure
2179 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) ixgbe_clock_out_i2c_bit() argument
2182 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_clock_out_i2c_bit()
2184 status = ixgbe_set_i2c_data(hw, &i2cctl, data); ixgbe_clock_out_i2c_bit()
2186 ixgbe_raise_i2c_clk(hw, &i2cctl); ixgbe_clock_out_i2c_bit()
2191 ixgbe_lower_i2c_clk(hw, &i2cctl); ixgbe_clock_out_i2c_bit()
2198 hw_dbg(hw, "I2C data was not set to %X\n", data); ixgbe_clock_out_i2c_bit()
2206 * @hw: pointer to hardware structure
2212 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) ixgbe_raise_i2c_clk() argument
2214 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); ixgbe_raise_i2c_clk()
2221 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); ixgbe_raise_i2c_clk()
2225 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); ixgbe_raise_i2c_clk()
2226 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); ixgbe_raise_i2c_clk()
2227 IXGBE_WRITE_FLUSH(hw); ixgbe_raise_i2c_clk()
2231 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_raise_i2c_clk()
2232 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) ixgbe_raise_i2c_clk()
2239 * @hw: pointer to hardware structure
2245 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) ixgbe_lower_i2c_clk() argument
2248 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); ixgbe_lower_i2c_clk()
2249 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw); ixgbe_lower_i2c_clk()
2251 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); ixgbe_lower_i2c_clk()
2252 IXGBE_WRITE_FLUSH(hw); ixgbe_lower_i2c_clk()
2260 * @hw: pointer to hardware structure
2267 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) ixgbe_set_i2c_data() argument
2269 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); ixgbe_set_i2c_data()
2272 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); ixgbe_set_i2c_data()
2274 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); ixgbe_set_i2c_data()
2277 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); ixgbe_set_i2c_data()
2278 IXGBE_WRITE_FLUSH(hw); ixgbe_set_i2c_data()
2287 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); ixgbe_set_i2c_data()
2288 IXGBE_WRITE_FLUSH(hw); ixgbe_set_i2c_data()
2292 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_set_i2c_data()
2293 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { ixgbe_set_i2c_data()
2294 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); ixgbe_set_i2c_data()
2303 * @hw: pointer to hardware structure
2309 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) ixgbe_get_i2c_data() argument
2311 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); ixgbe_get_i2c_data()
2315 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); ixgbe_get_i2c_data()
2316 IXGBE_WRITE_FLUSH(hw); ixgbe_get_i2c_data()
2320 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) ixgbe_get_i2c_data()
2327 * @hw: pointer to hardware structure
2332 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) ixgbe_i2c_bus_clear() argument
2337 ixgbe_i2c_start(hw); ixgbe_i2c_bus_clear()
2338 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); ixgbe_i2c_bus_clear()
2340 ixgbe_set_i2c_data(hw, &i2cctl, 1); ixgbe_i2c_bus_clear()
2343 ixgbe_raise_i2c_clk(hw, &i2cctl); ixgbe_i2c_bus_clear()
2348 ixgbe_lower_i2c_clk(hw, &i2cctl); ixgbe_i2c_bus_clear()
2354 ixgbe_i2c_start(hw); ixgbe_i2c_bus_clear()
2357 ixgbe_i2c_stop(hw); ixgbe_i2c_bus_clear()
2362 * @hw: pointer to hardware structure
2366 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) ixgbe_tn_check_overtemp() argument
2370 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) ixgbe_tn_check_overtemp()
2374 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, ixgbe_tn_check_overtemp()
2384 * @hw: pointer to hardware structure
2387 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) ixgbe_set_copper_phy_power() argument
2393 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) ixgbe_set_copper_phy_power()
2396 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, ixgbe_set_copper_phy_power()
2405 if (ixgbe_check_reset_blocked(hw)) ixgbe_set_copper_phy_power()
2410 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, ixgbe_set_copper_phy_power()
H A Dixgbe_common.h35 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
36 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
37 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
38 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
39 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
40 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
41 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
43 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
46 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
47 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
48 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
50 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
51 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
53 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
54 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
55 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
57 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
58 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
60 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
61 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
63 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
65 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
67 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
68 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
70 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
72 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
74 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
75 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
76 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
78 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
79 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
80 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);
81 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);
82 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
83 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
84 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
85 void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
87 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);
88 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);
89 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
90 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
91 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
92 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
93 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
94 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
96 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
97 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
100 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
103 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
104 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
106 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
107 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
108 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
109 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
110 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
111 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
113 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
115 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
116 bool ixgbe_mng_present(struct ixgbe_hw *hw);
117 bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
119 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
134 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
135 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
136 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
137 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
138 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
141 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
148 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
149 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
156 static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) ixgbe_write_reg() argument
158 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); ixgbe_write_reg()
175 static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value) ixgbe_write_reg64() argument
177 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); ixgbe_write_reg64()
185 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg);
196 #define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev)
198 #define hw_dbg(hw, format, arg...) \
199 netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg)
200 #define hw_err(hw, format, arg...) \
201 netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg)
H A Dixgbe_x550.c29 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) ixgbe_get_invariants_X550_x() argument
31 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_get_invariants_X550_x()
32 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_get_invariants_X550_x()
35 ixgbe_get_invariants_X540(hw); ixgbe_get_invariants_X550_x()
37 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) ixgbe_get_invariants_X550_x()
44 * @hw: pointer to hardware structure
46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) ixgbe_setup_mux_ctl() argument
48 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_setup_mux_ctl()
50 if (hw->bus.lan_id) { ixgbe_setup_mux_ctl()
55 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_setup_mux_ctl()
56 IXGBE_WRITE_FLUSH(hw); ixgbe_setup_mux_ctl()
61 * @hw: pointer to hardware structure
67 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) ixgbe_read_cs4227() argument
69 return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, ixgbe_read_cs4227()
75 * @hw: pointer to hardware structure
81 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) ixgbe_write_cs4227() argument
83 return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, ixgbe_write_cs4227()
89 * @hw: pointer to hardware structure
96 static s32 ixgbe_check_cs4227_reg(struct ixgbe_hw *hw, u16 reg) ixgbe_check_cs4227_reg() argument
103 status = ixgbe_write_cs4227(hw, reg, reg_val); ixgbe_check_cs4227_reg()
109 ixgbe_read_cs4227(hw, reg, &reg_val); ixgbe_check_cs4227_reg()
114 hw_err(hw, "CS4227 reg 0x%04X failed diagnostic\n", reg); ixgbe_check_cs4227_reg()
123 * @hw: pointer to hardware structure
129 static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) ixgbe_get_cs4227_status() argument
135 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); ixgbe_get_cs4227_status()
142 status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB); ixgbe_get_cs4227_status()
146 status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB); ixgbe_get_cs4227_status()
151 status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB + ixgbe_get_cs4227_status()
156 return ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB + ixgbe_get_cs4227_status()
162 * @hw: pointer to hardware structure
168 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) ixgbe_read_pe() argument
172 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); ixgbe_read_pe()
174 hw_err(hw, "port expander access failed with %d\n", status); ixgbe_read_pe()
180 * @hw: pointer to hardware structure
186 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) ixgbe_write_pe() argument
190 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, ixgbe_write_pe()
193 hw_err(hw, "port expander access failed with %d\n", status); ixgbe_write_pe()
199 * @hw: pointer to hardware structure
204 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) ixgbe_reset_cs4227() argument
212 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg); ixgbe_reset_cs4227()
216 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); ixgbe_reset_cs4227()
220 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg); ixgbe_reset_cs4227()
224 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); ixgbe_reset_cs4227()
228 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg); ixgbe_reset_cs4227()
232 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); ixgbe_reset_cs4227()
238 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg); ixgbe_reset_cs4227()
242 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); ixgbe_reset_cs4227()
249 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, ixgbe_reset_cs4227()
256 hw_err(hw, "CS4227 reset did not complete\n"); ixgbe_reset_cs4227()
260 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); ixgbe_reset_cs4227()
262 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); ixgbe_reset_cs4227()
271 * @hw: pointer to hardware structure
273 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) ixgbe_check_cs4227() argument
275 u32 swfw_mask = hw->phy.phy_semaphore_mask; ixgbe_check_cs4227()
281 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); ixgbe_check_cs4227()
283 hw_err(hw, "semaphore failed with %d\n", status); ixgbe_check_cs4227()
289 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); ixgbe_check_cs4227()
297 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_check_cs4227()
302 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); ixgbe_check_cs4227()
304 hw_err(hw, "semaphore failed with %d\n", status); ixgbe_check_cs4227()
310 status = ixgbe_reset_cs4227(hw); ixgbe_check_cs4227()
312 hw_err(hw, "CS4227 reset failed: %d", status); ixgbe_check_cs4227()
319 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, ixgbe_check_cs4227()
321 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_check_cs4227()
323 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); ixgbe_check_cs4227()
325 hw_err(hw, "semaphore failed with %d", status); ixgbe_check_cs4227()
330 status = ixgbe_get_cs4227_status(hw); ixgbe_check_cs4227()
332 hw_err(hw, "CS4227 status failed: %d", status); ixgbe_check_cs4227()
337 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, ixgbe_check_cs4227()
341 hw->mac.ops.release_swfw_sync(hw, swfw_mask); ixgbe_check_cs4227()
342 msleep(hw->eeprom.semaphore_delay); ixgbe_check_cs4227()
346 * @hw: pointer to hardware structure
350 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) ixgbe_identify_phy_x550em() argument
352 switch (hw->device_id) { ixgbe_identify_phy_x550em()
355 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; ixgbe_identify_phy_x550em()
356 ixgbe_setup_mux_ctl(hw); ixgbe_identify_phy_x550em()
357 ixgbe_check_cs4227(hw); ixgbe_identify_phy_x550em()
358 return ixgbe_identify_module_generic(hw); ixgbe_identify_phy_x550em()
360 hw->phy.type = ixgbe_phy_x550em_kx4; ixgbe_identify_phy_x550em()
363 hw->phy.type = ixgbe_phy_x550em_kr; ixgbe_identify_phy_x550em()
367 return ixgbe_identify_phy_generic(hw); ixgbe_identify_phy_x550em()
374 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_read_phy_reg_x550em() argument
380 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_write_phy_reg_x550em() argument
387 * @hw: pointer to hardware structure
392 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) ixgbe_init_eeprom_params_X550() argument
394 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; ixgbe_init_eeprom_params_X550()
402 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_init_eeprom_params_X550()
408 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", ixgbe_init_eeprom_params_X550()
417 * @hw: pointer to hardware structure
424 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) ixgbe_iosf_wait() argument
433 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); ixgbe_iosf_wait()
441 hw_dbg(hw, "IOSF wait timed out\n"); ixgbe_iosf_wait()
450 * @hw: pointer to hardware structure
455 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_read_iosf_sb_reg_x550() argument
462 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); ixgbe_read_iosf_sb_reg_x550()
466 ret = ixgbe_iosf_wait(hw, NULL); ixgbe_read_iosf_sb_reg_x550()
474 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); ixgbe_read_iosf_sb_reg_x550()
476 ret = ixgbe_iosf_wait(hw, &command); ixgbe_read_iosf_sb_reg_x550()
481 hw_dbg(hw, "Failed to read, error %x\n", error); ixgbe_read_iosf_sb_reg_x550()
486 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); ixgbe_read_iosf_sb_reg_x550()
489 hw->mac.ops.release_swfw_sync(hw, gssr); ixgbe_read_iosf_sb_reg_x550()
495 * @hw: pointer to hardware structure
501 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, ixgbe_read_ee_hostif_data_X550() argument
517 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, ixgbe_read_ee_hostif_data_X550()
523 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, ixgbe_read_ee_hostif_data_X550()
530 * @hw: pointer to hardware structure
537 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, ixgbe_read_ee_hostif_buffer_X550() argument
547 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_read_ee_hostif_buffer_X550()
549 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); ixgbe_read_ee_hostif_buffer_X550()
568 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, ixgbe_read_ee_hostif_buffer_X550()
573 hw_dbg(hw, "Host interface command failed\n"); ixgbe_read_ee_hostif_buffer_X550()
580 u32 value = IXGBE_READ_REG(hw, reg); ixgbe_read_ee_hostif_buffer_X550()
595 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_read_ee_hostif_buffer_X550()
600 * @hw: pointer to hardware structure
607 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, ixgbe_checksum_ptr_x550() argument
620 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); ixgbe_checksum_ptr_x550()
622 hw_dbg(hw, "Failed to read EEPROM image\n"); ixgbe_checksum_ptr_x550()
641 (ptr + length) >= hw->eeprom.word_size) ixgbe_checksum_ptr_x550()
656 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, ixgbe_checksum_ptr_x550()
659 hw_dbg(hw, "Failed to read EEPROM image\n"); ixgbe_checksum_ptr_x550()
669 * @hw: pointer to hardware structure
675 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, ixgbe_calc_checksum_X550() argument
684 hw->eeprom.ops.init_params(hw); ixgbe_calc_checksum_X550()
688 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, ixgbe_calc_checksum_X550()
692 hw_dbg(hw, "Failed to read EEPROM image\n"); ixgbe_calc_checksum_X550()
720 pointer >= hw->eeprom.word_size) ixgbe_calc_checksum_X550()
736 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, ixgbe_calc_checksum_X550()
748 * @hw: pointer to hardware structure
752 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) ixgbe_calc_eeprom_checksum_X550() argument
754 return ixgbe_calc_checksum_X550(hw, NULL, 0); ixgbe_calc_eeprom_checksum_X550()
758 * @hw: pointer to hardware structure
764 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) ixgbe_read_ee_hostif_X550() argument
768 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { ixgbe_read_ee_hostif_X550()
769 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); ixgbe_read_ee_hostif_X550()
770 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_read_ee_hostif_X550()
779 * @hw: pointer to hardware structure
785 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, ixgbe_validate_eeprom_checksum_X550() argument
796 status = hw->eeprom.ops.read(hw, 0, &checksum); ixgbe_validate_eeprom_checksum_X550()
798 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_validate_eeprom_checksum_X550()
802 status = hw->eeprom.ops.calc_checksum(hw); ixgbe_validate_eeprom_checksum_X550()
808 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, ixgbe_validate_eeprom_checksum_X550()
818 hw_dbg(hw, "Invalid EEPROM checksum"); ixgbe_validate_eeprom_checksum_X550()
829 * @hw: pointer to hardware structure
835 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, ixgbe_write_ee_hostif_data_X550() argument
851 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, ixgbe_write_ee_hostif_data_X550()
858 * @hw: pointer to hardware structure
864 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) ixgbe_write_ee_hostif_X550() argument
868 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { ixgbe_write_ee_hostif_X550()
869 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); ixgbe_write_ee_hostif_X550()
870 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_write_ee_hostif_X550()
872 hw_dbg(hw, "write ee hostif failed to get semaphore"); ixgbe_write_ee_hostif_X550()
880 * @hw: pointer to hardware structure
884 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) ixgbe_update_flash_X550() argument
894 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, ixgbe_update_flash_X550()
902 * @hw: pointer to hardware structure
907 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) ixgbe_get_bus_info_X550em() argument
909 hw->bus.type = ixgbe_bus_type_internal; ixgbe_get_bus_info_X550em()
910 hw->bus.width = ixgbe_bus_width_unknown; ixgbe_get_bus_info_X550em()
911 hw->bus.speed = ixgbe_bus_speed_unknown; ixgbe_get_bus_info_X550em()
913 hw->mac.ops.set_lan_id(hw); ixgbe_get_bus_info_X550em()
922 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) ixgbe_disable_rx_x550() argument
928 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_disable_rx_x550()
930 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); ixgbe_disable_rx_x550()
933 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); ixgbe_disable_rx_x550()
934 hw->mac.set_lben = true; ixgbe_disable_rx_x550()
936 hw->mac.set_lben = false; ixgbe_disable_rx_x550()
942 fw_cmd.port_number = (u8)hw->bus.lan_id; ixgbe_disable_rx_x550()
944 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, ixgbe_disable_rx_x550()
950 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_disable_rx_x550()
953 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); ixgbe_disable_rx_x550()
960 * @hw: pointer to hardware structure
966 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) ixgbe_update_eeprom_checksum_X550() argument
975 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); ixgbe_update_eeprom_checksum_X550()
977 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_update_eeprom_checksum_X550()
981 status = ixgbe_calc_eeprom_checksum_X550(hw); ixgbe_update_eeprom_checksum_X550()
987 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, ixgbe_update_eeprom_checksum_X550()
992 status = ixgbe_update_flash_X550(hw); ixgbe_update_eeprom_checksum_X550()
998 * @hw: pointer to hardware structure
1006 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, ixgbe_write_ee_hostif_buffer_X550() argument
1014 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_write_ee_hostif_buffer_X550()
1016 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); ixgbe_write_ee_hostif_buffer_X550()
1021 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, ixgbe_write_ee_hostif_buffer_X550()
1024 hw_dbg(hw, "Eeprom buffered write failed\n"); ixgbe_write_ee_hostif_buffer_X550()
1029 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_write_ee_hostif_buffer_X550()
1037 * @hw: pointer to hardware structure
1042 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, ixgbe_write_iosf_sb_reg_x550() argument
1049 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); ixgbe_write_iosf_sb_reg_x550()
1053 ret = ixgbe_iosf_wait(hw, NULL); ixgbe_write_iosf_sb_reg_x550()
1061 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); ixgbe_write_iosf_sb_reg_x550()
1064 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); ixgbe_write_iosf_sb_reg_x550()
1066 ret = ixgbe_iosf_wait(hw, &command); ixgbe_write_iosf_sb_reg_x550()
1071 hw_dbg(hw, "Failed to write, error %x\n", error); ixgbe_write_iosf_sb_reg_x550()
1076 hw->mac.ops.release_swfw_sync(hw, gssr); ixgbe_write_iosf_sb_reg_x550()
1081 * @hw: pointer to hardware structure
1087 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) ixgbe_setup_ixfi_x550em() argument
1093 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1094 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1115 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1116 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1122 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1123 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1129 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1130 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1136 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1137 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1145 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1146 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1151 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1152 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1160 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1161 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1167 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1168 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1177 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1178 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1184 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1185 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1191 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_ixfi_x550em()
1192 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), ixgbe_setup_ixfi_x550em()
1200 * @hw: pointer to hardware structure
1203 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) ixgbe_supported_sfp_modules_X550em() argument
1205 switch (hw->phy.sfp_type) { ixgbe_supported_sfp_modules_X550em()
1234 * @hw: pointer to hardware structure
1239 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, ixgbe_setup_mac_link_sfp_x550em() argument
1248 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); ixgbe_setup_mac_link_sfp_x550em()
1261 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12); ixgbe_setup_mac_link_sfp_x550em()
1263 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice, ixgbe_setup_mac_link_sfp_x550em()
1267 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12); ixgbe_setup_mac_link_sfp_x550em()
1270 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice, ixgbe_setup_mac_link_sfp_x550em()
1273 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12); ixgbe_setup_mac_link_sfp_x550em()
1278 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice, ixgbe_setup_mac_link_sfp_x550em()
1282 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) ixgbe_setup_mac_link_sfp_x550em()
1283 status = ixgbe_setup_ixfi_x550em(hw, &speed); ixgbe_setup_mac_link_sfp_x550em()
1290 * @hw: pointer to hardware structure
1299 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, ixgbe_setup_mac_link_t_X550em() argument
1315 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { ixgbe_setup_mac_link_t_X550em()
1316 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); ixgbe_setup_mac_link_t_X550em()
1322 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); ixgbe_setup_mac_link_t_X550em()
1326 * @hw: pointer to hardware structure
1333 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_check_link_t_X550em() argument
1341 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) ixgbe_check_link_t_X550em()
1344 status = ixgbe_check_mac_link_generic(hw, speed, link_up, ixgbe_check_link_t_X550em()
1354 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, ixgbe_check_link_t_X550em()
1368 * @hw: pointer to hardware structure
1370 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) ixgbe_init_mac_link_ops_X550em() argument
1372 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_init_mac_link_ops_X550em()
1374 switch (mac->ops.get_media_type(hw)) { ixgbe_init_mac_link_ops_X550em()
1397 * @hw: pointer to hardware structure
1399 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) ixgbe_setup_sfp_modules_X550em() argument
1405 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); ixgbe_setup_sfp_modules_X550em()
1409 ixgbe_init_mac_link_ops_X550em(hw); ixgbe_setup_sfp_modules_X550em()
1410 hw->phy.ops.reset = NULL; ixgbe_setup_sfp_modules_X550em()
1416 * @hw: pointer to hardware structure
1420 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, ixgbe_get_link_capabilities_X550em() argument
1425 if (hw->phy.media_type == ixgbe_media_type_fiber) { ixgbe_get_link_capabilities_X550em()
1429 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || ixgbe_get_link_capabilities_X550em()
1430 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { ixgbe_get_link_capabilities_X550em()
1436 if (hw->phy.multispeed_fiber) ixgbe_get_link_capabilities_X550em()
1451 * @hw: pointer to hardware structure
1461 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) ixgbe_get_lasi_ext_t_x550em() argument
1469 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, ixgbe_get_lasi_ext_t_x550em()
1477 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, ixgbe_get_lasi_ext_t_x550em()
1486 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, ixgbe_get_lasi_ext_t_x550em()
1496 ixgbe_set_copper_phy_power(hw, false); ixgbe_get_lasi_ext_t_x550em()
1501 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, ixgbe_get_lasi_ext_t_x550em()
1508 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, ixgbe_get_lasi_ext_t_x550em()
1523 * @hw: pointer to hardware structure
1530 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) ixgbe_enable_lasi_ext_t_x550em() argument
1537 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); ixgbe_enable_lasi_ext_t_x550em()
1540 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, ixgbe_enable_lasi_ext_t_x550em()
1547 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, ixgbe_enable_lasi_ext_t_x550em()
1553 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, ixgbe_enable_lasi_ext_t_x550em()
1561 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, ixgbe_enable_lasi_ext_t_x550em()
1568 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, ixgbe_enable_lasi_ext_t_x550em()
1577 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, ixgbe_enable_lasi_ext_t_x550em()
1584 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, ixgbe_enable_lasi_ext_t_x550em()
1592 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, ixgbe_enable_lasi_ext_t_x550em()
1601 * @hw: pointer to hardware structure
1610 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) ixgbe_handle_lasi_ext_t_x550em() argument
1612 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_handle_lasi_ext_t_x550em()
1616 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); ixgbe_handle_lasi_ext_t_x550em()
1621 return phy->ops.setup_internal_link(hw); ixgbe_handle_lasi_ext_t_x550em()
1628 * @hw: pointer to hardware structure
1633 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, ixgbe_setup_kr_speed_x550em() argument
1639 status = ixgbe_read_iosf_sb_reg_x550(hw, ixgbe_setup_kr_speed_x550em()
1640 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), ixgbe_setup_kr_speed_x550em()
1661 status = ixgbe_write_iosf_sb_reg_x550(hw, ixgbe_setup_kr_speed_x550em()
1662 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), ixgbe_setup_kr_speed_x550em()
1669 * @hw: pointer to hardware structure
1673 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) ixgbe_setup_kx4_x550em() argument
1678 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, ixgbe_setup_kx4_x550em()
1680 hw->bus.lan_id, &reg_val); ixgbe_setup_kx4_x550em()
1690 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) ixgbe_setup_kx4_x550em()
1694 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) ixgbe_setup_kx4_x550em()
1699 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, ixgbe_setup_kx4_x550em()
1701 hw->bus.lan_id, reg_val); ixgbe_setup_kx4_x550em()
1707 * @hw: pointer to hardware structure
1711 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) ixgbe_setup_kr_x550em() argument
1713 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); ixgbe_setup_kr_x550em()
1717 * @hw: address of hardware structure
1722 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) ixgbe_ext_phy_t_x550em_get_link() argument
1730 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, ixgbe_ext_phy_t_x550em_get_link()
1736 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, ixgbe_ext_phy_t_x550em_get_link()
1748 * @hw: point to hardware structure
1758 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) ixgbe_setup_internal_phy_t_x550em() argument
1765 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) ixgbe_setup_internal_phy_t_x550em()
1769 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); ixgbe_setup_internal_phy_t_x550em()
1776 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, ixgbe_setup_internal_phy_t_x550em()
1783 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); ixgbe_setup_internal_phy_t_x550em()
1805 return ixgbe_setup_ixfi_x550em(hw, &force_speed); ixgbe_setup_internal_phy_t_x550em()
1809 * @hw: pointer to hardware structure
1811 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) ixgbe_reset_phy_t_X550em() argument
1815 status = ixgbe_reset_phy_generic(hw); ixgbe_reset_phy_t_X550em()
1821 return ixgbe_enable_lasi_ext_t_x550em(hw); ixgbe_reset_phy_t_X550em()
1825 * @hw: pointer to hardware structure
1830 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_get_lcd_t_x550em() argument
1835 u16 word = hw->eeprom.ctrl_word_3; ixgbe_get_lcd_t_x550em()
1839 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, ixgbe_get_lcd_t_x550em()
1852 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || ixgbe_get_lcd_t_x550em()
1862 * @hw: pointer to hardware structure
1868 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) ixgbe_enter_lplu_t_x550em() argument
1877 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))) ixgbe_enter_lplu_t_x550em()
1881 if (ixgbe_check_reset_blocked(hw)) ixgbe_enter_lplu_t_x550em()
1884 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); ixgbe_enter_lplu_t_x550em()
1888 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, ixgbe_enter_lplu_t_x550em()
1889 &hw->eeprom.ctrl_word_3); ixgbe_enter_lplu_t_x550em()
1897 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || ixgbe_enter_lplu_t_x550em()
1898 !(hw->wol_enabled || ixgbe_mng_present(hw))) ixgbe_enter_lplu_t_x550em()
1899 return ixgbe_set_copper_phy_power(hw, false); ixgbe_enter_lplu_t_x550em()
1902 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); ixgbe_enter_lplu_t_x550em()
1908 return ixgbe_set_copper_phy_power(hw, false); ixgbe_enter_lplu_t_x550em()
1910 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, ixgbe_enter_lplu_t_x550em()
1917 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); ixgbe_enter_lplu_t_x550em()
1919 return ixgbe_set_copper_phy_power(hw, false); ixgbe_enter_lplu_t_x550em()
1932 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, ixgbe_enter_lplu_t_x550em()
1938 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, ixgbe_enter_lplu_t_x550em()
1944 status = hw->phy.ops.read_reg(hw, ixgbe_enter_lplu_t_x550em()
1951 save_autoneg = hw->phy.autoneg_advertised; ixgbe_enter_lplu_t_x550em()
1954 status = hw->mac.ops.setup_link(hw, lcd_speed, false); ixgbe_enter_lplu_t_x550em()
1957 hw->phy.autoneg_advertised = save_autoneg; ixgbe_enter_lplu_t_x550em()
1963 * @hw: pointer to hardware structure
1969 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) ixgbe_init_phy_ops_X550em() argument
1971 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_init_phy_ops_X550em()
1975 hw->mac.ops.set_lan_id(hw); ixgbe_init_phy_ops_X550em()
1977 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { ixgbe_init_phy_ops_X550em()
1979 ixgbe_setup_mux_ctl(hw); ixgbe_init_phy_ops_X550em()
1984 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); ixgbe_init_phy_ops_X550em()
1990 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); ixgbe_init_phy_ops_X550em()
1995 ret_val = phy->ops.identify(hw); ixgbe_init_phy_ops_X550em()
1998 ixgbe_init_mac_link_ops_X550em(hw); ixgbe_init_phy_ops_X550em()
2003 switch (hw->phy.type) { ixgbe_init_phy_ops_X550em()
2018 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); ixgbe_init_phy_ops_X550em()
2029 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); ixgbe_init_phy_ops_X550em()
2033 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, ixgbe_init_phy_ops_X550em()
2048 * @hw: pointer to hardware structure
2053 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) ixgbe_get_media_type_X550em() argument
2058 switch (hw->device_id) { ixgbe_get_media_type_X550em()
2078 ** @hw: pointer to hardware structure
2080 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) ixgbe_init_ext_t_x550em() argument
2085 status = hw->phy.ops.read_reg(hw, ixgbe_init_ext_t_x550em()
2096 status = hw->phy.ops.read_reg(hw, ixgbe_init_ext_t_x550em()
2105 status = hw->phy.ops.write_reg(hw, ixgbe_init_ext_t_x550em()
2117 ** @hw: pointer to hardware structure
2123 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) ixgbe_reset_hw_X550em() argument
2133 status = hw->mac.ops.stop_adapter(hw); ixgbe_reset_hw_X550em()
2138 ixgbe_clear_tx_pending(hw); ixgbe_reset_hw_X550em()
2143 status = hw->phy.ops.init(hw); ixgbe_reset_hw_X550em()
2146 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { ixgbe_reset_hw_X550em()
2147 status = ixgbe_init_ext_t_x550em(hw); ixgbe_reset_hw_X550em()
2153 if (hw->phy.sfp_setup_needed) { ixgbe_reset_hw_X550em()
2154 status = hw->mac.ops.setup_sfp(hw); ixgbe_reset_hw_X550em()
2155 hw->phy.sfp_setup_needed = false; ixgbe_reset_hw_X550em()
2159 if (!hw->phy.reset_disable && hw->phy.ops.reset) ixgbe_reset_hw_X550em()
2160 hw->phy.ops.reset(hw); ixgbe_reset_hw_X550em()
2170 if (!hw->force_full_reset) { ixgbe_reset_hw_X550em()
2171 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ixgbe_reset_hw_X550em()
2176 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_X550em()
2177 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); ixgbe_reset_hw_X550em()
2178 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_hw_X550em()
2183 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_X550em()
2190 hw_dbg(hw, "Reset polling failed to complete.\n"); ixgbe_reset_hw_X550em()
2199 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { ixgbe_reset_hw_X550em()
2200 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; ixgbe_reset_hw_X550em()
2205 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); ixgbe_reset_hw_X550em()
2211 hw->mac.num_rar_entries = 128; ixgbe_reset_hw_X550em()
2212 hw->mac.ops.init_rx_addrs(hw); ixgbe_reset_hw_X550em()
2214 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { ixgbe_reset_hw_X550em()
2215 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); ixgbe_reset_hw_X550em()
2217 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); ixgbe_reset_hw_X550em()
2220 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) ixgbe_reset_hw_X550em()
2221 ixgbe_setup_mux_ctl(hw); ixgbe_reset_hw_X550em()
2228 * @hw: pointer to hardware structure
2232 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, ixgbe_set_ethertype_anti_spoofing_X550() argument
2239 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); ixgbe_set_ethertype_anti_spoofing_X550()
2245 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); ixgbe_set_ethertype_anti_spoofing_X550()
2249 * @hw: pointer to hardware structure
2253 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, ixgbe_set_source_address_pruning_X550() argument
2263 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); ixgbe_set_source_address_pruning_X550()
2264 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; ixgbe_set_source_address_pruning_X550()
2271 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); ixgbe_set_source_address_pruning_X550()
2272 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); ixgbe_set_source_address_pruning_X550()
2277 * @hw: pointer to hardware structure
2280 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) ixgbe_set_mux() argument
2284 if (!hw->bus.lan_id) ixgbe_set_mux()
2286 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_set_mux()
2291 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_set_mux()
2292 IXGBE_WRITE_FLUSH(hw); ixgbe_set_mux()
2297 * @hw: pointer to hardware structure
2302 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) ixgbe_acquire_swfw_sync_X550em() argument
2306 status = ixgbe_acquire_swfw_sync_X540(hw, mask); ixgbe_acquire_swfw_sync_X550em()
2311 ixgbe_set_mux(hw, 1); ixgbe_acquire_swfw_sync_X550em()
2318 * @hw: pointer to hardware structure
2323 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) ixgbe_release_swfw_sync_X550em() argument
2326 ixgbe_set_mux(hw, 0); ixgbe_release_swfw_sync_X550em()
2328 ixgbe_release_swfw_sync_X540(hw, mask); ixgbe_release_swfw_sync_X550em()
H A Dixgbe_82599.c44 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
52 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
58 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
62 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
64 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
66 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
67 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
69 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) ixgbe_mng_enabled() argument
73 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); ixgbe_mng_enabled()
77 manc = IXGBE_READ_REG(hw, IXGBE_MANC); ixgbe_mng_enabled()
81 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); ixgbe_mng_enabled()
88 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) ixgbe_init_mac_link_ops_82599() argument
90 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_init_mac_link_ops_82599()
95 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && ixgbe_init_mac_link_ops_82599()
96 !ixgbe_mng_enabled(hw)) { ixgbe_init_mac_link_ops_82599()
108 if (hw->phy.multispeed_fiber) { ixgbe_init_mac_link_ops_82599()
115 if ((mac->ops.get_media_type(hw) == ixgbe_init_mac_link_ops_82599()
117 (hw->phy.smart_speed == ixgbe_smart_speed_auto || ixgbe_init_mac_link_ops_82599()
118 hw->phy.smart_speed == ixgbe_smart_speed_on) && ixgbe_init_mac_link_ops_82599()
119 !ixgbe_verify_lesm_fw_enabled_82599(hw)) ixgbe_init_mac_link_ops_82599()
126 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) ixgbe_setup_sfp_modules_82599() argument
131 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { ixgbe_setup_sfp_modules_82599()
132 ixgbe_init_mac_link_ops_82599(hw); ixgbe_setup_sfp_modules_82599()
134 hw->phy.ops.reset = NULL; ixgbe_setup_sfp_modules_82599()
136 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, ixgbe_setup_sfp_modules_82599()
142 ret_val = hw->mac.ops.acquire_swfw_sync(hw, ixgbe_setup_sfp_modules_82599()
147 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) ixgbe_setup_sfp_modules_82599()
150 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); ixgbe_setup_sfp_modules_82599()
151 IXGBE_WRITE_FLUSH(hw); ixgbe_setup_sfp_modules_82599()
152 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) ixgbe_setup_sfp_modules_82599()
157 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); ixgbe_setup_sfp_modules_82599()
162 usleep_range(hw->eeprom.semaphore_delay * 1000, ixgbe_setup_sfp_modules_82599()
163 hw->eeprom.semaphore_delay * 2000); ixgbe_setup_sfp_modules_82599()
166 ret_val = hw->mac.ops.prot_autoc_write(hw, ixgbe_setup_sfp_modules_82599()
167 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, ixgbe_setup_sfp_modules_82599()
171 hw_dbg(hw, " sfp module setup not complete\n"); ixgbe_setup_sfp_modules_82599()
180 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); ixgbe_setup_sfp_modules_82599()
184 usleep_range(hw->eeprom.semaphore_delay * 1000, ixgbe_setup_sfp_modules_82599()
185 hw->eeprom.semaphore_delay * 2000); ixgbe_setup_sfp_modules_82599()
186 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); ixgbe_setup_sfp_modules_82599()
192 * @hw: pointer to hardware structure
201 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, prot_autoc_read_82599() argument
208 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { prot_autoc_read_82599()
209 ret_val = hw->mac.ops.acquire_swfw_sync(hw, prot_autoc_read_82599()
217 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); prot_autoc_read_82599()
223 * @hw: pointer to hardware structure
231 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) prot_autoc_write_82599() argument
236 if (ixgbe_check_reset_blocked(hw)) prot_autoc_write_82599()
243 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { prot_autoc_write_82599()
244 ret_val = hw->mac.ops.acquire_swfw_sync(hw, prot_autoc_write_82599()
252 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); prot_autoc_write_82599()
253 ret_val = ixgbe_reset_pipeline_82599(hw); prot_autoc_write_82599()
260 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); prot_autoc_write_82599()
265 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) ixgbe_get_invariants_82599() argument
267 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_get_invariants_82599()
269 ixgbe_init_mac_link_ops_82599(hw); ixgbe_get_invariants_82599()
277 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); ixgbe_get_invariants_82599()
284 * @hw: pointer to hardware structure
291 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) ixgbe_init_phy_ops_82599() argument
293 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_init_phy_ops_82599()
294 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_init_phy_ops_82599()
298 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { ixgbe_init_phy_ops_82599()
300 hw->phy.qsfp_shared_i2c_bus = true; ixgbe_init_phy_ops_82599()
303 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_init_phy_ops_82599()
309 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_init_phy_ops_82599()
310 IXGBE_WRITE_FLUSH(hw); ixgbe_init_phy_ops_82599()
317 ret_val = phy->ops.identify(hw); ixgbe_init_phy_ops_82599()
320 ixgbe_init_mac_link_ops_82599(hw); ixgbe_init_phy_ops_82599()
323 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { ixgbe_init_phy_ops_82599()
330 switch (hw->phy.type) { ixgbe_init_phy_ops_82599()
346 * @hw: pointer to hardware structure
352 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, ixgbe_get_link_capabilities_82599() argument
359 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || ixgbe_get_link_capabilities_82599()
360 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || ixgbe_get_link_capabilities_82599()
361 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || ixgbe_get_link_capabilities_82599()
362 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || ixgbe_get_link_capabilities_82599()
363 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || ixgbe_get_link_capabilities_82599()
364 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { ixgbe_get_link_capabilities_82599()
375 if (hw->mac.orig_link_settings_stored) ixgbe_get_link_capabilities_82599()
376 autoc = hw->mac.orig_autoc; ixgbe_get_link_capabilities_82599()
378 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_get_link_capabilities_82599()
433 if (hw->phy.multispeed_fiber) { ixgbe_get_link_capabilities_82599()
438 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) ixgbe_get_link_capabilities_82599()
449 * @hw: pointer to hardware structure
453 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) ixgbe_get_media_type_82599() argument
456 switch (hw->phy.type) { ixgbe_get_media_type_82599()
465 switch (hw->device_id) { ixgbe_get_media_type_82599()
502 * @hw: pointer to hardware structure
507 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) ixgbe_stop_mac_link_on_d3_82599() argument
512 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); ixgbe_stop_mac_link_on_d3_82599()
514 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && ixgbe_stop_mac_link_on_d3_82599()
516 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ixgbe_stop_mac_link_on_d3_82599()
518 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); ixgbe_stop_mac_link_on_d3_82599()
524 * @hw: pointer to hardware structure
530 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, ixgbe_start_mac_link_82599() argument
539 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { ixgbe_start_mac_link_82599()
540 status = hw->mac.ops.acquire_swfw_sync(hw, ixgbe_start_mac_link_82599()
549 ixgbe_reset_pipeline_82599(hw); ixgbe_start_mac_link_82599()
552 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); ixgbe_start_mac_link_82599()
556 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_start_mac_link_82599()
565 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_start_mac_link_82599()
572 hw_dbg(hw, "Autoneg did not complete.\n"); ixgbe_start_mac_link_82599()
585 * @hw: pointer to hardware structure
591 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) ixgbe_disable_tx_laser_multispeed_fiber() argument
593 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_disable_tx_laser_multispeed_fiber()
596 if (ixgbe_check_reset_blocked(hw)) ixgbe_disable_tx_laser_multispeed_fiber()
601 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ixgbe_disable_tx_laser_multispeed_fiber()
602 IXGBE_WRITE_FLUSH(hw); ixgbe_disable_tx_laser_multispeed_fiber()
608 * @hw: pointer to hardware structure
614 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) ixgbe_enable_tx_laser_multispeed_fiber() argument
616 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_enable_tx_laser_multispeed_fiber()
620 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ixgbe_enable_tx_laser_multispeed_fiber()
621 IXGBE_WRITE_FLUSH(hw); ixgbe_enable_tx_laser_multispeed_fiber()
627 * @hw: pointer to hardware structure
637 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) ixgbe_flap_tx_laser_multispeed_fiber() argument
640 if (ixgbe_check_reset_blocked(hw)) ixgbe_flap_tx_laser_multispeed_fiber()
643 if (hw->mac.autotry_restart) { ixgbe_flap_tx_laser_multispeed_fiber()
644 ixgbe_disable_tx_laser_multispeed_fiber(hw); ixgbe_flap_tx_laser_multispeed_fiber()
645 ixgbe_enable_tx_laser_multispeed_fiber(hw); ixgbe_flap_tx_laser_multispeed_fiber()
646 hw->mac.autotry_restart = false; ixgbe_flap_tx_laser_multispeed_fiber()
652 * @hw: pointer to hardware structure
658 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) ixgbe_set_hard_rate_select_speed() argument
660 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_set_hard_rate_select_speed()
671 hw_dbg(hw, "Invalid fixed module speed\n"); ixgbe_set_hard_rate_select_speed()
675 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); ixgbe_set_hard_rate_select_speed()
676 IXGBE_WRITE_FLUSH(hw); ixgbe_set_hard_rate_select_speed()
681 * @hw: pointer to hardware structure
687 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, ixgbe_setup_mac_link_smartspeed() argument
695 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_setup_mac_link_smartspeed()
698 hw->phy.autoneg_advertised = 0; ixgbe_setup_mac_link_smartspeed()
701 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; ixgbe_setup_mac_link_smartspeed()
704 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; ixgbe_setup_mac_link_smartspeed()
707 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; ixgbe_setup_mac_link_smartspeed()
717 hw->phy.smart_speed_active = false; ixgbe_setup_mac_link_smartspeed()
719 status = ixgbe_setup_mac_link_82599(hw, speed, ixgbe_setup_mac_link_smartspeed()
734 status = hw->mac.ops.check_link(hw, &link_speed, ixgbe_setup_mac_link_smartspeed()
753 hw->phy.smart_speed_active = true; ixgbe_setup_mac_link_smartspeed()
754 status = ixgbe_setup_mac_link_82599(hw, speed, ixgbe_setup_mac_link_smartspeed()
769 status = hw->mac.ops.check_link(hw, &link_speed, ixgbe_setup_mac_link_smartspeed()
779 hw->phy.smart_speed_active = false; ixgbe_setup_mac_link_smartspeed()
780 status = ixgbe_setup_mac_link_82599(hw, speed, ixgbe_setup_mac_link_smartspeed()
785 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); ixgbe_setup_mac_link_smartspeed()
791 * @hw: pointer to hardware structure
797 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_setup_mac_link_82599() argument
804 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ixgbe_setup_mac_link_82599()
809 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_setup_mac_link_82599()
816 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, ixgbe_setup_mac_link_82599()
827 if (hw->mac.orig_link_settings_stored) ixgbe_setup_mac_link_82599()
828 orig_autoc = hw->mac.orig_autoc; ixgbe_setup_mac_link_82599()
844 (hw->phy.smart_speed_active == false)) ixgbe_setup_mac_link_82599()
873 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); ixgbe_setup_mac_link_82599()
885 IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_setup_mac_link_82599()
893 hw_dbg(hw, "Autoneg did not complete.\n"); ixgbe_setup_mac_link_82599()
907 * @hw: pointer to hardware structure
913 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, ixgbe_setup_copper_link_82599() argument
920 status = hw->phy.ops.setup_link_speed(hw, speed, ixgbe_setup_copper_link_82599()
923 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); ixgbe_setup_copper_link_82599()
930 * @hw: pointer to hardware structure
936 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) ixgbe_reset_hw_82599() argument
945 status = hw->mac.ops.stop_adapter(hw); ixgbe_reset_hw_82599()
950 ixgbe_clear_tx_pending(hw); ixgbe_reset_hw_82599()
955 status = hw->phy.ops.init(hw); ixgbe_reset_hw_82599()
961 if (hw->phy.sfp_setup_needed) { ixgbe_reset_hw_82599()
962 status = hw->mac.ops.setup_sfp(hw); ixgbe_reset_hw_82599()
963 hw->phy.sfp_setup_needed = false; ixgbe_reset_hw_82599()
970 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) ixgbe_reset_hw_82599()
971 hw->phy.ops.reset(hw); ixgbe_reset_hw_82599()
974 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; ixgbe_reset_hw_82599()
984 if (!hw->force_full_reset) { ixgbe_reset_hw_82599()
985 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ixgbe_reset_hw_82599()
990 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_82599()
991 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); ixgbe_reset_hw_82599()
992 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_hw_82599()
997 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_82599()
1004 hw_dbg(hw, "Reset polling failed to complete.\n"); ixgbe_reset_hw_82599()
1014 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { ixgbe_reset_hw_82599()
1015 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; ixgbe_reset_hw_82599()
1024 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_reset_hw_82599()
1025 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ixgbe_reset_hw_82599()
1030 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); ixgbe_reset_hw_82599()
1031 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_hw_82599()
1034 if (hw->mac.orig_link_settings_stored == false) { ixgbe_reset_hw_82599()
1035 hw->mac.orig_autoc = autoc; ixgbe_reset_hw_82599()
1036 hw->mac.orig_autoc2 = autoc2; ixgbe_reset_hw_82599()
1037 hw->mac.orig_link_settings_stored = true; ixgbe_reset_hw_82599()
1046 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || ixgbe_reset_hw_82599()
1047 hw->wol_enabled) ixgbe_reset_hw_82599()
1048 hw->mac.orig_autoc = ixgbe_reset_hw_82599()
1049 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | ixgbe_reset_hw_82599()
1052 if (autoc != hw->mac.orig_autoc) { ixgbe_reset_hw_82599()
1053 status = hw->mac.ops.prot_autoc_write(hw, ixgbe_reset_hw_82599()
1054 hw->mac.orig_autoc, ixgbe_reset_hw_82599()
1061 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { ixgbe_reset_hw_82599()
1063 autoc2 |= (hw->mac.orig_autoc2 & ixgbe_reset_hw_82599()
1065 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); ixgbe_reset_hw_82599()
1070 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); ixgbe_reset_hw_82599()
1077 hw->mac.num_rar_entries = 128; ixgbe_reset_hw_82599()
1078 hw->mac.ops.init_rx_addrs(hw); ixgbe_reset_hw_82599()
1081 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); ixgbe_reset_hw_82599()
1084 if (is_valid_ether_addr(hw->mac.san_addr)) { ixgbe_reset_hw_82599()
1085 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, ixgbe_reset_hw_82599()
1086 hw->mac.san_addr, 0, IXGBE_RAH_AV); ixgbe_reset_hw_82599()
1089 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; ixgbe_reset_hw_82599()
1092 hw->mac.num_rar_entries--; ixgbe_reset_hw_82599()
1096 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, ixgbe_reset_hw_82599()
1097 &hw->mac.wwpn_prefix); ixgbe_reset_hw_82599()
1104 * @hw: pointer to hardware structure
1107 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) ixgbe_fdir_check_cmd_complete() argument
1112 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); ixgbe_fdir_check_cmd_complete()
1123 * @hw: pointer to hardware structure
1125 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) ixgbe_reinit_fdir_tables_82599() argument
1128 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); ixgbe_reinit_fdir_tables_82599()
1138 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); ixgbe_reinit_fdir_tables_82599()
1140 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); ixgbe_reinit_fdir_tables_82599()
1144 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); ixgbe_reinit_fdir_tables_82599()
1145 IXGBE_WRITE_FLUSH(hw); ixgbe_reinit_fdir_tables_82599()
1153 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, ixgbe_reinit_fdir_tables_82599()
1154 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | ixgbe_reinit_fdir_tables_82599()
1156 IXGBE_WRITE_FLUSH(hw); ixgbe_reinit_fdir_tables_82599()
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, ixgbe_reinit_fdir_tables_82599()
1158 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & ixgbe_reinit_fdir_tables_82599()
1160 IXGBE_WRITE_FLUSH(hw); ixgbe_reinit_fdir_tables_82599()
1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); ixgbe_reinit_fdir_tables_82599()
1166 IXGBE_WRITE_FLUSH(hw); ixgbe_reinit_fdir_tables_82599()
1168 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); ixgbe_reinit_fdir_tables_82599()
1169 IXGBE_WRITE_FLUSH(hw); ixgbe_reinit_fdir_tables_82599()
1173 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & ixgbe_reinit_fdir_tables_82599()
1179 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); ixgbe_reinit_fdir_tables_82599()
1184 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); ixgbe_reinit_fdir_tables_82599()
1185 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); ixgbe_reinit_fdir_tables_82599()
1186 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); ixgbe_reinit_fdir_tables_82599()
1187 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); ixgbe_reinit_fdir_tables_82599()
1188 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); ixgbe_reinit_fdir_tables_82599()
1195 * @hw: pointer to hardware structure
1198 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) ixgbe_fdir_enable_82599() argument
1203 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); ixgbe_fdir_enable_82599()
1204 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); ixgbe_fdir_enable_82599()
1219 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); ixgbe_fdir_enable_82599()
1220 IXGBE_WRITE_FLUSH(hw); ixgbe_fdir_enable_82599()
1222 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & ixgbe_fdir_enable_82599()
1229 hw_dbg(hw, "Flow Director poll time exceeded!\n"); ixgbe_fdir_enable_82599()
1234 * @hw: pointer to hardware structure
1238 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) ixgbe_init_fdir_signature_82599() argument
1251 ixgbe_fdir_enable_82599(hw, fdirctrl); ixgbe_init_fdir_signature_82599()
1258 * @hw: pointer to hardware structure
1262 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) ixgbe_init_fdir_perfect_82599() argument
1279 ixgbe_fdir_enable_82599(hw, fdirctrl); ixgbe_init_fdir_perfect_82599()
1376 * @hw: pointer to hardware structure
1384 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, ixgbe_fdir_add_signature_filter_82599() argument
1410 hw_dbg(hw, " Error on flow type input\n"); ixgbe_fdir_add_signature_filter_82599()
1428 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); ixgbe_fdir_add_signature_filter_82599()
1430 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); ixgbe_fdir_add_signature_filter_82599()
1540 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, ixgbe_fdir_set_input_mask_82599() argument
1559 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); ixgbe_fdir_set_input_mask_82599()
1568 hw_dbg(hw, " Error on vm pool mask\n"); ixgbe_fdir_set_input_mask_82599()
1577 hw_dbg(hw, " Error on src/dst port mask\n"); ixgbe_fdir_set_input_mask_82599()
1583 hw_dbg(hw, " Error on flow type mask\n"); ixgbe_fdir_set_input_mask_82599()
1602 hw_dbg(hw, " Error on VLAN mask\n"); ixgbe_fdir_set_input_mask_82599()
1613 hw_dbg(hw, " Error on flexible byte mask\n"); ixgbe_fdir_set_input_mask_82599()
1618 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); ixgbe_fdir_set_input_mask_82599()
1624 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); ixgbe_fdir_set_input_mask_82599()
1625 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); ixgbe_fdir_set_input_mask_82599()
1628 switch (hw->mac.type) { ixgbe_fdir_set_input_mask_82599()
1631 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); ixgbe_fdir_set_input_mask_82599()
1638 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, ixgbe_fdir_set_input_mask_82599()
1640 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, ixgbe_fdir_set_input_mask_82599()
1646 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, ixgbe_fdir_write_perfect_filter_82599() argument
1654 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), ixgbe_fdir_write_perfect_filter_82599()
1656 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), ixgbe_fdir_write_perfect_filter_82599()
1658 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), ixgbe_fdir_write_perfect_filter_82599()
1662 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); ixgbe_fdir_write_perfect_filter_82599()
1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); ixgbe_fdir_write_perfect_filter_82599()
1671 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); ixgbe_fdir_write_perfect_filter_82599()
1677 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); ixgbe_fdir_write_perfect_filter_82599()
1682 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); ixgbe_fdir_write_perfect_filter_82599()
1688 IXGBE_WRITE_FLUSH(hw); ixgbe_fdir_write_perfect_filter_82599()
1699 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); ixgbe_fdir_write_perfect_filter_82599()
1700 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); ixgbe_fdir_write_perfect_filter_82599()
1702 hw_dbg(hw, "Flow Director command did not complete!\n"); ixgbe_fdir_write_perfect_filter_82599()
1709 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, ixgbe_fdir_erase_perfect_filter_82599() argument
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); ixgbe_fdir_erase_perfect_filter_82599()
1723 IXGBE_WRITE_FLUSH(hw); ixgbe_fdir_erase_perfect_filter_82599()
1726 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); ixgbe_fdir_erase_perfect_filter_82599()
1728 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); ixgbe_fdir_erase_perfect_filter_82599()
1730 hw_dbg(hw, "Flow Director command did not complete!\n"); ixgbe_fdir_erase_perfect_filter_82599()
1736 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); ixgbe_fdir_erase_perfect_filter_82599()
1737 IXGBE_WRITE_FLUSH(hw); ixgbe_fdir_erase_perfect_filter_82599()
1738 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, ixgbe_fdir_erase_perfect_filter_82599()
1747 * @hw: pointer to hardware structure
1753 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) ixgbe_read_analog_reg8_82599() argument
1757 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | ixgbe_read_analog_reg8_82599()
1759 IXGBE_WRITE_FLUSH(hw); ixgbe_read_analog_reg8_82599()
1761 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); ixgbe_read_analog_reg8_82599()
1769 * @hw: pointer to hardware structure
1775 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) ixgbe_write_analog_reg8_82599() argument
1780 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); ixgbe_write_analog_reg8_82599()
1781 IXGBE_WRITE_FLUSH(hw); ixgbe_write_analog_reg8_82599()
1789 * @hw: pointer to hardware structure
1795 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) ixgbe_start_hw_82599() argument
1799 ret_val = ixgbe_start_hw_generic(hw); ixgbe_start_hw_82599()
1803 ret_val = ixgbe_start_hw_gen2(hw); ixgbe_start_hw_82599()
1808 hw->mac.autotry_restart = true; ixgbe_start_hw_82599()
1813 return ixgbe_verify_fw_version_82599(hw); ixgbe_start_hw_82599()
1818 * @hw: pointer to hardware structure
1821 * If PHY already detected, maintains current PHY type in hw struct,
1824 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) ixgbe_identify_phy_82599() argument
1829 status = ixgbe_identify_phy_generic(hw); ixgbe_identify_phy_82599()
1832 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) ixgbe_identify_phy_82599()
1834 status = ixgbe_identify_module_generic(hw); ixgbe_identify_phy_82599()
1838 if (hw->phy.type == ixgbe_phy_unknown) { ixgbe_identify_phy_82599()
1839 hw->phy.type = ixgbe_phy_none; ixgbe_identify_phy_82599()
1844 if (hw->phy.type == ixgbe_phy_sfp_unsupported) ixgbe_identify_phy_82599()
1852 * @hw: pointer to hardware structure
1857 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) ixgbe_enable_rx_dma_82599() argument
1865 hw->mac.ops.disable_rx_buff(hw); ixgbe_enable_rx_dma_82599()
1868 hw->mac.ops.enable_rx(hw); ixgbe_enable_rx_dma_82599()
1870 hw->mac.ops.disable_rx(hw); ixgbe_enable_rx_dma_82599()
1872 hw->mac.ops.enable_rx_buff(hw); ixgbe_enable_rx_dma_82599()
1879 * @hw: pointer to hardware structure
1887 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) ixgbe_verify_fw_version_82599() argument
1895 if (hw->phy.media_type != ixgbe_media_type_fiber) ixgbe_verify_fw_version_82599()
1900 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) ixgbe_verify_fw_version_82599()
1908 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) ixgbe_verify_fw_version_82599()
1916 if (hw->eeprom.ops.read(hw, offset, &fw_version)) ixgbe_verify_fw_version_82599()
1925 hw_err(hw, "eeprom read at offset %d failed\n", offset); ixgbe_verify_fw_version_82599()
1931 * @hw: pointer to hardware structure
1936 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) ixgbe_verify_lesm_fw_enabled_82599() argument
1942 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); ixgbe_verify_lesm_fw_enabled_82599()
1948 status = hw->eeprom.ops.read(hw, (fw_offset + ixgbe_verify_lesm_fw_enabled_82599()
1957 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + ixgbe_verify_lesm_fw_enabled_82599()
1971 * @hw: pointer to hardware structure
1978 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, ixgbe_read_eeprom_buffer_82599() argument
1981 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; ixgbe_read_eeprom_buffer_82599()
1988 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); ixgbe_read_eeprom_buffer_82599()
1990 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, ixgbe_read_eeprom_buffer_82599()
1998 * @hw: pointer to hardware structure
2004 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, ixgbe_read_eeprom_82599() argument
2007 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; ixgbe_read_eeprom_82599()
2014 return ixgbe_read_eerd_generic(hw, offset, data); ixgbe_read_eeprom_82599()
2016 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); ixgbe_read_eeprom_82599()
2022 * @hw: pointer to hardware structure
2028 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) ixgbe_reset_pipeline_82599() argument
2035 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ixgbe_reset_pipeline_82599()
2038 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); ixgbe_reset_pipeline_82599()
2039 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_pipeline_82599()
2042 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_reset_pipeline_82599()
2046 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ixgbe_reset_pipeline_82599()
2052 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); ixgbe_reset_pipeline_82599()
2058 hw_dbg(hw, "auto negotiation not completed\n"); ixgbe_reset_pipeline_82599()
2067 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); ixgbe_reset_pipeline_82599()
2068 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_pipeline_82599()
2075 * @hw: pointer to hardware structure
2082 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_byte_82599() argument
2089 if (hw->phy.qsfp_shared_i2c_bus == true) { ixgbe_read_i2c_byte_82599()
2091 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_read_i2c_byte_82599()
2093 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_read_i2c_byte_82599()
2094 IXGBE_WRITE_FLUSH(hw); ixgbe_read_i2c_byte_82599()
2097 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_read_i2c_byte_82599()
2106 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); ixgbe_read_i2c_byte_82599()
2112 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); ixgbe_read_i2c_byte_82599()
2115 if (hw->phy.qsfp_shared_i2c_bus == true) { ixgbe_read_i2c_byte_82599()
2117 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_read_i2c_byte_82599()
2119 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_read_i2c_byte_82599()
2120 IXGBE_WRITE_FLUSH(hw); ixgbe_read_i2c_byte_82599()
2128 * @hw: pointer to hardware structure
2135 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_write_i2c_byte_82599() argument
2142 if (hw->phy.qsfp_shared_i2c_bus == true) { ixgbe_write_i2c_byte_82599()
2144 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_write_i2c_byte_82599()
2146 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_write_i2c_byte_82599()
2147 IXGBE_WRITE_FLUSH(hw); ixgbe_write_i2c_byte_82599()
2150 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_write_i2c_byte_82599()
2159 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); ixgbe_write_i2c_byte_82599()
2165 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); ixgbe_write_i2c_byte_82599()
2168 if (hw->phy.qsfp_shared_i2c_bus == true) { ixgbe_write_i2c_byte_82599()
2170 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_write_i2c_byte_82599()
2172 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); ixgbe_write_i2c_byte_82599()
2173 IXGBE_WRITE_FLUSH(hw); ixgbe_write_i2c_byte_82599()
H A Dixgbe_common.c38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
68 * @hw: pointer to hardware structure
74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) ixgbe_device_supports_autoneg_fc() argument
80 switch (hw->phy.media_type) { ixgbe_device_supports_autoneg_fc()
82 hw->mac.ops.check_link(hw, &speed, &link_up, false); ixgbe_device_supports_autoneg_fc()
95 switch (hw->device_id) { ixgbe_device_supports_autoneg_fc()
115 * @hw: pointer to hardware structure
119 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw) ixgbe_setup_fc() argument
130 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { ixgbe_setup_fc()
131 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); ixgbe_setup_fc()
139 if (hw->fc.requested_mode == ixgbe_fc_default) ixgbe_setup_fc()
140 hw->fc.requested_mode = ixgbe_fc_full; ixgbe_setup_fc()
147 switch (hw->phy.media_type) { ixgbe_setup_fc()
150 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp); ixgbe_setup_fc()
156 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); ixgbe_setup_fc()
160 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_fc()
177 switch (hw->fc.requested_mode) { ixgbe_setup_fc()
181 if (hw->phy.media_type == ixgbe_media_type_backplane) ixgbe_setup_fc()
184 else if (hw->phy.media_type == ixgbe_media_type_copper) ixgbe_setup_fc()
194 if (hw->phy.media_type == ixgbe_media_type_backplane) { ixgbe_setup_fc()
197 } else if (hw->phy.media_type == ixgbe_media_type_copper) { ixgbe_setup_fc()
215 if (hw->phy.media_type == ixgbe_media_type_backplane) ixgbe_setup_fc()
218 else if (hw->phy.media_type == ixgbe_media_type_copper) ixgbe_setup_fc()
222 hw_dbg(hw, "Flow control param set incorrectly\n"); ixgbe_setup_fc()
226 if (hw->mac.type != ixgbe_mac_X540) { ixgbe_setup_fc()
231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); ixgbe_setup_fc()
232 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); ixgbe_setup_fc()
235 if (hw->fc.strict_ieee) ixgbe_setup_fc()
238 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); ixgbe_setup_fc()
239 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); ixgbe_setup_fc()
247 if (hw->phy.media_type == ixgbe_media_type_backplane) { ixgbe_setup_fc()
252 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); ixgbe_setup_fc()
256 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && ixgbe_setup_fc()
257 ixgbe_device_supports_autoneg_fc(hw)) { ixgbe_setup_fc()
258 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_fc()
262 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); ixgbe_setup_fc()
268 * @hw: pointer to hardware structure
275 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) ixgbe_start_hw_generic() argument
281 hw->phy.media_type = hw->mac.ops.get_media_type(hw); ixgbe_start_hw_generic()
284 hw->phy.ops.identify(hw); ixgbe_start_hw_generic()
287 hw->mac.ops.clear_vfta(hw); ixgbe_start_hw_generic()
290 hw->mac.ops.clear_hw_cntrs(hw); ixgbe_start_hw_generic()
293 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); ixgbe_start_hw_generic()
295 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); ixgbe_start_hw_generic()
296 IXGBE_WRITE_FLUSH(hw); ixgbe_start_hw_generic()
299 ret_val = ixgbe_setup_fc(hw); ixgbe_start_hw_generic()
304 hw->adapter_stopped = false; ixgbe_start_hw_generic()
311 * @hw: pointer to hw structure
319 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) ixgbe_start_hw_gen2() argument
324 for (i = 0; i < hw->mac.max_tx_queues; i++) { ixgbe_start_hw_gen2()
325 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); ixgbe_start_hw_gen2()
326 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); ixgbe_start_hw_gen2()
328 IXGBE_WRITE_FLUSH(hw); ixgbe_start_hw_gen2()
332 for (i = 0; i < hw->mac.max_tx_queues; i++) { ixgbe_start_hw_gen2()
335 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); ixgbe_start_hw_gen2()
337 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); ixgbe_start_hw_gen2()
340 for (i = 0; i < hw->mac.max_rx_queues; i++) { ixgbe_start_hw_gen2()
343 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); ixgbe_start_hw_gen2()
346 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); ixgbe_start_hw_gen2()
354 * @hw: pointer to hardware structure
362 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) ixgbe_init_hw_generic() argument
367 status = hw->mac.ops.reset_hw(hw); ixgbe_init_hw_generic()
371 status = hw->mac.ops.start_hw(hw); ixgbe_init_hw_generic()
379 * @hw: pointer to hardware structure
384 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) ixgbe_clear_hw_cntrs_generic() argument
388 IXGBE_READ_REG(hw, IXGBE_CRCERRS); ixgbe_clear_hw_cntrs_generic()
389 IXGBE_READ_REG(hw, IXGBE_ILLERRC); ixgbe_clear_hw_cntrs_generic()
390 IXGBE_READ_REG(hw, IXGBE_ERRBC); ixgbe_clear_hw_cntrs_generic()
391 IXGBE_READ_REG(hw, IXGBE_MSPDC); ixgbe_clear_hw_cntrs_generic()
393 IXGBE_READ_REG(hw, IXGBE_MPC(i)); ixgbe_clear_hw_cntrs_generic()
395 IXGBE_READ_REG(hw, IXGBE_MLFC); ixgbe_clear_hw_cntrs_generic()
396 IXGBE_READ_REG(hw, IXGBE_MRFC); ixgbe_clear_hw_cntrs_generic()
397 IXGBE_READ_REG(hw, IXGBE_RLEC); ixgbe_clear_hw_cntrs_generic()
398 IXGBE_READ_REG(hw, IXGBE_LXONTXC); ixgbe_clear_hw_cntrs_generic()
399 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); ixgbe_clear_hw_cntrs_generic()
400 if (hw->mac.type >= ixgbe_mac_82599EB) { ixgbe_clear_hw_cntrs_generic()
401 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); ixgbe_clear_hw_cntrs_generic()
402 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); ixgbe_clear_hw_cntrs_generic()
404 IXGBE_READ_REG(hw, IXGBE_LXONRXC); ixgbe_clear_hw_cntrs_generic()
405 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); ixgbe_clear_hw_cntrs_generic()
409 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); ixgbe_clear_hw_cntrs_generic()
410 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); ixgbe_clear_hw_cntrs_generic()
411 if (hw->mac.type >= ixgbe_mac_82599EB) { ixgbe_clear_hw_cntrs_generic()
412 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); ixgbe_clear_hw_cntrs_generic()
413 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); ixgbe_clear_hw_cntrs_generic()
415 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); ixgbe_clear_hw_cntrs_generic()
416 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); ixgbe_clear_hw_cntrs_generic()
419 if (hw->mac.type >= ixgbe_mac_82599EB) ixgbe_clear_hw_cntrs_generic()
421 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); ixgbe_clear_hw_cntrs_generic()
422 IXGBE_READ_REG(hw, IXGBE_PRC64); ixgbe_clear_hw_cntrs_generic()
423 IXGBE_READ_REG(hw, IXGBE_PRC127); ixgbe_clear_hw_cntrs_generic()
424 IXGBE_READ_REG(hw, IXGBE_PRC255); ixgbe_clear_hw_cntrs_generic()
425 IXGBE_READ_REG(hw, IXGBE_PRC511); ixgbe_clear_hw_cntrs_generic()
426 IXGBE_READ_REG(hw, IXGBE_PRC1023); ixgbe_clear_hw_cntrs_generic()
427 IXGBE_READ_REG(hw, IXGBE_PRC1522); ixgbe_clear_hw_cntrs_generic()
428 IXGBE_READ_REG(hw, IXGBE_GPRC); ixgbe_clear_hw_cntrs_generic()
429 IXGBE_READ_REG(hw, IXGBE_BPRC); ixgbe_clear_hw_cntrs_generic()
430 IXGBE_READ_REG(hw, IXGBE_MPRC); ixgbe_clear_hw_cntrs_generic()
431 IXGBE_READ_REG(hw, IXGBE_GPTC); ixgbe_clear_hw_cntrs_generic()
432 IXGBE_READ_REG(hw, IXGBE_GORCL); ixgbe_clear_hw_cntrs_generic()
433 IXGBE_READ_REG(hw, IXGBE_GORCH); ixgbe_clear_hw_cntrs_generic()
434 IXGBE_READ_REG(hw, IXGBE_GOTCL); ixgbe_clear_hw_cntrs_generic()
435 IXGBE_READ_REG(hw, IXGBE_GOTCH); ixgbe_clear_hw_cntrs_generic()
436 if (hw->mac.type == ixgbe_mac_82598EB) ixgbe_clear_hw_cntrs_generic()
438 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); ixgbe_clear_hw_cntrs_generic()
439 IXGBE_READ_REG(hw, IXGBE_RUC); ixgbe_clear_hw_cntrs_generic()
440 IXGBE_READ_REG(hw, IXGBE_RFC); ixgbe_clear_hw_cntrs_generic()
441 IXGBE_READ_REG(hw, IXGBE_ROC); ixgbe_clear_hw_cntrs_generic()
442 IXGBE_READ_REG(hw, IXGBE_RJC); ixgbe_clear_hw_cntrs_generic()
443 IXGBE_READ_REG(hw, IXGBE_MNGPRC); ixgbe_clear_hw_cntrs_generic()
444 IXGBE_READ_REG(hw, IXGBE_MNGPDC); ixgbe_clear_hw_cntrs_generic()
445 IXGBE_READ_REG(hw, IXGBE_MNGPTC); ixgbe_clear_hw_cntrs_generic()
446 IXGBE_READ_REG(hw, IXGBE_TORL); ixgbe_clear_hw_cntrs_generic()
447 IXGBE_READ_REG(hw, IXGBE_TORH); ixgbe_clear_hw_cntrs_generic()
448 IXGBE_READ_REG(hw, IXGBE_TPR); ixgbe_clear_hw_cntrs_generic()
449 IXGBE_READ_REG(hw, IXGBE_TPT); ixgbe_clear_hw_cntrs_generic()
450 IXGBE_READ_REG(hw, IXGBE_PTC64); ixgbe_clear_hw_cntrs_generic()
451 IXGBE_READ_REG(hw, IXGBE_PTC127); ixgbe_clear_hw_cntrs_generic()
452 IXGBE_READ_REG(hw, IXGBE_PTC255); ixgbe_clear_hw_cntrs_generic()
453 IXGBE_READ_REG(hw, IXGBE_PTC511); ixgbe_clear_hw_cntrs_generic()
454 IXGBE_READ_REG(hw, IXGBE_PTC1023); ixgbe_clear_hw_cntrs_generic()
455 IXGBE_READ_REG(hw, IXGBE_PTC1522); ixgbe_clear_hw_cntrs_generic()
456 IXGBE_READ_REG(hw, IXGBE_MPTC); ixgbe_clear_hw_cntrs_generic()
457 IXGBE_READ_REG(hw, IXGBE_BPTC); ixgbe_clear_hw_cntrs_generic()
459 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); ixgbe_clear_hw_cntrs_generic()
460 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); ixgbe_clear_hw_cntrs_generic()
461 if (hw->mac.type >= ixgbe_mac_82599EB) { ixgbe_clear_hw_cntrs_generic()
462 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); ixgbe_clear_hw_cntrs_generic()
463 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); ixgbe_clear_hw_cntrs_generic()
464 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); ixgbe_clear_hw_cntrs_generic()
465 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); ixgbe_clear_hw_cntrs_generic()
466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); ixgbe_clear_hw_cntrs_generic()
468 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); ixgbe_clear_hw_cntrs_generic()
469 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); ixgbe_clear_hw_cntrs_generic()
473 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { ixgbe_clear_hw_cntrs_generic()
474 if (hw->phy.id == 0) ixgbe_clear_hw_cntrs_generic()
475 hw->phy.ops.identify(hw); ixgbe_clear_hw_cntrs_generic()
476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); ixgbe_clear_hw_cntrs_generic()
477 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); ixgbe_clear_hw_cntrs_generic()
478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); ixgbe_clear_hw_cntrs_generic()
479 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); ixgbe_clear_hw_cntrs_generic()
487 * @hw: pointer to hardware structure
493 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, ixgbe_read_pba_string_generic() argument
503 hw_dbg(hw, "PBA string buffer was null\n"); ixgbe_read_pba_string_generic()
507 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); ixgbe_read_pba_string_generic()
509 hw_dbg(hw, "NVM Read Error\n"); ixgbe_read_pba_string_generic()
513 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); ixgbe_read_pba_string_generic()
515 hw_dbg(hw, "NVM Read Error\n"); ixgbe_read_pba_string_generic()
525 hw_dbg(hw, "NVM PBA number is not stored as string\n"); ixgbe_read_pba_string_generic()
529 hw_dbg(hw, "PBA string buffer too small\n"); ixgbe_read_pba_string_generic()
559 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); ixgbe_read_pba_string_generic()
561 hw_dbg(hw, "NVM Read Error\n"); ixgbe_read_pba_string_generic()
566 hw_dbg(hw, "NVM PBA number section invalid length\n"); ixgbe_read_pba_string_generic()
572 hw_dbg(hw, "PBA string buffer too small\n"); ixgbe_read_pba_string_generic()
581 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); ixgbe_read_pba_string_generic()
583 hw_dbg(hw, "NVM Read Error\n"); ixgbe_read_pba_string_generic()
596 * @hw: pointer to hardware structure
603 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) ixgbe_get_mac_addr_generic() argument
609 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); ixgbe_get_mac_addr_generic()
610 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); ixgbe_get_mac_addr_generic()
653 * @hw: pointer to hardware structure
657 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) ixgbe_get_bus_info_generic() argument
661 hw->bus.type = ixgbe_bus_type_pci_express; ixgbe_get_bus_info_generic()
664 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); ixgbe_get_bus_info_generic()
666 hw->bus.width = ixgbe_convert_bus_width(link_status); ixgbe_get_bus_info_generic()
667 hw->bus.speed = ixgbe_convert_bus_speed(link_status); ixgbe_get_bus_info_generic()
669 hw->mac.ops.set_lan_id(hw); ixgbe_get_bus_info_generic()
676 * @hw: pointer to the HW structure
681 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) ixgbe_set_lan_id_multi_port_pcie() argument
683 struct ixgbe_bus_info *bus = &hw->bus; ixgbe_set_lan_id_multi_port_pcie()
686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); ixgbe_set_lan_id_multi_port_pcie()
691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); ixgbe_set_lan_id_multi_port_pcie()
698 * @hw: pointer to hardware structure
705 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) ixgbe_stop_adapter_generic() argument
714 hw->adapter_stopped = true; ixgbe_stop_adapter_generic()
717 hw->mac.ops.disable_rx(hw); ixgbe_stop_adapter_generic()
720 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); ixgbe_stop_adapter_generic()
723 IXGBE_READ_REG(hw, IXGBE_EICR); ixgbe_stop_adapter_generic()
726 for (i = 0; i < hw->mac.max_tx_queues; i++) ixgbe_stop_adapter_generic()
727 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); ixgbe_stop_adapter_generic()
730 for (i = 0; i < hw->mac.max_rx_queues; i++) { ixgbe_stop_adapter_generic()
731 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); ixgbe_stop_adapter_generic()
734 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); ixgbe_stop_adapter_generic()
738 IXGBE_WRITE_FLUSH(hw); ixgbe_stop_adapter_generic()
745 return ixgbe_disable_pcie_master(hw); ixgbe_stop_adapter_generic()
750 * @hw: pointer to hardware structure
753 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) ixgbe_led_on_generic() argument
755 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_led_on_generic()
760 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); ixgbe_led_on_generic()
761 IXGBE_WRITE_FLUSH(hw); ixgbe_led_on_generic()
768 * @hw: pointer to hardware structure
771 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) ixgbe_led_off_generic() argument
773 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_led_off_generic()
778 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); ixgbe_led_off_generic()
779 IXGBE_WRITE_FLUSH(hw); ixgbe_led_off_generic()
786 * @hw: pointer to hardware structure
791 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) ixgbe_init_eeprom_params_generic() argument
793 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; ixgbe_init_eeprom_params_generic()
809 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_init_eeprom_params_generic()
827 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", ixgbe_init_eeprom_params_generic()
836 * @hw: pointer to hardware structure
843 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, ixgbe_write_eeprom_buffer_bit_bang_generic() argument
849 hw->eeprom.ops.init_params(hw); ixgbe_write_eeprom_buffer_bit_bang_generic()
854 if (offset + words > hw->eeprom.word_size) ixgbe_write_eeprom_buffer_bit_bang_generic()
861 if ((hw->eeprom.word_page_size == 0) && ixgbe_write_eeprom_buffer_bit_bang_generic()
863 ixgbe_detect_eeprom_page_size_generic(hw, offset); ixgbe_write_eeprom_buffer_bit_bang_generic()
873 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, ixgbe_write_eeprom_buffer_bit_bang_generic()
885 * @hw: pointer to hardware structure
893 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, ixgbe_write_eeprom_buffer_bit_bang() argument
903 status = ixgbe_acquire_eeprom(hw); ixgbe_write_eeprom_buffer_bit_bang()
907 if (ixgbe_ready_eeprom(hw) != 0) { ixgbe_write_eeprom_buffer_bit_bang()
908 ixgbe_release_eeprom(hw); ixgbe_write_eeprom_buffer_bit_bang()
913 ixgbe_standby_eeprom(hw); ixgbe_write_eeprom_buffer_bit_bang()
916 ixgbe_shift_out_eeprom_bits(hw, ixgbe_write_eeprom_buffer_bit_bang()
920 ixgbe_standby_eeprom(hw); ixgbe_write_eeprom_buffer_bit_bang()
925 if ((hw->eeprom.address_bits == 8) && ixgbe_write_eeprom_buffer_bit_bang()
930 ixgbe_shift_out_eeprom_bits(hw, write_opcode, ixgbe_write_eeprom_buffer_bit_bang()
932 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), ixgbe_write_eeprom_buffer_bit_bang()
933 hw->eeprom.address_bits); ixgbe_write_eeprom_buffer_bit_bang()
935 page_size = hw->eeprom.word_page_size; ixgbe_write_eeprom_buffer_bit_bang()
941 ixgbe_shift_out_eeprom_bits(hw, word, 16); ixgbe_write_eeprom_buffer_bit_bang()
952 ixgbe_standby_eeprom(hw); ixgbe_write_eeprom_buffer_bit_bang()
956 ixgbe_release_eeprom(hw); ixgbe_write_eeprom_buffer_bit_bang()
963 * @hw: pointer to hardware structure
970 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) ixgbe_write_eeprom_generic() argument
972 hw->eeprom.ops.init_params(hw); ixgbe_write_eeprom_generic()
974 if (offset >= hw->eeprom.word_size) ixgbe_write_eeprom_generic()
977 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); ixgbe_write_eeprom_generic()
982 * @hw: pointer to hardware structure
989 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, ixgbe_read_eeprom_buffer_bit_bang_generic() argument
995 hw->eeprom.ops.init_params(hw); ixgbe_read_eeprom_buffer_bit_bang_generic()
1000 if (offset + words > hw->eeprom.word_size) ixgbe_read_eeprom_buffer_bit_bang_generic()
1012 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, ixgbe_read_eeprom_buffer_bit_bang_generic()
1024 * @hw: pointer to hardware structure
1031 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, ixgbe_read_eeprom_buffer_bit_bang() argument
1040 status = ixgbe_acquire_eeprom(hw); ixgbe_read_eeprom_buffer_bit_bang()
1044 if (ixgbe_ready_eeprom(hw) != 0) { ixgbe_read_eeprom_buffer_bit_bang()
1045 ixgbe_release_eeprom(hw); ixgbe_read_eeprom_buffer_bit_bang()
1050 ixgbe_standby_eeprom(hw); ixgbe_read_eeprom_buffer_bit_bang()
1054 if ((hw->eeprom.address_bits == 8) && ixgbe_read_eeprom_buffer_bit_bang()
1059 ixgbe_shift_out_eeprom_bits(hw, read_opcode, ixgbe_read_eeprom_buffer_bit_bang()
1061 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), ixgbe_read_eeprom_buffer_bit_bang()
1062 hw->eeprom.address_bits); ixgbe_read_eeprom_buffer_bit_bang()
1065 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); ixgbe_read_eeprom_buffer_bit_bang()
1070 ixgbe_release_eeprom(hw); ixgbe_read_eeprom_buffer_bit_bang()
1077 * @hw: pointer to hardware structure
1083 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, ixgbe_read_eeprom_bit_bang_generic() argument
1086 hw->eeprom.ops.init_params(hw); ixgbe_read_eeprom_bit_bang_generic()
1088 if (offset >= hw->eeprom.word_size) ixgbe_read_eeprom_bit_bang_generic()
1091 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); ixgbe_read_eeprom_bit_bang_generic()
1096 * @hw: pointer to hardware structure
1103 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, ixgbe_read_eerd_buffer_generic() argument
1110 hw->eeprom.ops.init_params(hw); ixgbe_read_eerd_buffer_generic()
1115 if (offset >= hw->eeprom.word_size) ixgbe_read_eerd_buffer_generic()
1122 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); ixgbe_read_eerd_buffer_generic()
1123 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); ixgbe_read_eerd_buffer_generic()
1126 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> ixgbe_read_eerd_buffer_generic()
1129 hw_dbg(hw, "Eeprom read timed out\n"); ixgbe_read_eerd_buffer_generic()
1139 * @hw: pointer to hardware structure
1146 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, ixgbe_detect_eeprom_page_size_generic() argument
1156 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; ixgbe_detect_eeprom_page_size_generic()
1157 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, ixgbe_detect_eeprom_page_size_generic()
1159 hw->eeprom.word_page_size = 0; ixgbe_detect_eeprom_page_size_generic()
1163 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); ixgbe_detect_eeprom_page_size_generic()
1171 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; ixgbe_detect_eeprom_page_size_generic()
1173 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", ixgbe_detect_eeprom_page_size_generic()
1174 hw->eeprom.word_page_size); ixgbe_detect_eeprom_page_size_generic()
1180 * @hw: pointer to hardware structure
1186 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) ixgbe_read_eerd_generic() argument
1188 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); ixgbe_read_eerd_generic()
1193 * @hw: pointer to hardware structure
1200 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, ixgbe_write_eewr_buffer_generic() argument
1207 hw->eeprom.ops.init_params(hw); ixgbe_write_eewr_buffer_generic()
1212 if (offset >= hw->eeprom.word_size) ixgbe_write_eewr_buffer_generic()
1220 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); ixgbe_write_eewr_buffer_generic()
1222 hw_dbg(hw, "Eeprom write EEWR timed out\n"); ixgbe_write_eewr_buffer_generic()
1226 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); ixgbe_write_eewr_buffer_generic()
1228 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); ixgbe_write_eewr_buffer_generic()
1230 hw_dbg(hw, "Eeprom write EEWR timed out\n"); ixgbe_write_eewr_buffer_generic()
1240 * @hw: pointer to hardware structure
1246 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) ixgbe_write_eewr_generic() argument
1248 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); ixgbe_write_eewr_generic()
1253 * @hw: pointer to hardware structure
1259 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) ixgbe_poll_eerd_eewr_done() argument
1266 reg = IXGBE_READ_REG(hw, IXGBE_EERD); ixgbe_poll_eerd_eewr_done()
1268 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); ixgbe_poll_eerd_eewr_done()
1280 * @hw: pointer to hardware structure
1285 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) ixgbe_acquire_eeprom() argument
1290 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) ixgbe_acquire_eeprom()
1293 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_acquire_eeprom()
1297 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_acquire_eeprom()
1300 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_acquire_eeprom()
1309 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_acquire_eeprom()
1310 hw_dbg(hw, "Could not acquire EEPROM grant\n"); ixgbe_acquire_eeprom()
1312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_acquire_eeprom()
1319 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_acquire_eeprom()
1320 IXGBE_WRITE_FLUSH(hw); ixgbe_acquire_eeprom()
1327 * @hw: pointer to hardware structure
1331 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) ixgbe_get_eeprom_semaphore() argument
1343 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_get_eeprom_semaphore()
1350 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); ixgbe_get_eeprom_semaphore()
1356 ixgbe_release_eeprom_semaphore(hw); ixgbe_get_eeprom_semaphore()
1363 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_get_eeprom_semaphore()
1365 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); ixgbe_get_eeprom_semaphore()
1372 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_get_eeprom_semaphore()
1376 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); ixgbe_get_eeprom_semaphore()
1381 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_get_eeprom_semaphore()
1392 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); ixgbe_get_eeprom_semaphore()
1393 ixgbe_release_eeprom_semaphore(hw); ixgbe_get_eeprom_semaphore()
1402 * @hw: pointer to hardware structure
1406 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) ixgbe_release_eeprom_semaphore() argument
1410 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_release_eeprom_semaphore()
1414 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); ixgbe_release_eeprom_semaphore()
1415 IXGBE_WRITE_FLUSH(hw); ixgbe_release_eeprom_semaphore()
1420 * @hw: pointer to hardware structure
1422 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) ixgbe_ready_eeprom() argument
1434 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, ixgbe_ready_eeprom()
1436 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); ixgbe_ready_eeprom()
1441 ixgbe_standby_eeprom(hw); ixgbe_ready_eeprom()
1449 hw_dbg(hw, "SPI EEPROM Status error\n"); ixgbe_ready_eeprom()
1458 * @hw: pointer to hardware structure
1460 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) ixgbe_standby_eeprom() argument
1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_standby_eeprom()
1468 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_standby_eeprom()
1469 IXGBE_WRITE_FLUSH(hw); ixgbe_standby_eeprom()
1472 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_standby_eeprom()
1473 IXGBE_WRITE_FLUSH(hw); ixgbe_standby_eeprom()
1479 * @hw: pointer to hardware structure
1483 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, ixgbe_shift_out_eeprom_bits() argument
1490 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_shift_out_eeprom_bits()
1511 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_shift_out_eeprom_bits()
1512 IXGBE_WRITE_FLUSH(hw); ixgbe_shift_out_eeprom_bits()
1516 ixgbe_raise_eeprom_clk(hw, &eec); ixgbe_shift_out_eeprom_bits()
1517 ixgbe_lower_eeprom_clk(hw, &eec); ixgbe_shift_out_eeprom_bits()
1528 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_shift_out_eeprom_bits()
1529 IXGBE_WRITE_FLUSH(hw); ixgbe_shift_out_eeprom_bits()
1534 * @hw: pointer to hardware structure
1536 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) ixgbe_shift_in_eeprom_bits() argument
1549 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_shift_in_eeprom_bits()
1555 ixgbe_raise_eeprom_clk(hw, &eec); ixgbe_shift_in_eeprom_bits()
1557 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_shift_in_eeprom_bits()
1563 ixgbe_lower_eeprom_clk(hw, &eec); ixgbe_shift_in_eeprom_bits()
1571 * @hw: pointer to hardware structure
1574 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) ixgbe_raise_eeprom_clk() argument
1581 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); ixgbe_raise_eeprom_clk()
1582 IXGBE_WRITE_FLUSH(hw); ixgbe_raise_eeprom_clk()
1588 * @hw: pointer to hardware structure
1591 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) ixgbe_lower_eeprom_clk() argument
1598 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); ixgbe_lower_eeprom_clk()
1599 IXGBE_WRITE_FLUSH(hw); ixgbe_lower_eeprom_clk()
1605 * @hw: pointer to hardware structure
1607 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) ixgbe_release_eeprom() argument
1611 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_release_eeprom()
1616 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_release_eeprom()
1617 IXGBE_WRITE_FLUSH(hw); ixgbe_release_eeprom()
1623 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); ixgbe_release_eeprom()
1625 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_release_eeprom()
1631 usleep_range(hw->eeprom.semaphore_delay * 1000, ixgbe_release_eeprom()
1632 hw->eeprom.semaphore_delay * 2000); ixgbe_release_eeprom()
1637 * @hw: pointer to hardware structure
1639 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) ixgbe_calc_eeprom_checksum_generic() argument
1650 if (hw->eeprom.ops.read(hw, i, &word)) { ixgbe_calc_eeprom_checksum_generic()
1651 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_generic()
1659 if (hw->eeprom.ops.read(hw, i, &pointer)) { ixgbe_calc_eeprom_checksum_generic()
1660 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_generic()
1668 if (hw->eeprom.ops.read(hw, pointer, &length)) { ixgbe_calc_eeprom_checksum_generic()
1669 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_generic()
1677 if (hw->eeprom.ops.read(hw, j, &word)) { ixgbe_calc_eeprom_checksum_generic()
1678 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_generic()
1692 * @hw: pointer to hardware structure
1698 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, ixgbe_validate_eeprom_checksum_generic() argument
1710 status = hw->eeprom.ops.read(hw, 0, &checksum); ixgbe_validate_eeprom_checksum_generic()
1712 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_validate_eeprom_checksum_generic()
1716 status = hw->eeprom.ops.calc_checksum(hw); ixgbe_validate_eeprom_checksum_generic()
1722 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); ixgbe_validate_eeprom_checksum_generic()
1724 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_validate_eeprom_checksum_generic()
1743 * @hw: pointer to hardware structure
1745 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) ixgbe_update_eeprom_checksum_generic() argument
1755 status = hw->eeprom.ops.read(hw, 0, &checksum); ixgbe_update_eeprom_checksum_generic()
1757 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_update_eeprom_checksum_generic()
1761 status = hw->eeprom.ops.calc_checksum(hw); ixgbe_update_eeprom_checksum_generic()
1767 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); ixgbe_update_eeprom_checksum_generic()
1774 * @hw: pointer to hardware structure
1782 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, ixgbe_set_rar_generic() argument
1786 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_set_rar_generic()
1790 hw_dbg(hw, "RAR index %d is out of range.\n", index); ixgbe_set_rar_generic()
1795 hw->mac.ops.set_vmdq(hw, index, vmdq); ixgbe_set_rar_generic()
1810 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); ixgbe_set_rar_generic()
1817 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); ixgbe_set_rar_generic()
1818 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); ixgbe_set_rar_generic()
1825 * @hw: pointer to hardware structure
1830 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) ixgbe_clear_rar_generic() argument
1833 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_clear_rar_generic()
1837 hw_dbg(hw, "RAR index %d is out of range.\n", index); ixgbe_clear_rar_generic()
1846 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); ixgbe_clear_rar_generic()
1849 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); ixgbe_clear_rar_generic()
1850 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); ixgbe_clear_rar_generic()
1853 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); ixgbe_clear_rar_generic()
1860 * @hw: pointer to hardware structure
1866 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) ixgbe_init_rx_addrs_generic() argument
1869 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_init_rx_addrs_generic()
1876 if (!is_valid_ether_addr(hw->mac.addr)) { ixgbe_init_rx_addrs_generic()
1878 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); ixgbe_init_rx_addrs_generic()
1880 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); ixgbe_init_rx_addrs_generic()
1883 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); ixgbe_init_rx_addrs_generic()
1884 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); ixgbe_init_rx_addrs_generic()
1886 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); ixgbe_init_rx_addrs_generic()
1889 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); ixgbe_init_rx_addrs_generic()
1891 hw->addr_ctrl.overflow_promisc = 0; ixgbe_init_rx_addrs_generic()
1893 hw->addr_ctrl.rar_used_count = 1; ixgbe_init_rx_addrs_generic()
1896 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); ixgbe_init_rx_addrs_generic()
1898 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); ixgbe_init_rx_addrs_generic()
1899 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); ixgbe_init_rx_addrs_generic()
1903 hw->addr_ctrl.mta_in_use = 0; ixgbe_init_rx_addrs_generic()
1904 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); ixgbe_init_rx_addrs_generic()
1906 hw_dbg(hw, " Clearing MTA\n"); ixgbe_init_rx_addrs_generic()
1907 for (i = 0; i < hw->mac.mcft_size; i++) ixgbe_init_rx_addrs_generic()
1908 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); ixgbe_init_rx_addrs_generic()
1910 if (hw->mac.ops.init_uta_tables) ixgbe_init_rx_addrs_generic()
1911 hw->mac.ops.init_uta_tables(hw); ixgbe_init_rx_addrs_generic()
1918 * @hw: pointer to hardware structure
1928 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) ixgbe_mta_vector() argument
1932 switch (hw->mac.mc_filter_type) { ixgbe_mta_vector()
1946 hw_dbg(hw, "MC filter type param set incorrectly\n"); ixgbe_mta_vector()
1957 * @hw: pointer to hardware structure
1962 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) ixgbe_set_mta() argument
1968 hw->addr_ctrl.mta_in_use++; ixgbe_set_mta()
1970 vector = ixgbe_mta_vector(hw, mc_addr); ixgbe_set_mta()
1971 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); ixgbe_set_mta()
1984 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); ixgbe_set_mta()
1989 * @hw: pointer to hardware structure
1997 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, ixgbe_update_mc_addr_list_generic() argument
2007 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); ixgbe_update_mc_addr_list_generic()
2008 hw->addr_ctrl.mta_in_use = 0; ixgbe_update_mc_addr_list_generic()
2011 hw_dbg(hw, " Clearing MTA\n"); ixgbe_update_mc_addr_list_generic()
2012 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); ixgbe_update_mc_addr_list_generic()
2016 hw_dbg(hw, " Adding the multicast addresses:\n"); netdev_for_each_mc_addr()
2017 ixgbe_set_mta(hw, ha->addr); netdev_for_each_mc_addr()
2021 for (i = 0; i < hw->mac.mcft_size; i++)
2022 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2023 hw->mac.mta_shadow[i]);
2025 if (hw->addr_ctrl.mta_in_use > 0)
2026 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2027 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2029 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2035 * @hw: pointer to hardware structure
2039 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) ixgbe_enable_mc_generic() argument
2041 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; ixgbe_enable_mc_generic()
2044 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | ixgbe_enable_mc_generic()
2045 hw->mac.mc_filter_type); ixgbe_enable_mc_generic()
2052 * @hw: pointer to hardware structure
2056 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) ixgbe_disable_mc_generic() argument
2058 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; ixgbe_disable_mc_generic()
2061 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); ixgbe_disable_mc_generic()
2068 * @hw: pointer to hardware structure
2072 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) ixgbe_fc_enable_generic() argument
2080 if (!hw->fc.pause_time) ixgbe_fc_enable_generic()
2085 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && ixgbe_fc_enable_generic()
2086 hw->fc.high_water[i]) { ixgbe_fc_enable_generic()
2087 if (!hw->fc.low_water[i] || ixgbe_fc_enable_generic()
2088 hw->fc.low_water[i] >= hw->fc.high_water[i]) { ixgbe_fc_enable_generic()
2089 hw_dbg(hw, "Invalid water mark configuration\n"); ixgbe_fc_enable_generic()
2096 ixgbe_fc_autoneg(hw); ixgbe_fc_enable_generic()
2099 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); ixgbe_fc_enable_generic()
2102 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); ixgbe_fc_enable_generic()
2115 switch (hw->fc.current_mode) { ixgbe_fc_enable_generic()
2146 hw_dbg(hw, "Flow control param set incorrectly\n"); ixgbe_fc_enable_generic()
2152 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); ixgbe_fc_enable_generic()
2153 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); ixgbe_fc_enable_generic()
2157 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && ixgbe_fc_enable_generic()
2158 hw->fc.high_water[i]) { ixgbe_fc_enable_generic()
2159 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; ixgbe_fc_enable_generic()
2160 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); ixgbe_fc_enable_generic()
2161 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; ixgbe_fc_enable_generic()
2163 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); ixgbe_fc_enable_generic()
2171 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; ixgbe_fc_enable_generic()
2174 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); ixgbe_fc_enable_generic()
2178 reg = hw->fc.pause_time * 0x00010001; ixgbe_fc_enable_generic()
2180 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); ixgbe_fc_enable_generic()
2182 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); ixgbe_fc_enable_generic()
2189 * @hw: pointer to hardware structure
2200 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, ixgbe_negotiate_fc() argument
2214 if (hw->fc.requested_mode == ixgbe_fc_full) { ixgbe_negotiate_fc()
2215 hw->fc.current_mode = ixgbe_fc_full; ixgbe_negotiate_fc()
2216 hw_dbg(hw, "Flow Control = FULL.\n"); ixgbe_negotiate_fc()
2218 hw->fc.current_mode = ixgbe_fc_rx_pause; ixgbe_negotiate_fc()
2219 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); ixgbe_negotiate_fc()
2223 hw->fc.current_mode = ixgbe_fc_tx_pause; ixgbe_negotiate_fc()
2224 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); ixgbe_negotiate_fc()
2227 hw->fc.current_mode = ixgbe_fc_rx_pause; ixgbe_negotiate_fc()
2228 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); ixgbe_negotiate_fc()
2230 hw->fc.current_mode = ixgbe_fc_none; ixgbe_negotiate_fc()
2231 hw_dbg(hw, "Flow Control = NONE.\n"); ixgbe_negotiate_fc()
2238 * @hw: pointer to hardware structure
2242 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) ixgbe_fc_autoneg_fiber() argument
2253 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); ixgbe_fc_autoneg_fiber()
2258 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); ixgbe_fc_autoneg_fiber()
2259 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); ixgbe_fc_autoneg_fiber()
2261 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, ixgbe_fc_autoneg_fiber()
2272 * @hw: pointer to hardware structure
2276 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) ixgbe_fc_autoneg_backplane() argument
2286 links = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_fc_autoneg_backplane()
2290 if (hw->mac.type == ixgbe_mac_82599EB) { ixgbe_fc_autoneg_backplane()
2291 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); ixgbe_fc_autoneg_backplane()
2299 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_fc_autoneg_backplane()
2300 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); ixgbe_fc_autoneg_backplane()
2302 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, ixgbe_fc_autoneg_backplane()
2311 * @hw: pointer to hardware structure
2315 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) ixgbe_fc_autoneg_copper() argument
2320 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, ixgbe_fc_autoneg_copper()
2323 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, ixgbe_fc_autoneg_copper()
2327 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, ixgbe_fc_autoneg_copper()
2335 * @hw: pointer to hardware structure
2340 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) ixgbe_fc_autoneg() argument
2355 if (hw->fc.disable_fc_autoneg) ixgbe_fc_autoneg()
2358 hw->mac.ops.check_link(hw, &speed, &link_up, false); ixgbe_fc_autoneg()
2362 switch (hw->phy.media_type) { ixgbe_fc_autoneg()
2366 ret_val = ixgbe_fc_autoneg_fiber(hw); ixgbe_fc_autoneg()
2371 ret_val = ixgbe_fc_autoneg_backplane(hw); ixgbe_fc_autoneg()
2376 if (ixgbe_device_supports_autoneg_fc(hw)) ixgbe_fc_autoneg()
2377 ret_val = ixgbe_fc_autoneg_copper(hw); ixgbe_fc_autoneg()
2386 hw->fc.fc_was_autonegged = true; ixgbe_fc_autoneg()
2388 hw->fc.fc_was_autonegged = false; ixgbe_fc_autoneg()
2389 hw->fc.current_mode = hw->fc.requested_mode; ixgbe_fc_autoneg()
2395 * @hw: pointer to hardware structure
2403 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) ixgbe_pcie_timeout_poll() argument
2408 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); ixgbe_pcie_timeout_poll()
2442 * @hw: pointer to hardware structure
2449 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) ixgbe_disable_pcie_master() argument
2455 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); ixgbe_disable_pcie_master()
2458 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || ixgbe_disable_pcie_master()
2459 ixgbe_removed(hw->hw_addr)) ixgbe_disable_pcie_master()
2465 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) ixgbe_disable_pcie_master()
2477 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); ixgbe_disable_pcie_master()
2478 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; ixgbe_disable_pcie_master()
2480 if (hw->mac.type >= ixgbe_mac_X550) ixgbe_disable_pcie_master()
2487 poll = ixgbe_pcie_timeout_poll(hw); ixgbe_disable_pcie_master()
2490 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); ixgbe_disable_pcie_master()
2491 if (ixgbe_removed(hw->hw_addr)) ixgbe_disable_pcie_master()
2497 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); ixgbe_disable_pcie_master()
2503 * @hw: pointer to hardware structure
2509 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) ixgbe_acquire_swfw_sync() argument
2522 if (ixgbe_get_eeprom_semaphore(hw)) ixgbe_acquire_swfw_sync()
2525 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); ixgbe_acquire_swfw_sync()
2528 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); ixgbe_acquire_swfw_sync()
2529 ixgbe_release_eeprom_semaphore(hw); ixgbe_acquire_swfw_sync()
2533 ixgbe_release_eeprom_semaphore(hw); ixgbe_acquire_swfw_sync()
2540 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); ixgbe_acquire_swfw_sync()
2548 * @hw: pointer to hardware structure
2554 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) ixgbe_release_swfw_sync() argument
2559 ixgbe_get_eeprom_semaphore(hw); ixgbe_release_swfw_sync()
2561 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); ixgbe_release_swfw_sync()
2563 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); ixgbe_release_swfw_sync()
2565 ixgbe_release_eeprom_semaphore(hw); ixgbe_release_swfw_sync()
2570 * @hw: pointer to hardware structure
2577 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) prot_autoc_read_generic() argument
2580 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); prot_autoc_read_generic()
2586 * @hw: pointer to hardware structure
2591 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) prot_autoc_write_generic() argument
2593 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); prot_autoc_write_generic()
2599 * @hw: pointer to hardware structure
2604 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) ixgbe_disable_rx_buff_generic() argument
2610 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); ixgbe_disable_rx_buff_generic()
2612 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); ixgbe_disable_rx_buff_generic()
2614 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); ixgbe_disable_rx_buff_generic()
2624 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); ixgbe_disable_rx_buff_generic()
2632 * @hw: pointer to hardware structure
2636 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) ixgbe_enable_rx_buff_generic() argument
2640 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); ixgbe_enable_rx_buff_generic()
2642 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); ixgbe_enable_rx_buff_generic()
2643 IXGBE_WRITE_FLUSH(hw); ixgbe_enable_rx_buff_generic()
2650 * @hw: pointer to hardware structure
2655 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) ixgbe_enable_rx_dma_generic() argument
2658 hw->mac.ops.enable_rx(hw); ixgbe_enable_rx_dma_generic()
2660 hw->mac.ops.disable_rx(hw); ixgbe_enable_rx_dma_generic()
2667 * @hw: pointer to hardware structure
2670 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) ixgbe_blink_led_start_generic() argument
2674 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_blink_led_start_generic()
2675 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_blink_led_start_generic()
2683 hw->mac.ops.check_link(hw, &speed, &link_up, false); ixgbe_blink_led_start_generic()
2686 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); ixgbe_blink_led_start_generic()
2693 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); ixgbe_blink_led_start_generic()
2697 IXGBE_WRITE_FLUSH(hw); ixgbe_blink_led_start_generic()
2704 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); ixgbe_blink_led_start_generic()
2705 IXGBE_WRITE_FLUSH(hw); ixgbe_blink_led_start_generic()
2712 * @hw: pointer to hardware structure
2715 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) ixgbe_blink_led_stop_generic() argument
2718 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_blink_led_stop_generic()
2722 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); ixgbe_blink_led_stop_generic()
2729 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); ixgbe_blink_led_stop_generic()
2736 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); ixgbe_blink_led_stop_generic()
2737 IXGBE_WRITE_FLUSH(hw); ixgbe_blink_led_stop_generic()
2744 * @hw: pointer to hardware structure
2751 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, ixgbe_get_san_mac_addr_offset() argument
2760 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, ixgbe_get_san_mac_addr_offset()
2763 hw_err(hw, "eeprom read at offset %d failed\n", ixgbe_get_san_mac_addr_offset()
2771 * @hw: pointer to hardware structure
2779 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) ixgbe_get_san_mac_addr_generic() argument
2789 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); ixgbe_get_san_mac_addr_generic()
2795 hw->mac.ops.set_lan_id(hw); ixgbe_get_san_mac_addr_generic()
2797 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : ixgbe_get_san_mac_addr_generic()
2800 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, ixgbe_get_san_mac_addr_generic()
2803 hw_err(hw, "eeprom read at offset %d failed\n", ixgbe_get_san_mac_addr_generic()
2824 * @hw: pointer to hardware structure
2829 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) ixgbe_get_pcie_msix_count_generic() argument
2835 switch (hw->mac.type) { ixgbe_get_pcie_msix_count_generic()
2851 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); ixgbe_get_pcie_msix_count_generic()
2852 if (ixgbe_removed(hw->hw_addr)) ixgbe_get_pcie_msix_count_generic()
2867 * @hw: pointer to hardware struct
2871 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ixgbe_clear_vmdq_generic() argument
2874 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_clear_vmdq_generic()
2878 hw_dbg(hw, "RAR index %d is out of range.\n", rar); ixgbe_clear_vmdq_generic()
2882 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); ixgbe_clear_vmdq_generic()
2883 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); ixgbe_clear_vmdq_generic()
2885 if (ixgbe_removed(hw->hw_addr)) ixgbe_clear_vmdq_generic()
2893 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); ixgbe_clear_vmdq_generic()
2897 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); ixgbe_clear_vmdq_generic()
2902 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); ixgbe_clear_vmdq_generic()
2905 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); ixgbe_clear_vmdq_generic()
2910 hw->mac.ops.clear_rar(hw, rar); ixgbe_clear_vmdq_generic()
2916 * @hw: pointer to hardware struct
2920 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ixgbe_set_vmdq_generic() argument
2923 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_set_vmdq_generic()
2927 hw_dbg(hw, "RAR index %d is out of range.\n", rar); ixgbe_set_vmdq_generic()
2932 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); ixgbe_set_vmdq_generic()
2934 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); ixgbe_set_vmdq_generic()
2936 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); ixgbe_set_vmdq_generic()
2938 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); ixgbe_set_vmdq_generic()
2947 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2950 * @hw: pointer to hardware struct
2953 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) ixgbe_set_vmdq_san_mac_generic() argument
2955 u32 rar = hw->mac.san_mac_rar_index; ixgbe_set_vmdq_san_mac_generic()
2958 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); ixgbe_set_vmdq_san_mac_generic()
2959 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); ixgbe_set_vmdq_san_mac_generic()
2961 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); ixgbe_set_vmdq_san_mac_generic()
2962 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); ixgbe_set_vmdq_san_mac_generic()
2970 * @hw: pointer to hardware structure
2972 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) ixgbe_init_uta_tables_generic() argument
2977 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); ixgbe_init_uta_tables_generic()
2984 * @hw: pointer to hardware structure
2990 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) ixgbe_find_vlvf_slot() argument
3005 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); ixgbe_find_vlvf_slot()
3021 hw_dbg(hw, "No space in VLVF.\n"); ixgbe_find_vlvf_slot()
3031 * @hw: pointer to hardware structure
3038 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, ixgbe_set_vfta_generic() argument
3067 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); ixgbe_set_vfta_generic()
3089 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); ixgbe_set_vfta_generic()
3093 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); ixgbe_set_vfta_generic()
3100 bits = IXGBE_READ_REG(hw, ixgbe_set_vfta_generic()
3103 IXGBE_WRITE_REG(hw, ixgbe_set_vfta_generic()
3107 bits = IXGBE_READ_REG(hw, ixgbe_set_vfta_generic()
3110 IXGBE_WRITE_REG(hw, ixgbe_set_vfta_generic()
3117 bits = IXGBE_READ_REG(hw, ixgbe_set_vfta_generic()
3120 IXGBE_WRITE_REG(hw, ixgbe_set_vfta_generic()
3123 bits |= IXGBE_READ_REG(hw, ixgbe_set_vfta_generic()
3126 bits = IXGBE_READ_REG(hw, ixgbe_set_vfta_generic()
3129 IXGBE_WRITE_REG(hw, ixgbe_set_vfta_generic()
3132 bits |= IXGBE_READ_REG(hw, ixgbe_set_vfta_generic()
3153 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), ixgbe_set_vfta_generic()
3162 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); ixgbe_set_vfta_generic()
3167 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); ixgbe_set_vfta_generic()
3174 * @hw: pointer to hardware structure
3178 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) ixgbe_clear_vfta_generic() argument
3182 for (offset = 0; offset < hw->mac.vft_size; offset++) ixgbe_clear_vfta_generic()
3183 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); ixgbe_clear_vfta_generic()
3186 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); ixgbe_clear_vfta_generic()
3187 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); ixgbe_clear_vfta_generic()
3188 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); ixgbe_clear_vfta_generic()
3196 * @hw: pointer to hardware structure
3203 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, ixgbe_check_mac_link_generic() argument
3210 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_check_mac_link_generic()
3212 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_check_mac_link_generic()
3215 hw_dbg(hw, "LINKS changed from %08X to %08X\n", ixgbe_check_mac_link_generic()
3228 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_check_mac_link_generic()
3239 if ((hw->mac.type >= ixgbe_mac_X550) && ixgbe_check_mac_link_generic()
3249 if ((hw->mac.type >= ixgbe_mac_X550) && ixgbe_check_mac_link_generic()
3265 * @hw: pointer to hardware structure
3272 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, ixgbe_get_wwn_prefix_generic() argument
3284 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) ixgbe_get_wwn_prefix_generic()
3293 if (hw->eeprom.ops.read(hw, offset, &caps)) ixgbe_get_wwn_prefix_generic()
3300 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) ixgbe_get_wwn_prefix_generic()
3301 hw_err(hw, "eeprom read at offset %d failed\n", offset); ixgbe_get_wwn_prefix_generic()
3304 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) ixgbe_get_wwn_prefix_generic()
3310 hw_err(hw, "eeprom read at offset %d failed\n", offset); ixgbe_get_wwn_prefix_generic()
3316 * @hw: pointer to hardware structure
3321 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) ixgbe_set_mac_anti_spoofing() argument
3328 if (hw->mac.type == ixgbe_mac_82598EB) ixgbe_set_mac_anti_spoofing()
3339 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); ixgbe_set_mac_anti_spoofing()
3346 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); ixgbe_set_mac_anti_spoofing()
3353 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); ixgbe_set_mac_anti_spoofing()
3358 * @hw: pointer to hardware structure
3363 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) ixgbe_set_vlan_anti_spoofing() argument
3369 if (hw->mac.type == ixgbe_mac_82598EB) ixgbe_set_vlan_anti_spoofing()
3372 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); ixgbe_set_vlan_anti_spoofing()
3377 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); ixgbe_set_vlan_anti_spoofing()
3382 * @hw: pointer to hardware structure
3388 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) ixgbe_get_device_caps_generic() argument
3390 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); ixgbe_get_device_caps_generic()
3397 * @hw: pointer to hardware structure
3402 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, ixgbe_set_rxpba_generic() argument
3407 u32 pbsize = hw->mac.rx_pb_size; ixgbe_set_rxpba_generic()
3429 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); ixgbe_set_rxpba_generic()
3435 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); ixgbe_set_rxpba_generic()
3449 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); ixgbe_set_rxpba_generic()
3450 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); ixgbe_set_rxpba_generic()
3455 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); ixgbe_set_rxpba_generic()
3456 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); ixgbe_set_rxpba_generic()
3457 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); ixgbe_set_rxpba_generic()
3485 * @hw: pointer to the HW structure
3500 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, ixgbe_host_interface_command() argument
3509 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); ixgbe_host_interface_command()
3514 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); ixgbe_host_interface_command()
3515 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); ixgbe_host_interface_command()
3518 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); ixgbe_host_interface_command()
3520 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); ixgbe_host_interface_command()
3526 hw_dbg(hw, "Buffer length failure, not aligned to dword"); ixgbe_host_interface_command()
3537 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, ixgbe_host_interface_command()
3541 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); ixgbe_host_interface_command()
3544 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); ixgbe_host_interface_command()
3552 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { ixgbe_host_interface_command()
3553 hw_dbg(hw, "Command has failed with no status valid.\n"); ixgbe_host_interface_command()
3565 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); ixgbe_host_interface_command()
3575 hw_dbg(hw, "Buffer not large enough for reply message.\n"); ixgbe_host_interface_command()
3584 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); ixgbe_host_interface_command()
3593 * @hw: pointer to the HW structure
3604 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, ixgbe_set_fw_drv_ver_generic() argument
3611 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)) ixgbe_set_fw_drv_ver_generic()
3617 fw_cmd.port_num = (u8)hw->bus.func; ixgbe_set_fw_drv_ver_generic()
3629 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, ixgbe_set_fw_drv_ver_generic()
3645 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); ixgbe_set_fw_drv_ver_generic()
3651 * @hw: pointer to the hardware structure
3657 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) ixgbe_clear_tx_pending() argument
3666 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) ixgbe_clear_tx_pending()
3674 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); ixgbe_clear_tx_pending()
3675 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); ixgbe_clear_tx_pending()
3678 IXGBE_WRITE_FLUSH(hw); ixgbe_clear_tx_pending()
3684 poll = ixgbe_pcie_timeout_poll(hw); ixgbe_clear_tx_pending()
3687 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); ixgbe_clear_tx_pending()
3688 if (ixgbe_removed(hw->hw_addr)) ixgbe_clear_tx_pending()
3695 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); ixgbe_clear_tx_pending()
3696 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, ixgbe_clear_tx_pending()
3700 IXGBE_WRITE_FLUSH(hw); ixgbe_clear_tx_pending()
3704 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); ixgbe_clear_tx_pending()
3705 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); ixgbe_clear_tx_pending()
3723 * @hw: pointer to hardware structure
3729 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, ixgbe_get_ets_data() argument
3734 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); ixgbe_get_ets_data()
3741 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); ixgbe_get_ets_data()
3753 * @hw: pointer to hardware structure
3757 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) ixgbe_get_thermal_sensor_data_generic() argument
3765 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; ixgbe_get_thermal_sensor_data_generic()
3768 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) ixgbe_get_thermal_sensor_data_generic()
3771 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); ixgbe_get_thermal_sensor_data_generic()
3783 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), ixgbe_get_thermal_sensor_data_generic()
3794 status = hw->phy.ops.read_i2c_byte(hw, ixgbe_get_thermal_sensor_data_generic()
3808 * @hw: pointer to hardware structure
3813 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) ixgbe_init_thermal_sensor_thresh_generic() argument
3823 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; ixgbe_init_thermal_sensor_thresh_generic()
3828 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) ixgbe_init_thermal_sensor_thresh_generic()
3831 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); ixgbe_init_thermal_sensor_thresh_generic()
3845 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { ixgbe_init_thermal_sensor_thresh_generic()
3846 hw_err(hw, "eeprom read at offset %d failed\n", ixgbe_init_thermal_sensor_thresh_generic()
3856 hw->phy.ops.write_i2c_byte(hw, ixgbe_init_thermal_sensor_thresh_generic()
3871 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) ixgbe_disable_rx_generic() argument
3875 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_disable_rx_generic()
3877 if (hw->mac.type != ixgbe_mac_82598EB) { ixgbe_disable_rx_generic()
3880 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); ixgbe_disable_rx_generic()
3883 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); ixgbe_disable_rx_generic()
3884 hw->mac.set_lben = true; ixgbe_disable_rx_generic()
3886 hw->mac.set_lben = false; ixgbe_disable_rx_generic()
3890 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); ixgbe_disable_rx_generic()
3894 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) ixgbe_enable_rx_generic() argument
3898 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_enable_rx_generic()
3899 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); ixgbe_enable_rx_generic()
3901 if (hw->mac.type != ixgbe_mac_82598EB) { ixgbe_enable_rx_generic()
3902 if (hw->mac.set_lben) { ixgbe_enable_rx_generic()
3905 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); ixgbe_enable_rx_generic()
3907 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); ixgbe_enable_rx_generic()
3908 hw->mac.set_lben = false; ixgbe_enable_rx_generic()
3914 * @hw: pointer to hardware structure
3916 bool ixgbe_mng_present(struct ixgbe_hw *hw) ixgbe_mng_present() argument
3920 if (hw->mac.type < ixgbe_mac_82599EB) ixgbe_mng_present()
3923 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); ixgbe_mng_present()
3930 * @hw: pointer to hardware structure
3936 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, ixgbe_setup_mac_link_multispeed_fiber() argument
3948 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); ixgbe_setup_mac_link_multispeed_fiber()
3962 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, ixgbe_setup_mac_link_multispeed_fiber()
3971 switch (hw->phy.media_type) { ixgbe_setup_mac_link_multispeed_fiber()
3973 hw->mac.ops.set_rate_select_speed(hw, ixgbe_setup_mac_link_multispeed_fiber()
3980 hw_dbg(hw, "Unexpected media type\n"); ixgbe_setup_mac_link_multispeed_fiber()
3987 status = hw->mac.ops.setup_mac_link(hw, ixgbe_setup_mac_link_multispeed_fiber()
3994 if (hw->mac.ops.flap_tx_laser) ixgbe_setup_mac_link_multispeed_fiber()
3995 hw->mac.ops.flap_tx_laser(hw); ixgbe_setup_mac_link_multispeed_fiber()
4006 status = hw->mac.ops.check_link(hw, &link_speed, ixgbe_setup_mac_link_multispeed_fiber()
4022 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, ixgbe_setup_mac_link_multispeed_fiber()
4031 switch (hw->phy.media_type) { ixgbe_setup_mac_link_multispeed_fiber()
4033 hw->mac.ops.set_rate_select_speed(hw, ixgbe_setup_mac_link_multispeed_fiber()
4040 hw_dbg(hw, "Unexpected media type\n"); ixgbe_setup_mac_link_multispeed_fiber()
4047 status = hw->mac.ops.setup_mac_link(hw, ixgbe_setup_mac_link_multispeed_fiber()
4054 if (hw->mac.ops.flap_tx_laser) ixgbe_setup_mac_link_multispeed_fiber()
4055 hw->mac.ops.flap_tx_laser(hw); ixgbe_setup_mac_link_multispeed_fiber()
4061 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, ixgbe_setup_mac_link_multispeed_fiber()
4075 status = ixgbe_setup_mac_link_multispeed_fiber(hw, ixgbe_setup_mac_link_multispeed_fiber()
4081 hw->phy.autoneg_advertised = 0; ixgbe_setup_mac_link_multispeed_fiber()
4084 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; ixgbe_setup_mac_link_multispeed_fiber()
4087 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; ixgbe_setup_mac_link_multispeed_fiber()
4094 * @hw: pointer to hardware structure
4099 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, ixgbe_set_soft_rate_select_speed() argument
4114 hw_dbg(hw, "Invalid fixed module speed\n"); ixgbe_set_soft_rate_select_speed()
4119 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, ixgbe_set_soft_rate_select_speed()
4123 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); ixgbe_set_soft_rate_select_speed()
4129 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, ixgbe_set_soft_rate_select_speed()
4133 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); ixgbe_set_soft_rate_select_speed()
H A Dixgbe_82598.c43 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
51 * @hw: pointer to the HW structure
59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) ixgbe_set_pcie_completion_timeout() argument
61 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); ixgbe_set_pcie_completion_timeout()
64 if (ixgbe_removed(hw->hw_addr)) ixgbe_set_pcie_completion_timeout()
85 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); ixgbe_set_pcie_completion_timeout()
87 ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); ixgbe_set_pcie_completion_timeout()
91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); ixgbe_set_pcie_completion_timeout()
94 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) ixgbe_get_invariants_82598() argument
96 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_get_invariants_82598()
99 ixgbe_identify_phy_generic(hw); ixgbe_get_invariants_82598()
107 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); ixgbe_get_invariants_82598()
114 * @hw: pointer to hardware structure
121 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) ixgbe_init_phy_ops_82598() argument
123 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_init_phy_ops_82598()
124 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_init_phy_ops_82598()
129 phy->ops.identify(hw); ixgbe_init_phy_ops_82598()
132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { ixgbe_init_phy_ops_82598()
138 switch (hw->phy.type) { ixgbe_init_phy_ops_82598()
149 ret_val = phy->ops.identify_sfp(hw); ixgbe_init_phy_ops_82598()
152 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) ixgbe_init_phy_ops_82598()
156 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, ixgbe_init_phy_ops_82598()
171 * @hw: pointer to hardware structure
178 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) ixgbe_start_hw_82598() argument
186 ret_val = ixgbe_start_hw_generic(hw); ixgbe_start_hw_82598()
190 for (i = 0; ((i < hw->mac.max_tx_queues) && ixgbe_start_hw_82598()
192 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); ixgbe_start_hw_82598()
194 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); ixgbe_start_hw_82598()
197 for (i = 0; ((i < hw->mac.max_rx_queues) && ixgbe_start_hw_82598()
199 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); ixgbe_start_hw_82598()
202 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); ixgbe_start_hw_82598()
209 ixgbe_set_pcie_completion_timeout(hw); ixgbe_start_hw_82598()
216 * @hw: pointer to hardware structure
222 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, ixgbe_get_link_capabilities_82598() argument
233 if (hw->mac.orig_link_settings_stored) ixgbe_get_link_capabilities_82598()
234 autoc = hw->mac.orig_autoc; ixgbe_get_link_capabilities_82598()
236 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_get_link_capabilities_82598()
273 * @hw: pointer to hardware structure
277 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) ixgbe_get_media_type_82598() argument
280 switch (hw->phy.type) { ixgbe_get_media_type_82598()
290 switch (hw->device_id) { ixgbe_get_media_type_82598()
319 * @hw: pointer to hardware structure
323 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) ixgbe_fc_enable_82598() argument
334 if (!hw->fc.pause_time) ixgbe_fc_enable_82598()
339 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && ixgbe_fc_enable_82598()
340 hw->fc.high_water[i]) { ixgbe_fc_enable_82598()
341 if (!hw->fc.low_water[i] || ixgbe_fc_enable_82598()
342 hw->fc.low_water[i] >= hw->fc.high_water[i]) { ixgbe_fc_enable_82598()
343 hw_dbg(hw, "Invalid water mark configuration\n"); ixgbe_fc_enable_82598()
354 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ixgbe_fc_enable_82598()
356 switch (hw->fc.requested_mode) { ixgbe_fc_enable_82598()
358 hw->fc.requested_mode = ixgbe_fc_tx_pause; ixgbe_fc_enable_82598()
361 hw->fc.requested_mode = ixgbe_fc_none; ixgbe_fc_enable_82598()
370 ixgbe_fc_autoneg(hw); ixgbe_fc_enable_82598()
373 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); ixgbe_fc_enable_82598()
376 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); ixgbe_fc_enable_82598()
389 switch (hw->fc.current_mode) { ixgbe_fc_enable_82598()
420 hw_dbg(hw, "Flow control param set incorrectly\n"); ixgbe_fc_enable_82598()
426 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); ixgbe_fc_enable_82598()
427 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); ixgbe_fc_enable_82598()
431 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && ixgbe_fc_enable_82598()
432 hw->fc.high_water[i]) { ixgbe_fc_enable_82598()
433 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; ixgbe_fc_enable_82598()
434 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; ixgbe_fc_enable_82598()
435 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); ixgbe_fc_enable_82598()
436 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); ixgbe_fc_enable_82598()
438 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); ixgbe_fc_enable_82598()
439 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); ixgbe_fc_enable_82598()
445 reg = hw->fc.pause_time * 0x00010001; ixgbe_fc_enable_82598()
447 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); ixgbe_fc_enable_82598()
450 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); ixgbe_fc_enable_82598()
457 * @hw: pointer to hardware structure
462 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, ixgbe_start_mac_link_82598() argument
471 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_start_mac_link_82598()
473 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); ixgbe_start_mac_link_82598()
483 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_start_mac_link_82598()
490 hw_dbg(hw, "Autonegotiation did not complete.\n"); ixgbe_start_mac_link_82598()
503 * @hw: pointer to hardware structure
508 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) ixgbe_validate_link_ready() argument
513 if (hw->device_id != IXGBE_DEV_ID_82598AT2) ixgbe_validate_link_ready()
518 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); ixgbe_validate_link_ready()
528 hw_dbg(hw, "Link was indicated but link is down\n"); ixgbe_validate_link_ready()
537 * @hw: pointer to hardware structure
544 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_check_mac_link_82598() argument
558 if (hw->phy.type == ixgbe_phy_nl) { ixgbe_check_mac_link_82598()
559 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); ixgbe_check_mac_link_82598()
560 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); ixgbe_check_mac_link_82598()
561 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, ixgbe_check_mac_link_82598()
573 hw->phy.ops.read_reg(hw, 0xC79F, ixgbe_check_mac_link_82598()
576 hw->phy.ops.read_reg(hw, 0xC00C, ixgbe_check_mac_link_82598()
591 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_check_mac_link_82598()
601 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_check_mac_link_82598()
615 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && ixgbe_check_mac_link_82598()
616 (ixgbe_validate_link_ready(hw) != 0)) ixgbe_check_mac_link_82598()
624 * @hw: pointer to hardware structure
630 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, ixgbe_setup_mac_link_82598() argument
636 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_setup_mac_link_82598()
641 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); ixgbe_setup_mac_link_82598()
656 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); ixgbe_setup_mac_link_82598()
663 return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); ixgbe_setup_mac_link_82598()
669 * @hw: pointer to hardware structure
675 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, ixgbe_setup_copper_link_82598() argument
682 status = hw->phy.ops.setup_link_speed(hw, speed, ixgbe_setup_copper_link_82598()
685 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); ixgbe_setup_copper_link_82598()
692 * @hw: pointer to hardware structure
698 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) ixgbe_reset_hw_82598() argument
709 status = hw->mac.ops.stop_adapter(hw); ixgbe_reset_hw_82598()
718 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); ixgbe_reset_hw_82598()
721 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, ixgbe_reset_hw_82598()
724 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, ixgbe_reset_hw_82598()
727 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, ixgbe_reset_hw_82598()
730 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, ixgbe_reset_hw_82598()
733 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, ixgbe_reset_hw_82598()
736 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, ixgbe_reset_hw_82598()
739 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, ixgbe_reset_hw_82598()
742 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, ixgbe_reset_hw_82598()
747 if (hw->phy.reset_disable == false) { ixgbe_reset_hw_82598()
751 phy_status = hw->phy.ops.init(hw); ixgbe_reset_hw_82598()
757 hw->phy.ops.reset(hw); ixgbe_reset_hw_82598()
765 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; ixgbe_reset_hw_82598()
766 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); ixgbe_reset_hw_82598()
767 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_hw_82598()
772 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_82598()
778 hw_dbg(hw, "Reset polling failed to complete.\n"); ixgbe_reset_hw_82598()
788 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { ixgbe_reset_hw_82598()
789 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; ixgbe_reset_hw_82598()
793 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); ixgbe_reset_hw_82598()
795 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); ixgbe_reset_hw_82598()
802 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_reset_hw_82598()
803 if (hw->mac.orig_link_settings_stored == false) { ixgbe_reset_hw_82598()
804 hw->mac.orig_autoc = autoc; ixgbe_reset_hw_82598()
805 hw->mac.orig_link_settings_stored = true; ixgbe_reset_hw_82598()
806 } else if (autoc != hw->mac.orig_autoc) { ixgbe_reset_hw_82598()
807 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); ixgbe_reset_hw_82598()
811 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); ixgbe_reset_hw_82598()
817 hw->mac.ops.init_rx_addrs(hw); ixgbe_reset_hw_82598()
827 * @hw: pointer to hardware struct
831 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ixgbe_set_vmdq_82598() argument
834 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_set_vmdq_82598()
838 hw_dbg(hw, "RAR index %d is out of range.\n", rar); ixgbe_set_vmdq_82598()
842 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); ixgbe_set_vmdq_82598()
845 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); ixgbe_set_vmdq_82598()
851 * @hw: pointer to hardware struct
855 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) ixgbe_clear_vmdq_82598() argument
858 u32 rar_entries = hw->mac.num_rar_entries; ixgbe_clear_vmdq_82598()
863 hw_dbg(hw, "RAR index %d is out of range.\n", rar); ixgbe_clear_vmdq_82598()
867 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); ixgbe_clear_vmdq_82598()
870 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); ixgbe_clear_vmdq_82598()
878 * @hw: pointer to hardware structure
885 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, ixgbe_set_vfta_82598() argument
904 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); ixgbe_set_vfta_82598()
907 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); ixgbe_set_vfta_82598()
912 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); ixgbe_set_vfta_82598()
919 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); ixgbe_set_vfta_82598()
926 * @hw: pointer to hardware structure
930 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) ixgbe_clear_vfta_82598() argument
935 for (offset = 0; offset < hw->mac.vft_size; offset++) ixgbe_clear_vfta_82598()
936 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); ixgbe_clear_vfta_82598()
939 for (offset = 0; offset < hw->mac.vft_size; offset++) ixgbe_clear_vfta_82598()
940 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), ixgbe_clear_vfta_82598()
948 * @hw: pointer to hardware structure
954 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) ixgbe_read_analog_reg8_82598() argument
958 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, ixgbe_read_analog_reg8_82598()
960 IXGBE_WRITE_FLUSH(hw); ixgbe_read_analog_reg8_82598()
962 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); ixgbe_read_analog_reg8_82598()
970 * @hw: pointer to hardware structure
976 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) ixgbe_write_analog_reg8_82598() argument
981 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); ixgbe_write_analog_reg8_82598()
982 IXGBE_WRITE_FLUSH(hw); ixgbe_write_analog_reg8_82598()
990 * @hw: pointer to hardware structure
997 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, ixgbe_read_i2c_phy_82598() argument
1007 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) ixgbe_read_i2c_phy_82598()
1012 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) ixgbe_read_i2c_phy_82598()
1015 if (hw->phy.type == ixgbe_phy_nl) { ixgbe_read_i2c_phy_82598()
1023 hw->phy.ops.write_reg_mdi(hw, ixgbe_read_i2c_phy_82598()
1030 hw->phy.ops.read_reg_mdi(hw, ixgbe_read_i2c_phy_82598()
1041 hw_dbg(hw, "EEPROM read did not pass.\n"); ixgbe_read_i2c_phy_82598()
1047 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, ixgbe_read_i2c_phy_82598()
1056 hw->mac.ops.release_swfw_sync(hw, gssr); ixgbe_read_i2c_phy_82598()
1062 * @hw: pointer to hardware structure
1068 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_eeprom_82598() argument
1071 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, ixgbe_read_i2c_eeprom_82598()
1077 * @hw: pointer to hardware structure
1083 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, ixgbe_read_i2c_sff8472_82598() argument
1086 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, ixgbe_read_i2c_sff8472_82598()
1093 * @hw: pointer to the HW structure
1098 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) ixgbe_set_lan_id_multi_port_pcie_82598() argument
1100 struct ixgbe_bus_info *bus = &hw->bus; ixgbe_set_lan_id_multi_port_pcie_82598()
1104 ixgbe_set_lan_id_multi_port_pcie(hw); ixgbe_set_lan_id_multi_port_pcie_82598()
1107 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); ixgbe_set_lan_id_multi_port_pcie_82598()
1110 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); ixgbe_set_lan_id_multi_port_pcie_82598()
1124 * @hw: pointer to hardware structure
1129 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, ixgbe_set_rxpba_82598() argument
1144 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); ixgbe_set_rxpba_82598()
1152 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); ixgbe_set_rxpba_82598()
1158 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); ixgbe_set_rxpba_82598()
H A Dixgbe_dcb_82598.c36 * @hw: pointer to hardware structure
41 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, ixgbe_dcb_config_rx_arbiter_82598() argument
51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; ixgbe_dcb_config_rx_arbiter_82598()
52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); ixgbe_dcb_config_rx_arbiter_82598()
54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); ixgbe_dcb_config_rx_arbiter_82598()
62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); ixgbe_dcb_config_rx_arbiter_82598()
74 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); ixgbe_dcb_config_rx_arbiter_82598()
77 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); ixgbe_dcb_config_rx_arbiter_82598()
81 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); ixgbe_dcb_config_rx_arbiter_82598()
83 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_dcb_config_rx_arbiter_82598()
86 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); ixgbe_dcb_config_rx_arbiter_82598()
93 * @hw: pointer to hardware structure
98 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, ixgbe_dcb_config_tx_desc_arbiter_82598() argument
107 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); ixgbe_dcb_config_tx_desc_arbiter_82598()
116 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); ixgbe_dcb_config_tx_desc_arbiter_82598()
131 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); ixgbe_dcb_config_tx_desc_arbiter_82598()
139 * @hw: pointer to hardware structure
144 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, ixgbe_dcb_config_tx_data_arbiter_82598() argument
153 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); ixgbe_dcb_config_tx_data_arbiter_82598()
159 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); ixgbe_dcb_config_tx_data_arbiter_82598()
173 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); ixgbe_dcb_config_tx_data_arbiter_82598()
177 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); ixgbe_dcb_config_tx_data_arbiter_82598()
179 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); ixgbe_dcb_config_tx_data_arbiter_82598()
186 * @hw: pointer to hardware structure
191 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) ixgbe_dcb_config_pfc_82598() argument
197 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); ixgbe_dcb_config_pfc_82598()
200 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); ixgbe_dcb_config_pfc_82598()
203 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); ixgbe_dcb_config_pfc_82598()
209 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); ixgbe_dcb_config_pfc_82598()
214 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); ixgbe_dcb_config_pfc_82598()
215 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); ixgbe_dcb_config_pfc_82598()
219 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; ixgbe_dcb_config_pfc_82598()
220 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; ixgbe_dcb_config_pfc_82598()
221 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); ixgbe_dcb_config_pfc_82598()
222 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); ixgbe_dcb_config_pfc_82598()
226 reg = hw->fc.pause_time * 0x00010001; ixgbe_dcb_config_pfc_82598()
228 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); ixgbe_dcb_config_pfc_82598()
231 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); ixgbe_dcb_config_pfc_82598()
239 * @hw: pointer to hardware structure
244 static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) ixgbe_dcb_config_tc_stats_82598() argument
252 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); ixgbe_dcb_config_tc_stats_82598()
254 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); ixgbe_dcb_config_tc_stats_82598()
255 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); ixgbe_dcb_config_tc_stats_82598()
257 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); ixgbe_dcb_config_tc_stats_82598()
261 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); ixgbe_dcb_config_tc_stats_82598()
263 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); ixgbe_dcb_config_tc_stats_82598()
271 * @hw: pointer to hardware structure
276 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, ixgbe_dcb_hw_config_82598() argument
279 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type); ixgbe_dcb_hw_config_82598()
280 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, ixgbe_dcb_hw_config_82598()
282 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, ixgbe_dcb_hw_config_82598()
284 ixgbe_dcb_config_pfc_82598(hw, pfc_en); ixgbe_dcb_hw_config_82598()
285 ixgbe_dcb_config_tc_stats_82598(hw); ixgbe_dcb_hw_config_82598()
H A Dixgbe_x540.c44 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
45 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) ixgbe_get_media_type_X540() argument
54 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) ixgbe_get_invariants_X540() argument
56 struct ixgbe_mac_info *mac = &hw->mac; ixgbe_get_invariants_X540()
57 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_get_invariants_X540()
60 if (!ixgbe_mng_present(hw)) ixgbe_get_invariants_X540()
69 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); ixgbe_get_invariants_X540()
76 * @hw: pointer to hardware structure
80 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, ixgbe_setup_mac_link_X540() argument
83 return hw->phy.ops.setup_link_speed(hw, speed, ixgbe_setup_mac_link_X540()
89 * @hw: pointer to hardware structure
95 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) ixgbe_reset_hw_X540() argument
101 status = hw->mac.ops.stop_adapter(hw); ixgbe_reset_hw_X540()
106 ixgbe_clear_tx_pending(hw); ixgbe_reset_hw_X540()
110 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_X540()
111 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); ixgbe_reset_hw_X540()
112 IXGBE_WRITE_FLUSH(hw); ixgbe_reset_hw_X540()
117 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_reset_hw_X540()
124 hw_dbg(hw, "Reset polling failed to complete.\n"); ixgbe_reset_hw_X540()
133 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { ixgbe_reset_hw_X540()
134 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; ixgbe_reset_hw_X540()
139 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); ixgbe_reset_hw_X540()
142 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); ixgbe_reset_hw_X540()
149 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; ixgbe_reset_hw_X540()
150 hw->mac.ops.init_rx_addrs(hw); ixgbe_reset_hw_X540()
153 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); ixgbe_reset_hw_X540()
156 if (is_valid_ether_addr(hw->mac.san_addr)) { ixgbe_reset_hw_X540()
157 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, ixgbe_reset_hw_X540()
158 hw->mac.san_addr, 0, IXGBE_RAH_AV); ixgbe_reset_hw_X540()
161 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; ixgbe_reset_hw_X540()
164 hw->mac.num_rar_entries--; ixgbe_reset_hw_X540()
168 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, ixgbe_reset_hw_X540()
169 &hw->mac.wwpn_prefix); ixgbe_reset_hw_X540()
176 * @hw: pointer to hardware structure
182 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) ixgbe_start_hw_X540() argument
186 ret_val = ixgbe_start_hw_generic(hw); ixgbe_start_hw_X540()
190 return ixgbe_start_hw_gen2(hw); ixgbe_start_hw_X540()
195 * @hw: pointer to hardware structure
200 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) ixgbe_init_eeprom_params_X540() argument
202 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; ixgbe_init_eeprom_params_X540()
210 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_init_eeprom_params_X540()
216 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", ixgbe_init_eeprom_params_X540()
225 * @hw: pointer to hardware structure
231 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) ixgbe_read_eerd_X540() argument
235 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) ixgbe_read_eerd_X540()
238 status = ixgbe_read_eerd_generic(hw, offset, data); ixgbe_read_eerd_X540()
240 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_read_eerd_X540()
246 * @hw: pointer to hardware structure
253 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, ixgbe_read_eerd_buffer_X540() argument
258 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) ixgbe_read_eerd_buffer_X540()
261 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data); ixgbe_read_eerd_buffer_X540()
263 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_read_eerd_buffer_X540()
269 * @hw: pointer to hardware structure
275 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) ixgbe_write_eewr_X540() argument
279 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) ixgbe_write_eewr_X540()
282 status = ixgbe_write_eewr_generic(hw, offset, data); ixgbe_write_eewr_X540()
284 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_write_eewr_X540()
290 * @hw: pointer to hardware structure
297 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, ixgbe_write_eewr_buffer_X540() argument
302 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) ixgbe_write_eewr_buffer_X540()
305 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data); ixgbe_write_eewr_buffer_X540()
307 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_write_eewr_buffer_X540()
317 * @hw: pointer to hardware structure
319 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) ixgbe_calc_eeprom_checksum_X540() argument
331 * Do not use hw->eeprom.ops.read because we do not want to take ixgbe_calc_eeprom_checksum_X540()
338 if (ixgbe_read_eerd_generic(hw, i, &word)) { ixgbe_calc_eeprom_checksum_X540()
339 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_X540()
353 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { ixgbe_calc_eeprom_checksum_X540()
354 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_X540()
360 pointer >= hw->eeprom.word_size) ixgbe_calc_eeprom_checksum_X540()
363 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { ixgbe_calc_eeprom_checksum_X540()
364 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_X540()
371 (pointer + length) >= hw->eeprom.word_size) ixgbe_calc_eeprom_checksum_X540()
375 if (ixgbe_read_eerd_generic(hw, j, &word)) { ixgbe_calc_eeprom_checksum_X540()
376 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_calc_eeprom_checksum_X540()
390 * @hw: pointer to hardware structure
396 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, ixgbe_validate_eeprom_checksum_X540() argument
407 status = hw->eeprom.ops.read(hw, 0, &checksum); ixgbe_validate_eeprom_checksum_X540()
409 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_validate_eeprom_checksum_X540()
413 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) ixgbe_validate_eeprom_checksum_X540()
416 status = hw->eeprom.ops.calc_checksum(hw); ixgbe_validate_eeprom_checksum_X540()
422 /* Do not use hw->eeprom.ops.read because we do not want to take ixgbe_validate_eeprom_checksum_X540()
425 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, ixgbe_validate_eeprom_checksum_X540()
434 hw_dbg(hw, "Invalid EEPROM checksum"); ixgbe_validate_eeprom_checksum_X540()
443 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_validate_eeprom_checksum_X540()
450 * @hw: pointer to hardware structure
456 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) ixgbe_update_eeprom_checksum_X540() argument
465 status = hw->eeprom.ops.read(hw, 0, &checksum); ixgbe_update_eeprom_checksum_X540()
467 hw_dbg(hw, "EEPROM read failed\n"); ixgbe_update_eeprom_checksum_X540()
471 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) ixgbe_update_eeprom_checksum_X540()
474 status = hw->eeprom.ops.calc_checksum(hw); ixgbe_update_eeprom_checksum_X540()
480 /* Do not use hw->eeprom.ops.write because we do not want to ixgbe_update_eeprom_checksum_X540()
483 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); ixgbe_update_eeprom_checksum_X540()
487 status = ixgbe_update_flash_X540(hw); ixgbe_update_eeprom_checksum_X540()
490 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); ixgbe_update_eeprom_checksum_X540()
496 * @hw: pointer to hardware structure
501 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) ixgbe_update_flash_X540() argument
506 status = ixgbe_poll_flash_update_done_X540(hw); ixgbe_update_flash_X540()
508 hw_dbg(hw, "Flash update time out\n"); ixgbe_update_flash_X540()
512 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP; ixgbe_update_flash_X540()
513 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup); ixgbe_update_flash_X540()
515 status = ixgbe_poll_flash_update_done_X540(hw); ixgbe_update_flash_X540()
517 hw_dbg(hw, "Flash update complete\n"); ixgbe_update_flash_X540()
519 hw_dbg(hw, "Flash update time out\n"); ixgbe_update_flash_X540()
521 if (hw->revision_id == 0) { ixgbe_update_flash_X540()
522 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_update_flash_X540()
526 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup); ixgbe_update_flash_X540()
529 status = ixgbe_poll_flash_update_done_X540(hw); ixgbe_update_flash_X540()
531 hw_dbg(hw, "Flash update complete\n"); ixgbe_update_flash_X540()
533 hw_dbg(hw, "Flash update time out\n"); ixgbe_update_flash_X540()
541 * @hw: pointer to hardware structure
546 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) ixgbe_poll_flash_update_done_X540() argument
552 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_poll_flash_update_done_X540()
562 * @hw: pointer to hardware structure
568 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) ixgbe_acquire_swfw_sync_X540() argument
591 if (ixgbe_get_swfw_sync_semaphore(hw)) ixgbe_acquire_swfw_sync_X540()
594 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); ixgbe_acquire_swfw_sync_X540()
597 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); ixgbe_acquire_swfw_sync_X540()
598 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_acquire_swfw_sync_X540()
606 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_acquire_swfw_sync_X540()
612 hw_dbg(hw, "Failed to get SW only semaphore\n"); ixgbe_acquire_swfw_sync_X540()
621 if (ixgbe_get_swfw_sync_semaphore(hw)) ixgbe_acquire_swfw_sync_X540()
623 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); ixgbe_acquire_swfw_sync_X540()
626 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); ixgbe_acquire_swfw_sync_X540()
627 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_acquire_swfw_sync_X540()
642 ixgbe_release_swfw_sync_X540(hw, rmask); ixgbe_acquire_swfw_sync_X540()
643 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_acquire_swfw_sync_X540()
646 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_acquire_swfw_sync_X540()
653 * @hw: pointer to hardware structure
659 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) ixgbe_release_swfw_sync_X540() argument
666 ixgbe_get_swfw_sync_semaphore(hw); ixgbe_release_swfw_sync_X540()
668 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); ixgbe_release_swfw_sync_X540()
670 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); ixgbe_release_swfw_sync_X540()
672 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_release_swfw_sync_X540()
678 * @hw: pointer to hardware structure
682 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) ixgbe_get_swfw_sync_semaphore() argument
693 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_get_swfw_sync_semaphore()
700 hw_dbg(hw, ixgbe_get_swfw_sync_semaphore()
707 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); ixgbe_get_swfw_sync_semaphore()
717 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n"); ixgbe_get_swfw_sync_semaphore()
718 ixgbe_release_swfw_sync_semaphore(hw); ixgbe_get_swfw_sync_semaphore()
724 * @hw: pointer to hardware structure
728 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) ixgbe_release_swfw_sync_semaphore() argument
734 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); ixgbe_release_swfw_sync_semaphore()
736 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm); ixgbe_release_swfw_sync_semaphore()
738 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); ixgbe_release_swfw_sync_semaphore()
740 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); ixgbe_release_swfw_sync_semaphore()
742 IXGBE_WRITE_FLUSH(hw); ixgbe_release_swfw_sync_semaphore()
747 * @hw: pointer to hardware structure
753 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) ixgbe_blink_led_start_X540() argument
765 hw->mac.ops.check_link(hw, &speed, &link_up, false); ixgbe_blink_led_start_X540()
767 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); ixgbe_blink_led_start_X540()
769 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); ixgbe_blink_led_start_X540()
772 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_blink_led_start_X540()
775 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); ixgbe_blink_led_start_X540()
776 IXGBE_WRITE_FLUSH(hw); ixgbe_blink_led_start_X540()
783 * @hw: pointer to hardware structure
789 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) ixgbe_blink_led_stop_X540() argument
795 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_blink_led_stop_X540()
799 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); ixgbe_blink_led_stop_X540()
802 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); ixgbe_blink_led_stop_X540()
804 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); ixgbe_blink_led_stop_X540()
805 IXGBE_WRITE_FLUSH(hw); ixgbe_blink_led_stop_X540()
H A Dixgbe_mbx.c36 * @hw: pointer to the HW structure
43 s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) ixgbe_read_mbx() argument
45 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_read_mbx()
54 return mbx->ops.read(hw, msg, size, mbx_id); ixgbe_read_mbx()
59 * @hw: pointer to the HW structure
66 s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) ixgbe_write_mbx() argument
68 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_write_mbx()
76 return mbx->ops.write(hw, msg, size, mbx_id); ixgbe_write_mbx()
81 * @hw: pointer to the HW structure
86 s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id) ixgbe_check_for_msg() argument
88 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_check_for_msg()
93 return mbx->ops.check_for_msg(hw, mbx_id); ixgbe_check_for_msg()
98 * @hw: pointer to the HW structure
103 s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id) ixgbe_check_for_ack() argument
105 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_check_for_ack()
110 return mbx->ops.check_for_ack(hw, mbx_id); ixgbe_check_for_ack()
115 * @hw: pointer to the HW structure
120 s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id) ixgbe_check_for_rst() argument
122 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_check_for_rst()
127 return mbx->ops.check_for_rst(hw, mbx_id); ixgbe_check_for_rst()
132 * @hw: pointer to the HW structure
137 static s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id) ixgbe_poll_for_msg() argument
139 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_poll_for_msg()
145 while (mbx->ops.check_for_msg(hw, mbx_id)) { ixgbe_poll_for_msg()
157 * @hw: pointer to the HW structure
162 static s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id) ixgbe_poll_for_ack() argument
164 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_poll_for_ack()
170 while (mbx->ops.check_for_ack(hw, mbx_id)) { ixgbe_poll_for_ack()
182 * @hw: pointer to the HW structure
190 static s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, ixgbe_read_posted_mbx() argument
193 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_read_posted_mbx()
199 ret_val = ixgbe_poll_for_msg(hw, mbx_id); ixgbe_read_posted_mbx()
204 return mbx->ops.read(hw, msg, size, mbx_id); ixgbe_read_posted_mbx()
209 * @hw: pointer to the HW structure
217 static s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, ixgbe_write_posted_mbx() argument
220 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_write_posted_mbx()
228 ret_val = mbx->ops.write(hw, msg, size, mbx_id); ixgbe_write_posted_mbx()
233 return ixgbe_poll_for_ack(hw, mbx_id); ixgbe_write_posted_mbx()
236 static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) ixgbe_check_for_bit_pf() argument
238 u32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index)); ixgbe_check_for_bit_pf()
241 IXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask); ixgbe_check_for_bit_pf()
250 * @hw: pointer to the HW structure
255 static s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number) ixgbe_check_for_msg_pf() argument
260 if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit, ixgbe_check_for_msg_pf()
262 hw->mbx.stats.reqs++; ixgbe_check_for_msg_pf()
271 * @hw: pointer to the HW structure
276 static s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number) ixgbe_check_for_ack_pf() argument
281 if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit, ixgbe_check_for_ack_pf()
283 hw->mbx.stats.acks++; ixgbe_check_for_ack_pf()
292 * @hw: pointer to the HW structure
297 static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) ixgbe_check_for_rst_pf() argument
303 switch (hw->mac.type) { ixgbe_check_for_rst_pf()
305 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); ixgbe_check_for_rst_pf()
310 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); ixgbe_check_for_rst_pf()
317 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); ixgbe_check_for_rst_pf()
318 hw->mbx.stats.rsts++; ixgbe_check_for_rst_pf()
327 * @hw: pointer to the HW structure
332 static s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number) ixgbe_obtain_mbx_lock_pf() argument
337 IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_PFU); ixgbe_obtain_mbx_lock_pf()
340 p2v_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_number)); ixgbe_obtain_mbx_lock_pf()
349 * @hw: pointer to the HW structure
356 static s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size, ixgbe_write_mbx_pf() argument
363 ret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number); ixgbe_write_mbx_pf()
368 ixgbe_check_for_msg_pf(hw, vf_number); ixgbe_write_mbx_pf()
369 ixgbe_check_for_ack_pf(hw, vf_number); ixgbe_write_mbx_pf()
373 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i, msg[i]); ixgbe_write_mbx_pf()
376 IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_STS); ixgbe_write_mbx_pf()
379 hw->mbx.stats.msgs_tx++; ixgbe_write_mbx_pf()
386 * @hw: pointer to the HW structure
395 static s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size, ixgbe_read_mbx_pf() argument
402 ret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number); ixgbe_read_mbx_pf()
408 msg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i); ixgbe_read_mbx_pf()
411 IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_ACK); ixgbe_read_mbx_pf()
414 hw->mbx.stats.msgs_rx++; ixgbe_read_mbx_pf()
422 * @hw: pointer to the HW structure
424 * Initializes the hw->mbx struct to correct values for pf mailbox
426 void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw) ixgbe_init_mbx_params_pf() argument
428 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbe_init_mbx_params_pf()
430 if (hw->mac.type != ixgbe_mac_82599EB && ixgbe_init_mbx_params_pf()
431 hw->mac.type != ixgbe_mac_X550 && ixgbe_init_mbx_params_pf()
432 hw->mac.type != ixgbe_mac_X550EM_x && ixgbe_init_mbx_params_pf()
433 hw->mac.type != ixgbe_mac_X540) ixgbe_init_mbx_params_pf()
H A Dixgbe_ethtool.c158 struct ixgbe_hw *hw = &adapter->hw; ixgbe_get_settings() local
164 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); ixgbe_get_settings()
177 if (hw->phy.autoneg_advertised) { ixgbe_get_settings()
178 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) ixgbe_get_settings()
180 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) ixgbe_get_settings()
182 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) ixgbe_get_settings()
184 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) ixgbe_get_settings()
195 if (hw->phy.multispeed_fiber && !autoneg) { ixgbe_get_settings()
211 switch (adapter->hw.phy.type) { ixgbe_get_settings()
233 switch (adapter->hw.phy.sfp_type) { ixgbe_get_settings()
287 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); ixgbe_get_settings()
318 struct ixgbe_hw *hw = &adapter->hw; ixgbe_set_settings() local
322 if ((hw->phy.media_type == ixgbe_media_type_copper) || ixgbe_set_settings()
323 (hw->phy.multispeed_fiber)) { ixgbe_set_settings()
332 if (!ecmd->autoneg && hw->phy.multispeed_fiber) { ixgbe_set_settings()
339 old = hw->phy.autoneg_advertised; ixgbe_set_settings()
356 hw->mac.autotry_restart = true; ixgbe_set_settings()
357 err = hw->mac.ops.setup_link(hw, advertised, true); ixgbe_set_settings()
360 hw->mac.ops.setup_link(hw, old, true); ixgbe_set_settings()
379 struct ixgbe_hw *hw = &adapter->hw; ixgbe_get_pauseparam() local
381 if (ixgbe_device_supports_autoneg_fc(hw) && ixgbe_get_pauseparam()
382 !hw->fc.disable_fc_autoneg) ixgbe_get_pauseparam()
387 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { ixgbe_get_pauseparam()
389 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { ixgbe_get_pauseparam()
391 } else if (hw->fc.current_mode == ixgbe_fc_full) { ixgbe_get_pauseparam()
401 struct ixgbe_hw *hw = &adapter->hw; ixgbe_set_pauseparam() local
402 struct ixgbe_fc_info fc = hw->fc; ixgbe_set_pauseparam()
405 if ((hw->mac.type == ixgbe_mac_82598EB) && ixgbe_set_pauseparam()
411 !ixgbe_device_supports_autoneg_fc(hw)) ixgbe_set_pauseparam()
426 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { ixgbe_set_pauseparam()
427 hw->fc = fc; ixgbe_set_pauseparam()
461 struct ixgbe_hw *hw = &adapter->hw; ixgbe_get_regs() local
467 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | ixgbe_get_regs()
468 hw->device_id; ixgbe_get_regs()
471 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); ixgbe_get_regs()
472 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); ixgbe_get_regs()
473 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); ixgbe_get_regs()
474 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); ixgbe_get_regs()
475 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); ixgbe_get_regs()
476 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_get_regs()
477 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); ixgbe_get_regs()
478 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); ixgbe_get_regs()
481 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); ixgbe_get_regs()
482 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); ixgbe_get_regs()
483 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); ixgbe_get_regs()
484 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); ixgbe_get_regs()
485 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); ixgbe_get_regs()
486 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); ixgbe_get_regs()
487 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); ixgbe_get_regs()
488 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); ixgbe_get_regs()
489 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); ixgbe_get_regs()
490 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); ixgbe_get_regs()
495 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); ixgbe_get_regs()
496 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); ixgbe_get_regs()
497 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); ixgbe_get_regs()
498 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); ixgbe_get_regs()
499 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); ixgbe_get_regs()
500 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); ixgbe_get_regs()
501 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); ixgbe_get_regs()
502 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); ixgbe_get_regs()
503 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); ixgbe_get_regs()
504 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); ixgbe_get_regs()
505 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); ixgbe_get_regs()
506 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); ixgbe_get_regs()
509 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); ixgbe_get_regs()
510 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); ixgbe_get_regs()
511 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); ixgbe_get_regs()
512 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); ixgbe_get_regs()
513 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); ixgbe_get_regs()
515 switch (hw->mac.type) { ixgbe_get_regs()
517 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); ixgbe_get_regs()
518 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); ixgbe_get_regs()
524 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); ixgbe_get_regs()
525 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); ixgbe_get_regs()
531 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); ixgbe_get_regs()
532 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); ixgbe_get_regs()
536 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); ixgbe_get_regs()
538 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); ixgbe_get_regs()
540 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); ixgbe_get_regs()
542 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); ixgbe_get_regs()
544 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); ixgbe_get_regs()
546 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); ixgbe_get_regs()
548 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); ixgbe_get_regs()
550 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); ixgbe_get_regs()
551 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); ixgbe_get_regs()
553 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); ixgbe_get_regs()
554 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_get_regs()
555 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); ixgbe_get_regs()
558 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); ixgbe_get_regs()
559 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); ixgbe_get_regs()
561 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); ixgbe_get_regs()
563 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); ixgbe_get_regs()
564 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); ixgbe_get_regs()
565 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); ixgbe_get_regs()
566 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); ixgbe_get_regs()
567 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); ixgbe_get_regs()
568 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); ixgbe_get_regs()
569 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); ixgbe_get_regs()
571 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); ixgbe_get_regs()
573 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); ixgbe_get_regs()
574 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); ixgbe_get_regs()
578 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); ixgbe_get_regs()
580 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); ixgbe_get_regs()
582 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); ixgbe_get_regs()
584 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); ixgbe_get_regs()
586 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); ixgbe_get_regs()
588 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); ixgbe_get_regs()
590 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); ixgbe_get_regs()
592 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); ixgbe_get_regs()
593 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); ixgbe_get_regs()
595 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); ixgbe_get_regs()
596 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); ixgbe_get_regs()
598 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); ixgbe_get_regs()
599 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); ixgbe_get_regs()
602 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); ixgbe_get_regs()
603 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); ixgbe_get_regs()
604 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); ixgbe_get_regs()
605 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); ixgbe_get_regs()
606 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); ixgbe_get_regs()
607 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); ixgbe_get_regs()
608 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); ixgbe_get_regs()
609 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); ixgbe_get_regs()
610 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); ixgbe_get_regs()
613 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ ixgbe_get_regs()
614 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ ixgbe_get_regs()
616 switch (hw->mac.type) { ixgbe_get_regs()
618 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); ixgbe_get_regs()
619 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); ixgbe_get_regs()
622 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); ixgbe_get_regs()
625 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); ixgbe_get_regs()
628 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); ixgbe_get_regs()
631 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); ixgbe_get_regs()
637 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); ixgbe_get_regs()
638 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); ixgbe_get_regs()
641 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); ixgbe_get_regs()
644 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); ixgbe_get_regs()
647 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); ixgbe_get_regs()
650 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); ixgbe_get_regs()
658 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ ixgbe_get_regs()
661 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ ixgbe_get_regs()
728 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); ixgbe_get_regs()
729 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); ixgbe_get_regs()
730 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); ixgbe_get_regs()
731 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); ixgbe_get_regs()
732 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); ixgbe_get_regs()
733 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); ixgbe_get_regs()
734 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); ixgbe_get_regs()
735 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); ixgbe_get_regs()
736 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); ixgbe_get_regs()
737 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); ixgbe_get_regs()
738 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); ixgbe_get_regs()
739 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); ixgbe_get_regs()
740 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); ixgbe_get_regs()
741 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); ixgbe_get_regs()
742 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); ixgbe_get_regs()
743 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); ixgbe_get_regs()
744 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); ixgbe_get_regs()
745 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); ixgbe_get_regs()
746 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); ixgbe_get_regs()
747 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); ixgbe_get_regs()
748 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); ixgbe_get_regs()
749 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); ixgbe_get_regs()
750 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); ixgbe_get_regs()
751 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); ixgbe_get_regs()
752 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); ixgbe_get_regs()
753 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); ixgbe_get_regs()
754 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); ixgbe_get_regs()
755 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); ixgbe_get_regs()
756 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); ixgbe_get_regs()
757 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); ixgbe_get_regs()
758 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); ixgbe_get_regs()
759 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); ixgbe_get_regs()
760 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); ixgbe_get_regs()
763 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); ixgbe_get_regs()
765 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); ixgbe_get_regs()
766 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); ixgbe_get_regs()
768 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); ixgbe_get_regs()
769 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); ixgbe_get_regs()
770 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); ixgbe_get_regs()
772 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); ixgbe_get_regs()
773 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); ixgbe_get_regs()
775 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); ixgbe_get_regs()
776 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); ixgbe_get_regs()
777 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); ixgbe_get_regs()
778 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); ixgbe_get_regs()
779 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); ixgbe_get_regs()
780 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); ixgbe_get_regs()
781 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); ixgbe_get_regs()
782 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); ixgbe_get_regs()
783 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); ixgbe_get_regs()
784 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); ixgbe_get_regs()
785 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); ixgbe_get_regs()
786 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); ixgbe_get_regs()
788 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); ixgbe_get_regs()
789 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); ixgbe_get_regs()
790 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); ixgbe_get_regs()
791 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); ixgbe_get_regs()
792 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); ixgbe_get_regs()
793 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); ixgbe_get_regs()
794 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); ixgbe_get_regs()
795 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); ixgbe_get_regs()
796 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); ixgbe_get_regs()
797 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); ixgbe_get_regs()
800 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); ixgbe_get_regs()
803 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); ixgbe_get_regs()
804 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); ixgbe_get_regs()
806 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); ixgbe_get_regs()
807 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); ixgbe_get_regs()
809 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); ixgbe_get_regs()
813 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); ixgbe_get_regs()
814 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); ixgbe_get_regs()
820 return adapter->hw.eeprom.word_size * 2; ixgbe_get_eeprom_len()
827 struct ixgbe_hw *hw = &adapter->hw; ixgbe_get_eeprom() local
836 eeprom->magic = hw->vendor_id | (hw->device_id << 16); ixgbe_get_eeprom()
846 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, ixgbe_get_eeprom()
863 struct ixgbe_hw *hw = &adapter->hw; ixgbe_set_eeprom() local
872 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) ixgbe_set_eeprom()
875 max_len = hw->eeprom.word_size * 2; ixgbe_set_eeprom()
890 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); ixgbe_set_eeprom()
901 ret_val = hw->eeprom.ops.read(hw, last_word, ixgbe_set_eeprom()
916 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, ixgbe_set_eeprom()
922 hw->eeprom.ops.update_checksum(hw); ixgbe_set_eeprom()
1254 struct ixgbe_hw *hw = &adapter->hw; ixgbe_link_test() local
1258 if (ixgbe_removed(hw->hw_addr)) { ixgbe_link_test()
1264 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); ixgbe_link_test()
1357 if (ixgbe_removed(adapter->hw.hw_addr)) { reg_pattern_test()
1362 before = ixgbe_read_reg(&adapter->hw, reg); reg_pattern_test()
1363 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); reg_pattern_test()
1364 val = ixgbe_read_reg(&adapter->hw, reg); reg_pattern_test()
1369 ixgbe_write_reg(&adapter->hw, reg, before); reg_pattern_test()
1372 ixgbe_write_reg(&adapter->hw, reg, before); reg_pattern_test()
1382 if (ixgbe_removed(adapter->hw.hw_addr)) { reg_set_and_check()
1386 before = ixgbe_read_reg(&adapter->hw, reg); reg_set_and_check()
1387 ixgbe_write_reg(&adapter->hw, reg, write & mask); reg_set_and_check()
1388 val = ixgbe_read_reg(&adapter->hw, reg); reg_set_and_check()
1393 ixgbe_write_reg(&adapter->hw, reg, before); reg_set_and_check()
1396 ixgbe_write_reg(&adapter->hw, reg, before); reg_set_and_check()
1406 if (ixgbe_removed(adapter->hw.hw_addr)) { ixgbe_reg_test()
1411 switch (adapter->hw.mac.type) { ixgbe_reg_test()
1434 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); ixgbe_reg_test()
1435 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); ixgbe_reg_test()
1436 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); ixgbe_reg_test()
1437 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; ixgbe_reg_test()
1445 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); ixgbe_reg_test()
1469 ixgbe_write_reg(&adapter->hw, ixgbe_reg_test()
1504 struct ixgbe_hw *hw = &adapter->hw; ixgbe_eeprom_test() local
1505 if (hw->eeprom.ops.validate_checksum(hw, NULL)) ixgbe_eeprom_test()
1517 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); ixgbe_test_intr()
1549 e_info(hw, "testing %s interrupt\n", shared_int ? ixgbe_intr_test()
1553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); ixgbe_intr_test()
1554 IXGBE_WRITE_FLUSH(&adapter->hw); ixgbe_intr_test()
1571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ixgbe_intr_test()
1573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, ixgbe_intr_test()
1575 IXGBE_WRITE_FLUSH(&adapter->hw); ixgbe_intr_test()
1591 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); ixgbe_intr_test()
1592 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); ixgbe_intr_test()
1593 IXGBE_WRITE_FLUSH(&adapter->hw); ixgbe_intr_test()
1610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ixgbe_intr_test()
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, ixgbe_intr_test()
1614 IXGBE_WRITE_FLUSH(&adapter->hw); ixgbe_intr_test()
1625 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); ixgbe_intr_test()
1626 IXGBE_WRITE_FLUSH(&adapter->hw); ixgbe_intr_test()
1639 struct ixgbe_hw *hw = &adapter->hw; ixgbe_free_desc_rings() local
1645 hw->mac.ops.disable_rx(hw); ixgbe_free_desc_rings()
1649 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); ixgbe_free_desc_rings()
1651 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); ixgbe_free_desc_rings()
1653 switch (hw->mac.type) { ixgbe_free_desc_rings()
1658 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); ixgbe_free_desc_rings()
1660 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); ixgbe_free_desc_rings()
1676 struct ixgbe_hw *hw = &adapter->hw; ixgbe_setup_desc_rings() local
1692 switch (adapter->hw.mac.type) { ixgbe_setup_desc_rings()
1697 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); ixgbe_setup_desc_rings()
1699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); ixgbe_setup_desc_rings()
1720 hw->mac.ops.disable_rx(hw); ixgbe_setup_desc_rings()
1724 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); ixgbe_setup_desc_rings()
1726 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); ixgbe_setup_desc_rings()
1728 hw->mac.ops.enable_rx(hw); ixgbe_setup_desc_rings()
1739 struct ixgbe_hw *hw = &adapter->hw; ixgbe_setup_loopback_test() local
1744 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); ixgbe_setup_loopback_test()
1746 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); ixgbe_setup_loopback_test()
1748 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); ixgbe_setup_loopback_test()
1750 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); ixgbe_setup_loopback_test()
1753 switch (adapter->hw.mac.type) { ixgbe_setup_loopback_test()
1757 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); ixgbe_setup_loopback_test()
1759 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); ixgbe_setup_loopback_test()
1762 if (hw->mac.orig_autoc) { ixgbe_setup_loopback_test()
1763 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; ixgbe_setup_loopback_test()
1764 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); ixgbe_setup_loopback_test()
1769 IXGBE_WRITE_FLUSH(hw); ixgbe_setup_loopback_test()
1773 if (hw->mac.type == ixgbe_mac_82598EB) { ixgbe_setup_loopback_test()
1776 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); ixgbe_setup_loopback_test()
1778 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); ixgbe_setup_loopback_test()
1780 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); ixgbe_setup_loopback_test()
1782 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); ixgbe_setup_loopback_test()
1784 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); ixgbe_setup_loopback_test()
1786 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); ixgbe_setup_loopback_test()
1788 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); ixgbe_setup_loopback_test()
1790 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); ixgbe_setup_loopback_test()
1800 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); ixgbe_loopback_cleanup()
1802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); ixgbe_loopback_cleanup()
1987 if (ixgbe_removed(adapter->hw.hw_addr)) { ixgbe_diag_test()
1988 e_err(hw, "Adapter removed - test blocked\n"); ixgbe_diag_test()
1999 struct ixgbe_hw *hw = &adapter->hw; ixgbe_diag_test() local
2020 e_info(hw, "offline testing starting\n"); ixgbe_diag_test()
2034 e_info(hw, "register testing starting\n"); ixgbe_diag_test()
2039 e_info(hw, "eeprom testing starting\n"); ixgbe_diag_test()
2044 e_info(hw, "interrupt testing starting\n"); ixgbe_diag_test()
2052 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); ixgbe_diag_test()
2058 e_info(hw, "loopback testing starting\n"); ixgbe_diag_test()
2069 else if (hw->mac.ops.disable_tx_laser) ixgbe_diag_test()
2070 hw->mac.ops.disable_tx_laser(hw); ixgbe_diag_test()
2072 e_info(hw, "online testing starting\n"); ixgbe_diag_test()
2094 struct ixgbe_hw *hw = &adapter->hw; ixgbe_wol_exclusion() local
2098 if (!ixgbe_wol_supported(adapter, hw->device_id, ixgbe_wol_exclusion()
2099 hw->subsystem_device_id)) { ixgbe_wol_exclusion()
2170 struct ixgbe_hw *hw = &adapter->hw; ixgbe_set_phys_id() local
2174 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ixgbe_set_phys_id()
2178 hw->mac.ops.led_on(hw, IXGBE_LED_ON); ixgbe_set_phys_id()
2182 hw->mac.ops.led_off(hw, IXGBE_LED_ON); ixgbe_set_phys_id()
2187 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); ixgbe_set_phys_id()
2501 struct ixgbe_hw *hw = &adapter->hw; ixgbe_update_ethtool_fdir_entry() local
2521 err = ixgbe_fdir_erase_perfect_filter_82599(hw, ixgbe_update_ethtool_fdir_entry()
2599 struct ixgbe_hw *hw = &adapter->hw; ixgbe_add_ethtool_fdir_entry() local
2693 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); ixgbe_add_ethtool_fdir_entry()
2707 err = ixgbe_fdir_write_perfect_filter_82599(hw, ixgbe_add_ethtool_fdir_entry()
2812 struct ixgbe_hw *hw = &adapter->hw; ixgbe_set_rss_hash_opt() local
2816 if ((hw->mac.type >= ixgbe_mac_X550) && ixgbe_set_rss_hash_opt()
2818 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); ixgbe_set_rss_hash_opt()
2820 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); ixgbe_set_rss_hash_opt()
2843 if ((hw->mac.type >= ixgbe_mac_X550) && ixgbe_set_rss_hash_opt()
2845 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); ixgbe_set_rss_hash_opt()
2847 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); ixgbe_set_rss_hash_opt()
2877 if (adapter->hw.mac.type < ixgbe_mac_X550) ixgbe_rss_indir_tbl_max()
2965 switch (adapter->hw.mac.type) { ixgbe_get_ts_info()
3012 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { ixgbe_max_channels()
3112 struct ixgbe_hw *hw = &adapter->hw; ixgbe_get_module_info() local
3118 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_get_module_info()
3125 status = hw->phy.ops.read_i2c_eeprom(hw, ixgbe_get_module_info()
3154 struct ixgbe_hw *hw = &adapter->hw; ixgbe_get_module_eeprom() local
3168 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); ixgbe_get_module_eeprom()
3170 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); ixgbe_get_module_eeprom()
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
H A Di40e_adminq.c33 static void i40e_resume_aq(struct i40e_hw *hw);
47 * @hw: pointer to the hardware structure
51 static void i40e_adminq_init_regs(struct i40e_hw *hw) i40e_adminq_init_regs() argument
54 if (i40e_is_vf(hw)) { i40e_adminq_init_regs()
55 hw->aq.asq.tail = I40E_VF_ATQT1; i40e_adminq_init_regs()
56 hw->aq.asq.head = I40E_VF_ATQH1; i40e_adminq_init_regs()
57 hw->aq.asq.len = I40E_VF_ATQLEN1; i40e_adminq_init_regs()
58 hw->aq.asq.bal = I40E_VF_ATQBAL1; i40e_adminq_init_regs()
59 hw->aq.asq.bah = I40E_VF_ATQBAH1; i40e_adminq_init_regs()
60 hw->aq.arq.tail = I40E_VF_ARQT1; i40e_adminq_init_regs()
61 hw->aq.arq.head = I40E_VF_ARQH1; i40e_adminq_init_regs()
62 hw->aq.arq.len = I40E_VF_ARQLEN1; i40e_adminq_init_regs()
63 hw->aq.arq.bal = I40E_VF_ARQBAL1; i40e_adminq_init_regs()
64 hw->aq.arq.bah = I40E_VF_ARQBAH1; i40e_adminq_init_regs()
66 hw->aq.asq.tail = I40E_PF_ATQT; i40e_adminq_init_regs()
67 hw->aq.asq.head = I40E_PF_ATQH; i40e_adminq_init_regs()
68 hw->aq.asq.len = I40E_PF_ATQLEN; i40e_adminq_init_regs()
69 hw->aq.asq.bal = I40E_PF_ATQBAL; i40e_adminq_init_regs()
70 hw->aq.asq.bah = I40E_PF_ATQBAH; i40e_adminq_init_regs()
71 hw->aq.arq.tail = I40E_PF_ARQT; i40e_adminq_init_regs()
72 hw->aq.arq.head = I40E_PF_ARQH; i40e_adminq_init_regs()
73 hw->aq.arq.len = I40E_PF_ARQLEN; i40e_adminq_init_regs()
74 hw->aq.arq.bal = I40E_PF_ARQBAL; i40e_adminq_init_regs()
75 hw->aq.arq.bah = I40E_PF_ARQBAH; i40e_adminq_init_regs()
81 * @hw: pointer to the hardware structure
83 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) i40e_alloc_adminq_asq_ring() argument
87 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, i40e_alloc_adminq_asq_ring()
89 (hw->aq.num_asq_entries * i40e_alloc_adminq_asq_ring()
95 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, i40e_alloc_adminq_asq_ring()
96 (hw->aq.num_asq_entries * i40e_alloc_adminq_asq_ring()
99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); i40e_alloc_adminq_asq_ring()
108 * @hw: pointer to the hardware structure
110 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) i40e_alloc_adminq_arq_ring() argument
114 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, i40e_alloc_adminq_arq_ring()
116 (hw->aq.num_arq_entries * i40e_alloc_adminq_arq_ring()
125 * @hw: pointer to the hardware structure
130 static void i40e_free_adminq_asq(struct i40e_hw *hw) i40e_free_adminq_asq() argument
132 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); i40e_free_adminq_asq()
137 * @hw: pointer to the hardware structure
142 static void i40e_free_adminq_arq(struct i40e_hw *hw) i40e_free_adminq_arq() argument
144 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); i40e_free_adminq_arq()
149 * @hw: pointer to the hardware structure
151 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) i40e_alloc_arq_bufs() argument
163 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, i40e_alloc_arq_bufs()
164 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); i40e_alloc_arq_bufs()
167 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; i40e_alloc_arq_bufs()
170 for (i = 0; i < hw->aq.num_arq_entries; i++) { i40e_alloc_arq_bufs()
171 bi = &hw->aq.arq.r.arq_bi[i]; i40e_alloc_arq_bufs()
172 ret_code = i40e_allocate_dma_mem(hw, bi, i40e_alloc_arq_bufs()
174 hw->aq.arq_buf_size, i40e_alloc_arq_bufs()
180 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); i40e_alloc_arq_bufs()
183 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) i40e_alloc_arq_bufs()
208 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); i40e_alloc_arq_bufs()
209 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); i40e_alloc_arq_bufs()
216 * @hw: pointer to the hardware structure
218 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) i40e_alloc_asq_bufs() argument
225 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, i40e_alloc_asq_bufs()
226 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); i40e_alloc_asq_bufs()
229 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; i40e_alloc_asq_bufs()
232 for (i = 0; i < hw->aq.num_asq_entries; i++) { i40e_alloc_asq_bufs()
233 bi = &hw->aq.asq.r.asq_bi[i]; i40e_alloc_asq_bufs()
234 ret_code = i40e_allocate_dma_mem(hw, bi, i40e_alloc_asq_bufs()
236 hw->aq.asq_buf_size, i40e_alloc_asq_bufs()
248 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); i40e_alloc_asq_bufs()
249 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); i40e_alloc_asq_bufs()
256 * @hw: pointer to the hardware structure
258 static void i40e_free_arq_bufs(struct i40e_hw *hw) i40e_free_arq_bufs() argument
263 for (i = 0; i < hw->aq.num_arq_entries; i++) i40e_free_arq_bufs()
264 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); i40e_free_arq_bufs()
267 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); i40e_free_arq_bufs()
270 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); i40e_free_arq_bufs()
275 * @hw: pointer to the hardware structure
277 static void i40e_free_asq_bufs(struct i40e_hw *hw) i40e_free_asq_bufs() argument
282 for (i = 0; i < hw->aq.num_asq_entries; i++) i40e_free_asq_bufs()
283 if (hw->aq.asq.r.asq_bi[i].pa) i40e_free_asq_bufs()
284 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); i40e_free_asq_bufs()
287 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); i40e_free_asq_bufs()
290 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); i40e_free_asq_bufs()
293 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); i40e_free_asq_bufs()
298 * @hw: pointer to the hardware structure
302 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) i40e_config_asq_regs() argument
308 wr32(hw, hw->aq.asq.head, 0); i40e_config_asq_regs()
309 wr32(hw, hw->aq.asq.tail, 0); i40e_config_asq_regs()
312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | i40e_config_asq_regs()
314 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); i40e_config_asq_regs()
315 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); i40e_config_asq_regs()
318 reg = rd32(hw, hw->aq.asq.bal); i40e_config_asq_regs()
319 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) i40e_config_asq_regs()
327 * @hw: pointer to the hardware structure
331 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) i40e_config_arq_regs() argument
337 wr32(hw, hw->aq.arq.head, 0); i40e_config_arq_regs()
338 wr32(hw, hw->aq.arq.tail, 0); i40e_config_arq_regs()
341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | i40e_config_arq_regs()
343 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); i40e_config_arq_regs()
344 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); i40e_config_arq_regs()
347 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); i40e_config_arq_regs()
350 reg = rd32(hw, hw->aq.arq.bal); i40e_config_arq_regs()
351 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) i40e_config_arq_regs()
359 * @hw: pointer to the hardware structure
363 * in the hw->aq structure:
364 * - hw->aq.num_asq_entries
365 * - hw->aq.arq_buf_size
370 static i40e_status i40e_init_asq(struct i40e_hw *hw) i40e_init_asq() argument
374 if (hw->aq.asq.count > 0) { i40e_init_asq()
381 if ((hw->aq.num_asq_entries == 0) || i40e_init_asq()
382 (hw->aq.asq_buf_size == 0)) { i40e_init_asq()
387 hw->aq.asq.next_to_use = 0; i40e_init_asq()
388 hw->aq.asq.next_to_clean = 0; i40e_init_asq()
391 ret_code = i40e_alloc_adminq_asq_ring(hw); i40e_init_asq()
396 ret_code = i40e_alloc_asq_bufs(hw); i40e_init_asq()
401 ret_code = i40e_config_asq_regs(hw); i40e_init_asq()
406 hw->aq.asq.count = hw->aq.num_asq_entries; i40e_init_asq()
410 i40e_free_adminq_asq(hw); i40e_init_asq()
418 * @hw: pointer to the hardware structure
422 * in the hw->aq structure:
423 * - hw->aq.num_asq_entries
424 * - hw->aq.arq_buf_size
429 static i40e_status i40e_init_arq(struct i40e_hw *hw) i40e_init_arq() argument
433 if (hw->aq.arq.count > 0) { i40e_init_arq()
440 if ((hw->aq.num_arq_entries == 0) || i40e_init_arq()
441 (hw->aq.arq_buf_size == 0)) { i40e_init_arq()
446 hw->aq.arq.next_to_use = 0; i40e_init_arq()
447 hw->aq.arq.next_to_clean = 0; i40e_init_arq()
450 ret_code = i40e_alloc_adminq_arq_ring(hw); i40e_init_arq()
455 ret_code = i40e_alloc_arq_bufs(hw); i40e_init_arq()
460 ret_code = i40e_config_arq_regs(hw); i40e_init_arq()
465 hw->aq.arq.count = hw->aq.num_arq_entries; i40e_init_arq()
469 i40e_free_adminq_arq(hw); i40e_init_arq()
477 * @hw: pointer to the hardware structure
481 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) i40e_shutdown_asq() argument
485 mutex_lock(&hw->aq.asq_mutex); i40e_shutdown_asq()
487 if (hw->aq.asq.count == 0) { i40e_shutdown_asq()
493 wr32(hw, hw->aq.asq.head, 0); i40e_shutdown_asq()
494 wr32(hw, hw->aq.asq.tail, 0); i40e_shutdown_asq()
495 wr32(hw, hw->aq.asq.len, 0); i40e_shutdown_asq()
496 wr32(hw, hw->aq.asq.bal, 0); i40e_shutdown_asq()
497 wr32(hw, hw->aq.asq.bah, 0); i40e_shutdown_asq()
499 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ i40e_shutdown_asq()
502 i40e_free_asq_bufs(hw); i40e_shutdown_asq()
505 mutex_unlock(&hw->aq.asq_mutex); i40e_shutdown_asq()
511 * @hw: pointer to the hardware structure
515 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) i40e_shutdown_arq() argument
519 mutex_lock(&hw->aq.arq_mutex); i40e_shutdown_arq()
521 if (hw->aq.arq.count == 0) { i40e_shutdown_arq()
527 wr32(hw, hw->aq.arq.head, 0); i40e_shutdown_arq()
528 wr32(hw, hw->aq.arq.tail, 0); i40e_shutdown_arq()
529 wr32(hw, hw->aq.arq.len, 0); i40e_shutdown_arq()
530 wr32(hw, hw->aq.arq.bal, 0); i40e_shutdown_arq()
531 wr32(hw, hw->aq.arq.bah, 0); i40e_shutdown_arq()
533 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ i40e_shutdown_arq()
536 i40e_free_arq_bufs(hw); i40e_shutdown_arq()
539 mutex_unlock(&hw->aq.arq_mutex); i40e_shutdown_arq()
545 * @hw: pointer to the hardware structure
548 * in the hw->aq structure:
549 * - hw->aq.num_asq_entries
550 * - hw->aq.num_arq_entries
551 * - hw->aq.arq_buf_size
552 * - hw->aq.asq_buf_size
554 i40e_status i40e_init_adminq(struct i40e_hw *hw) i40e_init_adminq() argument
562 if ((hw->aq.num_arq_entries == 0) || i40e_init_adminq()
563 (hw->aq.num_asq_entries == 0) || i40e_init_adminq()
564 (hw->aq.arq_buf_size == 0) || i40e_init_adminq()
565 (hw->aq.asq_buf_size == 0)) { i40e_init_adminq()
571 i40e_adminq_init_regs(hw); i40e_init_adminq()
574 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; i40e_init_adminq()
577 ret_code = i40e_init_asq(hw); i40e_init_adminq()
582 ret_code = i40e_init_arq(hw); i40e_init_adminq()
591 ret_code = i40e_aq_get_firmware_version(hw, i40e_init_adminq()
592 &hw->aq.fw_maj_ver, i40e_init_adminq()
593 &hw->aq.fw_min_ver, i40e_init_adminq()
594 &hw->aq.fw_build, i40e_init_adminq()
595 &hw->aq.api_maj_ver, i40e_init_adminq()
596 &hw->aq.api_min_ver, i40e_init_adminq()
602 i40e_resume_aq(hw); i40e_init_adminq()
608 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, i40e_init_adminq()
609 &hw->nvm.version); i40e_init_adminq()
610 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); i40e_init_adminq()
611 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); i40e_init_adminq()
612 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; i40e_init_adminq()
613 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); i40e_init_adminq()
614 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), i40e_init_adminq()
616 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), i40e_init_adminq()
618 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; i40e_init_adminq()
620 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { i40e_init_adminq()
626 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); i40e_init_adminq()
627 hw->aq.nvm_release_on_done = false; i40e_init_adminq()
628 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; i40e_init_adminq()
630 ret_code = i40e_aq_set_hmc_resource_profile(hw, i40e_init_adminq()
640 i40e_shutdown_arq(hw); i40e_init_adminq()
642 i40e_shutdown_asq(hw); i40e_init_adminq()
651 * @hw: pointer to the hardware structure
653 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) i40e_shutdown_adminq() argument
657 if (i40e_check_asq_alive(hw)) i40e_shutdown_adminq()
658 i40e_aq_queue_shutdown(hw, true); i40e_shutdown_adminq()
660 i40e_shutdown_asq(hw); i40e_shutdown_adminq()
661 i40e_shutdown_arq(hw); i40e_shutdown_adminq()
663 if (hw->nvm_buff.va) i40e_shutdown_adminq()
664 i40e_free_virt_mem(hw, &hw->nvm_buff); i40e_shutdown_adminq()
671 * @hw: pointer to the hardware structure
675 static u16 i40e_clean_asq(struct i40e_hw *hw) i40e_clean_asq() argument
677 struct i40e_adminq_ring *asq = &(hw->aq.asq); i40e_clean_asq()
685 while (rd32(hw, hw->aq.asq.head) != ntc) { i40e_clean_asq()
686 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_clean_asq()
687 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); i40e_clean_asq()
693 cb_func(hw, &desc_cb); i40e_clean_asq()
711 * @hw: pointer to the hw struct
716 static bool i40e_asq_done(struct i40e_hw *hw) i40e_asq_done() argument
721 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; i40e_asq_done()
727 * @hw: pointer to the hw struct
736 i40e_status i40e_asq_send_command(struct i40e_hw *hw, i40e_asq_send_command() argument
750 mutex_lock(&hw->aq.asq_mutex); i40e_asq_send_command()
752 if (hw->aq.asq.count == 0) { i40e_asq_send_command()
753 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_asq_send_command()
759 hw->aq.asq_last_status = I40E_AQ_RC_OK; i40e_asq_send_command()
761 val = rd32(hw, hw->aq.asq.head); i40e_asq_send_command()
762 if (val >= hw->aq.num_asq_entries) { i40e_asq_send_command()
763 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_asq_send_command()
769 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); i40e_asq_send_command()
791 if (buff_size > hw->aq.asq_buf_size) { i40e_asq_send_command()
792 i40e_debug(hw, i40e_asq_send_command()
801 i40e_debug(hw, i40e_asq_send_command()
815 if (i40e_clean_asq(hw) == 0) { i40e_asq_send_command()
816 i40e_debug(hw, i40e_asq_send_command()
824 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); i40e_asq_send_command()
831 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); i40e_asq_send_command()
846 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n"); i40e_asq_send_command()
847 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, i40e_asq_send_command()
849 (hw->aq.asq.next_to_use)++; i40e_asq_send_command()
850 if (hw->aq.asq.next_to_use == hw->aq.asq.count) i40e_asq_send_command()
851 hw->aq.asq.next_to_use = 0; i40e_asq_send_command()
853 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); i40e_asq_send_command()
865 if (i40e_asq_done(hw)) i40e_asq_send_command()
869 } while (total_delay < hw->aq.asq_cmd_timeout); i40e_asq_send_command()
873 if (i40e_asq_done(hw)) { i40e_asq_send_command()
879 i40e_debug(hw, i40e_asq_send_command()
892 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; i40e_asq_send_command()
895 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_asq_send_command()
897 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); i40e_asq_send_command()
906 i40e_debug(hw, i40e_asq_send_command()
913 mutex_unlock(&hw->aq.asq_mutex); i40e_asq_send_command()
935 * @hw: pointer to the hw struct
943 i40e_status i40e_clean_arq_element(struct i40e_hw *hw, i40e_clean_arq_element() argument
948 u16 ntc = hw->aq.arq.next_to_clean; i40e_clean_arq_element()
957 mutex_lock(&hw->aq.arq_mutex); i40e_clean_arq_element()
959 if (hw->aq.arq.count == 0) { i40e_clean_arq_element()
960 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_clean_arq_element()
967 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); i40e_clean_arq_element()
975 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); i40e_clean_arq_element()
981 hw->aq.arq_last_status = i40e_clean_arq_element()
983 i40e_debug(hw, i40e_clean_arq_element()
986 hw->aq.arq_last_status); i40e_clean_arq_element()
993 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, i40e_clean_arq_element()
996 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n"); i40e_clean_arq_element()
997 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, i40e_clean_arq_element()
998 hw->aq.arq_buf_size); i40e_clean_arq_element()
1004 bi = &hw->aq.arq.r.arq_bi[ntc]; i40e_clean_arq_element()
1008 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) i40e_clean_arq_element()
1015 wr32(hw, hw->aq.arq.tail, ntc); i40e_clean_arq_element()
1018 if (ntc == hw->aq.num_arq_entries) i40e_clean_arq_element()
1020 hw->aq.arq.next_to_clean = ntc; i40e_clean_arq_element()
1021 hw->aq.arq.next_to_use = ntu; i40e_clean_arq_element()
1026 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); i40e_clean_arq_element()
1029 mutex_unlock(&hw->aq.arq_mutex); i40e_clean_arq_element()
1032 if (hw->aq.nvm_release_on_done) { i40e_clean_arq_element()
1033 i40e_release_nvm(hw); i40e_clean_arq_element()
1034 hw->aq.nvm_release_on_done = false; i40e_clean_arq_element()
1037 switch (hw->nvmupd_state) { i40e_clean_arq_element()
1039 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; i40e_clean_arq_element()
1043 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; i40e_clean_arq_element()
1054 static void i40e_resume_aq(struct i40e_hw *hw) i40e_resume_aq() argument
1057 hw->aq.asq.next_to_use = 0; i40e_resume_aq()
1058 hw->aq.asq.next_to_clean = 0; i40e_resume_aq()
1060 i40e_config_asq_regs(hw); i40e_resume_aq()
1062 hw->aq.arq.next_to_use = 0; i40e_resume_aq()
1063 hw->aq.arq.next_to_clean = 0; i40e_resume_aq()
1065 i40e_config_arq_regs(hw); i40e_resume_aq()
H A Di40e_prototype.h42 i40e_status i40e_init_adminq(struct i40e_hw *hw);
43 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw);
44 void i40e_adminq_init_ring_data(struct i40e_hw *hw);
45 i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
48 i40e_status i40e_asq_send_command(struct i40e_hw *hw,
55 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
58 void i40e_idle_aq(struct i40e_hw *hw);
59 bool i40e_check_asq_alive(struct i40e_hw *hw);
60 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
61 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
62 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err);
64 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
66 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
68 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
71 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
75 u32 i40e_led_get(struct i40e_hw *hw);
76 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);
80 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
85 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
88 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
91 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
93 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
95 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
99 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
102 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
104 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask,
106 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
108 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
111 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
114 i40e_status i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
117 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
120 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
123 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
126 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
128 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
130 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
133 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
136 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
141 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
146 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,
149 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
152 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
155 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
159 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
164 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
168 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
172 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
175 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
179 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
183 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
187 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
190 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
192 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
194 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
197 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
201 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
203 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
205 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
208 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
211 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
213 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
217 i40e_status i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
220 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,
223 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
228 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
232 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
236 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
240 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
244 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
248 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
252 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
254 i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
257 i40e_status i40e_init_shared_code(struct i40e_hw *hw);
258 i40e_status i40e_pf_reset(struct i40e_hw *hw);
259 void i40e_clear_hw(struct i40e_hw *hw);
260 void i40e_clear_pxe_mode(struct i40e_hw *hw);
261 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up);
262 i40e_status i40e_update_link_info(struct i40e_hw *hw);
263 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
264 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
267 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
270 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
271 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
274 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);
276 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
279 i40e_status i40e_init_nvm(struct i40e_hw *hw);
280 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
282 void i40e_release_nvm(struct i40e_hw *hw);
283 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
285 i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
287 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw);
288 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
290 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
293 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);
305 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
307 i40e_status i40e_vf_reset(struct i40e_hw *hw);
308 i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
313 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
315 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
320 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
325 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
H A Di40e_diag.c32 * @hw: pointer to the hw struct
36 static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw, i40e_diag_reg_pattern_test() argument
43 orig_val = rd32(hw, reg); i40e_diag_reg_pattern_test()
46 wr32(hw, reg, (pat & mask)); i40e_diag_reg_pattern_test()
47 val = rd32(hw, reg); i40e_diag_reg_pattern_test()
49 i40e_debug(hw, I40E_DEBUG_DIAG, i40e_diag_reg_pattern_test()
56 wr32(hw, reg, orig_val); i40e_diag_reg_pattern_test()
57 val = rd32(hw, reg); i40e_diag_reg_pattern_test()
59 i40e_debug(hw, I40E_DEBUG_DIAG, i40e_diag_reg_pattern_test()
94 * @hw: pointer to the hw struct
98 i40e_status i40e_diag_reg_test(struct i40e_hw *hw) i40e_diag_reg_test() argument
109 hw->func_caps.num_tx_qp != 0) i40e_diag_reg_test()
110 i40e_reg_list[i].elements = hw->func_caps.num_tx_qp; i40e_diag_reg_test()
116 hw->func_caps.num_msix_vectors != 0) i40e_diag_reg_test()
118 hw->func_caps.num_msix_vectors - 1; i40e_diag_reg_test()
125 ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); i40e_diag_reg_test()
134 * @hw: pointer to the hw struct
138 i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw) i40e_diag_eeprom_test() argument
144 ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val); i40e_diag_eeprom_test()
148 return i40e_validate_nvm_checksum(hw, NULL); i40e_diag_eeprom_test()
H A Di40e_nvm.c31 * @hw: pointer to the HW structure
39 i40e_status i40e_init_nvm(struct i40e_hw *hw) i40e_init_nvm() argument
41 struct i40e_nvm_info *nvm = &hw->nvm; i40e_init_nvm()
49 gens = rd32(hw, I40E_GLNVM_GENS); i40e_init_nvm()
56 fla = rd32(hw, I40E_GLNVM_FLA); i40e_init_nvm()
64 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n"); i40e_init_nvm()
72 * @hw: pointer to the HW structure
78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw, i40e_acquire_nvm() argument
85 if (hw->nvm.blank_nvm_mode) i40e_acquire_nvm()
88 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, i40e_acquire_nvm()
91 gtime = rd32(hw, I40E_GLVFGEN_TIMER); i40e_acquire_nvm()
94 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; i40e_acquire_nvm()
97 i40e_debug(hw, I40E_DEBUG_NVM, i40e_acquire_nvm()
99 access, time_left, ret_code, hw->aq.asq_last_status); i40e_acquire_nvm()
106 gtime = rd32(hw, I40E_GLVFGEN_TIMER); i40e_acquire_nvm()
107 ret_code = i40e_aq_request_resource(hw, i40e_acquire_nvm()
112 hw->nvm.hw_semaphore_timeout = i40e_acquire_nvm()
118 hw->nvm.hw_semaphore_timeout = 0; i40e_acquire_nvm()
119 i40e_debug(hw, I40E_DEBUG_NVM, i40e_acquire_nvm()
121 time_left, ret_code, hw->aq.asq_last_status); i40e_acquire_nvm()
131 * @hw: pointer to the HW structure
135 void i40e_release_nvm(struct i40e_hw *hw) i40e_release_nvm() argument
137 if (!hw->nvm.blank_nvm_mode) i40e_release_nvm()
138 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); i40e_release_nvm()
143 * @hw: pointer to the HW structure
147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) i40e_poll_sr_srctl_done_bit() argument
154 srctl = rd32(hw, I40E_GLNVM_SRCTL); i40e_poll_sr_srctl_done_bit()
162 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); i40e_poll_sr_srctl_done_bit()
168 * @hw: pointer to the HW structure
174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, i40e_read_nvm_word_srctl() argument
180 if (offset >= hw->nvm.sr_size) { i40e_read_nvm_word_srctl()
181 i40e_debug(hw, I40E_DEBUG_NVM, i40e_read_nvm_word_srctl()
183 offset, hw->nvm.sr_size); i40e_read_nvm_word_srctl()
189 ret_code = i40e_poll_sr_srctl_done_bit(hw); i40e_read_nvm_word_srctl()
194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg); i40e_read_nvm_word_srctl()
197 ret_code = i40e_poll_sr_srctl_done_bit(hw); i40e_read_nvm_word_srctl()
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); i40e_read_nvm_word_srctl()
206 i40e_debug(hw, I40E_DEBUG_NVM, i40e_read_nvm_word_srctl()
216 * @hw: pointer to the HW structure.
225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, i40e_read_nvm_aq() argument
239 if ((offset + words) > hw->nvm.sr_size) i40e_read_nvm_aq()
240 i40e_debug(hw, I40E_DEBUG_NVM, i40e_read_nvm_aq()
242 (offset + words), hw->nvm.sr_size); i40e_read_nvm_aq()
245 i40e_debug(hw, I40E_DEBUG_NVM, i40e_read_nvm_aq()
251 i40e_debug(hw, I40E_DEBUG_NVM, i40e_read_nvm_aq()
255 ret_code = i40e_aq_read_nvm(hw, module_pointer, i40e_read_nvm_aq()
265 * @hw: pointer to the HW structure
271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, i40e_read_nvm_word_aq() argument
276 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true); i40e_read_nvm_word_aq()
284 * @hw: pointer to the HW structure
290 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, i40e_read_nvm_word() argument
295 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { i40e_read_nvm_word()
296 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); i40e_read_nvm_word()
298 ret_code = i40e_read_nvm_word_aq(hw, offset, data); i40e_read_nvm_word()
299 i40e_release_nvm(hw); i40e_read_nvm_word()
302 ret_code = i40e_read_nvm_word_srctl(hw, offset, data); i40e_read_nvm_word()
309 * @hw: pointer to the HW structure
318 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, i40e_read_nvm_buffer_srctl() argument
327 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]); i40e_read_nvm_buffer_srctl()
340 * @hw: pointer to the HW structure
349 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, i40e_read_nvm_buffer_aq() argument
375 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size, i40e_read_nvm_buffer_aq()
397 * @hw: pointer to the HW structure
406 i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, i40e_read_nvm_buffer() argument
411 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { i40e_read_nvm_buffer()
412 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); i40e_read_nvm_buffer()
414 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, i40e_read_nvm_buffer()
416 i40e_release_nvm(hw); i40e_read_nvm_buffer()
419 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); i40e_read_nvm_buffer()
426 * @hw: pointer to the HW structure.
435 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, i40e_write_nvm_aq() argument
443 cmd_details.wb_desc = &hw->nvm_wb_desc; i40e_write_nvm_aq()
450 if ((offset + words) > hw->nvm.sr_size) i40e_write_nvm_aq()
451 i40e_debug(hw, I40E_DEBUG_NVM, i40e_write_nvm_aq()
453 (offset + words), hw->nvm.sr_size); i40e_write_nvm_aq()
456 i40e_debug(hw, I40E_DEBUG_NVM, i40e_write_nvm_aq()
462 i40e_debug(hw, I40E_DEBUG_NVM, i40e_write_nvm_aq()
466 ret_code = i40e_aq_update_nvm(hw, module_pointer, i40e_write_nvm_aq()
476 * @hw: pointer to hardware structure
484 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, i40e_calc_nvm_checksum() argument
495 ret_code = i40e_allocate_virt_mem(hw, &vmem, i40e_calc_nvm_checksum()
502 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); i40e_calc_nvm_checksum()
509 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, i40e_calc_nvm_checksum()
519 for (i = 0; i < hw->nvm.sr_size; i++) { i40e_calc_nvm_checksum()
524 ret_code = i40e_read_nvm_buffer(hw, i, &words, data); i40e_calc_nvm_checksum()
553 i40e_free_virt_mem(hw, &vmem); i40e_calc_nvm_checksum()
559 * @hw: pointer to hardware structure
565 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw) i40e_update_nvm_checksum() argument
571 ret_code = i40e_calc_nvm_checksum(hw, &checksum); i40e_update_nvm_checksum()
574 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, i40e_update_nvm_checksum()
583 * @hw: pointer to hardware structure
589 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, i40e_validate_nvm_checksum() argument
596 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); i40e_validate_nvm_checksum()
603 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); i40e_validate_nvm_checksum()
619 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
622 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
625 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
628 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
631 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
634 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
637 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
640 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
643 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
676 * @hw: pointer to hardware structure
683 i40e_status i40e_nvmupd_command(struct i40e_hw *hw, i40e_nvmupd_command() argument
694 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); i40e_nvmupd_command()
696 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n", i40e_nvmupd_command()
698 hw->nvmupd_state, i40e_nvmupd_command()
699 hw->aq.nvm_release_on_done); i40e_nvmupd_command()
703 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_command()
712 bytes[0] = hw->nvmupd_state; i40e_nvmupd_command()
716 switch (hw->nvmupd_state) { i40e_nvmupd_command()
718 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); i40e_nvmupd_command()
722 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); i40e_nvmupd_command()
726 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); i40e_nvmupd_command()
737 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_command()
738 "NVMUPD: no such state %d\n", hw->nvmupd_state); i40e_nvmupd_command()
748 * @hw: pointer to hardware structure
756 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, i40e_nvmupd_state_init() argument
763 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); i40e_nvmupd_state_init()
767 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); i40e_nvmupd_state_init()
770 hw->aq.asq_last_status); i40e_nvmupd_state_init()
772 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); i40e_nvmupd_state_init()
773 i40e_release_nvm(hw); i40e_nvmupd_state_init()
778 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); i40e_nvmupd_state_init()
781 hw->aq.asq_last_status); i40e_nvmupd_state_init()
783 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); i40e_nvmupd_state_init()
785 i40e_release_nvm(hw); i40e_nvmupd_state_init()
787 hw->nvmupd_state = I40E_NVMUPD_STATE_READING; i40e_nvmupd_state_init()
792 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); i40e_nvmupd_state_init()
795 hw->aq.asq_last_status); i40e_nvmupd_state_init()
797 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); i40e_nvmupd_state_init()
799 i40e_release_nvm(hw); i40e_nvmupd_state_init()
801 hw->aq.nvm_release_on_done = true; i40e_nvmupd_state_init()
802 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; i40e_nvmupd_state_init()
808 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); i40e_nvmupd_state_init()
811 hw->aq.asq_last_status); i40e_nvmupd_state_init()
813 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); i40e_nvmupd_state_init()
815 i40e_release_nvm(hw); i40e_nvmupd_state_init()
817 hw->aq.nvm_release_on_done = true; i40e_nvmupd_state_init()
818 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; i40e_nvmupd_state_init()
824 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); i40e_nvmupd_state_init()
827 hw->aq.asq_last_status); i40e_nvmupd_state_init()
829 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); i40e_nvmupd_state_init()
831 i40e_release_nvm(hw); i40e_nvmupd_state_init()
833 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; i40e_nvmupd_state_init()
838 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); i40e_nvmupd_state_init()
841 hw->aq.asq_last_status); i40e_nvmupd_state_init()
843 status = i40e_update_nvm_checksum(hw); i40e_nvmupd_state_init()
845 *perrno = hw->aq.asq_last_status ? i40e_nvmupd_state_init()
847 hw->aq.asq_last_status) : i40e_nvmupd_state_init()
849 i40e_release_nvm(hw); i40e_nvmupd_state_init()
851 hw->aq.nvm_release_on_done = true; i40e_nvmupd_state_init()
852 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; i40e_nvmupd_state_init()
858 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); i40e_nvmupd_state_init()
862 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); i40e_nvmupd_state_init()
866 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_state_init()
878 * @hw: pointer to hardware structure
886 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, i40e_nvmupd_state_reading() argument
893 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); i40e_nvmupd_state_reading()
898 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); i40e_nvmupd_state_reading()
902 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); i40e_nvmupd_state_reading()
903 i40e_release_nvm(hw); i40e_nvmupd_state_reading()
904 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; i40e_nvmupd_state_reading()
908 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_state_reading()
920 * @hw: pointer to hardware structure
928 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, i40e_nvmupd_state_writing() argument
936 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); i40e_nvmupd_state_writing()
941 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); i40e_nvmupd_state_writing()
943 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; i40e_nvmupd_state_writing()
947 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); i40e_nvmupd_state_writing()
949 *perrno = hw->aq.asq_last_status ? i40e_nvmupd_state_writing()
951 hw->aq.asq_last_status) : i40e_nvmupd_state_writing()
953 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; i40e_nvmupd_state_writing()
955 hw->aq.nvm_release_on_done = true; i40e_nvmupd_state_writing()
956 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; i40e_nvmupd_state_writing()
961 status = i40e_update_nvm_checksum(hw); i40e_nvmupd_state_writing()
963 *perrno = hw->aq.asq_last_status ? i40e_nvmupd_state_writing()
965 hw->aq.asq_last_status) : i40e_nvmupd_state_writing()
967 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; i40e_nvmupd_state_writing()
969 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; i40e_nvmupd_state_writing()
974 status = i40e_update_nvm_checksum(hw); i40e_nvmupd_state_writing()
976 *perrno = hw->aq.asq_last_status ? i40e_nvmupd_state_writing()
978 hw->aq.asq_last_status) : i40e_nvmupd_state_writing()
980 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; i40e_nvmupd_state_writing()
982 hw->aq.nvm_release_on_done = true; i40e_nvmupd_state_writing()
983 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; i40e_nvmupd_state_writing()
988 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_state_writing()
1002 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && i40e_nvmupd_state_writing()
1005 u32 old_asq_status = hw->aq.asq_last_status; i40e_nvmupd_state_writing()
1008 gtime = rd32(hw, I40E_GLVFGEN_TIMER); i40e_nvmupd_state_writing()
1009 if (gtime >= hw->nvm.hw_semaphore_timeout) { i40e_nvmupd_state_writing()
1010 i40e_debug(hw, I40E_DEBUG_ALL, i40e_nvmupd_state_writing()
1012 gtime, hw->nvm.hw_semaphore_timeout); i40e_nvmupd_state_writing()
1013 i40e_release_nvm(hw); i40e_nvmupd_state_writing()
1014 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); i40e_nvmupd_state_writing()
1016 i40e_debug(hw, I40E_DEBUG_ALL, i40e_nvmupd_state_writing()
1018 hw->aq.asq_last_status); i40e_nvmupd_state_writing()
1020 hw->aq.asq_last_status = old_asq_status; i40e_nvmupd_state_writing()
1033 * @hw: pointer to hardware structure
1039 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, i40e_nvmupd_validate_command() argument
1055 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_validate_command()
1125 * @hw: pointer to hardware structure
1132 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, i40e_nvmupd_exec_aq() argument
1144 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); i40e_nvmupd_exec_aq()
1146 cmd_details.wb_desc = &hw->nvm_wb_desc; i40e_nvmupd_exec_aq()
1149 memset(&hw->nvm_wb_desc, 0, aq_desc_len); i40e_nvmupd_exec_aq()
1153 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_exec_aq()
1165 if (!hw->nvm_buff.va) { i40e_nvmupd_exec_aq()
1166 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff, i40e_nvmupd_exec_aq()
1167 hw->aq.asq_buf_size); i40e_nvmupd_exec_aq()
1169 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_exec_aq()
1174 if (hw->nvm_buff.va) { i40e_nvmupd_exec_aq()
1175 buff = hw->nvm_buff.va; i40e_nvmupd_exec_aq()
1181 status = i40e_asq_send_command(hw, aq_desc, buff, i40e_nvmupd_exec_aq()
1184 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_exec_aq()
1186 i40e_stat_str(hw, status), i40e_nvmupd_exec_aq()
1187 i40e_aq_str(hw, hw->aq.asq_last_status)); i40e_nvmupd_exec_aq()
1188 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); i40e_nvmupd_exec_aq()
1196 * @hw: pointer to hardware structure
1203 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, i40e_nvmupd_get_aq_result() argument
1212 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); i40e_nvmupd_get_aq_result()
1215 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen); i40e_nvmupd_get_aq_result()
1219 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n", i40e_nvmupd_get_aq_result()
1229 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n", i40e_nvmupd_get_aq_result()
1239 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n", i40e_nvmupd_get_aq_result()
1242 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset; i40e_nvmupd_get_aq_result()
1247 buff = hw->nvm_buff.va; i40e_nvmupd_get_aq_result()
1249 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len); i40e_nvmupd_get_aq_result()
1253 int start_byte = buff - (u8 *)hw->nvm_buff.va; i40e_nvmupd_get_aq_result()
1255 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n", i40e_nvmupd_get_aq_result()
1265 * @hw: pointer to hardware structure
1272 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, i40e_nvmupd_nvm_read() argument
1286 cmd_details.wb_desc = &hw->nvm_wb_desc; i40e_nvmupd_nvm_read()
1288 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, i40e_nvmupd_nvm_read()
1291 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_nvm_read()
1294 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_nvm_read()
1296 status, hw->aq.asq_last_status); i40e_nvmupd_nvm_read()
1297 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); i40e_nvmupd_nvm_read()
1305 * @hw: pointer to hardware structure
1311 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, i40e_nvmupd_nvm_erase() argument
1325 cmd_details.wb_desc = &hw->nvm_wb_desc; i40e_nvmupd_nvm_erase()
1327 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, i40e_nvmupd_nvm_erase()
1330 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_nvm_erase()
1333 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_nvm_erase()
1335 status, hw->aq.asq_last_status); i40e_nvmupd_nvm_erase()
1336 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); i40e_nvmupd_nvm_erase()
1344 * @hw: pointer to hardware structure
1351 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, i40e_nvmupd_nvm_write() argument
1365 cmd_details.wb_desc = &hw->nvm_wb_desc; i40e_nvmupd_nvm_write()
1367 status = i40e_aq_update_nvm(hw, module, cmd->offset, i40e_nvmupd_nvm_write()
1371 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_nvm_write()
1374 i40e_debug(hw, I40E_DEBUG_NVM, i40e_nvmupd_nvm_write()
1376 status, hw->aq.asq_last_status); i40e_nvmupd_nvm_write()
1377 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); i40e_nvmupd_nvm_write()
/linux-4.4.14/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.c32 int atl1c_check_eeprom_exist(struct atl1c_hw *hw) atl1c_check_eeprom_exist() argument
36 AT_READ_REG(hw, REG_TWSI_DEBUG, &data); atl1c_check_eeprom_exist()
40 AT_READ_REG(hw, REG_MASTER_CTRL, &data); atl1c_check_eeprom_exist()
46 void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr) atl1c_hw_set_mac_addr() argument
58 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); atl1c_hw_set_mac_addr()
62 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); atl1c_hw_set_mac_addr()
66 static bool atl1c_read_current_addr(struct atl1c_hw *hw, u8 *eth_addr) atl1c_read_current_addr() argument
70 AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]); atl1c_read_current_addr()
71 AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]); atl1c_read_current_addr()
83 static int atl1c_get_permanent_address(struct atl1c_hw *hw) atl1c_get_permanent_address() argument
92 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) atl1c_get_permanent_address()
96 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); atl1c_get_permanent_address()
97 if (atl1c_check_eeprom_exist(hw)) { atl1c_get_permanent_address()
98 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { atl1c_get_permanent_address()
102 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); atl1c_get_permanent_address()
103 AT_WRITE_FLUSH(hw); atl1c_get_permanent_address()
108 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { atl1c_get_permanent_address()
109 atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data); atl1c_get_permanent_address()
111 atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data); atl1c_get_permanent_address()
112 atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); atl1c_get_permanent_address()
114 atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); atl1c_get_permanent_address()
119 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data); atl1c_get_permanent_address()
121 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); atl1c_get_permanent_address()
124 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data); atl1c_get_permanent_address()
132 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) { atl1c_get_permanent_address()
134 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); atl1c_get_permanent_address()
138 atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data); atl1c_get_permanent_address()
140 atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data); atl1c_get_permanent_address()
141 atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); atl1c_get_permanent_address()
143 atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); atl1c_get_permanent_address()
147 if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) atl1c_get_permanent_address()
153 bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value) atl1c_read_eeprom() argument
164 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); atl1c_read_eeprom()
166 AT_WRITE_REG(hw, REG_OTP_CTRL, atl1c_read_eeprom()
169 AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0); atl1c_read_eeprom()
171 AT_WRITE_REG(hw, REG_EEPROM_CTRL, control); atl1c_read_eeprom()
175 AT_READ_REG(hw, REG_EEPROM_CTRL, &control); atl1c_read_eeprom()
180 AT_READ_REG(hw, REG_EEPROM_CTRL, &data); atl1c_read_eeprom()
181 AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value); atl1c_read_eeprom()
187 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); atl1c_read_eeprom()
194 * hw - Struct containing variables accessed by shared code
196 int atl1c_read_mac_addr(struct atl1c_hw *hw) atl1c_read_mac_addr() argument
200 err = atl1c_get_permanent_address(hw); atl1c_read_mac_addr()
202 eth_random_addr(hw->perm_mac_addr); atl1c_read_mac_addr()
204 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); atl1c_read_mac_addr()
216 u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr) atl1c_hash_mc_addr() argument
231 * hw - Struct containing variables accessed by shared code
234 void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value) atl1c_hash_set() argument
251 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); atl1c_hash_set()
255 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); atl1c_hash_set()
263 bool atl1c_wait_mdio_idle(struct atl1c_hw *hw) atl1c_wait_mdio_idle() argument
269 AT_READ_REG(hw, REG_MDIO_CTRL, &val); atl1c_wait_mdio_idle()
278 void atl1c_stop_phy_polling(struct atl1c_hw *hw) atl1c_stop_phy_polling() argument
280 if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION)) atl1c_stop_phy_polling()
283 AT_WRITE_REG(hw, REG_MDIO_CTRL, 0); atl1c_stop_phy_polling()
284 atl1c_wait_mdio_idle(hw); atl1c_stop_phy_polling()
287 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel) atl1c_start_phy_polling() argument
291 if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION)) atl1c_start_phy_polling()
299 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); atl1c_start_phy_polling()
300 atl1c_wait_mdio_idle(hw); atl1c_start_phy_polling()
303 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); atl1c_start_phy_polling()
315 int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, atl1c_read_phy_core() argument
321 atl1c_stop_phy_polling(hw); atl1c_read_phy_core()
326 if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) && atl1c_read_phy_core()
327 hw->hibernate) atl1c_read_phy_core()
331 AT_WRITE_REG(hw, REG_MDIO_EXTN, val); atl1c_read_phy_core()
344 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); atl1c_read_phy_core()
346 if (!atl1c_wait_mdio_idle(hw)) atl1c_read_phy_core()
349 AT_READ_REG(hw, REG_MDIO_CTRL, &val); atl1c_read_phy_core()
352 atl1c_start_phy_polling(hw, clk_sel); atl1c_read_phy_core()
364 int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, atl1c_write_phy_core() argument
370 atl1c_stop_phy_polling(hw); atl1c_write_phy_core()
374 if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) && atl1c_write_phy_core()
375 hw->hibernate) atl1c_write_phy_core()
380 AT_WRITE_REG(hw, REG_MDIO_EXTN, val); atl1c_write_phy_core()
393 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); atl1c_write_phy_core()
395 if (!atl1c_wait_mdio_idle(hw)) atl1c_write_phy_core()
398 atl1c_start_phy_polling(hw, clk_sel); atl1c_write_phy_core()
405 * hw - Struct containing variables accessed by shared code
408 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) atl1c_read_phy_reg() argument
410 return atl1c_read_phy_core(hw, false, 0, reg_addr, phy_data); atl1c_read_phy_reg()
415 * hw - Struct containing variables accessed by shared code
419 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data) atl1c_write_phy_reg() argument
421 return atl1c_write_phy_core(hw, false, 0, reg_addr, phy_data); atl1c_write_phy_reg()
425 int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, atl1c_read_phy_ext() argument
428 return atl1c_read_phy_core(hw, true, dev_addr, reg_addr, phy_data); atl1c_read_phy_ext()
432 int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, atl1c_write_phy_ext() argument
435 return atl1c_write_phy_core(hw, true, dev_addr, reg_addr, phy_data); atl1c_write_phy_ext()
438 int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) atl1c_read_phy_dbg() argument
442 err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr); atl1c_read_phy_dbg()
446 err = atl1c_read_phy_reg(hw, MII_DBG_DATA, phy_data); atl1c_read_phy_dbg()
451 int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data) atl1c_write_phy_dbg() argument
455 err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr); atl1c_write_phy_dbg()
459 err = atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data); atl1c_write_phy_dbg()
467 * hw - Struct containing variables accessed by shared code
469 static int atl1c_phy_setup_adv(struct atl1c_hw *hw) atl1c_phy_setup_adv() argument
475 if (hw->autoneg_advertised & ADVERTISED_10baseT_Half) atl1c_phy_setup_adv()
477 if (hw->autoneg_advertised & ADVERTISED_10baseT_Full) atl1c_phy_setup_adv()
479 if (hw->autoneg_advertised & ADVERTISED_100baseT_Half) atl1c_phy_setup_adv()
481 if (hw->autoneg_advertised & ADVERTISED_100baseT_Full) atl1c_phy_setup_adv()
484 if (hw->autoneg_advertised & ADVERTISED_Autoneg) atl1c_phy_setup_adv()
488 if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) { atl1c_phy_setup_adv()
489 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half) atl1c_phy_setup_adv()
491 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full) atl1c_phy_setup_adv()
493 if (hw->autoneg_advertised & ADVERTISED_Autoneg) atl1c_phy_setup_adv()
498 if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 || atl1c_phy_setup_adv()
499 atl1c_write_phy_reg(hw, MII_CTRL1000, mii_giga_ctrl_data) != 0) atl1c_phy_setup_adv()
504 void atl1c_phy_disable(struct atl1c_hw *hw) atl1c_phy_disable() argument
506 atl1c_power_saving(hw, 0); atl1c_phy_disable()
510 int atl1c_phy_reset(struct atl1c_hw *hw) atl1c_phy_reset() argument
512 struct atl1c_adapter *adapter = hw->adapter; atl1c_phy_reset()
519 AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data); atl1c_phy_reset()
523 if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE)) atl1c_phy_reset()
527 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data); atl1c_phy_reset()
528 AT_WRITE_FLUSH(hw); atl1c_phy_reset()
530 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data | GPHY_CTRL_EXT_RESET); atl1c_phy_reset()
531 AT_WRITE_FLUSH(hw); atl1c_phy_reset()
535 if (hw->nic_type == athr_l2c_b) { atl1c_phy_reset()
536 atl1c_read_phy_dbg(hw, MIIDBG_CFGLPSPD, &phy_data); atl1c_phy_reset()
537 atl1c_write_phy_dbg(hw, MIIDBG_CFGLPSPD, atl1c_phy_reset()
542 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { atl1c_phy_reset()
543 atl1c_read_phy_dbg(hw, MIIDBG_CABLE1TH_DET, &phy_data); atl1c_phy_reset()
545 atl1c_write_phy_dbg(hw, MIIDBG_CABLE1TH_DET, phy_data); atl1c_phy_reset()
549 if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE)) { atl1c_phy_reset()
550 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { atl1c_phy_reset()
551 atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); atl1c_phy_reset()
553 atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); atl1c_phy_reset()
557 hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 ? atl1c_phy_reset()
559 atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS, phy_data); atl1c_phy_reset()
561 atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL, atl1c_phy_reset()
565 atl1c_read_phy_dbg(hw, MIIDBG_LEGCYPS, &phy_data); atl1c_phy_reset()
566 atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS, atl1c_phy_reset()
569 atl1c_read_phy_dbg(hw, MIIDBG_HIBNEG, &phy_data); atl1c_phy_reset()
570 atl1c_write_phy_dbg(hw, MIIDBG_HIBNEG, atl1c_phy_reset()
574 if (hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 || atl1c_phy_reset()
575 hw->nic_type == athr_l2c_b2) { atl1c_phy_reset()
576 AT_READ_REG(hw, REG_LPI_CTRL, &lpi_ctrl); atl1c_phy_reset()
577 AT_WRITE_REG(hw, REG_LPI_CTRL, lpi_ctrl & ~LPI_CTRL_EN); atl1c_phy_reset()
578 atl1c_write_phy_ext(hw, MIIEXT_ANEG, MIIEXT_LOCAL_EEEADV, 0); atl1c_phy_reset()
579 atl1c_write_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL3, atl1c_phy_reset()
584 atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, ANACTRL_DEF); atl1c_phy_reset()
585 atl1c_write_phy_dbg(hw, MIIDBG_SRDSYSMOD, SRDSYSMOD_DEF); atl1c_phy_reset()
586 atl1c_write_phy_dbg(hw, MIIDBG_TST10BTCFG, TST10BTCFG_DEF); atl1c_phy_reset()
588 atl1c_write_phy_dbg(hw, MIIDBG_TST100BTCFG, atl1c_phy_reset()
593 err = atl1c_write_phy_reg(hw, MII_IER, phy_data); atl1c_phy_reset()
603 int atl1c_phy_init(struct atl1c_hw *hw) atl1c_phy_init() argument
605 struct atl1c_adapter *adapter = hw->adapter; atl1c_phy_init()
610 if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id1) != 0) || atl1c_phy_init()
611 (atl1c_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id2) != 0)) { atl1c_phy_init()
615 switch (hw->media_type) { atl1c_phy_init()
617 ret_val = atl1c_phy_setup_adv(hw); atl1c_phy_init()
640 hw->media_type); atl1c_phy_init()
644 ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data); atl1c_phy_init()
647 hw->phy_configured = true; atl1c_phy_init()
655 * hw - Struct containing variables accessed by shared code
659 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex) atl1c_get_speed_and_duplex() argument
665 err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data); atl1c_get_speed_and_duplex()
695 int atl1c_phy_to_ps_link(struct atl1c_hw *hw) atl1c_phy_to_ps_link() argument
697 struct atl1c_adapter *adapter = hw->adapter; atl1c_phy_to_ps_link()
708 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); atl1c_phy_to_ps_link()
709 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); atl1c_phy_to_ps_link()
711 atl1c_read_phy_reg(hw, MII_LPA, &mii_lpa_data); atl1c_phy_to_ps_link()
721 save_autoneg_advertised = hw->autoneg_advertised; atl1c_phy_to_ps_link()
722 hw->phy_configured = false; atl1c_phy_to_ps_link()
723 hw->autoneg_advertised = autoneg_advertised; atl1c_phy_to_ps_link()
724 if (atl1c_restart_autoneg(hw) != 0) { atl1c_phy_to_ps_link()
728 hw->autoneg_advertised = save_autoneg_advertised; atl1c_phy_to_ps_link()
733 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); atl1c_phy_to_ps_link()
734 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); atl1c_phy_to_ps_link()
736 if (atl1c_get_speed_and_duplex(hw, &speed, atl1c_phy_to_ps_link()
754 int atl1c_restart_autoneg(struct atl1c_hw *hw) atl1c_restart_autoneg() argument
759 err = atl1c_phy_setup_adv(hw); atl1c_restart_autoneg()
764 return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data); atl1c_restart_autoneg()
767 int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc) atl1c_power_saving() argument
769 struct atl1c_adapter *adapter = hw->adapter; atl1c_power_saving()
779 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl); atl1c_power_saving()
780 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl); atl1c_power_saving()
781 AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl); atl1c_power_saving()
794 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl); atl1c_power_saving()
795 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl); atl1c_power_saving()
796 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl); atl1c_power_saving()
797 AT_WRITE_REG(hw, REG_WOL_CTRL, 0); atl1c_power_saving()
798 hw->phy_configured = false; /* re-init PHY when resume */ atl1c_power_saving()
805 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V11) atl1c_power_saving()
810 if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) { atl1c_power_saving()
816 atl1c_read_phy_reg(hw, MII_ISR, &phy_data); atl1c_power_saving()
820 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl); atl1c_power_saving()
821 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl); atl1c_power_saving()
822 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl); atl1c_power_saving()
823 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl); atl1c_power_saving()
830 void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed) atl1c_post_phy_linkchg() argument
835 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 || atl1c_post_phy_linkchg()
836 hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2) atl1c_post_phy_linkchg()
841 if (hw->nic_type == athr_l1d_2) { atl1c_post_phy_linkchg()
842 atl1c_read_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL6, atl1c_post_phy_linkchg()
847 atl1c_write_phy_dbg(hw, MIIDBG_AZ_ANADECT, phy_val); atl1c_post_phy_linkchg()
850 if (adj_thresh && link_speed == SPEED_100 && hw->msi_lnkpatch) { atl1c_post_phy_linkchg()
851 atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, L1D_MSE16DB_UP); atl1c_post_phy_linkchg()
852 atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL, atl1c_post_phy_linkchg()
856 if (adj_thresh && hw->msi_lnkpatch) { atl1c_post_phy_linkchg()
857 atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL, atl1c_post_phy_linkchg()
859 atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, atl1c_post_phy_linkchg()
H A Datl1c_ethtool.c33 struct atl1c_hw *hw = &adapter->hw; atl1c_get_settings() local
41 if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) atl1c_get_settings()
46 ecmd->advertising |= hw->autoneg_advertised; atl1c_get_settings()
71 struct atl1c_hw *hw = &adapter->hw; atl1c_set_settings() local
103 if (hw->autoneg_advertised != autoneg_advertised) { atl1c_set_settings()
104 hw->autoneg_advertised = autoneg_advertised; atl1c_set_settings()
105 if (atl1c_restart_autoneg(hw) != 0) { atl1c_set_settings()
138 struct atl1c_hw *hw = &adapter->hw; atl1c_get_regs() local
145 AT_READ_REG(hw, REG_PM_CTRL, p++); atl1c_get_regs()
146 AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++); atl1c_get_regs()
147 AT_READ_REG(hw, REG_TWSI_CTRL, p++); atl1c_get_regs()
148 AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL, p++); atl1c_get_regs()
149 AT_READ_REG(hw, REG_MASTER_CTRL, p++); atl1c_get_regs()
150 AT_READ_REG(hw, REG_MANUAL_TIMER_INIT, p++); atl1c_get_regs()
151 AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++); atl1c_get_regs()
152 AT_READ_REG(hw, REG_GPHY_CTRL, p++); atl1c_get_regs()
153 AT_READ_REG(hw, REG_LINK_CTRL, p++); atl1c_get_regs()
154 AT_READ_REG(hw, REG_IDLE_STATUS, p++); atl1c_get_regs()
155 AT_READ_REG(hw, REG_MDIO_CTRL, p++); atl1c_get_regs()
156 AT_READ_REG(hw, REG_SERDES, p++); atl1c_get_regs()
157 AT_READ_REG(hw, REG_MAC_CTRL, p++); atl1c_get_regs()
158 AT_READ_REG(hw, REG_MAC_IPG_IFG, p++); atl1c_get_regs()
159 AT_READ_REG(hw, REG_MAC_STA_ADDR, p++); atl1c_get_regs()
160 AT_READ_REG(hw, REG_MAC_STA_ADDR+4, p++); atl1c_get_regs()
161 AT_READ_REG(hw, REG_RX_HASH_TABLE, p++); atl1c_get_regs()
162 AT_READ_REG(hw, REG_RX_HASH_TABLE+4, p++); atl1c_get_regs()
163 AT_READ_REG(hw, REG_RXQ_CTRL, p++); atl1c_get_regs()
164 AT_READ_REG(hw, REG_TXQ_CTRL, p++); atl1c_get_regs()
165 AT_READ_REG(hw, REG_MTU, p++); atl1c_get_regs()
166 AT_READ_REG(hw, REG_WOL_CTRL, p++); atl1c_get_regs()
168 atl1c_read_phy_reg(hw, MII_BMCR, &phy_data); atl1c_get_regs()
170 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); atl1c_get_regs()
178 if (atl1c_check_eeprom_exist(&adapter->hw)) atl1c_get_eeprom_len()
188 struct atl1c_hw *hw = &adapter->hw; atl1c_get_eeprom() local
197 if (!atl1c_check_eeprom_exist(hw)) /* not exist */ atl1c_get_eeprom()
212 if (!atl1c_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) { atl1c_get_eeprom()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dhw.h29 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
30 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw);
32 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
34 int rtl8821ae_hw_init(struct ieee80211_hw *hw);
35 void rtl8821ae_card_disable(struct ieee80211_hw *hw);
36 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw);
37 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw);
38 int rtl8821ae_set_network_type(struct ieee80211_hw *hw,
40 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
41 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci);
42 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw);
43 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw);
44 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
46 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
47 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
50 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw);
51 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
52 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw);
53 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
57 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw);
58 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw);
59 void rtl8821ae_suspend(struct ieee80211_hw *hw);
60 void rtl8821ae_resume(struct ieee80211_hw *hw);
61 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
64 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw);
65 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw);
66 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
H A DMakefile4 hw.o \
H A Dphy.h46 #define RT_CANNOT_IO(hw) false
208 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
210 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
212 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
215 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
218 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
219 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
220 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
221 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw,
223 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
224 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
226 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw,
228 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
230 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
231 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
233 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
234 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
235 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw,
237 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw,
239 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
240 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
241 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
242 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
244 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
246 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
247 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
250 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
252 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
254 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
256 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
257 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, u8 rf_path);
H A Dled.c31 static void _rtl8821ae_init_led(struct ieee80211_hw *hw, _rtl8821ae_init_led() argument
35 pled->hw = hw; _rtl8821ae_init_led()
40 void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl8821ae_sw_led_on() argument
43 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_sw_led_on()
69 void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl8812ae_sw_led_on() argument
73 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8812ae_sw_led_on()
101 void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl8821ae_sw_led_off() argument
103 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_sw_led_off()
104 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl8821ae_sw_led_off()
142 void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl8812ae_sw_led_off() argument
145 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8812ae_sw_led_off()
146 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl8812ae_sw_led_off()
183 void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw) rtl8821ae_init_sw_leds() argument
185 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl8821ae_init_sw_leds()
187 _rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0); rtl8821ae_init_sw_leds()
188 _rtl8821ae_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1); rtl8821ae_init_sw_leds()
191 static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw, _rtl8821ae_sw_led_control() argument
194 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8821ae_sw_led_control()
196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8821ae_sw_led_control()
203 rtl8812ae_sw_led_on(hw, pLed0); _rtl8821ae_sw_led_control()
205 rtl8821ae_sw_led_on(hw, pLed0); _rtl8821ae_sw_led_control()
209 rtl8812ae_sw_led_off(hw, pLed0); _rtl8821ae_sw_led_control()
211 rtl8821ae_sw_led_off(hw, pLed0); _rtl8821ae_sw_led_control()
218 void rtl8821ae_led_control(struct ieee80211_hw *hw, rtl8821ae_led_control() argument
221 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_led_control()
222 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8821ae_led_control()
236 _rtl8821ae_sw_led_control(hw, ledaction); rtl8821ae_led_control()
H A Dphy.c37 #include "hw.h"
47 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
49 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
53 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
54 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/
55 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
56 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
58 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
60 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
62 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
65 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
66 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
68 static void rtl8812ae_fixspur(struct ieee80211_hw *hw, rtl8812ae_fixspur() argument
71 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8812ae_fixspur()
76 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3); rtl8812ae_fixspur()
79 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2); rtl8812ae_fixspur()
87 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); rtl8812ae_fixspur()
89 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); rtl8812ae_fixspur()
93 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); rtl8812ae_fixspur()
96 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2); rtl8812ae_fixspur()
98 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); rtl8812ae_fixspur()
107 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); rtl8812ae_fixspur()
110 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2); rtl8812ae_fixspur()
115 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, rtl8821ae_phy_query_bb_reg() argument
118 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_query_bb_reg()
134 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw, rtl8821ae_phy_set_bb_reg() argument
137 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_bb_reg()
158 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw, rtl8821ae_phy_query_rf_reg() argument
162 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_query_rf_reg()
172 original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); rtl8821ae_phy_query_rf_reg()
185 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw, rtl8821ae_phy_set_rf_reg() argument
189 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_rf_reg()
201 _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); rtl8821ae_phy_set_rf_reg()
206 _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data); rtl8821ae_phy_set_rf_reg()
215 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw, _rtl8821ae_phy_rf_serial_read() argument
218 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_rf_serial_read()
219 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8821ae_phy_rf_serial_read()
225 if (RT_CANNOT_IO(hw)) { _rtl8821ae_phy_rf_serial_read()
235 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1); _rtl8821ae_phy_rf_serial_read()
239 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4); _rtl8821ae_phy_rf_serial_read()
241 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4); _rtl8821ae_phy_rf_serial_read()
243 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset); _rtl8821ae_phy_rf_serial_read()
252 rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA); _rtl8821ae_phy_rf_serial_read()
255 rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA); _rtl8821ae_phy_rf_serial_read()
259 rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA); _rtl8821ae_phy_rf_serial_read()
262 rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA); _rtl8821ae_phy_rf_serial_read()
272 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0); _rtl8821ae_phy_rf_serial_read()
276 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw, _rtl8821ae_phy_rf_serial_write() argument
280 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_rf_serial_write()
286 if (RT_CANNOT_IO(hw)) { _rtl8821ae_phy_rf_serial_write()
294 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl8821ae_phy_rf_serial_write()
311 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw) rtl8821ae_phy_mac_config() argument
315 rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw); rtl8821ae_phy_mac_config()
320 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw) rtl8821ae_phy_bb_config() argument
323 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_bb_config()
324 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8821ae_phy_bb_config()
326 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_bb_config()
330 phy_init_bb_rf_register_definition(hw); rtl8821ae_phy_bb_config()
341 rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw); rtl8821ae_phy_bb_config()
345 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000, rtl8821ae_phy_bb_config()
349 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, rtl8821ae_phy_bb_config()
357 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw) rtl8821ae_phy_rf_config() argument
359 return rtl8821ae_phy_rf6052_config(hw); rtl8821ae_phy_rf_config()
362 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, phy_get_tx_swing_8812A() argument
365 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_get_tx_swing_8812A()
366 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); phy_get_tx_swing_8812A()
368 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); phy_get_tx_swing_8812A()
425 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing); phy_get_tx_swing_8812A()
440 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing); phy_get_tx_swing_8812A()
520 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) rtl8821ae_phy_switch_wirelessband() argument
522 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_switch_wirelessband()
523 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_switch_wirelessband()
529 txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0); rtl8821ae_phy_switch_wirelessband()
530 rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000); rtl8821ae_phy_switch_wirelessband()
535 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03); rtl8821ae_phy_switch_wirelessband()
539 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7); rtl8821ae_phy_switch_wirelessband()
541 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7); rtl8821ae_phy_switch_wirelessband()
546 rtl_set_bbreg(hw, 0x834, 0x3, 0x1); rtl8821ae_phy_switch_wirelessband()
551 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0); rtl8821ae_phy_switch_wirelessband()
554 rtl_set_bbreg(hw, 0x82c, 0x3, 0); rtl8821ae_phy_switch_wirelessband()
557 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, rtl8821ae_phy_switch_wirelessband()
559 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, rtl8821ae_phy_switch_wirelessband()
561 rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x000); rtl8821ae_phy_switch_wirelessband()
562 rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x000); rtl8821ae_phy_switch_wirelessband()
565 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1); rtl8821ae_phy_switch_wirelessband()
566 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1); rtl8821ae_phy_switch_wirelessband()
574 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5); rtl8821ae_phy_switch_wirelessband()
576 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4); rtl8821ae_phy_switch_wirelessband()
603 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03); rtl8821ae_phy_switch_wirelessband()
607 rtl_set_bbreg(hw, 0x834, 0x3, 0x2); rtl8821ae_phy_switch_wirelessband()
613 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1); rtl8821ae_phy_switch_wirelessband()
616 rtl_set_bbreg(hw, 0x82c, 0x3, 1); rtl8821ae_phy_switch_wirelessband()
619 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, rtl8821ae_phy_switch_wirelessband()
621 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, rtl8821ae_phy_switch_wirelessband()
623 rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x010); rtl8821ae_phy_switch_wirelessband()
624 rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x010); rtl8821ae_phy_switch_wirelessband()
627 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0); rtl8821ae_phy_switch_wirelessband()
628 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf); rtl8821ae_phy_switch_wirelessband()
638 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8821ae_phy_switch_wirelessband()
639 phy_get_tx_swing_8812A(hw, band, RF90_PATH_A)); rtl8821ae_phy_switch_wirelessband()
641 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, rtl8821ae_phy_switch_wirelessband()
642 phy_get_tx_swing_8812A(hw, band, RF90_PATH_B)); rtl8821ae_phy_switch_wirelessband()
656 rtl8821ae_dm_clear_txpower_tracking_state(hw); rtl8821ae_phy_switch_wirelessband()
664 static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw, _rtl8821ae_check_condition() argument
667 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8821ae_check_condition()
692 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw, _rtl8821ae_config_rf_reg() argument
702 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); _rtl8821ae_config_rf_reg()
707 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw, _rtl8821ae_config_rf_radio_a() argument
713 _rtl8821ae_config_rf_reg(hw, addr, data, _rtl8821ae_config_rf_radio_a()
717 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw, _rtl8821ae_config_rf_radio_b() argument
723 _rtl8821ae_config_rf_reg(hw, addr, data, _rtl8821ae_config_rf_radio_b()
727 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw, _rtl8821ae_config_bb_reg() argument
743 rtl_set_bbreg(hw, addr, MASKDWORD, data); _rtl8821ae_config_bb_reg()
748 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) _rtl8821ae_phy_init_tx_power_by_rate() argument
750 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_init_tx_power_by_rate()
764 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, _rtl8821ae_phy_set_txpower_by_rate_base() argument
769 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_set_txpower_by_rate_base()
833 static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, _rtl8821ae_phy_get_txpower_by_rate_base() argument
837 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_get_txpower_by_rate_base()
905 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) _rtl8821ae_phy_store_txpower_by_rate_base() argument
907 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_store_txpower_by_rate_base()
915 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
919 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
923 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
927 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
931 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
935 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
939 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
943 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
947 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
951 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
955 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); _rtl8821ae_phy_store_txpower_by_rate_base()
984 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw) _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit() argument
986 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit()
1025 static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw, _rtl8812ae_phy_get_txpower_by_rate_base_index() argument
1028 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8812ae_phy_get_txpower_by_rate_base_index()
1150 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw) _rtl8812ae_phy_convert_txpower_limit_to_power_index() argument
1152 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1164 _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw); _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1174 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1178 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1182 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1186 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1231 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1235 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1239 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1243 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1247 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, _rtl8812ae_phy_convert_txpower_limit_to_power_index()
1290 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw) _rtl8821ae_phy_init_txpower_limit() argument
1292 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_init_txpower_limit()
1322 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw) _rtl8821ae_phy_convert_txpower_dbm_to_relative_value() argument
1324 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1329 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, CCK); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1334 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, OFDM); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1342 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, HT_MCS0_MCS7); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1350 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, HT_MCS8_MCS15); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1360 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1371 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1382 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, OFDM); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1390 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, HT_MCS0_MCS7); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1398 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, HT_MCS8_MCS15); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1406 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1417 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9); _rtl8821ae_phy_convert_txpower_dbm_to_relative_value()
1433 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw) _rtl8821ae_phy_txpower_by_rate_configuration() argument
1435 _rtl8821ae_phy_store_txpower_by_rate_base(hw); _rtl8821ae_phy_txpower_by_rate_configuration()
1436 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw); _rtl8821ae_phy_txpower_by_rate_configuration()
1470 static char _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt() argument
1473 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt()
1501 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation, _rtl8812ae_phy_set_txpower_limit() argument
1506 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8812ae_phy_set_txpower_limit()
1559 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, _rtl8812ae_phy_set_txpower_limit()
1583 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, _rtl8812ae_phy_set_txpower_limit()
1612 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw, _rtl8812ae_phy_config_bb_txpwr_lmt() argument
1618 _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth, _rtl8812ae_phy_config_bb_txpwr_lmt()
1623 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) _rtl8821ae_phy_read_and_config_txpwr_lmt() argument
1625 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_read_and_config_txpwr_lmt()
1651 _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band, _rtl8821ae_phy_read_and_config_txpwr_lmt()
1657 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw) _rtl8821ae_phy_bb8821a_config_parafile() argument
1659 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_bb8821a_config_parafile()
1661 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8821ae_phy_bb8821a_config_parafile()
1664 _rtl8821ae_phy_init_txpower_limit(hw); _rtl8821ae_phy_bb8821a_config_parafile()
1668 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw); _rtl8821ae_phy_bb8821a_config_parafile()
1670 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw, _rtl8821ae_phy_bb8821a_config_parafile()
1676 _rtl8821ae_phy_init_tx_power_by_rate(hw); _rtl8821ae_phy_bb8821a_config_parafile()
1678 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw, _rtl8821ae_phy_bb8821a_config_parafile()
1686 _rtl8821ae_phy_txpower_by_rate_configuration(hw); _rtl8821ae_phy_bb8821a_config_parafile()
1690 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw); _rtl8821ae_phy_bb8821a_config_parafile()
1692 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw, _rtl8821ae_phy_bb8821a_config_parafile()
1699 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, _rtl8821ae_phy_bb8821a_config_parafile()
1704 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl8821ae_phy_config_mac_with_headerfile() argument
1706 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_config_mac_with_headerfile()
1729 if (!_rtl8821ae_check_condition(hw, v1)) { _rtl8821ae_phy_config_mac_with_headerfile()
1755 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, _rtl8821ae_phy_config_bb_with_headerfile() argument
1758 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_config_bb_with_headerfile()
1778 _rtl8821ae_config_bb_reg(hw, v1, v2); _rtl8821ae_phy_config_bb_with_headerfile()
1781 if (!_rtl8821ae_check_condition(hw, v1)) { _rtl8821ae_phy_config_bb_with_headerfile()
1799 _rtl8821ae_config_bb_reg(hw, v1, _rtl8821ae_phy_config_bb_with_headerfile()
1826 rtl_set_bbreg(hw, v1, MASKDWORD, v2); _rtl8821ae_phy_config_bb_with_headerfile()
1830 if (!_rtl8821ae_check_condition(hw, v1)) { _rtl8821ae_phy_config_bb_with_headerfile()
1847 rtl_set_bbreg(hw, v1, MASKDWORD, _rtl8821ae_phy_config_bb_with_headerfile()
1883 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw, _rtl8821ae_store_tx_power_by_rate() argument
1888 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_store_tx_power_by_rate()
1911 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, _rtl8821ae_phy_config_bb_with_pgheaderfile() argument
1914 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_config_bb_with_pgheaderfile()
1963 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, _rtl8821ae_phy_config_bb_with_pgheaderfile()
1968 if (!_rtl8821ae_check_condition(hw, v1)) { _rtl8821ae_phy_config_bb_with_pgheaderfile()
1986 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl8812ae_phy_config_rf_with_headerfile() argument
1993 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8812ae_phy_config_rf_with_headerfile()
2010 _rtl8821ae_config_rf_radio_a(hw, v1, v2); rtl8812ae_phy_config_rf_with_headerfile()
2013 if (!_rtl8821ae_check_condition(hw, v1)) { rtl8812ae_phy_config_rf_with_headerfile()
2027 _rtl8821ae_config_rf_radio_a(hw, v1, v2); rtl8812ae_phy_config_rf_with_headerfile()
2043 _rtl8821ae_config_rf_radio_b(hw, v1, v2); rtl8812ae_phy_config_rf_with_headerfile()
2046 if (!_rtl8821ae_check_condition(hw, v1)) { rtl8812ae_phy_config_rf_with_headerfile()
2060 _rtl8821ae_config_rf_radio_b(hw, v1, v2); rtl8812ae_phy_config_rf_with_headerfile()
2082 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl8821ae_phy_config_rf_with_headerfile() argument
2097 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_config_rf_with_headerfile()
2098 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */ rtl8821ae_phy_config_rf_with_headerfile()
2113 _rtl8821ae_config_rf_radio_a(hw, v1, v2); rtl8821ae_phy_config_rf_with_headerfile()
2115 if (!_rtl8821ae_check_condition(hw, v1)) { rtl8821ae_phy_config_rf_with_headerfile()
2129 _rtl8821ae_config_rf_radio_a(hw, v1, v2); rtl8821ae_phy_config_rf_with_headerfile()
2156 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl8821ae_phy_get_hw_reg_originalvalue() argument
2158 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_get_hw_reg_originalvalue()
2162 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl8821ae_phy_get_hw_reg_originalvalue()
2164 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl8821ae_phy_get_hw_reg_originalvalue()
2166 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl8821ae_phy_get_hw_reg_originalvalue()
2168 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl8821ae_phy_get_hw_reg_originalvalue()
2177 rtlphy->framesync = (u8)rtl_get_bbreg(hw, rtl8821ae_phy_get_hw_reg_originalvalue()
2179 rtlphy->framesync_c34 = rtl_get_bbreg(hw, rtl8821ae_phy_get_hw_reg_originalvalue()
2187 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) phy_init_bb_rf_register_definition() argument
2189 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_init_bb_rf_register_definition()
2214 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) rtl8821ae_phy_get_txpower_level() argument
2216 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_get_txpower_level()
2222 txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw, rtl8821ae_phy_get_txpower_level()
2225 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw, rtl8821ae_phy_get_txpower_level()
2229 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, rtl8821ae_phy_get_txpower_level()
2232 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw, rtl8821ae_phy_get_txpower_level()
2236 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, rtl8821ae_phy_get_txpower_level()
2365 static char _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw, _rtl8812ae_phy_get_txpower_limit() argument
2371 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8812ae_phy_get_txpower_limit()
2480 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, _rtl8812ae_phy_get_txpower_limit()
2483 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, _rtl8812ae_phy_get_txpower_limit()
2534 static char _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw, _rtl8821ae_phy_get_txpower_by_rate() argument
2537 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_get_txpower_by_rate()
2621 limit = _rtl8812ae_phy_get_txpower_limit(hw, band, _rtl8821ae_phy_get_txpower_by_rate()
2645 static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path, _rtl8821ae_get_txpower_index() argument
2648 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_get_txpower_index()
2650 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8821ae_get_txpower_index()
2755 _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g), _rtl8821ae_get_txpower_index()
2775 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw, _rtl8821ae_phy_set_txpower_index() argument
2778 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_set_txpower_index()
2783 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2787 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2791 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2795 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2799 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
2803 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
2807 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
2811 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
2815 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
2819 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
2823 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
2827 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
2831 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
2835 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
2839 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
2843 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
2847 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
2851 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
2855 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
2859 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
2863 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
2867 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
2871 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
2875 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
2879 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
2883 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
2887 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
2891 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
2895 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
2899 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
2903 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
2907 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
2911 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
2915 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
2919 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
2923 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
2927 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
2931 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
2935 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
2939 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
2943 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
2947 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
2951 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
2955 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
2959 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
2963 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
2967 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
2971 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
2982 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2986 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2990 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2994 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, _rtl8821ae_phy_set_txpower_index()
2998 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
3002 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
3006 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
3010 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, _rtl8821ae_phy_set_txpower_index()
3014 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
3018 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
3022 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
3026 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, _rtl8821ae_phy_set_txpower_index()
3030 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
3034 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
3038 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
3042 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, _rtl8821ae_phy_set_txpower_index()
3046 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
3050 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
3054 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
3058 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, _rtl8821ae_phy_set_txpower_index()
3062 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
3066 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
3070 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
3074 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, _rtl8821ae_phy_set_txpower_index()
3078 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
3082 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
3086 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
3090 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, _rtl8821ae_phy_set_txpower_index()
3094 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
3098 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
3102 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
3106 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, _rtl8821ae_phy_set_txpower_index()
3110 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
3114 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
3118 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
3122 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, _rtl8821ae_phy_set_txpower_index()
3126 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
3130 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
3134 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
3138 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, _rtl8821ae_phy_set_txpower_index()
3142 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
3146 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
3150 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
3154 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, _rtl8821ae_phy_set_txpower_index()
3158 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
3162 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
3166 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
3170 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, _rtl8821ae_phy_set_txpower_index()
3184 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, _rtl8821ae_phy_set_txpower_level_by_path() argument
3188 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_set_txpower_level_by_path()
3195 _rtl8821ae_get_txpower_index(hw, path, array[i], _rtl8821ae_phy_set_txpower_level_by_path()
3198 _rtl8821ae_phy_set_txpower_index(hw, power_index, path, _rtl8821ae_phy_set_txpower_level_by_path()
3203 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw, _rtl8821ae_phy_txpower_training_by_path() argument
3206 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_txpower_training_by_path()
3218 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A, _rtl8821ae_phy_txpower_training_by_path()
3223 _rtl8821ae_get_txpower_index(hw, RF90_PATH_B, _rtl8821ae_phy_txpower_training_by_path()
3238 rtl_set_bbreg(hw, offset, 0xffffff, data); _rtl8821ae_phy_txpower_training_by_path()
3241 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, rtl8821ae_phy_set_txpower_level_by_path() argument
3244 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */ rtl8821ae_phy_set_txpower_level_by_path()
3245 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_set_txpower_level_by_path()
3246 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_txpower_level_by_path()
3277 _rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel, rtl8821ae_phy_set_txpower_level_by_path()
3280 _rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel, rtl8821ae_phy_set_txpower_level_by_path()
3282 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel, rtl8821ae_phy_set_txpower_level_by_path()
3284 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel, rtl8821ae_phy_set_txpower_level_by_path()
3288 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path, rtl8821ae_phy_set_txpower_level_by_path()
3291 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path, rtl8821ae_phy_set_txpower_level_by_path()
3296 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, rtl8821ae_phy_set_txpower_level_by_path()
3301 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl8821ae_phy_set_txpower_level() argument
3303 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_txpower_level()
3308 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path); rtl8821ae_phy_set_txpower_level()
3311 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, _rtl8821ae_phy_txpwr_idx_to_dbm() argument
3334 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) rtl8821ae_phy_scan_operation_backup() argument
3336 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_scan_operation_backup()
3337 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_scan_operation_backup()
3344 rtlpriv->cfg->ops->set_hw_reg(hw, rtl8821ae_phy_scan_operation_backup()
3351 rtlpriv->cfg->ops->set_hw_reg(hw, rtl8821ae_phy_scan_operation_backup()
3358 rtlpriv->cfg->ops->set_hw_reg(hw, rtl8821ae_phy_scan_operation_backup()
3435 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl8821ae_phy_set_bw_mode_callback() argument
3437 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_bw_mode_callback()
3455 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200); rtl8821ae_phy_set_bw_mode_callback()
3456 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); rtl8821ae_phy_set_bw_mode_callback()
3459 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7); rtl8821ae_phy_set_bw_mode_callback()
3461 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8); rtl8821ae_phy_set_bw_mode_callback()
3464 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201); rtl8821ae_phy_set_bw_mode_callback()
3465 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); rtl8821ae_phy_set_bw_mode_callback()
3466 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl); rtl8821ae_phy_set_bw_mode_callback()
3467 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl); rtl8821ae_phy_set_bw_mode_callback()
3478 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); rtl8821ae_phy_set_bw_mode_callback()
3481 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1); rtl8821ae_phy_set_bw_mode_callback()
3483 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0); rtl8821ae_phy_set_bw_mode_callback()
3488 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202); rtl8821ae_phy_set_bw_mode_callback()
3490 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); rtl8821ae_phy_set_bw_mode_callback()
3491 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl); rtl8821ae_phy_set_bw_mode_callback()
3492 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl); rtl8821ae_phy_set_bw_mode_callback()
3502 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); rtl8821ae_phy_set_bw_mode_callback()
3511 rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel); rtl8821ae_phy_set_bw_mode_callback()
3513 rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl8821ae_phy_set_bw_mode_callback()
3519 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw, rtl8821ae_phy_set_bw_mode() argument
3522 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_bw_mode()
3524 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_set_bw_mode()
3530 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) rtl8821ae_phy_set_bw_mode()
3531 rtl8821ae_phy_set_bw_mode_callback(hw); rtl8821ae_phy_set_bw_mode()
3540 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw) rtl8821ae_phy_sw_chnl_callback() argument
3542 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_sw_chnl_callback()
3543 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_sw_chnl_callback()
3564 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data); rtl8821ae_phy_sw_chnl_callback()
3575 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW, rtl8821ae_phy_sw_chnl_callback()
3578 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW, rtl8821ae_phy_sw_chnl_callback()
3589 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK, rtl8821ae_phy_sw_chnl_callback()
3597 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw) rtl8821ae_phy_sw_chnl() argument
3599 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_sw_chnl()
3601 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8821ae_phy_sw_chnl()
3610 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { rtl8821ae_phy_sw_chnl()
3621 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G); rtl8821ae_phy_sw_chnl()
3623 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); rtl8821ae_phy_sw_chnl()
3633 rtl8821ae_phy_sw_chnl_callback(hw); rtl8821ae_phy_sw_chnl()
3635 rtl8821ae_dm_clear_txpower_tracking_state(hw); rtl8821ae_phy_sw_chnl()
3636 rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel); rtl8821ae_phy_sw_chnl()
3667 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw, _rtl8821ae_iqk_backup_macbb() argument
3671 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_backup_macbb()
3674 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ _rtl8821ae_iqk_backup_macbb()
3682 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup, _rtl8821ae_iqk_backup_afe() argument
3685 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_backup_afe()
3688 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ _rtl8821ae_iqk_backup_afe()
3695 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup, _rtl8821ae_iqk_backup_rf() argument
3699 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_backup_rf()
3702 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ _rtl8821ae_iqk_backup_rf()
3705 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], _rtl8821ae_iqk_backup_rf()
3707 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], _rtl8821ae_iqk_backup_rf()
3714 struct ieee80211_hw *hw _rtl8821ae_iqk_configure_mac()
3717 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_configure_mac()
3719 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ _rtl8821ae_iqk_configure_mac()
3721 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0); _rtl8821ae_iqk_configure_mac()
3723 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/ _rtl8821ae_iqk_configure_mac()
3726 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw, _rtl8821ae_iqk_tx_fill_iqc() argument
3729 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_tx_fill_iqc()
3733 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); _rtl8821ae_iqk_tx_fill_iqc()
3737 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y); _rtl8821ae_iqk_tx_fill_iqc()
3738 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x); _rtl8821ae_iqk_tx_fill_iqc()
3744 rtl_get_bbreg(hw, 0xcd4, 0x000007ff), _rtl8821ae_iqk_tx_fill_iqc()
3745 rtl_get_bbreg(hw, 0xccc, 0x000007ff)); _rtl8821ae_iqk_tx_fill_iqc()
3752 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw, _rtl8821ae_iqk_rx_fill_iqc() argument
3755 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_rx_fill_iqc()
3758 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_rx_fill_iqc()
3759 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1); _rtl8821ae_iqk_rx_fill_iqc()
3760 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1); _rtl8821ae_iqk_rx_fill_iqc()
3775 static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path) _rtl8821ae_iqk_tx() argument
3777 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_tx()
3779 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8821ae_iqk_tx()
3799 temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff); _rtl8821ae_iqk_tx()
3801 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ _rtl8821ae_iqk_tx()
3815 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/ _rtl8821ae_iqk_tx()
3820 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7); _rtl8821ae_iqk_tx()
3823 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002); _rtl8821ae_iqk_tx()
3824 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3); /* BW 20M */ _rtl8821ae_iqk_tx()
3825 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000); _rtl8821ae_iqk_tx()
3826 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f); _rtl8821ae_iqk_tx()
3827 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3); _rtl8821ae_iqk_tx()
3828 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5); _rtl8821ae_iqk_tx()
3829 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); _rtl8821ae_iqk_tx()
3830 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd); _rtl8821ae_iqk_tx()
3833 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); _rtl8821ae_iqk_tx()
3838 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
3855 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
3856 rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */ _rtl8821ae_iqk_tx()
3860 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1); _rtl8821ae_iqk_tx()
3863 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0); _rtl8821ae_iqk_tx()
3869 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
3872 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
3873 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); _rtl8821ae_iqk_tx()
3874 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000); _rtl8821ae_iqk_tx()
3875 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f); _rtl8821ae_iqk_tx()
3876 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3); _rtl8821ae_iqk_tx()
3877 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5); _rtl8821ae_iqk_tx()
3878 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); _rtl8821ae_iqk_tx()
3879 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); _rtl8821ae_iqk_tx()
3883 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); _rtl8821ae_iqk_tx()
3888 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
3902 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); _rtl8821ae_iqk_tx()
3905 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0); _rtl8821ae_iqk_tx()
3906 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0); _rtl8821ae_iqk_tx()
3907 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); _rtl8821ae_iqk_tx()
3919 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); _rtl8821ae_iqk_tx()
3920 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff); _rtl8821ae_iqk_tx()
3936 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); _rtl8821ae_iqk_tx()
3947 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); _rtl8821ae_iqk_tx()
3951 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
3953 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
3957 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0); _rtl8821ae_iqk_tx()
3958 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200); _rtl8821ae_iqk_tx()
3990 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); _rtl8821ae_iqk_tx()
4001 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); _rtl8821ae_iqk_tx()
4005 tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4007 tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4011 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0); _rtl8821ae_iqk_tx()
4012 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200); _rtl8821ae_iqk_tx()
4031 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */ _rtl8821ae_iqk_tx()
4035 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
4037 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); _rtl8821ae_iqk_tx()
4038 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); _rtl8821ae_iqk_tx()
4039 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029); _rtl8821ae_iqk_tx()
4040 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb); _rtl8821ae_iqk_tx()
4041 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); _rtl8821ae_iqk_tx()
4042 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); _rtl8821ae_iqk_tx()
4043 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); _rtl8821ae_iqk_tx()
4045 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd); _rtl8821ae_iqk_tx()
4051 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
4057 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); _rtl8821ae_iqk_tx()
4064 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); _rtl8821ae_iqk_tx()
4081 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff); _rtl8821ae_iqk_tx()
4100 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); _rtl8821ae_iqk_tx()
4111 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); _rtl8821ae_iqk_tx()
4115 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4117 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4145 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
4147 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); _rtl8821ae_iqk_tx()
4148 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); _rtl8821ae_iqk_tx()
4149 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f); _rtl8821ae_iqk_tx()
4150 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb); _rtl8821ae_iqk_tx()
4151 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001); _rtl8821ae_iqk_tx()
4152 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8); _rtl8821ae_iqk_tx()
4153 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); _rtl8821ae_iqk_tx()
4155 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff); _rtl8821ae_iqk_tx()
4156 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff); _rtl8821ae_iqk_tx()
4157 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); _rtl8821ae_iqk_tx()
4158 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); _rtl8821ae_iqk_tx()
4159 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe); _rtl8821ae_iqk_tx()
4163 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
4164 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1); _rtl8821ae_iqk_tx()
4165 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0); _rtl8821ae_iqk_tx()
4171 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */ _rtl8821ae_iqk_tx()
4184 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); _rtl8821ae_iqk_tx()
4195 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); _rtl8821ae_iqk_tx()
4198 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4200 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4204 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1); _rtl8821ae_iqk_tx()
4205 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1); _rtl8821ae_iqk_tx()
4225 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */ _rtl8821ae_iqk_tx()
4230 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
4232 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); _rtl8821ae_iqk_tx()
4233 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); _rtl8821ae_iqk_tx()
4234 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029); _rtl8821ae_iqk_tx()
4235 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb); _rtl8821ae_iqk_tx()
4236 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); _rtl8821ae_iqk_tx()
4237 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); _rtl8821ae_iqk_tx()
4238 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); _rtl8821ae_iqk_tx()
4243 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
4259 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); _rtl8821ae_iqk_tx()
4270 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); _rtl8821ae_iqk_tx()
4274 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4276 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4302 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
4304 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); _rtl8821ae_iqk_tx()
4305 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); _rtl8821ae_iqk_tx()
4306 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f); _rtl8821ae_iqk_tx()
4307 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb); _rtl8821ae_iqk_tx()
4308 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001); _rtl8821ae_iqk_tx()
4309 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8); _rtl8821ae_iqk_tx()
4310 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); _rtl8821ae_iqk_tx()
4312 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff); _rtl8821ae_iqk_tx()
4313 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff); _rtl8821ae_iqk_tx()
4314 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); _rtl8821ae_iqk_tx()
4315 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); _rtl8821ae_iqk_tx()
4320 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_tx()
4339 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); _rtl8821ae_iqk_tx()
4350 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); _rtl8821ae_iqk_tx()
4353 rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4355 rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; _rtl8821ae_iqk_tx()
4359 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1); _rtl8821ae_iqk_tx()
4360 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1); _rtl8821ae_iqk_tx()
4380 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_tx()
4381 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); _rtl8821ae_iqk_tx()
4425 _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */ _rtl8821ae_iqk_tx()
4427 _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0); _rtl8821ae_iqk_tx()
4455 _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y); _rtl8821ae_iqk_tx()
4457 _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0); _rtl8821ae_iqk_tx()
4464 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw, _rtl8821ae_iqk_restore_rf() argument
4469 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_restore_rf()
4472 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_restore_rf()
4474 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK, _rtl8821ae_iqk_restore_rf()
4487 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw, _rtl8821ae_iqk_restore_afe() argument
4492 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_restore_afe()
4494 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_restore_afe()
4498 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ _rtl8821ae_iqk_restore_afe()
4511 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw, _rtl8821ae_iqk_restore_macbb() argument
4517 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_iqk_restore_macbb()
4519 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ _rtl8821ae_iqk_restore_macbb()
4534 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw) _rtl8821ae_phy_iq_calibrate() argument
4550 _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, _rtl8821ae_phy_iq_calibrate()
4552 _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM); _rtl8821ae_phy_iq_calibrate()
4553 _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, _rtl8821ae_phy_iq_calibrate()
4556 _rtl8821ae_iqk_configure_mac(hw); _rtl8821ae_phy_iq_calibrate()
4557 _rtl8821ae_iqk_tx(hw, RF90_PATH_A); _rtl8821ae_phy_iq_calibrate()
4558 _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, _rtl8821ae_phy_iq_calibrate()
4561 _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM); _rtl8821ae_phy_iq_calibrate()
4562 _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, _rtl8821ae_phy_iq_calibrate()
4566 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main) _rtl8821ae_phy_set_rfpath_switch() argument
4568 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_set_rfpath_switch()
4569 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */ _rtl8821ae_phy_set_rfpath_switch()
4570 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */ _rtl8821ae_phy_set_rfpath_switch()
4574 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1); _rtl8821ae_phy_set_rfpath_switch()
4576 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2); _rtl8821ae_phy_set_rfpath_switch()
4582 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl8812ae_phy_iq_calibrate() argument
4586 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index, rtl8812ae_do_iqk() argument
4589 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl8812ae_do_iqk()
4592 rtl8812ae_phy_iq_calibrate(hw, false); rtl8812ae_do_iqk()
4595 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl8821ae_phy_iq_calibrate() argument
4597 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_iq_calibrate()
4605 _rtl8821ae_phy_iq_calibrate(hw); rtl8821ae_phy_iq_calibrate()
4613 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw) rtl8821ae_reset_iqk_result() argument
4615 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_reset_iqk_result()
4640 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index, rtl8821ae_do_iqk() argument
4643 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl8821ae_do_iqk()
4645 rtl8821ae_reset_iqk_result(hw); rtl8821ae_do_iqk()
4648 rtl8821ae_phy_iq_calibrate(hw, false); rtl8821ae_do_iqk()
4651 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw) rtl8821ae_phy_lc_calibrate() argument
4655 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) rtl8821ae_phy_ap_calibrate() argument
4659 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) rtl8821ae_phy_set_rfpath_switch() argument
4661 _rtl8821ae_phy_set_rfpath_switch(hw, bmain); rtl8821ae_phy_set_rfpath_switch()
4664 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl8821ae_phy_set_io_cmd() argument
4666 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_io_cmd()
4698 rtl8821ae_phy_set_io(hw); rtl8821ae_phy_set_io_cmd()
4703 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw) rtl8821ae_phy_set_io() argument
4705 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_io()
4715 _rtl8821ae_resume_tx_beacon(hw); rtl8821ae_phy_set_io()
4716 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); rtl8821ae_phy_set_io()
4717 rtl8821ae_dm_write_cck_cca_thres(hw, rtl8821ae_phy_set_io()
4722 _rtl8821ae_stop_tx_beacon(hw); rtl8821ae_phy_set_io()
4724 rtl8821ae_dm_write_dig(hw, 0x17); rtl8821ae_phy_set_io()
4726 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40); rtl8821ae_phy_set_io()
4740 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw) rtl8821ae_phy_set_rf_on() argument
4742 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8821ae_phy_set_rf_on()
4751 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl8821ae_phy_set_rf_power_state() argument
4754 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8821ae_phy_set_rf_power_state()
4755 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8821ae_phy_set_rf_power_state()
4756 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl8821ae_phy_set_rf_power_state()
4757 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl8821ae_phy_set_rf_power_state()
4773 rtstatus = rtl_ps_enable_nic(hw); _rtl8821ae_phy_set_rf_power_state()
4784 rtl8821ae_phy_set_rf_on(hw); _rtl8821ae_phy_set_rf_power_state()
4787 rtlpriv->cfg->ops->led_control(hw, _rtl8821ae_phy_set_rf_power_state()
4790 rtlpriv->cfg->ops->led_control(hw, _rtl8821ae_phy_set_rf_power_state()
4824 rtl_ps_disable_nic(hw); _rtl8821ae_phy_set_rf_power_state()
4828 rtlpriv->cfg->ops->led_control(hw, _rtl8821ae_phy_set_rf_power_state()
4831 rtlpriv->cfg->ops->led_control(hw, _rtl8821ae_phy_set_rf_power_state()
4847 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl8821ae_phy_set_rf_power_state() argument
4850 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8821ae_phy_set_rf_power_state()
4856 bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state); rtl8821ae_phy_set_rf_power_state()
H A Dled.h29 void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
30 void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
31 void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
32 void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
33 void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
34 void rtl8821ae_led_control(struct ieee80211_hw *hw,
/linux-4.4.14/drivers/isdn/hisax/
H A Dhfc4s8s_l1.c151 struct _hfc4s8s_hw *hw; /* pointer to hardware area */ member in struct:hfc4s8s_l1
274 Read_hfc8_stable(hfc4s8s_hw *hw, int reg) Read_hfc8_stable() argument
278 ref8 = Read_hfc8(hw, reg); Read_hfc8_stable()
279 while (((in8 = Read_hfc8(hw, reg)) != ref8)) { Read_hfc8_stable()
286 Read_hfc16_stable(hfc4s8s_hw *hw, int reg) Read_hfc16_stable() argument
291 ref16 = Read_hfc16(hw, reg); Read_hfc16_stable()
292 while (((in16 = Read_hfc16(hw, reg)) != ref16)) { Read_hfc16_stable()
319 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= dch_l2l1()
322 schedule_work(&l1->hw->tqueue); dch_l2l1()
335 Write_hfc8(l1->hw, R_ST_SEL, dch_l2l1()
337 Write_hfc8(l1->hw, A_ST_WR_STA, dch_l2l1()
352 Write_hfc8(l1->hw, R_ST_SEL, dch_l2l1()
354 Write_hfc8(l1->hw, A_ST_WR_STA, dch_l2l1()
399 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= bch_l2l1()
402 schedule_work(&l1->hw->tqueue); bch_l2l1()
418 l1->hw->mr.timer_usg_cnt++; bch_l2l1()
419 l1->hw->mr. bch_l2l1()
425 Write_hfc8(l1->hw, R_FIFO, bch_l2l1()
429 wait_busy(l1->hw); bch_l2l1()
430 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ bch_l2l1()
431 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ bch_l2l1()
432 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ bch_l2l1()
433 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ bch_l2l1()
434 wait_busy(l1->hw); bch_l2l1()
436 Write_hfc8(l1->hw, R_FIFO, bch_l2l1()
440 wait_busy(l1->hw); bch_l2l1()
441 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ bch_l2l1()
442 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ bch_l2l1()
443 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ bch_l2l1()
444 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ bch_l2l1()
446 Write_hfc8(l1->hw, R_ST_SEL, bch_l2l1()
448 l1->hw->mr.r_ctrl0 |= bch_l2l1()
450 Write_hfc8(l1->hw, A_ST_CTRL0, bch_l2l1()
451 l1->hw->mr.r_ctrl0); bch_l2l1()
465 l1->hw->mr. bch_l2l1()
471 l1->hw->mr.timer_usg_cnt++; bch_l2l1()
472 Write_hfc8(l1->hw, R_FIFO, bch_l2l1()
476 wait_busy(l1->hw); bch_l2l1()
477 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ bch_l2l1()
478 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ bch_l2l1()
479 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ bch_l2l1()
480 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ bch_l2l1()
481 wait_busy(l1->hw); bch_l2l1()
483 Write_hfc8(l1->hw, R_FIFO, bch_l2l1()
487 wait_busy(l1->hw); bch_l2l1()
488 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ bch_l2l1()
489 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ bch_l2l1()
490 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ bch_l2l1()
491 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ bch_l2l1()
493 Write_hfc8(l1->hw, R_ST_SEL, bch_l2l1()
495 l1->hw->mr.r_ctrl0 |= bch_l2l1()
497 Write_hfc8(l1->hw, A_ST_CTRL0, bch_l2l1()
498 l1->hw->mr.r_ctrl0); bch_l2l1()
514 l1->hw->mr. bch_l2l1()
520 l1->hw->mr. bch_l2l1()
526 l1->hw->mr.timer_usg_cnt--; bch_l2l1()
527 Write_hfc8(l1->hw, R_FIFO, bch_l2l1()
531 wait_busy(l1->hw); bch_l2l1()
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ bch_l2l1()
533 wait_busy(l1->hw); bch_l2l1()
534 Write_hfc8(l1->hw, R_FIFO, bch_l2l1()
538 wait_busy(l1->hw); bch_l2l1()
539 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ bch_l2l1()
540 Write_hfc8(l1->hw, R_ST_SEL, bch_l2l1()
542 l1->hw->mr.r_ctrl0 &= bch_l2l1()
544 Write_hfc8(l1->hw, A_ST_CTRL0, bch_l2l1()
545 l1->hw->mr.r_ctrl0); bch_l2l1()
570 if (l1->hw->mr.timer_usg_cnt) { bch_l2l1()
571 Write_hfc8(l1->hw, R_IRQMSK_MISC, bch_l2l1()
574 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); bch_l2l1()
604 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); hfc_l1_timer()
605 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); hfc_l1_timer()
611 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); hfc_l1_timer()
615 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); hfc_l1_timer()
616 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); hfc_l1_timer()
621 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); hfc_l1_timer()
622 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); hfc_l1_timer()
643 Write_hfc8(l1p->hw, R_FIFO, rx_d_frame()
645 wait_busy(l1p->hw); rx_d_frame()
647 f1 = Read_hfc8_stable(l1p->hw, A_F1); rx_d_frame()
648 f2 = Read_hfc8(l1p->hw, A_F2); rx_d_frame()
658 z1 = Read_hfc16_stable(l1p->hw, A_Z1); rx_d_frame()
659 z2 = Read_hfc16(l1p->hw, A_Z2); rx_d_frame()
669 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); rx_d_frame()
670 wait_busy(l1p->hw); rx_d_frame()
680 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); rx_d_frame()
681 wait_busy(l1p->hw); rx_d_frame()
685 SetRegAddr(l1p->hw, A_FIFO_DATA0); rx_d_frame()
688 fRead_hfc32(l1p->hw); rx_d_frame()
693 fRead_hfc8(l1p->hw); rx_d_frame()
695 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); rx_d_frame()
696 wait_busy(l1p->hw); rx_d_frame()
703 SetRegAddr(l1p->hw, A_FIFO_DATA0); rx_d_frame()
706 *((unsigned long *) cp) = fRead_hfc32(l1p->hw); rx_d_frame()
712 *cp++ = fRead_hfc8(l1p->hw); rx_d_frame()
714 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ rx_d_frame()
715 wait_busy(l1p->hw); rx_d_frame()
749 Write_hfc8(l1->hw, R_FIFO, rx_b_frame()
751 wait_busy(l1->hw); rx_b_frame()
754 f1 = Read_hfc8_stable(l1->hw, A_F1); rx_b_frame()
755 f2 = Read_hfc8(l1->hw, A_F2); rx_b_frame()
759 z1 = Read_hfc16_stable(l1->hw, A_Z1); rx_b_frame()
760 z2 = Read_hfc16(l1->hw, A_Z2); rx_b_frame()
794 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ rx_b_frame()
795 wait_busy(l1->hw); rx_b_frame()
798 SetRegAddr(l1->hw, A_FIFO_DATA0); rx_b_frame()
802 fRead_hfc32(l1->hw); rx_b_frame()
808 *(bch->rx_ptr++) = fRead_hfc8(l1->hw); rx_b_frame()
812 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); rx_b_frame()
813 wait_busy(l1->hw); rx_b_frame()
849 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); tx_d_frame()
850 wait_busy(l1p->hw); tx_d_frame()
852 f1 = Read_hfc8(l1p->hw, A_F1); tx_d_frame()
853 f2 = Read_hfc8_stable(l1p->hw, A_F2); tx_d_frame()
868 SetRegAddr(l1p->hw, A_FIFO_DATA0); tx_d_frame()
871 SetRegAddr(l1p->hw, A_FIFO_DATA0); tx_d_frame()
872 fWrite_hfc32(l1p->hw, *(unsigned long *) cp); tx_d_frame()
878 fWrite_hfc8(l1p->hw, *cp++); tx_d_frame()
881 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ tx_d_frame()
882 wait_busy(l1p->hw); tx_d_frame()
904 Write_hfc8(l1->hw, R_FIFO, tx_b_frame()
906 wait_busy(l1->hw); tx_b_frame()
910 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; tx_b_frame()
912 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); tx_b_frame()
922 l1->hw->mr.fifo_slow_timer_service[l1-> tx_b_frame()
932 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= tx_b_frame()
935 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= tx_b_frame()
938 max = Read_hfc16_stable(l1->hw, A_Z2); tx_b_frame()
939 max -= Read_hfc16(l1->hw, A_Z1); tx_b_frame()
953 SetRegAddr(l1->hw, A_FIFO_DATA0); tx_b_frame()
955 fWrite_hfc32(l1->hw, *(unsigned long *) cp); tx_b_frame()
961 fWrite_hfc8(l1->hw, *cp++); tx_b_frame()
966 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); tx_b_frame()
974 Write_hfc8(l1->hw, R_FIFO, tx_b_frame()
977 wait_busy(l1->hw); tx_b_frame()
991 hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue); hfc4s8s_bh() local
999 l1p = hw->l1; hfc4s8s_bh()
1001 if ((b & hw->mr.r_irq_statech)) { hfc4s8s_bh()
1003 hw->mr.r_irq_statech &= ~b; hfc4s8s_bh()
1008 Write_hfc8(l1p->hw, R_ST_SEL, hfc4s8s_bh()
1011 Read_hfc8(l1p->hw, hfc4s8s_bh()
1037 Write_hfc8(hw, A_ST_WR_STA, hfc4s8s_bh()
1050 Write_hfc8(l1p->hw, R_ST_SEL, hfc4s8s_bh()
1053 Read_hfc8(l1p->hw, hfc4s8s_bh()
1094 l1p->hw->cardnum, hfc4s8s_bh()
1106 fifo_stat = hw->mr.r_irq_fifo_blx; hfc4s8s_bh()
1107 l1p = hw->l1; hfc4s8s_bh()
1108 while (idx < hw->driver_data.max_st_ports) { hfc4s8s_bh()
1110 if (hw->mr.timer_irq) { hfc4s8s_bh()
1111 *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx]; hfc4s8s_bh()
1112 if (hw->fifo_sched_cnt <= 0) { hfc4s8s_bh()
1114 hw->mr.fifo_slow_timer_service[l1p-> hfc4s8s_bh()
1166 if (hw->fifo_sched_cnt <= 0) hfc4s8s_bh()
1167 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE)); hfc4s8s_bh()
1168 hw->mr.timer_irq = 0; /* clear requested timer irq */ hfc4s8s_bh()
1177 hfc4s8s_hw *hw = dev_id; hfc4s8s_interrupt() local
1183 if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) hfc4s8s_interrupt()
1187 old_ioreg = GetRegAddr(hw); hfc4s8s_interrupt()
1190 hw->mr.r_irq_statech |= hfc4s8s_interrupt()
1191 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg); hfc4s8s_interrupt()
1193 (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) hfc4s8s_interrupt()
1194 && !hw->mr.r_irq_statech) { hfc4s8s_interrupt()
1195 SetRegAddr(hw, old_ioreg); hfc4s8s_interrupt()
1200 if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) { hfc4s8s_interrupt()
1201 hw->mr.timer_irq = 1; hfc4s8s_interrupt()
1202 hw->fifo_sched_cnt--; hfc4s8s_interrupt()
1206 if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) { hfc4s8s_interrupt()
1207 hw->mr.r_irq_oview |= ovr; hfc4s8s_interrupt()
1209 ovp = hw->mr.r_irq_fifo_blx; hfc4s8s_interrupt()
1212 *ovp |= Read_hfc8(hw, idx); hfc4s8s_interrupt()
1221 schedule_work(&hw->tqueue); hfc4s8s_interrupt()
1223 SetRegAddr(hw, old_ioreg); hfc4s8s_interrupt()
1231 chipreset(hfc4s8s_hw *hw) chipreset() argument
1235 spin_lock_irqsave(&hw->lock, flags); chipreset()
1236 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */ chipreset()
1237 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */ chipreset()
1238 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */ chipreset()
1239 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */ chipreset()
1240 hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */ chipreset()
1241 spin_unlock_irqrestore(&hw->lock, flags); chipreset()
1244 Write_hfc8(hw, R_CIRM, 0); /* disable reset */ chipreset()
1245 wait_busy(hw); chipreset()
1247 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */ chipreset()
1248 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */ chipreset()
1249 if (hw->driver_data.clock_mode == 1) chipreset()
1250 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */ chipreset()
1251 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */ chipreset()
1253 memset(&hw->mr, 0, sizeof(hw->mr)); chipreset()
1260 hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode) hfc_hardware_enable() argument
1268 hw->nt_mode = nt_mode; hfc_hardware_enable()
1271 hw->mr.r_irq_ctrl = M_FIFO_IRQ; hfc_hardware_enable()
1272 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); hfc_hardware_enable()
1273 hw->mr.r_irqmsk_statchg = 0; hfc_hardware_enable()
1274 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); hfc_hardware_enable()
1275 Write_hfc8(hw, R_PWM_MD, 0x80); hfc_hardware_enable()
1276 Write_hfc8(hw, R_PWM1, 26); hfc_hardware_enable()
1278 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); hfc_hardware_enable()
1281 for (i = 0; i < hw->driver_data.max_st_ports; i++) { hfc_hardware_enable()
1282 hw->mr.r_irqmsk_statchg |= (1 << i); hfc_hardware_enable()
1283 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); hfc_hardware_enable()
1284 Write_hfc8(hw, R_ST_SEL, i); hfc_hardware_enable()
1285 Write_hfc8(hw, A_ST_CLK_DLY, hfc_hardware_enable()
1287 hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE); hfc_hardware_enable()
1288 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); hfc_hardware_enable()
1289 Write_hfc8(hw, A_ST_CTRL2, 3); hfc_hardware_enable()
1290 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */ hfc_hardware_enable()
1292 hw->l1[i].enabled = 1; hfc_hardware_enable()
1293 hw->l1[i].nt_mode = nt_mode; hfc_hardware_enable()
1297 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */ hfc_hardware_enable()
1298 wait_busy(hw); hfc_hardware_enable()
1299 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ hfc_hardware_enable()
1300 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ hfc_hardware_enable()
1301 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ hfc_hardware_enable()
1302 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ hfc_hardware_enable()
1303 wait_busy(hw); hfc_hardware_enable()
1306 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */ hfc_hardware_enable()
1307 wait_busy(hw); hfc_hardware_enable()
1308 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ hfc_hardware_enable()
1309 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ hfc_hardware_enable()
1310 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ hfc_hardware_enable()
1311 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ hfc_hardware_enable()
1312 wait_busy(hw); hfc_hardware_enable()
1315 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */ hfc_hardware_enable()
1316 wait_busy(hw); hfc_hardware_enable()
1317 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ hfc_hardware_enable()
1318 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ hfc_hardware_enable()
1319 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ hfc_hardware_enable()
1320 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ hfc_hardware_enable()
1321 wait_busy(hw); hfc_hardware_enable()
1324 sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i); hfc_hardware_enable()
1327 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name, hfc_hardware_enable()
1330 hw->l1[i].enabled = 0; hfc_hardware_enable()
1331 hw->mr.r_irqmsk_statchg &= ~(1 << i); hfc_hardware_enable()
1332 Write_hfc8(hw, R_SCI_MSK, hfc_hardware_enable()
1333 hw->mr.r_irqmsk_statchg); hfc_hardware_enable()
1340 spin_lock_irqsave(&hw->lock, flags); hfc_hardware_enable()
1341 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN; hfc_hardware_enable()
1342 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); hfc_hardware_enable()
1343 spin_unlock_irqrestore(&hw->lock, flags); hfc_hardware_enable()
1346 spin_lock_irqsave(&hw->lock, flags); hfc_hardware_enable()
1347 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN; hfc_hardware_enable()
1348 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); hfc_hardware_enable()
1349 spin_unlock_irqrestore(&hw->lock, flags); hfc_hardware_enable()
1351 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) { hfc_hardware_enable()
1352 hw->l1[i].enabled = 0; hfc_hardware_enable()
1353 hisax_unregister(&hw->l1[i].d_if); hfc_hardware_enable()
1354 del_timer(&hw->l1[i].l1_timer); hfc_hardware_enable()
1355 skb_queue_purge(&hw->l1[i].d_tx_queue); hfc_hardware_enable()
1356 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); hfc_hardware_enable()
1357 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); hfc_hardware_enable()
1359 chipreset(hw); hfc_hardware_enable()
1367 release_pci_ports(hfc4s8s_hw *hw) release_pci_ports() argument
1369 pci_write_config_word(hw->pdev, PCI_COMMAND, 0); release_pci_ports()
1370 if (hw->iobase) release_pci_ports()
1371 release_region(hw->iobase, 8); release_pci_ports()
1378 enable_pci_ports(hfc4s8s_hw *hw) enable_pci_ports() argument
1380 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); enable_pci_ports()
1388 setup_instance(hfc4s8s_hw *hw) setup_instance() argument
1396 l1p = hw->l1 + i; setup_instance()
1398 l1p->hw = hw; setup_instance()
1404 l1p->d_if.ifc.priv = hw->l1 + i; setup_instance()
1410 l1p->b_ch[0].l1p = hw->l1 + i; setup_instance()
1418 l1p->b_ch[1].l1p = hw->l1 + i; setup_instance()
1424 enable_pci_ports(hw); setup_instance()
1425 chipreset(hw); setup_instance()
1427 i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT; setup_instance()
1428 if (i != hw->driver_data.chip_id) { setup_instance()
1431 i, hw->driver_data.chip_id); setup_instance()
1435 i = Read_hfc8(hw, R_CHIP_RV) & 0xf; setup_instance()
1442 INIT_WORK(&hw->tqueue, hfc4s8s_bh); setup_instance()
1445 (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) { setup_instance()
1448 hw->irq); setup_instance()
1453 hw->iobase, hw->irq); setup_instance()
1455 hfc_hardware_enable(hw, 1, 0); setup_instance()
1460 hw->irq = 0; setup_instance()
1461 release_pci_ports(hw); setup_instance()
1462 kfree(hw); setup_instance()
1474 hfc4s8s_hw *hw; hfc4s8s_probe() local
1476 if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) { hfc4s8s_probe()
1481 hw->pdev = pdev; hfc4s8s_probe()
1487 hw->cardnum = card_cnt; hfc4s8s_probe()
1488 sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum); hfc4s8s_probe()
1490 driver_data->device_name, hw->card_name, pci_name(pdev)); hfc4s8s_probe()
1492 spin_lock_init(&hw->lock); hfc4s8s_probe()
1494 hw->driver_data = *driver_data; hfc4s8s_probe()
1495 hw->irq = pdev->irq; hfc4s8s_probe()
1496 hw->iobase = pci_resource_start(pdev, 0); hfc4s8s_probe()
1498 if (!request_region(hw->iobase, 8, hw->card_name)) { hfc4s8s_probe()
1501 hw->iobase); hfc4s8s_probe()
1505 pci_set_drvdata(pdev, hw); hfc4s8s_probe()
1506 err = setup_instance(hw); hfc4s8s_probe()
1512 kfree(hw); hfc4s8s_probe()
1522 hfc4s8s_hw *hw = pci_get_drvdata(pdev); hfc4s8s_remove() local
1524 printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum); hfc4s8s_remove()
1525 hfc_hardware_enable(hw, 0, 0); hfc4s8s_remove()
1527 if (hw->irq) hfc4s8s_remove()
1528 free_irq(hw->irq, hw); hfc4s8s_remove()
1529 hw->irq = 0; hfc4s8s_remove()
1530 release_pci_ports(hw); hfc4s8s_remove()
1534 kfree(hw); hfc4s8s_remove()
H A Dteleint.c105 cs->hw.hfc.cip = offset; ReadISAC()
106 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); ReadISAC()
112 cs->hw.hfc.cip = offset; WriteISAC()
113 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); WriteISAC()
119 cs->hw.hfc.cip = 0; ReadISACfifo()
120 readfifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); ReadISACfifo()
126 cs->hw.hfc.cip = 0; WriteISACfifo()
127 writefifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); WriteISACfifo()
136 cs->hw.hfc.cip = reg; ReadHFC()
137 byteout(cs->hw.hfc.addr | 1, reg); ReadHFC()
138 ret = bytein(cs->hw.hfc.addr); ReadHFC()
142 ret = bytein(cs->hw.hfc.addr | 1); ReadHFC()
149 byteout(cs->hw.hfc.addr | 1, reg); WriteHFC()
150 cs->hw.hfc.cip = reg; WriteHFC()
152 byteout(cs->hw.hfc.addr, value); WriteHFC()
165 val = readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_ISTA); TeleInt_interrupt()
169 val = readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_ISTA); TeleInt_interrupt()
175 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0xFF); TeleInt_interrupt()
176 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0x0); TeleInt_interrupt()
200 cs->hw.hfc.timer.expires = jiffies + stat; TeleInt_Timer()
201 add_timer(&cs->hw.hfc.timer); TeleInt_Timer()
207 del_timer(&cs->hw.hfc.timer); release_io_TeleInt()
209 if (cs->hw.hfc.addr) release_io_TeleInt()
210 release_region(cs->hw.hfc.addr, 2); release_io_TeleInt()
217 cs->hw.hfc.cirm |= HFC_RESET; reset_TeleInt()
218 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.cirm); /* Reset On */ reset_TeleInt()
220 cs->hw.hfc.cirm &= ~HFC_RESET; reset_TeleInt()
221 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.cirm); /* Reset Off */ reset_TeleInt()
253 cs->hw.hfc.timer.expires = jiffies + delay; TeleInt_card_msg()
254 add_timer(&cs->hw.hfc.timer); TeleInt_card_msg()
272 cs->hw.hfc.addr = card->para[1] & 0x3fe; setup_TeleInt()
274 cs->hw.hfc.cirm = HFC_CIRM; setup_TeleInt()
275 cs->hw.hfc.isac_spcr = 0x00; setup_TeleInt()
276 cs->hw.hfc.cip = 0; setup_TeleInt()
277 cs->hw.hfc.ctmt = HFC_CTMT | HFC_CLTIMER; setup_TeleInt()
278 cs->bcs[0].hw.hfc.send = NULL; setup_TeleInt()
279 cs->bcs[1].hw.hfc.send = NULL; setup_TeleInt()
280 cs->hw.hfc.fifosize = 7 * 1024 + 512; setup_TeleInt()
281 cs->hw.hfc.timer.function = (void *) TeleInt_Timer; setup_TeleInt()
282 cs->hw.hfc.timer.data = (long) cs; setup_TeleInt()
283 init_timer(&cs->hw.hfc.timer); setup_TeleInt()
284 if (!request_region(cs->hw.hfc.addr, 2, "TeleInt isdn")) { setup_TeleInt()
287 cs->hw.hfc.addr, setup_TeleInt()
288 cs->hw.hfc.addr + 2); setup_TeleInt()
292 byteout(cs->hw.hfc.addr, cs->hw.hfc.addr & 0xff); setup_TeleInt()
293 byteout(cs->hw.hfc.addr | 1, ((cs->hw.hfc.addr & 0x300) >> 8) | 0x54); setup_TeleInt()
296 cs->hw.hfc.cirm |= HFC_INTA; setup_TeleInt()
299 cs->hw.hfc.cirm |= HFC_INTB; setup_TeleInt()
302 cs->hw.hfc.cirm |= HFC_INTC; setup_TeleInt()
305 cs->hw.hfc.cirm |= HFC_INTD; setup_TeleInt()
308 cs->hw.hfc.cirm |= HFC_INTE; setup_TeleInt()
311 cs->hw.hfc.cirm |= HFC_INTF; setup_TeleInt()
318 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.cirm); setup_TeleInt()
319 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.ctmt); setup_TeleInt()
322 cs->hw.hfc.addr, cs->irq); setup_TeleInt()
H A Dsaphir.c70 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); ReadISAC()
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); WriteISAC()
82 readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); ReadISACfifo()
88 writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); WriteISACfifo()
94 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, ReadHSCX()
101 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, WriteHSCX()
105 #define READHSCX(cs, nr, reg) readreg(cs->hw.saphir.ale, \
106 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
107 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
108 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data)
110 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.saphir.ale, \
111 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
113 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.saphir.ale, \
114 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
126 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); saphir_interrupt()
130 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); saphir_interrupt()
134 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); saphir_interrupt()
140 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); saphir_interrupt()
147 if (cs->hw.saphir.timer.function) saphir_interrupt()
148 mod_timer(&cs->hw.saphir.timer, jiffies + 1 * HZ); saphir_interrupt()
151 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); saphir_interrupt()
152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); saphir_interrupt()
153 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); saphir_interrupt()
154 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); saphir_interrupt()
155 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); saphir_interrupt()
156 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); saphir_interrupt()
170 mod_timer(&cs->hw.saphir.timer, jiffies + 1 * HZ); SaphirWatchDog()
176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff); release_io_saphir()
177 del_timer(&cs->hw.saphir.timer); release_io_saphir()
178 cs->hw.saphir.timer.function = NULL; release_io_saphir()
179 if (cs->hw.saphir.cfg_reg) release_io_saphir()
180 release_region(cs->hw.saphir.cfg_reg, 6); release_io_saphir()
207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); saphir_reset()
208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1); saphir_reset()
210 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0); saphir_reset()
212 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); saphir_reset()
213 byteout(cs->hw.saphir.cfg_reg + SPARE_REG, 0x02); saphir_reset()
254 cs->hw.saphir.cfg_reg = card->para[1]; setup_saphir()
255 cs->hw.saphir.isac = card->para[1] + ISAC_DATA; setup_saphir()
256 cs->hw.saphir.hscx = card->para[1] + HSCX_DATA; setup_saphir()
257 cs->hw.saphir.ale = card->para[1] + ADDRESS_REG; setup_saphir()
259 if (!request_region(cs->hw.saphir.cfg_reg, 6, "saphir")) { setup_saphir()
262 cs->hw.saphir.cfg_reg, setup_saphir()
263 cs->hw.saphir.cfg_reg + 5); setup_saphir()
268 cs->irq, cs->hw.saphir.cfg_reg); setup_saphir()
271 cs->hw.saphir.timer.function = (void *) SaphirWatchDog; setup_saphir()
272 cs->hw.saphir.timer.data = (long) cs; setup_saphir()
273 init_timer(&cs->hw.saphir.timer); setup_saphir()
274 cs->hw.saphir.timer.expires = jiffies + 4 * HZ; setup_saphir()
275 add_timer(&cs->hw.saphir.timer); setup_saphir()
H A Dsedlbauer.c156 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset)); ReadISAC()
162 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); WriteISAC()
168 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); ReadISACfifo()
174 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); WriteISACfifo()
180 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80)); ReadISAC_IPAC()
186 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80, value); WriteISAC_IPAC()
192 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0x80, data, size); ReadISACfifo_IPAC()
198 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0x80, data, size); WriteISACfifo_IPAC()
204 return (readreg(cs->hw.sedl.adr, ReadHSCX()
205 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
211 writereg(cs->hw.sedl.adr, WriteHSCX()
212 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
225 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset)); ReadISAR()
227 byteout(cs->hw.sedl.adr, offset); ReadISAR()
228 return (bytein(cs->hw.sedl.hscx)); ReadISAR()
235 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); WriteISAR()
238 byteout(cs->hw.sedl.adr, offset); WriteISAR()
239 byteout(cs->hw.sedl.hscx, value); WriteISAR()
247 #define READHSCX(cs, nr, reg) readreg(cs->hw.sedl.adr, \
248 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0))
249 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.sedl.adr, \
250 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0), data)
252 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.sedl.adr, \
253 cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt)
255 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.sedl.adr, \
256 cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt)
268 if ((cs->hw.sedl.bus == SEDL_BUS_PCMCIA) && (*cs->busy_flag == 1)) { sedlbauer_interrupt()
276 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt()
280 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt()
284 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt()
290 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt()
296 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); sedlbauer_interrupt()
297 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); sedlbauer_interrupt()
298 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); sedlbauer_interrupt()
299 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); sedlbauer_interrupt()
300 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0x0); sedlbauer_interrupt()
301 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0x0); sedlbauer_interrupt()
314 ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); sedlbauer_interrupt_ipac()
319 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt_ipac()
330 val = 0xfe & readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA | 0x80); sedlbauer_interrupt_ipac()
339 ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); sedlbauer_interrupt_ipac()
347 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xFF); sedlbauer_interrupt_ipac()
348 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xC0); sedlbauer_interrupt_ipac()
362 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT); sedlbauer_interrupt_isar()
366 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt_isar()
370 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT); sedlbauer_interrupt_isar()
376 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt_isar()
386 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT, 0); sedlbauer_interrupt_isar()
387 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); sedlbauer_interrupt_isar()
388 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); sedlbauer_interrupt_isar()
389 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT, ISAR_IRQMSK); sedlbauer_interrupt_isar()
401 } else if (cs->hw.sedl.bus == SEDL_BUS_PCI) { release_io_sedlbauer()
404 if (cs->hw.sedl.cfg_reg) release_io_sedlbauer()
405 release_region(cs->hw.sedl.cfg_reg, bytecnt); release_io_sedlbauer()
413 if (!((cs->hw.sedl.bus == SEDL_BUS_PCMCIA) && reset_sedlbauer()
414 (cs->hw.sedl.chip == SEDL_CHIP_ISAC_HSCX))) { reset_sedlbauer()
415 if (cs->hw.sedl.chip == SEDL_CHIP_IPAC) { reset_sedlbauer()
416 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_POTA2, 0x20); reset_sedlbauer()
418 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_POTA2, 0x0); reset_sedlbauer()
420 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_CONF, 0x0); reset_sedlbauer()
421 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ACFG, 0xff); reset_sedlbauer()
422 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_AOE, 0x0); reset_sedlbauer()
423 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xc0); reset_sedlbauer()
424 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_PCFG, 0x12); reset_sedlbauer()
425 } else if ((cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) && reset_sedlbauer()
426 (cs->hw.sedl.bus == SEDL_BUS_PCI)) { reset_sedlbauer()
427 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_on); reset_sedlbauer()
429 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); reset_sedlbauer()
432 byteout(cs->hw.sedl.reset_on, SEDL_RESET); /* Reset On */ reset_sedlbauer()
434 byteout(cs->hw.sedl.reset_off, 0); /* Reset Off */ reset_sedlbauer()
452 if (cs->hw.sedl.bus == SEDL_BUS_PCI) Sedl_card_msg()
454 byteout(cs->hw.sedl.cfg_reg + 5, 0); Sedl_card_msg()
455 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { Sedl_card_msg()
457 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg()
459 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, Sedl_card_msg()
462 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg()
464 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, Sedl_card_msg()
472 if (cs->hw.sedl.bus == SEDL_BUS_PCI) Sedl_card_msg()
474 byteout(cs->hw.sedl.cfg_reg + 5, 0x02); Sedl_card_msg()
476 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { Sedl_card_msg()
478 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg()
498 cs->hw.sedl.reset_off &= ~SEDL_ISAR_PCI_LED2; Sedl_card_msg()
500 cs->hw.sedl.reset_off &= ~SEDL_ISAR_PCI_LED1; Sedl_card_msg()
501 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); Sedl_card_msg()
509 cs->hw.sedl.reset_off |= SEDL_ISAR_PCI_LED2; Sedl_card_msg()
511 cs->hw.sedl.reset_off |= SEDL_ISAR_PCI_LED1; Sedl_card_msg()
512 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); Sedl_card_msg()
567 cs->hw.sedl.cfg_reg = card->para[1]; setup_sedlbauer_isapnp()
571 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer_isapnp()
575 cs->hw.sedl.chip = SEDL_CHIP_TEST; setup_sedlbauer_isapnp()
616 cs->hw.sedl.cfg_reg = pci_resource_start(dev_sedl, 0); setup_sedlbauer_pci()
622 cs->hw.sedl.bus = SEDL_BUS_PCI; setup_sedlbauer_pci()
628 cs->hw.sedl.cfg_reg); setup_sedlbauer_pci()
634 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer_pci()
637 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer_pci()
640 cs->hw.sedl.chip = SEDL_CHIP_IPAC; setup_sedlbauer_pci()
643 cs->hw.sedl.chip = SEDL_CHIP_IPAC; setup_sedlbauer_pci()
651 cs->hw.sedl.reset_on = SEDL_ISAR_PCI_ISAR_RESET_ON; setup_sedlbauer_pci()
652 cs->hw.sedl.reset_off = SEDL_ISAR_PCI_ISAR_RESET_OFF; setup_sedlbauer_pci()
653 byteout(cs->hw.sedl.cfg_reg, 0xff); setup_sedlbauer_pci()
654 byteout(cs->hw.sedl.cfg_reg, 0x00); setup_sedlbauer_pci()
655 byteout(cs->hw.sedl.cfg_reg + 2, 0xdd); setup_sedlbauer_pci()
656 byteout(cs->hw.sedl.cfg_reg + 5, 0); /* disable all IRQ */ setup_sedlbauer_pci()
657 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_on); setup_sedlbauer_pci()
659 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); setup_sedlbauer_pci()
685 cs->hw.sedl.bus = SEDL_BUS_ISA; setup_sedlbauer()
686 cs->hw.sedl.chip = SEDL_CHIP_TEST; setup_sedlbauer()
689 cs->hw.sedl.bus = SEDL_BUS_PCMCIA; setup_sedlbauer()
690 cs->hw.sedl.chip = SEDL_CHIP_TEST; setup_sedlbauer()
693 cs->hw.sedl.bus = SEDL_BUS_ISA; setup_sedlbauer()
694 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer()
700 cs->hw.sedl.cfg_reg = card->para[1]; setup_sedlbauer()
702 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { setup_sedlbauer()
726 if (cs->hw.sedl.bus != SEDL_BUS_PCMCIA && setup_sedlbauer()
727 !request_region(cs->hw.sedl.cfg_reg, bytecnt, "sedlbauer isdn")) { setup_sedlbauer()
731 cs->hw.sedl.cfg_reg, setup_sedlbauer()
732 cs->hw.sedl.cfg_reg + bytecnt); setup_sedlbauer()
738 cs->hw.sedl.cfg_reg, setup_sedlbauer()
739 cs->hw.sedl.cfg_reg + bytecnt, setup_sedlbauer()
752 if (cs->hw.sedl.bus != SEDL_BUS_PCI) { setup_sedlbauer()
753 val = readreg(cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_ADR, setup_sedlbauer()
754 cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC, IPAC_ID); setup_sedlbauer()
759 if (cs->hw.sedl.bus == SEDL_BUS_PCMCIA) { setup_sedlbauer()
762 cs->hw.sedl.chip = SEDL_CHIP_IPAC; setup_sedlbauer()
765 if (cs->hw.sedl.chip == SEDL_CHIP_TEST) { setup_sedlbauer()
766 cs->hw.sedl.chip = SEDL_CHIP_ISAC_HSCX; setup_sedlbauer()
772 * hw.sedl.chip is now properly set setup_sedlbauer()
778 if (cs->hw.sedl.chip == SEDL_CHIP_IPAC) { setup_sedlbauer()
779 if (cs->hw.sedl.bus == SEDL_BUS_PCI) { setup_sedlbauer()
780 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_ADR; setup_sedlbauer()
781 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_IPAC; setup_sedlbauer()
782 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_IPAC; setup_sedlbauer()
784 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_ADR; setup_sedlbauer()
785 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC; setup_sedlbauer()
786 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC; setup_sedlbauer()
794 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ID); setup_sedlbauer()
802 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { setup_sedlbauer()
803 if (cs->hw.sedl.bus == SEDL_BUS_PCI) { setup_sedlbauer()
804 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + setup_sedlbauer()
806 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + setup_sedlbauer()
808 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + setup_sedlbauer()
811 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + setup_sedlbauer()
813 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + setup_sedlbauer()
815 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + setup_sedlbauer()
817 cs->hw.sedl.reset_on = cs->hw.sedl.cfg_reg + setup_sedlbauer()
819 cs->hw.sedl.reset_off = cs->hw.sedl.cfg_reg + setup_sedlbauer()
822 cs->bcs[0].hw.isar.reg = &cs->hw.sedl.isar; setup_sedlbauer()
823 cs->bcs[1].hw.isar.reg = &cs->hw.sedl.isar; setup_sedlbauer()
847 if (cs->hw.sedl.bus == SEDL_BUS_PCMCIA) { setup_sedlbauer()
848 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_ADR; setup_sedlbauer()
849 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_ISAC; setup_sedlbauer()
850 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_HSCX; setup_sedlbauer()
851 cs->hw.sedl.reset_on = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_RESET; setup_sedlbauer()
852 cs->hw.sedl.reset_off = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_RESET; setup_sedlbauer()
855 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_ADR; setup_sedlbauer()
856 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_ISAC; setup_sedlbauer()
857 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_HSCX; setup_sedlbauer()
858 cs->hw.sedl.reset_on = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_RESET_ON; setup_sedlbauer()
859 cs->hw.sedl.reset_off = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_RESET_OFF; setup_sedlbauer()
H A Dniccy.c80 return readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset); ReadISAC()
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); WriteISAC()
90 readfifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); ReadISACfifo()
95 writefifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); WriteISACfifo()
100 return readreg(cs->hw.niccy.hscx_ale, ReadHSCX()
101 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0)); ReadHSCX()
107 writereg(cs->hw.niccy.hscx_ale, WriteHSCX()
108 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
111 #define READHSCX(cs, nr, reg) readreg(cs->hw.niccy.hscx_ale, \
112 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0))
113 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
114 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0), data)
116 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.niccy.hscx_ale, \
117 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
119 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.niccy.hscx_ale, \
120 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
133 ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_interrupt()
138 outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_interrupt()
140 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, niccy_interrupt()
145 val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); niccy_interrupt()
149 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, niccy_interrupt()
156 val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); niccy_interrupt()
162 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); niccy_interrupt()
163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, niccy_interrupt()
165 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); niccy_interrupt()
166 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); niccy_interrupt()
167 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); niccy_interrupt()
168 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); niccy_interrupt()
178 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); release_io_niccy()
180 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); release_io_niccy()
181 release_region(cs->hw.niccy.cfg_reg, 0x40); release_io_niccy()
182 release_region(cs->hw.niccy.isac, 4); release_io_niccy()
184 release_region(cs->hw.niccy.isac, 2); release_io_niccy()
185 release_region(cs->hw.niccy.isac_ale, 2); release_io_niccy()
194 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_reset()
196 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_reset()
278 cs->hw.niccy.isac = card->para[1] + ISAC_PNP; setup_niccy()
279 cs->hw.niccy.hscx = card->para[1] + HSCX_PNP; setup_niccy()
280 cs->hw.niccy.isac_ale = card->para[2] + ISAC_PNP; setup_niccy()
281 cs->hw.niccy.hscx_ale = card->para[2] + HSCX_PNP; setup_niccy()
282 cs->hw.niccy.cfg_reg = 0; setup_niccy()
285 if (!request_region(cs->hw.niccy.isac, 2, "niccy data")) { setup_niccy()
288 cs->hw.niccy.isac, cs->hw.niccy.isac + 1); setup_niccy()
291 if (!request_region(cs->hw.niccy.isac_ale, 2, "niccy addr")) { setup_niccy()
294 cs->hw.niccy.isac_ale, setup_niccy()
295 cs->hw.niccy.isac_ale + 1); setup_niccy()
296 release_region(cs->hw.niccy.isac, 2); setup_niccy()
317 cs->hw.niccy.cfg_reg = pci_resource_start(niccy_dev, 0); setup_niccy()
318 if (!cs->hw.niccy.cfg_reg) { setup_niccy()
335 cs->hw.niccy.isac = pci_ioaddr + ISAC_PCI_DATA; setup_niccy()
336 cs->hw.niccy.isac_ale = pci_ioaddr + ISAC_PCI_ADDR; setup_niccy()
337 cs->hw.niccy.hscx = pci_ioaddr + HSCX_PCI_DATA; setup_niccy()
338 cs->hw.niccy.hscx_ale = pci_ioaddr + HSCX_PCI_ADDR; setup_niccy()
339 if (!request_region(cs->hw.niccy.isac, 4, "niccy")) { setup_niccy()
342 cs->hw.niccy.isac, cs->hw.niccy.isac + 4); setup_niccy()
345 if (!request_region(cs->hw.niccy.cfg_reg, 0x40, "niccy pci")) { setup_niccy()
348 cs->hw.niccy.cfg_reg, setup_niccy()
349 cs->hw.niccy.cfg_reg + 0x40); setup_niccy()
350 release_region(cs->hw.niccy.isac, 4); setup_niccy()
361 cs->irq, cs->hw.niccy.isac, cs->hw.niccy.isac_ale); setup_niccy()
H A Ddiva.c134 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset)); ReadISAC()
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); WriteISAC()
146 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); ReadISACfifo()
152 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); WriteISACfifo()
158 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset + 0x80)); ReadISAC_IPAC()
164 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset | 0x80, value); WriteISAC_IPAC()
170 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size); ReadISACfifo_IPAC()
176 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size); WriteISACfifo_IPAC()
182 return (readreg(cs->hw.diva.hscx_adr, ReadHSCX()
183 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
189 writereg(cs->hw.diva.hscx_adr, WriteHSCX()
190 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
196 return (memreadreg(cs->hw.diva.cfg_reg, offset + 0x80)); MemReadISAC_IPAC()
202 memwritereg(cs->hw.diva.cfg_reg, offset | 0x80, value); MemWriteISAC_IPAC()
209 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80); MemReadISACfifo_IPAC()
216 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++); MemWriteISACfifo_IPAC()
222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0))); MemReadHSCX()
228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value); MemWriteHSCX()
235 return (memreadreg(cs->hw.diva.cfg_reg, offset)); MemReadISAC_IPACX()
241 memwritereg(cs->hw.diva.cfg_reg, offset, value); MemWriteISAC_IPACX()
248 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0); MemReadISACfifo_IPACX()
255 memwritereg(cs->hw.diva.cfg_reg, 0, *data++); MemWriteISACfifo_IPACX()
261 return (memreadreg(cs->hw.diva.cfg_reg, offset + MemReadHSCX_IPACX()
268 memwritereg(cs->hw.diva.cfg_reg, offset + MemWriteHSCX_IPACX()
276 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
277 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
278 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
279 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
281 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
282 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
284 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
285 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
298 while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) { diva_interrupt()
299 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40); diva_interrupt()
302 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA); diva_interrupt()
309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); diva_interrupt()
310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); diva_interrupt()
311 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); diva_interrupt()
312 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); diva_interrupt()
313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); diva_interrupt()
314 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0); diva_interrupt()
328 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); diva_irq_ipac_isa()
333 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40); diva_irq_ipac_isa()
344 val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80); diva_irq_ipac_isa()
353 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); diva_irq_ipac_isa()
360 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF); diva_irq_ipac_isa()
361 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0); diva_irq_ipac_isa()
410 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { Memhscx_empty_fifo()
413 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); Memhscx_empty_fifo()
414 bcs->hw.hscx.rcvidx = 0; Memhscx_empty_fifo()
417 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; Memhscx_empty_fifo()
420 *ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0); Memhscx_empty_fifo()
421 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); Memhscx_empty_fifo()
422 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; Memhscx_empty_fifo()
423 bcs->hw.hscx.rcvidx += count; Memhscx_empty_fifo()
428 bcs->hw.hscx.hscx ? 'B' : 'A', count); Memhscx_empty_fifo()
457 MemwaitforXFW(cs, bcs->hw.hscx.hscx); Memhscx_fill_fifo()
461 bcs->hw.hscx.count += count; Memhscx_fill_fifo()
463 memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0, Memhscx_fill_fifo()
465 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa); Memhscx_fill_fifo()
470 bcs->hw.hscx.hscx ? 'B' : 'A', count); Memhscx_fill_fifo()
508 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { Memhscx_interrupt()
514 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count); Memhscx_interrupt()
519 bcs->hw.hscx.rcvidx = 0; Memhscx_interrupt()
529 memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size); Memhscx_interrupt()
532 bcs->hw.hscx.rcvidx = 0; Memhscx_interrupt()
546 bcs->ackcnt += bcs->hw.hscx.count; Memhscx_interrupt()
551 bcs->hw.hscx.count = 0; Memhscx_interrupt()
556 bcs->hw.hscx.count = 0; Memhscx_interrupt()
584 skb_push(bcs->tx_skb, bcs->hw.hscx.count); Memhscx_int_main()
585 bcs->tx_cnt += bcs->hw.hscx.count; Memhscx_int_main()
586 bcs->hw.hscx.count = 0; Memhscx_int_main()
588 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); Memhscx_int_main()
611 skb_push(bcs->tx_skb, bcs->hw.hscx.count); Memhscx_int_main()
612 bcs->tx_cnt += bcs->hw.hscx.count; Memhscx_int_main()
613 bcs->hw.hscx.count = 0; Memhscx_int_main()
615 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); Memhscx_int_main()
640 cfg = (u_char *) cs->hw.diva.pci_cfg; diva_irq_ipac_pci()
647 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA); diva_irq_ipac_pci()
652 val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40); diva_irq_ipac_pci()
663 val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80); diva_irq_ipac_pci()
672 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA); diva_irq_ipac_pci()
679 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF); diva_irq_ipac_pci()
680 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0); diva_irq_ipac_pci()
694 cfg = (u_char *) cs->hw.diva.pci_cfg; diva_irq_ipacx_pci()
713 u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg; release_io_diva()
717 if (cs->hw.diva.cfg_reg) release_io_diva()
718 iounmap((void *)cs->hw.diva.cfg_reg); release_io_diva()
719 if (cs->hw.diva.pci_cfg) release_io_diva()
720 iounmap((void *)cs->hw.diva.pci_cfg); release_io_diva()
723 del_timer(&cs->hw.diva.tl); release_io_diva()
724 if (cs->hw.diva.cfg_reg) release_io_diva()
725 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */ release_io_diva()
731 if (cs->hw.diva.cfg_reg) { release_io_diva()
732 release_region(cs->hw.diva.cfg_reg, bytecnt); release_io_diva()
740 if (cs->hw.diva.cfg_reg) { iounmap_diva()
741 iounmap((void *)cs->hw.diva.cfg_reg); iounmap_diva()
742 cs->hw.diva.cfg_reg = 0; iounmap_diva()
744 if (cs->hw.diva.pci_cfg) { iounmap_diva()
745 iounmap((void *)cs->hw.diva.pci_cfg); iounmap_diva()
746 cs->hw.diva.pci_cfg = 0; iounmap_diva()
757 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20); reset_diva()
759 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00); reset_diva()
761 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0); reset_diva()
763 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg + reset_diva()
769 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0); reset_diva()
771 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg + reset_diva()
779 cs->hw.diva.ctrl_reg = 0; /* Reset On */ reset_diva()
780 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); reset_diva()
782 cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */ reset_diva()
783 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); reset_diva()
786 cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A; reset_diva()
789 byteout(cs->hw.diva.pci_cfg + 0x69, 9); reset_diva()
790 cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A; reset_diva()
792 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); reset_diva()
807 del_timer(&cs->hw.diva.tl); diva_led_handler()
808 if (cs->hw.diva.status & DIVA_ASSIGN) diva_led_handler()
809 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
812 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
816 if (cs->hw.diva.status & 0xf000) diva_led_handler()
817 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
819 else if (cs->hw.diva.status & 0x0f00) { diva_led_handler()
820 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
824 cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ? diva_led_handler()
827 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); diva_led_handler()
829 init_timer(&cs->hw.diva.tl); diva_led_handler()
830 cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000); diva_led_handler()
831 add_timer(&cs->hw.diva.tl); diva_led_handler()
854 ireg = (unsigned int *)cs->hw.diva.pci_cfg; Diva_card_msg()
861 ireg = (unsigned int *)cs->hw.diva.pci_cfg; Diva_card_msg()
870 cs->hw.diva.status = 0; Diva_card_msg()
873 cs->hw.diva.status |= DIVA_ASSIGN; Diva_card_msg()
877 cs->hw.diva.status |= 0x0200; Diva_card_msg()
879 cs->hw.diva.status |= 0x0100; Diva_card_msg()
883 cs->hw.diva.status |= 0x2000; Diva_card_msg()
885 cs->hw.diva.status |= 0x1000; Diva_card_msg()
889 cs->hw.diva.status &= ~0x2000; Diva_card_msg()
890 cs->hw.diva.status &= ~0x0200; Diva_card_msg()
892 cs->hw.diva.status &= ~0x1000; Diva_card_msg()
893 cs->hw.diva.status &= ~0x0100; Diva_card_msg()
923 cs->hw.diva.cfg_reg, cs->irq); setup_diva_common()
930 cs->hw.diva.pci_cfg); setup_diva_common()
933 if (!request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn")) { setup_diva_common()
937 cs->hw.diva.cfg_reg, setup_diva_common()
938 cs->hw.diva.cfg_reg + bytecnt); setup_diva_common()
954 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID); setup_diva_common()
965 val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID); setup_diva_common()
979 cs->hw.diva.tl.function = (void *) diva_led_handler; setup_diva_common()
980 cs->hw.diva.tl.data = (long) cs; setup_diva_common()
981 init_timer(&cs->hw.diva.tl); setup_diva_common()
1008 cs->hw.diva.ctrl_reg = 0; setup_diva_isa()
1009 cs->hw.diva.cfg_reg = card->para[1]; setup_diva_isa()
1010 val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR, setup_diva_isa()
1011 cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID); setup_diva_isa()
1015 cs->hw.diva.ctrl = 0; setup_diva_isa()
1016 cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA; setup_diva_isa()
1017 cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA; setup_diva_isa()
1018 cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR; setup_diva_isa()
1019 cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR; setup_diva_isa()
1023 cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL; setup_diva_isa()
1024 cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA; setup_diva_isa()
1025 cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA; setup_diva_isa()
1026 cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR; setup_diva_isa()
1027 cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR; setup_diva_isa()
1102 cs->hw.diva.cfg_reg = card->para[1]; setup_diva_isapnp()
1106 cs->hw.diva.ctrl = 0; setup_diva_isapnp()
1107 cs->hw.diva.isac = setup_diva_isapnp()
1109 cs->hw.diva.hscx = setup_diva_isapnp()
1111 cs->hw.diva.isac_adr = setup_diva_isapnp()
1113 cs->hw.diva.hscx_adr = setup_diva_isapnp()
1118 cs->hw.diva.ctrl = setup_diva_isapnp()
1120 cs->hw.diva.isac = setup_diva_isapnp()
1122 cs->hw.diva.hscx = setup_diva_isapnp()
1124 cs->hw.diva.isac_adr = setup_diva_isapnp()
1126 cs->hw.diva.hscx_adr = setup_diva_isapnp()
1168 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva, 2); setup_diva_pci()
1175 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva_u, 2); setup_diva_pci()
1182 cs->hw.diva.pci_cfg = setup_diva_pci()
1184 cs->hw.diva.cfg_reg = setup_diva_pci()
1192 cs->hw.diva.pci_cfg = setup_diva_pci()
1194 cs->hw.diva.cfg_reg = setup_diva_pci()
1206 if (!cs->hw.diva.cfg_reg) { setup_diva_pci()
1215 cs->hw.diva.ctrl = 0; setup_diva_pci()
1216 cs->hw.diva.isac = 0; setup_diva_pci()
1217 cs->hw.diva.hscx = 0; setup_diva_pci()
1218 cs->hw.diva.isac_adr = 0; setup_diva_pci()
1219 cs->hw.diva.hscx_adr = 0; setup_diva_pci()
1222 cs->hw.diva.ctrl = cs->hw.diva.cfg_reg + DIVA_PCI_CTRL; setup_diva_pci()
1223 cs->hw.diva.isac = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_DATA; setup_diva_pci()
1224 cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA; setup_diva_pci()
1225 cs->hw.diva.isac_adr = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_ADR; setup_diva_pci()
1226 cs->hw.diva.hscx_adr = cs->hw.diva.cfg_reg + DIVA_HSCX_ADR; setup_diva_pci()
1251 cs->hw.diva.status = 0; setup_diva()
H A Ds0box.c98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); ReadISAC()
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); WriteISAC()
110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); ReadISACfifo()
116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); WriteISACfifo()
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); ReadHSCX()
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); WriteHSCX()
135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
137 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
152 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); s0box_interrupt()
156 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA); s0box_interrupt()
161 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); s0box_interrupt()
167 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA); s0box_interrupt()
175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); s0box_interrupt()
176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); s0box_interrupt()
177 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF); s0box_interrupt()
178 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0); s0box_interrupt()
179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); s0box_interrupt()
180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); s0box_interrupt()
188 release_region(cs->hw.teles3.cfg_reg, 8); release_io_s0box()
223 cs->hw.teles3.cfg_reg = card->para[1]; setup_s0box()
224 cs->hw.teles3.hscx[0] = -0x20; setup_s0box()
225 cs->hw.teles3.hscx[1] = 0x0; setup_s0box()
226 cs->hw.teles3.isac = 0x20; setup_s0box()
227 cs->hw.teles3.isacfifo = cs->hw.teles3.isac + 0x3e; setup_s0box()
228 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e; setup_s0box()
229 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e; setup_s0box()
231 if (!request_region(cs->hw.teles3.cfg_reg, 8, "S0Box parallel I/O")) { setup_s0box()
233 cs->hw.teles3.cfg_reg, setup_s0box()
234 cs->hw.teles3.cfg_reg + 7); setup_s0box()
239 cs->hw.teles3.isac, cs->hw.teles3.cfg_reg); setup_s0box()
241 cs->hw.teles3.hscx[0], cs->hw.teles3.hscx[1]); setup_s0box()
H A Davm_a1.c58 return (readreg(cs->hw.avm.isac, offset)); ReadISAC()
64 writereg(cs->hw.avm.isac, offset, value); WriteISAC()
70 read_fifo(cs->hw.avm.isacfifo, data, size); ReadISACfifo()
76 write_fifo(cs->hw.avm.isacfifo, data, size); WriteISACfifo()
82 return (readreg(cs->hw.avm.hscx[hscx], offset)); ReadHSCX()
88 writereg(cs->hw.avm.hscx[hscx], offset, value); WriteHSCX()
95 #define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg)
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
97 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
98 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
110 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { avm_a1_interrupt()
112 byteout(cs->hw.avm.cfg_reg, 0x1E); avm_a1_interrupt()
113 sval = bytein(cs->hw.avm.cfg_reg); avm_a1_interrupt()
117 val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); avm_a1_interrupt()
122 val = readreg(cs->hw.avm.isac, ISAC_ISTA); avm_a1_interrupt()
127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); avm_a1_interrupt()
128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); avm_a1_interrupt()
129 writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); avm_a1_interrupt()
130 writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); avm_a1_interrupt()
131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); avm_a1_interrupt()
132 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); avm_a1_interrupt()
140 release_region(cs->hw.avm.cfg_reg, 8); release_ioregs()
142 release_region(cs->hw.avm.isac + 32, 32); release_ioregs()
144 release_region(cs->hw.avm.isacfifo, 1); release_ioregs()
146 release_region(cs->hw.avm.hscx[0] + 32, 32); release_ioregs()
148 release_region(cs->hw.avm.hscxfifo[0], 1); release_ioregs()
150 release_region(cs->hw.avm.hscx[1] + 32, 32); release_ioregs()
152 release_region(cs->hw.avm.hscxfifo[1], 1); release_ioregs()
169 byteout(cs->hw.avm.cfg_reg, 0x16); AVM_card_msg()
170 byteout(cs->hw.avm.cfg_reg, 0x1E); AVM_card_msg()
191 cs->hw.avm.cfg_reg = card->para[1] + 0x1800; setup_avm_a1()
192 cs->hw.avm.isac = card->para[1] + 0x1400 - 0x20; setup_avm_a1()
193 cs->hw.avm.hscx[0] = card->para[1] + 0x400 - 0x20; setup_avm_a1()
194 cs->hw.avm.hscx[1] = card->para[1] + 0xc00 - 0x20; setup_avm_a1()
195 cs->hw.avm.isacfifo = card->para[1] + 0x1000; setup_avm_a1()
196 cs->hw.avm.hscxfifo[0] = card->para[1]; setup_avm_a1()
197 cs->hw.avm.hscxfifo[1] = card->para[1] + 0x800; setup_avm_a1()
199 if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) { setup_avm_a1()
202 cs->hw.avm.cfg_reg, setup_avm_a1()
203 cs->hw.avm.cfg_reg + 8); setup_avm_a1()
206 if (!request_region(cs->hw.avm.isac + 32, 32, "HiSax isac")) { setup_avm_a1()
209 cs->hw.avm.isac + 32, setup_avm_a1()
210 cs->hw.avm.isac + 64); setup_avm_a1()
214 if (!request_region(cs->hw.avm.isacfifo, 1, "HiSax isac fifo")) { setup_avm_a1()
217 cs->hw.avm.isacfifo); setup_avm_a1()
221 if (!request_region(cs->hw.avm.hscx[0] + 32, 32, "HiSax hscx A")) { setup_avm_a1()
224 cs->hw.avm.hscx[0] + 32, setup_avm_a1()
225 cs->hw.avm.hscx[0] + 64); setup_avm_a1()
229 if (!request_region(cs->hw.avm.hscxfifo[0], 1, "HiSax hscx A fifo")) { setup_avm_a1()
232 cs->hw.avm.hscxfifo[0]); setup_avm_a1()
236 if (!request_region(cs->hw.avm.hscx[1] + 32, 32, "HiSax hscx B")) { setup_avm_a1()
239 cs->hw.avm.hscx[1] + 32, setup_avm_a1()
240 cs->hw.avm.hscx[1] + 64); setup_avm_a1()
244 if (!request_region(cs->hw.avm.hscxfifo[1], 1, "HiSax hscx B fifo")) { setup_avm_a1()
247 cs->hw.avm.hscxfifo[1]); setup_avm_a1()
251 byteout(cs->hw.avm.cfg_reg, 0x0); setup_avm_a1()
253 byteout(cs->hw.avm.cfg_reg, 0x1); setup_avm_a1()
255 byteout(cs->hw.avm.cfg_reg, 0x0); setup_avm_a1()
260 byteout(cs->hw.avm.cfg_reg + 1, val); setup_avm_a1()
262 byteout(cs->hw.avm.cfg_reg, 0x0); setup_avm_a1()
265 val = bytein(cs->hw.avm.cfg_reg); setup_avm_a1()
267 cs->hw.avm.cfg_reg, val); setup_avm_a1()
268 val = bytein(cs->hw.avm.cfg_reg + 3); setup_avm_a1()
270 cs->hw.avm.cfg_reg + 3, val); setup_avm_a1()
271 val = bytein(cs->hw.avm.cfg_reg + 2); setup_avm_a1()
273 cs->hw.avm.cfg_reg + 2, val); setup_avm_a1()
274 val = bytein(cs->hw.avm.cfg_reg); setup_avm_a1()
276 cs->hw.avm.cfg_reg, val); setup_avm_a1()
280 cs->hw.avm.cfg_reg); setup_avm_a1()
283 cs->hw.avm.isac + 32, cs->hw.avm.isacfifo); setup_avm_a1()
286 cs->hw.avm.hscx[0] + 32, cs->hw.avm.hscxfifo[0], setup_avm_a1()
287 cs->hw.avm.hscx[1] + 32, cs->hw.avm.hscxfifo[1]); setup_avm_a1()
H A Dasuscom.c80 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset)); ReadISAC()
86 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); WriteISAC()
92 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); ReadISACfifo()
98 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); WriteISACfifo()
104 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80)); ReadISAC_IPAC()
110 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80, value); WriteISAC_IPAC()
116 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0x80, data, size); ReadISACfifo_IPAC()
122 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0x80, data, size); WriteISACfifo_IPAC()
128 return (readreg(cs->hw.asus.adr, ReadHSCX()
129 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
135 writereg(cs->hw.asus.adr, WriteHSCX()
136 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
143 #define READHSCX(cs, nr, reg) readreg(cs->hw.asus.adr, \
144 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0))
145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.asus.adr, \
146 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0), data)
148 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.asus.adr, \
149 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
151 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.asus.adr, \
152 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
164 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt()
168 val = readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA); asuscom_interrupt()
172 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt()
178 val = readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA); asuscom_interrupt()
184 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); asuscom_interrupt()
185 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); asuscom_interrupt()
186 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0xFF); asuscom_interrupt()
187 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0x0); asuscom_interrupt()
188 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0x0); asuscom_interrupt()
189 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0x0); asuscom_interrupt()
202 ista = readreg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_ISTA); asuscom_interrupt_ipac()
207 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt_ipac()
218 val = 0xfe & readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA | 0x80); asuscom_interrupt_ipac()
227 ista = readreg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_ISTA); asuscom_interrupt_ipac()
234 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_MASK, 0xFF); asuscom_interrupt_ipac()
235 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_MASK, 0xC0); asuscom_interrupt_ipac()
245 if (cs->hw.asus.cfg_reg) release_io_asuscom()
246 release_region(cs->hw.asus.cfg_reg, bytecnt); release_io_asuscom()
253 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_POTA2, 0x20); reset_asuscom()
255 byteout(cs->hw.asus.adr, ASUS_RESET); /* Reset On */ reset_asuscom()
258 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_POTA2, 0x0); reset_asuscom()
260 byteout(cs->hw.asus.adr, 0); /* Reset Off */ reset_asuscom()
263 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_CONF, 0x0); reset_asuscom()
264 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_ACFG, 0xff); reset_asuscom()
265 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_AOE, 0x0); reset_asuscom()
266 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_MASK, 0xc0); reset_asuscom()
267 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_PCFG, 0x12); reset_asuscom()
372 cs->hw.asus.cfg_reg = card->para[1]; setup_asuscom()
374 if (!request_region(cs->hw.asus.cfg_reg, bytecnt, "asuscom isdn")) { setup_asuscom()
377 cs->hw.asus.cfg_reg, setup_asuscom()
378 cs->hw.asus.cfg_reg + bytecnt); setup_asuscom()
382 cs->hw.asus.cfg_reg, cs->irq); setup_asuscom()
388 val = readreg(cs->hw.asus.cfg_reg + ASUS_IPAC_ALE, setup_asuscom()
389 cs->hw.asus.cfg_reg + ASUS_IPAC_DATA, IPAC_ID); setup_asuscom()
392 cs->hw.asus.adr = cs->hw.asus.cfg_reg + ASUS_IPAC_ALE; setup_asuscom()
393 cs->hw.asus.isac = cs->hw.asus.cfg_reg + ASUS_IPAC_DATA; setup_asuscom()
394 cs->hw.asus.hscx = cs->hw.asus.cfg_reg + ASUS_IPAC_DATA; setup_asuscom()
404 cs->hw.asus.adr = cs->hw.asus.cfg_reg + ASUS_ADR; setup_asuscom()
405 cs->hw.asus.isac = cs->hw.asus.cfg_reg + ASUS_ISAC; setup_asuscom()
406 cs->hw.asus.hscx = cs->hw.asus.cfg_reg + ASUS_HSCX; setup_asuscom()
407 cs->hw.asus.u7 = cs->hw.asus.cfg_reg + ASUS_CTRL_U7; setup_asuscom()
408 cs->hw.asus.pots = cs->hw.asus.cfg_reg + ASUS_CTRL_POTS; setup_asuscom()
H A Dteles3.c58 return (readreg(cs->hw.teles3.isac, offset)); ReadISAC()
64 writereg(cs->hw.teles3.isac, offset, value); WriteISAC()
70 read_fifo(cs->hw.teles3.isacfifo, data, size); ReadISACfifo()
76 write_fifo(cs->hw.teles3.isacfifo, data, size); WriteISACfifo()
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); ReadHSCX()
88 writereg(cs->hw.teles3.hscx[hscx], offset, value); WriteHSCX()
95 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg)
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
97 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
98 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
112 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); teles3_interrupt()
116 val = readreg(cs->hw.teles3.isac, ISAC_ISTA); teles3_interrupt()
121 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); teles3_interrupt()
127 val = readreg(cs->hw.teles3.isac, ISAC_ISTA); teles3_interrupt()
135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); teles3_interrupt()
136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); teles3_interrupt()
137 writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); teles3_interrupt()
138 writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); teles3_interrupt()
139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); teles3_interrupt()
140 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); teles3_interrupt()
149 release_region(cs->hw.teles3.isac + 32, 32); release_ioregs()
151 release_region(cs->hw.teles3.hscx[0] + 32, 32); release_ioregs()
153 release_region(cs->hw.teles3.hscx[1] + 32, 32); release_ioregs()
160 release_region(cs->hw.teles3.hscx[1], 96); release_io_teles3()
162 if (cs->hw.teles3.cfg_reg) { release_io_teles3()
164 release_region(cs->hw.teles3.cfg_reg, 1); release_io_teles3()
166 release_region(cs->hw.teles3.cfg_reg, 8); release_io_teles3()
179 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) { reset_teles3()
209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg); reset_teles3()
211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1); reset_teles3()
214 byteout(cs->hw.teles3.cfg_reg, 0xff); reset_teles3()
216 byteout(cs->hw.teles3.cfg_reg, 0x00); reset_teles3()
220 byteout(cs->hw.teles3.isac + 0x3c, 0); reset_teles3()
222 byteout(cs->hw.teles3.isac + 0x3c, 1); reset_teles3()
330 cs->hw.teles3.cfg_reg = card->para[1]; setup_teles3()
331 switch (cs->hw.teles3.cfg_reg) { setup_teles3()
335 cs->hw.teles3.cfg_reg |= 0xc00; setup_teles3()
338 cs->hw.teles3.isac = cs->hw.teles3.cfg_reg - 0x420; setup_teles3()
339 cs->hw.teles3.hscx[0] = cs->hw.teles3.cfg_reg - 0xc20; setup_teles3()
340 cs->hw.teles3.hscx[1] = cs->hw.teles3.cfg_reg - 0x820; setup_teles3()
342 cs->hw.teles3.cfg_reg = 0; setup_teles3()
343 cs->hw.teles3.hscx[0] = card->para[1] - 0x20; setup_teles3()
344 cs->hw.teles3.hscx[1] = card->para[1]; setup_teles3()
345 cs->hw.teles3.isac = card->para[1] + 0x20; setup_teles3()
347 cs->hw.teles3.cfg_reg = card->para[3]; setup_teles3()
348 cs->hw.teles3.isac = card->para[2] - 32; setup_teles3()
349 cs->hw.teles3.hscx[0] = card->para[1] - 32; setup_teles3()
350 cs->hw.teles3.hscx[1] = card->para[1]; setup_teles3()
352 cs->hw.teles3.cfg_reg = 0; setup_teles3()
353 cs->hw.teles3.isac = card->para[1] - 32; setup_teles3()
354 cs->hw.teles3.hscx[0] = card->para[2] - 32; setup_teles3()
355 cs->hw.teles3.hscx[1] = card->para[2]; setup_teles3()
358 cs->hw.teles3.isacfifo = cs->hw.teles3.isac + 0x3e; setup_teles3()
359 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e; setup_teles3()
360 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e; setup_teles3()
362 if (!request_region(cs->hw.teles3.hscx[1], 96, "HiSax Teles PCMCIA")) { setup_teles3()
366 cs->hw.teles3.hscx[1], setup_teles3()
367 cs->hw.teles3.hscx[1] + 96); setup_teles3()
372 if (cs->hw.teles3.cfg_reg) { setup_teles3()
374 if (!request_region(cs->hw.teles3.cfg_reg, 1, "teles3 cfg")) { setup_teles3()
378 cs->hw.teles3.cfg_reg); setup_teles3()
382 if (!request_region(cs->hw.teles3.cfg_reg, 8, "teles3 cfg")) { setup_teles3()
386 cs->hw.teles3.cfg_reg, setup_teles3()
387 cs->hw.teles3.cfg_reg + 8); setup_teles3()
392 if (!request_region(cs->hw.teles3.isac + 32, 32, "HiSax isac")) { setup_teles3()
396 cs->hw.teles3.isac + 32, setup_teles3()
397 cs->hw.teles3.isac + 64); setup_teles3()
398 if (cs->hw.teles3.cfg_reg) { setup_teles3()
400 release_region(cs->hw.teles3.cfg_reg, 1); setup_teles3()
402 release_region(cs->hw.teles3.cfg_reg, 8); setup_teles3()
407 if (!request_region(cs->hw.teles3.hscx[0] + 32, 32, "HiSax hscx A")) { setup_teles3()
411 cs->hw.teles3.hscx[0] + 32, setup_teles3()
412 cs->hw.teles3.hscx[0] + 64); setup_teles3()
413 if (cs->hw.teles3.cfg_reg) { setup_teles3()
415 release_region(cs->hw.teles3.cfg_reg, 1); setup_teles3()
417 release_region(cs->hw.teles3.cfg_reg, 8); setup_teles3()
423 if (!request_region(cs->hw.teles3.hscx[1] + 32, 32, "HiSax hscx B")) { setup_teles3()
427 cs->hw.teles3.hscx[1] + 32, setup_teles3()
428 cs->hw.teles3.hscx[1] + 64); setup_teles3()
429 if (cs->hw.teles3.cfg_reg) { setup_teles3()
431 release_region(cs->hw.teles3.cfg_reg, 1); setup_teles3()
433 release_region(cs->hw.teles3.cfg_reg, 8); setup_teles3()
440 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) { setup_teles3()
441 if ((val = bytein(cs->hw.teles3.cfg_reg + 0)) != 0x51) { setup_teles3()
443 cs->hw.teles3.cfg_reg + 0, val); setup_teles3()
447 if ((val = bytein(cs->hw.teles3.cfg_reg + 1)) != 0x93) { setup_teles3()
449 cs->hw.teles3.cfg_reg + 1, val); setup_teles3()
453 val = bytein(cs->hw.teles3.cfg_reg + 2);/* 0x1e=without AB setup_teles3()
462 cs->hw.teles3.cfg_reg + 2, val); setup_teles3()
470 cs->hw.teles3.isac + 32, cs->hw.teles3.cfg_reg); setup_teles3()
473 cs->hw.teles3.hscx[0] + 32, cs->hw.teles3.hscx[1] + 32); setup_teles3()
H A Dnetjet.c35 cs->hw.njet.auxd &= 0xfc; NETjet_ReadIC()
36 cs->hw.njet.auxd |= (offset >> 4) & 3; NETjet_ReadIC()
37 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_ReadIC()
38 ret = bytein(cs->hw.njet.isac + ((offset & 0xf) << 2)); NETjet_ReadIC()
45 cs->hw.njet.auxd &= 0xfc; NETjet_WriteIC()
46 cs->hw.njet.auxd |= (offset >> 4) & 3; NETjet_WriteIC()
47 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_WriteIC()
48 byteout(cs->hw.njet.isac + ((offset & 0xf) << 2), value); NETjet_WriteIC()
54 cs->hw.njet.auxd &= 0xfc; NETjet_ReadICfifo()
55 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_ReadICfifo()
56 insb(cs->hw.njet.isac, data, size); NETjet_ReadICfifo()
62 cs->hw.njet.auxd &= 0xfc; NETjet_WriteICfifo()
63 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_WriteICfifo()
64 outsb(cs->hw.njet.isac, data, size); NETjet_WriteICfifo()
81 if (p > bcs->hw.tiger.s_end) fill_mem()
82 p = bcs->hw.tiger.send; fill_mem()
99 fill_mem(bcs, bcs->hw.tiger.send, mode_tiger()
103 bcs->hw.tiger.r_tot, bcs->hw.tiger.r_err, mode_tiger()
104 bcs->hw.tiger.s_tot); mode_tiger()
107 cs->hw.njet.dmactrl = 0; mode_tiger()
108 byteout(cs->hw.njet.base + NETJET_DMACTRL, mode_tiger()
109 cs->hw.njet.dmactrl); mode_tiger()
110 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0); mode_tiger()
118 cs->hw.njet.auxd &= led; mode_tiger()
119 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); mode_tiger()
126 fill_mem(bcs, bcs->hw.tiger.send, mode_tiger()
128 bcs->hw.tiger.r_state = HDLC_ZERO_SEARCH; mode_tiger()
129 bcs->hw.tiger.r_tot = 0; mode_tiger()
130 bcs->hw.tiger.r_bitcnt = 0; mode_tiger()
131 bcs->hw.tiger.r_one = 0; mode_tiger()
132 bcs->hw.tiger.r_err = 0; mode_tiger()
133 bcs->hw.tiger.s_tot = 0; mode_tiger()
134 if (!cs->hw.njet.dmactrl) { mode_tiger()
135 fill_mem(bcs, bcs->hw.tiger.send, mode_tiger()
137 cs->hw.njet.dmactrl = 1; mode_tiger()
138 byteout(cs->hw.njet.base + NETJET_DMACTRL, mode_tiger()
139 cs->hw.njet.dmactrl); mode_tiger()
140 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0x0f); mode_tiger()
143 bcs->hw.tiger.sendp = bcs->hw.tiger.send; mode_tiger()
144 bcs->hw.tiger.free = NETJET_DMA_TXSIZE; mode_tiger()
151 cs->hw.njet.auxd |= led; mode_tiger()
152 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); mode_tiger()
158 bytein(cs->hw.njet.base + NETJET_DMACTRL), mode_tiger()
159 bytein(cs->hw.njet.base + NETJET_IRQMASK0), mode_tiger()
160 bytein(cs->hw.njet.base + NETJET_IRQSTAT0), mode_tiger()
161 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR), mode_tiger()
162 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR), mode_tiger()
163 bytein(cs->hw.njet.base + NETJET_PULSE_CNT)); mode_tiger()
200 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; \
210 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; \
230 bcs->hw.tiger.sendbuf[s_cnt++] = HDLC_FLAG_VALUE; make_raw_data()
251 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; make_raw_data()
264 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; make_raw_data()
265 bcs->hw.tiger.sendbuf[s_cnt++] = 0xff; // NJ<->NJ thoughput bug fix make_raw_data()
267 bcs->hw.tiger.sendcnt = s_cnt; make_raw_data()
269 bcs->hw.tiger.sp = bcs->hw.tiger.sendbuf; make_raw_data()
288 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; \
300 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; \
331 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; make_raw_data_56k()
358 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; make_raw_data_56k()
371 bcs->hw.tiger.sendbuf[s_cnt++] = s_val; make_raw_data_56k()
372 bcs->hw.tiger.sendbuf[s_cnt++] = 0xff; // NJ<->NJ thoughput bug fix make_raw_data_56k()
374 bcs->hw.tiger.sendcnt = s_cnt; make_raw_data_56k()
376 bcs->hw.tiger.sp = bcs->hw.tiger.sendbuf; make_raw_data_56k()
386 memcpy(skb_put(skb, count), bcs->hw.tiger.rcvbuf, count); got_frame()
393 printframe(bcs->cs, bcs->hw.tiger.rcvbuf, count, "rec"); got_frame()
402 u_int *pend = bcs->hw.tiger.rec + NETJET_DMA_RXSIZE - 1; read_raw()
403 register u_char state = bcs->hw.tiger.r_state; read_raw()
404 register u_char r_one = bcs->hw.tiger.r_one; read_raw()
405 register u_char r_val = bcs->hw.tiger.r_val; read_raw()
406 register u_int bitcnt = bcs->hw.tiger.r_bitcnt; read_raw()
423 p = bcs->hw.tiger.rec; read_raw()
426 bcs->hw.tiger.r_tot++; read_raw()
440 bcs->hw.tiger.r_tot, i, j, val); read_raw()
455 bcs->hw.tiger.r_tot, i, j, val); read_raw()
486 bcs->hw.tiger.r_fcs = PPP_INITFCS; read_raw()
487 bcs->hw.tiger.rcvbuf[0] = r_val; read_raw()
488 bcs->hw.tiger.r_fcs = PPP_FCS(bcs->hw.tiger.r_fcs, r_val); read_raw()
491 bcs->hw.tiger.r_tot, i, j, r_val, val, read_raw()
492 bcs->cs->hw.njet.irqstat0); read_raw()
513 bcs->hw.tiger.r_err++; read_raw()
520 i, j, bcs->hw.tiger.r_fcs, bcs->cs->hw.njet.irqstat0); read_raw()
521 if (bcs->hw.tiger.r_fcs == PPP_GOODFCS) { read_raw()
526 printframe(bcs->cs, bcs->hw.tiger.rcvbuf, read_raw()
528 bcs->hw.tiger.r_err++; read_raw()
554 bcs->hw.tiger.r_err++; read_raw()
559 bcs->hw.tiger.rcvbuf[(bitcnt >> 3) - 1] = r_val; read_raw()
560 bcs->hw.tiger.r_fcs = read_raw()
561 PPP_FCS(bcs->hw.tiger.r_fcs, r_val); read_raw()
567 bcs->hw.tiger.r_tot++; read_raw()
569 bcs->hw.tiger.r_state = state; read_raw()
570 bcs->hw.tiger.r_one = r_one; read_raw()
571 bcs->hw.tiger.r_val = r_val; read_raw()
572 bcs->hw.tiger.r_bitcnt = bitcnt; read_raw()
579 if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_READ) { read_tiger()
581 cs->hw.njet.irqstat0, cs->hw.njet.last_is0); read_tiger()
590 cs->hw.njet.last_is0 &= ~NETJET_IRQM0_READ; read_tiger()
591 cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ); read_tiger()
593 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ_1) read_tiger()
594 p = cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1; read_tiger()
596 p = cs->bcs[0].hw.tiger.rec + cnt - 1; read_tiger()
602 cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_READ; read_tiger()
631 write_raw(bcs, bcs->hw.tiger.sendp, bcs->hw.tiger.free); netjet_fill_dma()
633 p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR)); netjet_fill_dma()
634 sp = bcs->hw.tiger.sendp; netjet_fill_dma()
635 if (p == bcs->hw.tiger.s_end) netjet_fill_dma()
636 p = bcs->hw.tiger.send - 1; netjet_fill_dma()
637 if (sp == bcs->hw.tiger.s_end) netjet_fill_dma()
638 sp = bcs->hw.tiger.send - 1; netjet_fill_dma()
641 write_raw(bcs, bcs->hw.tiger.sendp, bcs->hw.tiger.free); netjet_fill_dma()
645 if (p > bcs->hw.tiger.s_end) netjet_fill_dma()
646 p = bcs->hw.tiger.send; netjet_fill_dma()
649 if (p > bcs->hw.tiger.s_end) netjet_fill_dma()
650 p = bcs->hw.tiger.send; netjet_fill_dma()
651 write_raw(bcs, p, bcs->hw.tiger.free - cnt); netjet_fill_dma()
654 p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR)); netjet_fill_dma()
655 cnt = bcs->hw.tiger.s_end - p; netjet_fill_dma()
657 p = bcs->hw.tiger.send + 1; netjet_fill_dma()
681 if (bcs->hw.tiger.sendcnt > cnt) { write_raw()
683 bcs->hw.tiger.sendcnt -= cnt; write_raw()
685 s_cnt = bcs->hw.tiger.sendcnt; write_raw()
686 bcs->hw.tiger.sendcnt = 0; write_raw()
693 val = bcs->channel ? ((bcs->hw.tiger.sp[i] << 8) & 0xff00) : write_raw()
694 (bcs->hw.tiger.sp[i]); write_raw()
697 if (p > bcs->hw.tiger.s_end) write_raw()
698 p = bcs->hw.tiger.send; write_raw()
700 bcs->hw.tiger.s_tot += s_cnt; write_raw()
704 bcs->hw.tiger.sendcnt, bcs->cs->hw.njet.irqstat0); write_raw()
706 printframe(bcs->cs, bcs->hw.tiger.sp, s_cnt, "snd"); write_raw()
707 bcs->hw.tiger.sp += s_cnt; write_raw()
708 bcs->hw.tiger.sendp = p; write_raw()
709 if (!bcs->hw.tiger.sendcnt) { write_raw()
725 bcs->hw.tiger.free = cnt - s_cnt; write_raw()
726 if (bcs->hw.tiger.free > (NETJET_DMA_TXSIZE / 2)) write_raw()
739 if (p > bcs->hw.tiger.s_end) write_raw()
740 p = bcs->hw.tiger.send; write_raw()
753 bcs->hw.tiger.free += cnt; write_raw()
767 if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_WRITE) { write_tiger()
769 cs->hw.njet.irqstat0, cs->hw.njet.last_is0); write_tiger()
778 cs->hw.njet.last_is0 &= ~NETJET_IRQM0_WRITE; write_tiger()
779 cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE); write_tiger()
781 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE_1) write_tiger()
782 p = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1; write_tiger()
784 p = cs->bcs[0].hw.tiger.send + cnt - 1; write_tiger()
789 cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_WRITE; write_tiger()
858 kfree(bcs->hw.tiger.rcvbuf); close_tigerstate()
859 bcs->hw.tiger.rcvbuf = NULL; close_tigerstate()
860 kfree(bcs->hw.tiger.sendbuf); close_tigerstate()
861 bcs->hw.tiger.sendbuf = NULL; close_tigerstate()
876 if (!(bcs->hw.tiger.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { open_tigerstate()
881 if (!(bcs->hw.tiger.sendbuf = kmalloc(RAW_BUFMAX, GFP_ATOMIC))) { open_tigerstate()
890 bcs->hw.tiger.sendcnt = 0; open_tigerstate()
915 if (!(cs->bcs[0].hw.tiger.send = kmalloc(NETJET_DMA_TXSIZE * sizeof(unsigned int), inittiger()
921 cs->bcs[0].hw.tiger.s_irq = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE / 2 - 1; inittiger()
922 cs->bcs[0].hw.tiger.s_end = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1; inittiger()
923 cs->bcs[1].hw.tiger.send = cs->bcs[0].hw.tiger.send; inittiger()
924 cs->bcs[1].hw.tiger.s_irq = cs->bcs[0].hw.tiger.s_irq; inittiger()
925 cs->bcs[1].hw.tiger.s_end = cs->bcs[0].hw.tiger.s_end; inittiger()
927 memset(cs->bcs[0].hw.tiger.send, 0xff, NETJET_DMA_TXSIZE * sizeof(unsigned int)); inittiger()
928 debugl1(cs, "tiger: send buf %p - %p", cs->bcs[0].hw.tiger.send, inittiger()
929 cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1); inittiger()
930 outl(virt_to_bus(cs->bcs[0].hw.tiger.send), inittiger()
931 cs->hw.njet.base + NETJET_DMA_READ_START); inittiger()
932 outl(virt_to_bus(cs->bcs[0].hw.tiger.s_irq), inittiger()
933 cs->hw.njet.base + NETJET_DMA_READ_IRQ); inittiger()
934 outl(virt_to_bus(cs->bcs[0].hw.tiger.s_end), inittiger()
935 cs->hw.njet.base + NETJET_DMA_READ_END); inittiger()
936 if (!(cs->bcs[0].hw.tiger.rec = kmalloc(NETJET_DMA_RXSIZE * sizeof(unsigned int), inittiger()
942 debugl1(cs, "tiger: rec buf %p - %p", cs->bcs[0].hw.tiger.rec, inittiger()
943 cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1); inittiger()
944 cs->bcs[1].hw.tiger.rec = cs->bcs[0].hw.tiger.rec; inittiger()
945 memset(cs->bcs[0].hw.tiger.rec, 0xff, NETJET_DMA_RXSIZE * sizeof(unsigned int)); inittiger()
946 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec), inittiger()
947 cs->hw.njet.base + NETJET_DMA_WRITE_START); inittiger()
948 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE / 2 - 1), inittiger()
949 cs->hw.njet.base + NETJET_DMA_WRITE_IRQ); inittiger()
950 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1), inittiger()
951 cs->hw.njet.base + NETJET_DMA_WRITE_END); inittiger()
953 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR), inittiger()
954 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR), inittiger()
955 bytein(cs->hw.njet.base + NETJET_PULSE_CNT)); inittiger()
956 cs->hw.njet.last_is0 = 0; inittiger()
966 kfree(cs->bcs[0].hw.tiger.send); releasetiger()
967 cs->bcs[0].hw.tiger.send = NULL; releasetiger()
968 cs->bcs[1].hw.tiger.send = NULL; releasetiger()
969 kfree(cs->bcs[0].hw.tiger.rec); releasetiger()
970 cs->bcs[0].hw.tiger.rec = NULL; releasetiger()
971 cs->bcs[1].hw.tiger.rec = NULL; releasetiger()
977 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0); release_io_netjet()
978 byteout(cs->hw.njet.base + NETJET_IRQMASK1, 0); release_io_netjet()
980 release_region(cs->hw.njet.base, 256); release_io_netjet()
H A Delsa.c178 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset)); ReadISAC()
184 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); WriteISAC()
190 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); ReadISACfifo()
196 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); WriteISACfifo()
202 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset + 0x80)); ReadISAC_IPAC()
208 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset | 0x80, value); WriteISAC_IPAC()
214 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0x80, data, size); ReadISACfifo_IPAC()
220 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0x80, data, size); WriteISACfifo_IPAC()
226 return (readreg(cs->hw.elsa.ale, ReadHSCX()
227 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
233 writereg(cs->hw.elsa.ale, WriteHSCX()
234 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
242 byteout(cs->hw.elsa.ale, off); readitac()
243 ret = bytein(cs->hw.elsa.itac); readitac()
250 byteout(cs->hw.elsa.ale, off); writeitac()
251 byteout(cs->hw.elsa.itac, data); writeitac()
259 v = bytein(cs->hw.elsa.cfg); TimerRun()
270 #define READHSCX(cs, nr, reg) readreg(cs->hw.elsa.ale, \
271 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0))
272 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.elsa.ale, \
273 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0), data)
275 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.elsa.ale, \
276 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
278 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.elsa.ale, \
279 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
299 if (cs->hw.elsa.MFlag) { elsa_interrupt()
307 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt()
312 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA); elsa_interrupt()
317 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt()
324 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA); elsa_interrupt()
333 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); elsa_interrupt()
334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); elsa_interrupt()
335 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF); elsa_interrupt()
336 if (cs->hw.elsa.status & ELIRQF_TIMER_AKTIV) { elsa_interrupt()
339 byteout(cs->hw.elsa.timer, 0); elsa_interrupt()
340 cs->hw.elsa.counter++; elsa_interrupt()
344 if (cs->hw.elsa.MFlag) { elsa_interrupt()
353 if (cs->hw.elsa.trig) elsa_interrupt()
354 byteout(cs->hw.elsa.trig, 0x00); elsa_interrupt()
355 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); elsa_interrupt()
356 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0); elsa_interrupt()
357 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0x0); elsa_interrupt()
372 val = bytein(cs->hw.elsa.cfg + 0x4c); /* PCI IRQ */ elsa_interrupt_ipac()
379 if (cs->hw.elsa.MFlag) { elsa_interrupt_ipac()
387 ista = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ISTA); elsa_interrupt_ipac()
392 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt_ipac()
403 val = 0xfe & readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA + 0x80); elsa_interrupt_ipac()
412 ista = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ISTA); elsa_interrupt_ipac()
419 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xFF); elsa_interrupt_ipac()
420 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xC0); elsa_interrupt_ipac()
430 del_timer(&cs->hw.elsa.tl); release_io_elsa()
434 if (cs->hw.elsa.ctrl) release_io_elsa()
435 byteout(cs->hw.elsa.ctrl, 0); /* LEDs Out */ release_io_elsa()
437 byteout(cs->hw.elsa.cfg + 0x4c, 0x01); /* disable IRQ */ release_io_elsa()
438 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); release_io_elsa()
440 release_region(cs->hw.elsa.cfg, 0x80); release_io_elsa()
443 byteout(cs->hw.elsa.cfg + 0x4c, 0x03); /* disable ELSA PCI IRQ */ release_io_elsa()
444 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); release_io_elsa()
445 release_region(cs->hw.elsa.cfg, 0x80); release_io_elsa()
448 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); release_io_elsa()
459 if (cs->hw.elsa.base) release_io_elsa()
460 release_region(cs->hw.elsa.base, bytecnt); release_io_elsa()
466 if (cs->hw.elsa.timer) { reset_elsa()
468 byteout(cs->hw.elsa.timer, 0); reset_elsa()
470 cs->hw.elsa.ctrl_reg |= 0x50; reset_elsa()
471 cs->hw.elsa.ctrl_reg &= ~ELSA_ISDN_RESET; /* Reset On */ reset_elsa()
472 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); reset_elsa()
474 byteout(cs->hw.elsa.timer, 0); reset_elsa()
476 cs->hw.elsa.ctrl_reg |= ELSA_ISDN_RESET; /* Reset Off */ reset_elsa()
477 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); reset_elsa()
479 byteout(cs->hw.elsa.timer, 0); reset_elsa()
481 if (cs->hw.elsa.trig) reset_elsa()
482 byteout(cs->hw.elsa.trig, 0xff); reset_elsa()
485 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_POTA2, 0x20); reset_elsa()
487 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_POTA2, 0x00); reset_elsa()
488 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xc0); reset_elsa()
491 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ACFG, 0x0); reset_elsa()
492 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_AOE, 0x3c); reset_elsa()
494 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_PCFG, 0x10); reset_elsa()
495 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ACFG, 0x4); reset_elsa()
496 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_AOE, 0xf8); reset_elsa()
498 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); reset_elsa()
500 byteout(cs->hw.elsa.cfg + 0x4c, 0x41); /* enable ELSA PCI IRQ */ reset_elsa()
502 byteout(cs->hw.elsa.cfg + 0x4c, 0x43); /* enable ELSA PCI IRQ */ reset_elsa()
571 cs->hw.elsa.base + 8); check_arcofi()
572 release_region(cs->hw.elsa.base, 8); check_arcofi()
573 if (!request_region(cs->hw.elsa.base, 16, "elsa isdn modem")) { check_arcofi()
577 cs->hw.elsa.base + 8, check_arcofi()
578 cs->hw.elsa.base + 16); check_arcofi()
585 cs->hw.elsa.base + 8); check_arcofi()
586 release_region(cs->hw.elsa.base, 8); check_arcofi()
587 if (!request_region(cs->hw.elsa.base, 16, "elsa isdn modem")) { check_arcofi()
591 cs->hw.elsa.base + 8, check_arcofi()
592 cs->hw.elsa.base + 16); check_arcofi()
598 cs->hw.elsa.base + 8); check_arcofi()
615 del_timer(&cs->hw.elsa.tl); elsa_led_handler()
616 if (cs->hw.elsa.status & ELSA_ASSIGN) elsa_led_handler()
617 cs->hw.elsa.ctrl_reg |= ELSA_STAT_LED; elsa_led_handler()
618 else if (cs->hw.elsa.status & ELSA_BAD_PWR) elsa_led_handler()
619 cs->hw.elsa.ctrl_reg &= ~ELSA_STAT_LED; elsa_led_handler()
621 cs->hw.elsa.ctrl_reg ^= ELSA_STAT_LED; elsa_led_handler()
624 if (cs->hw.elsa.status & 0xf000) elsa_led_handler()
625 cs->hw.elsa.ctrl_reg |= ELSA_LINE_LED; elsa_led_handler()
626 else if (cs->hw.elsa.status & 0x0f00) { elsa_led_handler()
627 cs->hw.elsa.ctrl_reg ^= ELSA_LINE_LED; elsa_led_handler()
630 cs->hw.elsa.ctrl_reg &= ~ELSA_LINE_LED; elsa_led_handler()
635 if (cs->hw.elsa.ctrl_reg & ELSA_LINE_LED) elsa_led_handler()
637 if (cs->hw.elsa.ctrl_reg & ELSA_STAT_LED) elsa_led_handler()
639 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, led); elsa_led_handler()
641 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); elsa_led_handler()
643 init_timer(&cs->hw.elsa.tl); elsa_led_handler()
644 cs->hw.elsa.tl.expires = jiffies + ((blink * HZ) / 1000); elsa_led_handler()
645 add_timer(&cs->hw.elsa.tl); elsa_led_handler()
672 byteout(cs->hw.elsa.timer, 0); Elsa_card_msg()
674 if (cs->hw.elsa.trig) Elsa_card_msg()
675 byteout(cs->hw.elsa.trig, 0xff); Elsa_card_msg()
688 cs->hw.elsa.counter = 0; Elsa_card_msg()
689 cs->hw.elsa.ctrl_reg |= ELSA_ENA_TIMER_INT; Elsa_card_msg()
690 cs->hw.elsa.status |= ELIRQF_TIMER_AKTIV; Elsa_card_msg()
691 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); Elsa_card_msg()
692 byteout(cs->hw.elsa.timer, 0); Elsa_card_msg()
696 cs->hw.elsa.ctrl_reg &= ~ELSA_ENA_TIMER_INT; Elsa_card_msg()
697 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); Elsa_card_msg()
698 cs->hw.elsa.status &= ~ELIRQF_TIMER_AKTIV; Elsa_card_msg()
701 cs->hw.elsa.counter); Elsa_card_msg()
702 if ((cs->hw.elsa.counter > 10) && Elsa_card_msg()
703 (cs->hw.elsa.counter < 16)) { Elsa_card_msg()
709 cs->hw.elsa.counter, cs->irq); Elsa_card_msg()
721 cs->hw.elsa.status &= 0; Elsa_card_msg()
724 cs->hw.elsa.status |= ELSA_ASSIGN; Elsa_card_msg()
728 cs->hw.elsa.status |= 0x0200; Elsa_card_msg()
730 cs->hw.elsa.status |= 0x0100; Elsa_card_msg()
734 cs->hw.elsa.status |= 0x2000; Elsa_card_msg()
736 cs->hw.elsa.status |= 0x1000; Elsa_card_msg()
740 cs->hw.elsa.status &= ~0x2000; Elsa_card_msg()
741 cs->hw.elsa.status &= ~0x0200; Elsa_card_msg()
743 cs->hw.elsa.status &= ~0x1000; Elsa_card_msg()
744 cs->hw.elsa.status &= ~0x0100; Elsa_card_msg()
749 if (cs->hw.elsa.MFlag) { Elsa_card_msg()
764 int pwr = bytein(cs->hw.elsa.ale); Elsa_card_msg()
766 cs->hw.elsa.status |= ELSA_BAD_PWR; Elsa_card_msg()
768 cs->hw.elsa.status &= ~ELSA_BAD_PWR; Elsa_card_msg()
842 cs->hw.elsa.base = card->para[0]; setup_elsa_isa()
844 if (cs->hw.elsa.base) { setup_elsa_isa()
845 if (!(cs->subtyp = probe_elsa_adr(cs->hw.elsa.base, setup_elsa_isa()
849 cs->hw.elsa.base); setup_elsa_isa()
853 cs->hw.elsa.base = probe_elsa(cs); setup_elsa_isa()
855 if (!cs->hw.elsa.base) { setup_elsa_isa()
861 cs->hw.elsa.cfg = cs->hw.elsa.base + ELSA_CONFIG; setup_elsa_isa()
862 cs->hw.elsa.ctrl = cs->hw.elsa.base + ELSA_CONTROL; setup_elsa_isa()
863 cs->hw.elsa.ale = cs->hw.elsa.base + ELSA_ALE; setup_elsa_isa()
864 cs->hw.elsa.isac = cs->hw.elsa.base + ELSA_ISAC; setup_elsa_isa()
865 cs->hw.elsa.itac = cs->hw.elsa.base + ELSA_ITAC; setup_elsa_isa()
866 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_isa()
867 cs->hw.elsa.trig = cs->hw.elsa.base + ELSA_TRIG_IRQ; setup_elsa_isa()
868 cs->hw.elsa.timer = cs->hw.elsa.base + ELSA_START_TIMER; setup_elsa_isa()
869 val = bytein(cs->hw.elsa.cfg); setup_elsa_isa()
883 val = bytein(cs->hw.elsa.ale) & ELSA_HW_RELEASE; setup_elsa_isa()
894 cs->hw.elsa.base, setup_elsa_isa()
896 val = bytein(cs->hw.elsa.ale) & ELSA_S0_POWER_BAD; setup_elsa_isa()
900 cs->hw.elsa.status |= ELSA_BAD_PWR; setup_elsa_isa()
975 cs->hw.elsa.base = card->para[1]; setup_elsa_isapnp()
982 cs->hw.elsa.cfg = cs->hw.elsa.base + ELSA_CONFIG; setup_elsa_isapnp()
983 cs->hw.elsa.ale = cs->hw.elsa.base + ELSA_ALE; setup_elsa_isapnp()
984 cs->hw.elsa.isac = cs->hw.elsa.base + ELSA_ISAC; setup_elsa_isapnp()
985 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_isapnp()
986 cs->hw.elsa.trig = cs->hw.elsa.base + ELSA_TRIG_IRQ; setup_elsa_isapnp()
987 cs->hw.elsa.timer = cs->hw.elsa.base + ELSA_START_TIMER; setup_elsa_isapnp()
988 cs->hw.elsa.ctrl = cs->hw.elsa.base + ELSA_CONTROL; setup_elsa_isapnp()
992 cs->hw.elsa.base, setup_elsa_isapnp()
1003 cs->hw.elsa.base = card->para[1]; setup_elsa_pcmcia()
1005 val = readreg(cs->hw.elsa.base + 0, cs->hw.elsa.base + 2, IPAC_ID); setup_elsa_pcmcia()
1008 cs->hw.elsa.ale = cs->hw.elsa.base + 0; setup_elsa_pcmcia()
1009 cs->hw.elsa.isac = cs->hw.elsa.base + 2; setup_elsa_pcmcia()
1010 cs->hw.elsa.hscx = cs->hw.elsa.base + 2; setup_elsa_pcmcia()
1014 cs->hw.elsa.ale = cs->hw.elsa.base + ELSA_ALE_PCM; setup_elsa_pcmcia()
1015 cs->hw.elsa.isac = cs->hw.elsa.base + ELSA_ISAC_PCM; setup_elsa_pcmcia()
1016 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_pcmcia()
1018 cs->hw.elsa.timer = 0; setup_elsa_pcmcia()
1019 cs->hw.elsa.trig = 0; setup_elsa_pcmcia()
1020 cs->hw.elsa.ctrl = 0; setup_elsa_pcmcia()
1025 cs->hw.elsa.base, setup_elsa_pcmcia()
1044 cs->hw.elsa.cfg = pci_resource_start(dev_qs1000, 1); setup_elsa_pci()
1045 cs->hw.elsa.base = pci_resource_start(dev_qs1000, 3); setup_elsa_pci()
1052 cs->hw.elsa.cfg = pci_resource_start(dev_qs3000, 1); setup_elsa_pci()
1053 cs->hw.elsa.base = pci_resource_start(dev_qs3000, 3); setup_elsa_pci()
1063 if (!(cs->hw.elsa.base && cs->hw.elsa.cfg)) { setup_elsa_pci()
1067 if ((cs->hw.elsa.cfg & 0xff) || (cs->hw.elsa.base & 0xf)) { setup_elsa_pci()
1072 cs->hw.elsa.ale = cs->hw.elsa.base; setup_elsa_pci()
1073 cs->hw.elsa.isac = cs->hw.elsa.base + 1; setup_elsa_pci()
1074 cs->hw.elsa.hscx = cs->hw.elsa.base + 1; setup_elsa_pci()
1076 cs->hw.elsa.timer = 0; setup_elsa_pci()
1077 cs->hw.elsa.trig = 0; setup_elsa_pci()
1082 cs->hw.elsa.base, setup_elsa_pci()
1083 cs->hw.elsa.cfg, setup_elsa_pci()
1129 if (cs->typ != ISDN_CTYPE_ELSA_PCMCIA && !request_region(cs->hw.elsa.base, bytecnt, "elsa isdn")) { setup_elsa_common()
1132 cs->hw.elsa.base, setup_elsa_common()
1133 cs->hw.elsa.base + bytecnt); setup_elsa_common()
1137 if (!request_region(cs->hw.elsa.cfg, 0x80, "elsa isdn pci")) { setup_elsa_common()
1140 cs->hw.elsa.cfg, setup_elsa_common()
1141 cs->hw.elsa.cfg + 0x80); setup_elsa_common()
1142 release_region(cs->hw.elsa.base, bytecnt); setup_elsa_common()
1150 cs->hw.elsa.tl.function = (void *) elsa_led_handler; setup_elsa_common()
1151 cs->hw.elsa.tl.data = (long) cs; setup_elsa_common()
1152 init_timer(&cs->hw.elsa.tl); setup_elsa_common()
1154 if (cs->hw.elsa.timer) { setup_elsa_common()
1155 byteout(cs->hw.elsa.trig, 0xff); setup_elsa_common()
1156 byteout(cs->hw.elsa.timer, 0); setup_elsa_common()
1158 byteout(cs->hw.elsa.timer, 0); /* 2. Versuch */ setup_elsa_common()
1184 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ID); setup_elsa_common()
1220 cs->hw.elsa.ctrl_reg = 0; setup_elsa()
1221 cs->hw.elsa.status = 0; setup_elsa()
1222 cs->hw.elsa.MFlag = 0; setup_elsa()
H A Dix1_micro.c78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); ReadISAC()
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); WriteISAC()
90 readfifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); ReadISACfifo()
96 writefifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); WriteISACfifo()
102 return (readreg(cs->hw.ix1.hscx_ale, ReadHSCX()
103 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
109 writereg(cs->hw.ix1.hscx_ale, WriteHSCX()
110 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
113 #define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale, \
114 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
116 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
118 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ix1.hscx_ale, \
119 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
121 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ix1.hscx_ale, \
122 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); ix1micro_interrupt()
138 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); ix1micro_interrupt()
142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); ix1micro_interrupt()
148 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); ix1micro_interrupt()
154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); ix1micro_interrupt()
155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); ix1micro_interrupt()
156 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); ix1micro_interrupt()
157 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); ix1micro_interrupt()
158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); ix1micro_interrupt()
159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); ix1micro_interrupt()
167 if (cs->hw.ix1.cfg_reg) release_io_ix1micro()
168 release_region(cs->hw.ix1.cfg_reg, 4); release_io_ix1micro()
179 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1); ix1_reset()
182 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0); ix1_reset()
280 cs->hw.ix1.isac_ale = card->para[1] + ISAC_COMMAND_OFFSET; setup_ix1micro()
281 cs->hw.ix1.hscx_ale = card->para[1] + HSCX_COMMAND_OFFSET; setup_ix1micro()
282 cs->hw.ix1.isac = card->para[1] + ISAC_DATA_OFFSET; setup_ix1micro()
283 cs->hw.ix1.hscx = card->para[1] + HSCX_DATA_OFFSET; setup_ix1micro()
284 cs->hw.ix1.cfg_reg = card->para[1]; setup_ix1micro()
286 if (cs->hw.ix1.cfg_reg) { setup_ix1micro()
287 if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) { setup_ix1micro()
291 cs->hw.ix1.cfg_reg, setup_ix1micro()
292 cs->hw.ix1.cfg_reg + 4); setup_ix1micro()
297 cs->irq, cs->hw.ix1.cfg_reg); setup_ix1micro()
H A Dmic.c68 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset)); ReadISAC()
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); WriteISAC()
80 readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); ReadISACfifo()
86 writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); WriteISACfifo()
92 return (readreg(cs->hw.mic.adr, ReadHSCX()
93 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
99 writereg(cs->hw.mic.adr, WriteHSCX()
100 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
107 #define READHSCX(cs, nr, reg) readreg(cs->hw.mic.adr, \
108 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
109 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
110 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data)
112 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.mic.adr, \
113 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
115 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.mic.adr, \
116 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
128 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); mic_interrupt()
132 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA); mic_interrupt()
136 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); mic_interrupt()
142 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA); mic_interrupt()
148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); mic_interrupt()
149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); mic_interrupt()
150 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF); mic_interrupt()
151 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0); mic_interrupt()
152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); mic_interrupt()
153 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0); mic_interrupt()
163 if (cs->hw.mic.cfg_reg) release_io_mic()
164 release_region(cs->hw.mic.cfg_reg, bytecnt); release_io_mic()
202 cs->hw.mic.cfg_reg = card->para[1]; setup_mic()
204 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR; setup_mic()
205 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC; setup_mic()
206 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX; setup_mic()
208 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) { setup_mic()
211 cs->hw.mic.cfg_reg, setup_mic()
212 cs->hw.mic.cfg_reg + bytecnt); setup_mic()
216 cs->hw.mic.cfg_reg, cs->irq); setup_mic()
H A Dhfcscard.c46 cs->hw.hfcD.timer.expires = jiffies + 75; hfcs_Timer()
48 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt | 0x80); hfcs_Timer()
49 add_timer(&cs->hw.hfcD.timer); hfcs_Timer()
57 del_timer(&cs->hw.hfcD.timer); release_io_hfcs()
58 if (cs->hw.hfcD.addr) release_io_hfcs()
59 release_region(cs->hw.hfcD.addr, 2); release_io_hfcs()
66 cs->hw.hfcD.cirm = HFCD_RESET; reset_hfcs()
68 cs->hw.hfcD.cirm |= HFCD_MEM8K; reset_hfcs()
69 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */ reset_hfcs()
71 cs->hw.hfcD.cirm = 0; reset_hfcs()
73 cs->hw.hfcD.cirm |= HFCD_MEM8K; reset_hfcs()
74 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */ reset_hfcs()
77 cs->hw.hfcD.cirm |= HFCD_INTB; reset_hfcs()
79 cs->hw.hfcD.cirm |= HFCD_INTA; reset_hfcs()
80 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); reset_hfcs()
83 cs->hw.hfcD.ctmt = HFCD_TIM25 | HFCD_AUTO_TIMER; reset_hfcs()
84 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); reset_hfcs()
85 cs->hw.hfcD.int_m2 = HFCD_IRQ_ENABLE; reset_hfcs()
86 cs->hw.hfcD.int_m1 = HFCD_INTS_B1TRANS | HFCD_INTS_B2TRANS | reset_hfcs()
89 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1); reset_hfcs()
90 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2); reset_hfcs()
94 cs->hw.hfcD.mst_m = HFCD_MASTER; reset_hfcs()
95 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */ reset_hfcs()
96 cs->hw.hfcD.sctrl = 0; reset_hfcs()
97 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); reset_hfcs()
119 mod_timer(&cs->hw.hfcD.timer, jiffies + delay); hfcs_card_msg()
127 cs->hw.hfcD.ctmt |= HFCD_TIM800; hfcs_card_msg()
128 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); hfcs_card_msg()
129 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); hfcs_card_msg()
218 cs->hw.hfcD.addr = card->para[1] & 0xfffe; setup_hfcs()
220 cs->hw.hfcD.cip = 0; setup_hfcs()
221 cs->hw.hfcD.int_s1 = 0; setup_hfcs()
222 cs->hw.hfcD.send = NULL; setup_hfcs()
223 cs->bcs[0].hw.hfc.send = NULL; setup_hfcs()
224 cs->bcs[1].hw.hfc.send = NULL; setup_hfcs()
225 cs->hw.hfcD.dfifosize = 512; setup_hfcs()
227 cs->hw.hfcD.fifo = 255; setup_hfcs()
229 cs->hw.hfcD.bfifosize = 1024 + 512; setup_hfcs()
231 cs->hw.hfcD.bfifosize = 7 * 1024 + 512; setup_hfcs()
234 if (!request_region(cs->hw.hfcD.addr, 2, "HFCS isdn")) { setup_hfcs()
238 cs->hw.hfcD.addr, setup_hfcs()
239 cs->hw.hfcD.addr + 2); setup_hfcs()
244 cs->hw.hfcD.addr, setup_hfcs()
248 outb(0x00, cs->hw.hfcD.addr); setup_hfcs()
249 outb(0x56, cs->hw.hfcD.addr | 1); setup_hfcs()
252 outb(0x00, cs->hw.hfcD.addr); setup_hfcs()
253 outb(0x57, cs->hw.hfcD.addr | 1); setup_hfcs()
256 cs->hw.hfcD.timer.function = (void *) hfcs_Timer; setup_hfcs()
257 cs->hw.hfcD.timer.data = (long) cs; setup_hfcs()
258 init_timer(&cs->hw.hfcD.timer); setup_hfcs()
H A Dnj_s.c36 s1val = bytein(cs->hw.njet.base + NETJET_IRQSTAT1); netjet_s_interrupt()
55 s0val = bytein(cs->hw.njet.base + NETJET_IRQSTAT0); netjet_s_interrupt()
61 byteout(cs->hw.njet.base + NETJET_IRQSTAT0, s0val); netjet_s_interrupt()
64 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < netjet_s_interrupt()
65 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) netjet_s_interrupt()
70 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < netjet_s_interrupt()
71 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) netjet_s_interrupt()
76 if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */ netjet_s_interrupt()
80 cs->hw.njet.last_is0, s0val); netjet_s_interrupt()
84 cs->hw.njet.irqstat0 = s0val; netjet_s_interrupt()
85 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != netjet_s_interrupt()
86 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) netjet_s_interrupt()
89 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != netjet_s_interrupt()
90 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) netjet_s_interrupt()
103 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ reset_netjet_s()
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_s()
109 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ reset_netjet_s()
111 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ reset_netjet_s()
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_s()
114 cs->hw.njet.auxd = 0; reset_netjet_s()
115 cs->hw.njet.dmactrl = 0; reset_netjet_s()
116 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); reset_netjet_s()
117 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); reset_netjet_s()
118 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); reset_netjet_s()
163 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); njs_pci_probe()
164 if (!cs->hw.njet.base) { njs_pci_probe()
192 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; njs_cs_init()
193 cs->hw.njet.isac = cs->hw.njet.base | NETJET_ISAC_OFF; njs_cs_init()
195 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ njs_cs_init()
196 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); njs_cs_init()
199 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ njs_cs_init()
200 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); njs_cs_init()
203 cs->hw.njet.auxd = 0xC0; njs_cs_init()
204 cs->hw.njet.dmactrl = 0; njs_cs_init()
206 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); njs_cs_init()
207 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); njs_cs_init()
208 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); njs_cs_init()
232 cs->subtyp ? "TJ320" : "TJ300", cs->hw.njet.base, cs->irq); njs_cs_init_rest()
233 if (!request_region(cs->hw.njet.base, bytecnt, "netjet-s isdn")) { njs_cs_init_rest()
236 cs->hw.njet.base, njs_cs_init_rest()
237 cs->hw.njet.base + bytecnt); njs_cs_init_rest()
H A Dnj_u.c36 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) & netjet_u_interrupt()
49 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < netjet_u_interrupt()
50 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) netjet_u_interrupt()
55 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < netjet_u_interrupt()
56 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) netjet_u_interrupt()
61 if (sval != cs->hw.njet.last_is0) /* we have a DMA interrupt */ netjet_u_interrupt()
67 cs->hw.njet.irqstat0 = sval; netjet_u_interrupt()
68 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != netjet_u_interrupt()
69 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) netjet_u_interrupt()
72 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != netjet_u_interrupt()
73 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) netjet_u_interrupt()
86 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ reset_netjet_u()
87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_u()
89 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ reset_netjet_u()
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_u()
93 cs->hw.njet.auxd = 0xC0; reset_netjet_u()
94 cs->hw.njet.dmactrl = 0; reset_netjet_u()
95 byteout(cs->hw.njet.auxa, 0); reset_netjet_u()
96 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); reset_netjet_u()
97 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); reset_netjet_u()
98 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); reset_netjet_u()
141 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); nju_pci_probe()
142 if (!cs->hw.njet.base) { nju_pci_probe()
152 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; nju_cs_init()
153 cs->hw.njet.isac = cs->hw.njet.base | NETJET_ISAC_OFF; nju_cs_init()
156 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ nju_cs_init()
157 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); nju_cs_init()
160 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ nju_cs_init()
161 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); nju_cs_init()
164 cs->hw.njet.auxd = 0xC0; nju_cs_init()
165 cs->hw.njet.dmactrl = 0; nju_cs_init()
167 byteout(cs->hw.njet.auxa, 0); nju_cs_init()
168 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); nju_cs_init()
169 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); nju_cs_init()
170 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); nju_cs_init()
194 cs->hw.njet.base, cs->irq); nju_cs_init_rest()
195 if (!request_region(cs->hw.njet.base, bytecnt, "netspider-u isdn")) { nju_cs_init_rest()
199 cs->hw.njet.base, nju_cs_init_rest()
200 cs->hw.njet.base + bytecnt); nju_cs_init_rest()
H A Delsa_ser.c51 u_int val = inb(cs->hw.elsa.base + 8 + offset); serial_in()
55 return inb(cs->hw.elsa.base + 8 + offset); serial_in()
63 u_int val = inb(cs->hw.elsa.base + 8 + offset); serial_inp()
66 u_int val = inb_p(cs->hw.elsa.base + 8 + offset); serial_inp()
72 return inb(cs->hw.elsa.base + 8 + offset); serial_inp()
74 return inb_p(cs->hw.elsa.base + 8 + offset); serial_inp()
84 outb(value, cs->hw.elsa.base + 8 + offset); serial_out()
98 outb(value, cs->hw.elsa.base + 8 + offset); serial_outp()
100 outb_p(value, cs->hw.elsa.base + 8 + offset); serial_outp()
130 cs->hw.elsa.IER &= ~UART_IER_MSI; change_speed()
131 cs->hw.elsa.IER |= UART_IER_MSI; change_speed()
132 serial_outp(cs, UART_IER, cs->hw.elsa.IER); change_speed()
174 cs->hw.elsa.MCR = 0; mstartup()
175 cs->hw.elsa.MCR = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; mstartup()
176 serial_outp(cs, UART_MCR, cs->hw.elsa.MCR); mstartup()
181 cs->hw.elsa.IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; mstartup()
182 serial_outp(cs, UART_IER, cs->hw.elsa.IER); /* enable interrupts */ mstartup()
192 cs->hw.elsa.transcnt = cs->hw.elsa.transp = 0; mstartup()
193 cs->hw.elsa.rcvcnt = cs->hw.elsa.rcvp = 0; mstartup()
199 cs->hw.elsa.MFlag = 1; mstartup()
220 cs->hw.elsa.IER = 0; mshutdown()
222 cs->hw.elsa.MCR &= ~UART_MCR_OUT2; mshutdown()
227 cs->hw.elsa.MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); mshutdown()
228 serial_outp(cs, UART_MCR, cs->hw.elsa.MCR); mshutdown()
250 if (len > MAX_MODEM_BUF - cs->hw.elsa.transcnt) write_modem()
251 len = MAX_MODEM_BUF - cs->hw.elsa.transcnt; write_modem()
252 fp = cs->hw.elsa.transcnt + cs->hw.elsa.transp; write_modem()
258 cs->hw.elsa.transbuf + fp, count); write_modem()
260 cs->hw.elsa.transcnt += count; write_modem()
266 cs->hw.elsa.transbuf + fp, count); write_modem()
268 cs->hw.elsa.transcnt += count; write_modem()
271 if (cs->hw.elsa.transcnt && write_modem()
272 !(cs->hw.elsa.IER & UART_IER_THRI)) { write_modem()
273 cs->hw.elsa.IER |= UART_IER_THRI; write_modem()
274 serial_outp(cs, UART_IER, cs->hw.elsa.IER); write_modem()
291 bcs->ackcnt += bcs->hw.hscx.count; modem_fill()
300 bcs->hw.hscx.count = 0; modem_fill()
317 if (cs->hw.elsa.rcvcnt >= MAX_MODEM_BUF) receive_chars()
319 cs->hw.elsa.rcvbuf[cs->hw.elsa.rcvcnt++] = ch; receive_chars()
332 if (cs->hw.elsa.MFlag == 2) { receive_chars()
333 if (!(skb = dev_alloc_skb(cs->hw.elsa.rcvcnt))) receive_chars()
336 memcpy(skb_put(skb, cs->hw.elsa.rcvcnt), cs->hw.elsa.rcvbuf, receive_chars()
337 cs->hw.elsa.rcvcnt); receive_chars()
338 skb_queue_tail(&cs->hw.elsa.bcs->rqueue, skb); receive_chars()
340 schedule_event(cs->hw.elsa.bcs, B_RCVBUFREADY); receive_chars()
345 t += sprintf(t, "modem read cnt %d", cs->hw.elsa.rcvcnt); receive_chars()
346 QuickHex(t, cs->hw.elsa.rcvbuf, cs->hw.elsa.rcvcnt); receive_chars()
349 cs->hw.elsa.rcvcnt = 0; receive_chars()
356 debugl1(cs, "transmit_chars: p(%x) cnt(%x)", cs->hw.elsa.transp, transmit_chars()
357 cs->hw.elsa.transcnt); transmit_chars()
359 if (cs->hw.elsa.transcnt <= 0) { transmit_chars()
360 cs->hw.elsa.IER &= ~UART_IER_THRI; transmit_chars()
361 serial_out(cs, UART_IER, cs->hw.elsa.IER); transmit_chars()
366 serial_outp(cs, UART_TX, cs->hw.elsa.transbuf[cs->hw.elsa.transp++]); transmit_chars()
367 if (cs->hw.elsa.transp >= MAX_MODEM_BUF) transmit_chars()
368 cs->hw.elsa.transp = 0; transmit_chars()
369 if (--cs->hw.elsa.transcnt <= 0) transmit_chars()
372 if ((cs->hw.elsa.transcnt < WAKEUP_CHARS) && (cs->hw.elsa.MFlag == 2)) transmit_chars()
373 modem_fill(cs->hw.elsa.bcs); transmit_chars()
380 if (cs->hw.elsa.transcnt <= 0) { transmit_chars()
381 cs->hw.elsa.IER &= ~UART_IER_THRI; transmit_chars()
382 serial_outp(cs, UART_IER, cs->hw.elsa.IER); transmit_chars()
431 if (bcs->hw.hscx.rcvbuf) { close_elsastate()
433 kfree(bcs->hw.hscx.rcvbuf); close_elsastate()
434 bcs->hw.hscx.rcvbuf = NULL; close_elsastate()
453 if (len > (MAX_MODEM_BUF - cs->hw.elsa.transcnt)) { modem_write_cmd()
456 fp = cs->hw.elsa.transcnt + cs->hw.elsa.transp; modem_write_cmd()
461 memcpy(cs->hw.elsa.transbuf + fp, msg, count); modem_write_cmd()
462 cs->hw.elsa.transcnt += count; modem_write_cmd()
467 memcpy(cs->hw.elsa.transbuf + fp, msg, count); modem_write_cmd()
468 cs->hw.elsa.transcnt += count; modem_write_cmd()
469 if (cs->hw.elsa.transcnt && modem_write_cmd()
470 !(cs->hw.elsa.IER & UART_IER_THRI)) { modem_write_cmd()
471 cs->hw.elsa.IER |= UART_IER_THRI; modem_write_cmd()
472 serial_outp(cs, UART_IER, cs->hw.elsa.IER); modem_write_cmd()
483 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
489 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
495 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
501 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
507 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
513 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
519 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
532 while (timeout-- && cs->hw.elsa.transcnt) modem_set_dial()
541 while (timeout-- && cs->hw.elsa.transcnt) modem_set_dial()
561 bcs->hw.hscx.count = 0; modem_l2l1()
571 bcs->cs->hw.elsa.MFlag = 2; modem_l2l1()
578 bcs->cs->hw.elsa.MFlag = 1; modem_l2l1()
599 bcs->hw.hscx.rcvbuf = bcs->cs->hw.elsa.rcvbuf; setstack_elsa()
606 bcs->hw.hscx.rcvidx = 0; setstack_elsa()
608 bcs->cs->hw.elsa.bcs = bcs; setstack_elsa()
626 if (!(cs->hw.elsa.rcvbuf = kmalloc(MAX_MODEM_BUF, init_modem()
629 "Elsa: No modem mem hw.elsa.rcvbuf\n"); init_modem()
632 if (!(cs->hw.elsa.transbuf = kmalloc(MAX_MODEM_BUF, init_modem()
635 "Elsa: No modem mem hw.elsa.transbuf\n"); init_modem()
636 kfree(cs->hw.elsa.rcvbuf); init_modem()
637 cs->hw.elsa.rcvbuf = NULL; init_modem()
649 cs->hw.elsa.MFlag = 0; release_modem()
650 if (cs->hw.elsa.transbuf) { release_modem()
651 if (cs->hw.elsa.rcvbuf) { release_modem()
653 kfree(cs->hw.elsa.rcvbuf); release_modem()
654 cs->hw.elsa.rcvbuf = NULL; release_modem()
656 kfree(cs->hw.elsa.transbuf); release_modem()
657 cs->hw.elsa.transbuf = NULL; release_modem()
H A Disurf.c39 return (readb(cs->hw.isurf.isac + offset)); ReadISAC()
45 writeb(value, cs->hw.isurf.isac + offset); mb(); WriteISAC()
53 data[i] = readb(cs->hw.isurf.isac); ReadISACfifo()
61 writeb(data[i], cs->hw.isurf.isac); mb(); WriteISACfifo()
74 return (readb(cs->hw.isurf.isar + offset)); ReadISAR()
80 writeb(value, cs->hw.isurf.isar + offset); mb(); WriteISAR()
92 val = readb(cs->hw.isurf.isar + ISAR_IRQBIT); isurf_interrupt()
96 val = readb(cs->hw.isurf.isac + ISAC_ISTA); isurf_interrupt()
100 val = readb(cs->hw.isurf.isar + ISAR_IRQBIT); isurf_interrupt()
106 val = readb(cs->hw.isurf.isac + ISAC_ISTA); isurf_interrupt()
115 writeb(0, cs->hw.isurf.isar + ISAR_IRQBIT); mb(); isurf_interrupt()
116 writeb(0xFF, cs->hw.isurf.isac + ISAC_MASK); mb(); isurf_interrupt()
117 writeb(0, cs->hw.isurf.isac + ISAC_MASK); mb(); isurf_interrupt()
118 writeb(ISAR_IRQMSK, cs->hw.isurf.isar + ISAR_IRQBIT); mb(); isurf_interrupt()
126 release_region(cs->hw.isurf.reset, 1); release_io_isurf()
127 iounmap(cs->hw.isurf.isar); release_io_isurf()
128 release_mem_region(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE); release_io_isurf()
136 byteout(cs->hw.isurf.reset, chips); /* Reset On */ reset_isurf()
138 byteout(cs->hw.isurf.reset, ISURF_ISAR_EA); /* Reset Off */ reset_isurf()
160 writeb(0, cs->hw.isurf.isar + ISAR_IRQBIT); mb(); ISurf_card_msg()
212 cs->hw.isurf.reset = card->para[1]; setup_isurf()
213 cs->hw.isurf.phymem = card->para[2]; setup_isurf()
238 cs->hw.isurf.reset = pnp_port_start(pnp_d, 0); setup_isurf()
239 cs->hw.isurf.phymem = pnp_mem_start(pnp_d, 1); setup_isurf()
241 if (!cs->irq || !cs->hw.isurf.reset || !cs->hw.isurf.phymem) { setup_isurf()
243 cs->irq, cs->hw.isurf.reset, cs->hw.isurf.phymem); setup_isurf()
260 if (!request_region(cs->hw.isurf.reset, 1, "isurf isdn")) { setup_isurf()
263 cs->hw.isurf.reset); setup_isurf()
266 if (!request_region(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE, "isurf iomem")) { setup_isurf()
269 cs->hw.isurf.phymem, setup_isurf()
270 cs->hw.isurf.phymem + ISURF_IOMEM_SIZE); setup_isurf()
271 release_region(cs->hw.isurf.reset, 1); setup_isurf()
274 cs->hw.isurf.isar = ioremap(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE); setup_isurf()
275 cs->hw.isurf.isac = cs->hw.isurf.isar + ISURF_ISAC_OFFSET; setup_isurf()
278 cs->hw.isurf.reset, setup_isurf()
279 cs->hw.isurf.phymem, setup_isurf()
290 cs->bcs[0].hw.isar.reg = &cs->hw.isurf.isar_r; setup_isurf()
291 cs->bcs[1].hw.isar.reg = &cs->hw.isurf.isar_r; setup_isurf()
H A Dbkm_a8.c80 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80)); ReadISAC()
86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); WriteISAC()
92 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); ReadISACfifo()
98 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); WriteISACfifo()
105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); ReadHSCX()
111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
119 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, set_ipac_active()
127 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
128 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
130 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
131 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
132 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
133 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
134 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
146 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); bkm_interrupt_ipac()
155 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40); bkm_interrupt_ipac()
167 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80); bkm_interrupt_ipac()
176 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); bkm_interrupt_ipac()
184 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); bkm_interrupt_ipac()
185 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); bkm_interrupt_ipac()
193 release_region(cs->hw.ax.base & 0xffffffc0, 128); release_io_sct_quadro()
195 release_region(cs->hw.ax.plx_adr, 64); release_io_sct_quadro()
203 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41)); enable_bkm_int()
205 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41)); enable_bkm_int()
213 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4)); reset_bkm()
216 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4)); reset_bkm()
370 cs->hw.ax.plx_adr = pci_ioaddr1; setup_sct_quadro()
374 cs->hw.ax.base = pci_ioaddr5 + 0x00; setup_sct_quadro()
390 cs->hw.ax.base = pci_ioaddr4 + 0x08; setup_sct_quadro()
395 cs->hw.ax.base = pci_ioaddr3 + 0x10; setup_sct_quadro()
400 cs->hw.ax.base = pci_ioaddr2 + 0x20; setup_sct_quadro()
406 cs->hw.ax.data_adr = cs->hw.ax.base + 4; setup_sct_quadro()
411 cs->hw.ax.plx_adr, setup_sct_quadro()
412 cs->hw.ax.base, setup_sct_quadro()
413 cs->hw.ax.data_adr, setup_sct_quadro()
431 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID)); setup_sct_quadro()
H A Dteles0.c100 return (readisac(cs->hw.teles0.membase, offset)); ReadISAC()
106 writeisac(cs->hw.teles0.membase, offset, value); WriteISAC()
112 read_fifo_isac(cs->hw.teles0.membase, data, size); ReadISACfifo()
118 write_fifo_isac(cs->hw.teles0.membase, data, size); WriteISACfifo()
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX()
130 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
153 val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); teles0_interrupt()
157 val = readisac(cs->hw.teles0.membase, ISAC_ISTA); teles0_interrupt()
162 val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); teles0_interrupt()
168 val = readisac(cs->hw.teles0.membase, ISAC_ISTA); teles0_interrupt()
174 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); teles0_interrupt()
175 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); teles0_interrupt()
176 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); teles0_interrupt()
177 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); teles0_interrupt()
178 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); teles0_interrupt()
179 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); teles0_interrupt()
187 if (cs->hw.teles0.cfg_reg) release_io_teles0()
188 release_region(cs->hw.teles0.cfg_reg, 8); release_io_teles0()
189 iounmap(cs->hw.teles0.membase); release_io_teles0()
190 release_mem_region(cs->hw.teles0.phymem, TELES_IOMEM_SIZE); release_io_teles0()
198 if (cs->hw.teles0.cfg_reg) { reset_teles0()
228 cfval |= ((cs->hw.teles0.phymem >> 9) & 0xF0); reset_teles0()
229 byteout(cs->hw.teles0.cfg_reg + 4, cfval); reset_teles0()
231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1); reset_teles0()
234 writeb(0, cs->hw.teles0.membase + 0x80); mb(); reset_teles0()
236 writeb(1, cs->hw.teles0.membase + 0x80); mb(); reset_teles0()
278 cs->hw.teles0.cfg_reg = card->para[2]; setup_teles0()
280 cs->hw.teles0.cfg_reg = 0; setup_teles0()
289 if (cs->hw.teles0.cfg_reg) { setup_teles0()
290 if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) { setup_teles0()
294 cs->hw.teles0.cfg_reg, setup_teles0()
295 cs->hw.teles0.cfg_reg + 8); setup_teles0()
299 if (cs->hw.teles0.cfg_reg) { setup_teles0()
300 if ((val = bytein(cs->hw.teles0.cfg_reg + 0)) != 0x51) { setup_teles0()
302 cs->hw.teles0.cfg_reg + 0, val); setup_teles0()
303 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
306 if ((val = bytein(cs->hw.teles0.cfg_reg + 1)) != 0x93) { setup_teles0()
308 cs->hw.teles0.cfg_reg + 1, val); setup_teles0()
309 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
312 val = bytein(cs->hw.teles0.cfg_reg + 2); /* 0x1e=without AB setup_teles0()
318 cs->hw.teles0.cfg_reg + 2, val); setup_teles0()
319 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
325 cs->hw.teles0.phymem = card->para[1]; setup_teles0()
326 if (!request_mem_region(cs->hw.teles0.phymem, TELES_IOMEM_SIZE, "teles iomem")) { setup_teles0()
330 cs->hw.teles0.phymem, setup_teles0()
331 cs->hw.teles0.phymem + TELES_IOMEM_SIZE); setup_teles0()
332 if (cs->hw.teles0.cfg_reg) setup_teles0()
333 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
336 cs->hw.teles0.membase = ioremap(cs->hw.teles0.phymem, TELES_IOMEM_SIZE); setup_teles0()
340 cs->hw.teles0.membase, cs->hw.teles0.cfg_reg); setup_teles0()
H A Dsportster.c56 return (bytein(calc_off(cs->hw.spt.isac, offset))); ReadISAC()
62 byteout(calc_off(cs->hw.spt.isac, offset), value); WriteISAC()
68 read_fifo(cs->hw.spt.isac, data, size); ReadISACfifo()
74 write_fifo(cs->hw.spt.isac, data, size); WriteISACfifo()
80 return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset))); ReadHSCX()
86 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value); WriteHSCX()
93 #define READHSCX(cs, nr, reg) bytein(calc_off(cs->hw.spt.hscx[nr], reg))
94 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
95 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
96 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
129 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ + 1); sportster_interrupt()
139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0); release_io_sportster()
141 adr = cs->hw.spt.cfg_reg + i * 1024; release_io_sportster()
149 cs->hw.spt.res_irq |= SPORTSTER_RESET; /* Reset On */ reset_sportster()
150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); reset_sportster()
152 cs->hw.spt.res_irq &= ~SPORTSTER_RESET; /* Reset Off */ reset_sportster()
153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); reset_sportster()
175 cs->hw.spt.res_irq |= SPORTSTER_INTE; /* IRQ On */ Sportster_card_msg()
176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); Sportster_card_msg()
191 adr = cs->hw.spt.cfg_reg + i * 1024; get_io_range()
203 adr = cs->hw.spt.cfg_reg + j * 1024; get_io_range()
220 cs->hw.spt.cfg_reg = card->para[1]; setup_sportster()
224 cs->hw.spt.isac = cs->hw.spt.cfg_reg + SPORTSTER_ISAC; setup_sportster()
225 cs->hw.spt.hscx[0] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXA; setup_sportster()
226 cs->hw.spt.hscx[1] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXB; setup_sportster()
229 case 5: cs->hw.spt.res_irq = 1; setup_sportster()
231 case 7: cs->hw.spt.res_irq = 2; setup_sportster()
233 case 10:cs->hw.spt.res_irq = 3; setup_sportster()
235 case 11:cs->hw.spt.res_irq = 4; setup_sportster()
237 case 12:cs->hw.spt.res_irq = 5; setup_sportster()
239 case 14:cs->hw.spt.res_irq = 6; setup_sportster()
241 case 15:cs->hw.spt.res_irq = 7; setup_sportster()
248 cs->irq, cs->hw.spt.cfg_reg); setup_sportster()
H A Denternow_pci.c85 * From address hw.njet.base + TJ_AMD_PORT onwards, the AMD
87 * -> 0x01 of the AMD at hw.njet.base + 0C4 */
101 return (inb(cs->hw.njet.isac + 4 * offset)); ReadByteAmd7930()
105 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); ReadByteAmd7930()
106 return (inb(cs->hw.njet.isac + 4 * AMD_DR)); ReadByteAmd7930()
116 outb(value, cs->hw.njet.isac + 4 * offset); WriteByteAmd7930()
120 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); WriteByteAmd7930()
121 outb(value, cs->hw.njet.isac + 4 * AMD_DR); WriteByteAmd7930()
129 outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1); enpci_setIrqMask()
131 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); enpci_setIrqMask()
156 cs->hw.njet.ctrl_reg = 0x07; reset_enpci()
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); reset_enpci()
160 cs->hw.njet.ctrl_reg = 0x30; reset_enpci()
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); reset_enpci()
164 cs->hw.njet.auxd = 0; // LED-status reset_enpci()
165 cs->hw.njet.dmactrl = 0; reset_enpci()
166 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); reset_enpci()
167 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); reset_enpci()
168 outb(cs->hw.njet.auxd, cs->hw.njet.auxa); // LED off reset_enpci()
201 cs->hw.njet.auxd = TJ_AMD_IRQ << 1; enpci_card_msg()
202 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
206 cs->hw.njet.auxd = 0; enpci_card_msg()
207 outb(0x00, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
218 cs->hw.njet.auxd |= TJ_AMD_IRQ << 2; enpci_card_msg()
219 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
231 cs->hw.njet.auxd &= ~(TJ_AMD_IRQ << 2); enpci_card_msg()
232 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
250 s1val = inb(cs->hw.njet.base + NETJET_IRQSTAT1); enpci_interrupt()
260 s0val = inb(cs->hw.njet.base + NETJET_IRQSTAT0); enpci_interrupt()
266 outb(s0val, cs->hw.njet.base + NETJET_IRQSTAT0); enpci_interrupt()
270 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < enpci_interrupt()
271 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) enpci_interrupt()
276 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < enpci_interrupt()
277 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) enpci_interrupt()
282 if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */ enpci_interrupt()
288 cs->hw.njet.irqstat0 = s0val; enpci_interrupt()
289 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != enpci_interrupt()
290 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) enpci_interrupt()
293 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != enpci_interrupt()
294 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) enpci_interrupt()
312 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); en_pci_probe()
313 if (!cs->hw.njet.base) { en_pci_probe()
330 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; en_cs_init()
331 cs->hw.njet.isac = cs->hw.njet.base + 0xC0; // Fenster zum AMD en_cs_init()
334 cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff en_cs_init()
335 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); en_cs_init()
339 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */ en_cs_init()
340 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); en_cs_init()
343 cs->hw.njet.auxd = 0x00; // war 0xc0 en_cs_init()
344 cs->hw.njet.dmactrl = 0; en_cs_init()
346 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); en_cs_init()
347 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); en_cs_init()
348 outb(cs->hw.njet.auxd, cs->hw.njet.auxa); en_cs_init()
357 cs->hw.njet.base, cs->irq); en_cs_init_rest()
358 if (!request_region(cs->hw.njet.base, bytecnt, "Fn_ISDN")) { en_cs_init_rest()
361 cs->hw.njet.base, en_cs_init_rest()
362 cs->hw.njet.base + bytecnt); en_cs_init_rest()
367 cs->hw.njet.last_is0 = 0; en_cs_init_rest()
H A Dhfc_sx.c64 byteout(cs->hw.hfcsx.base + 1, regnum); Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); Write_hfc()
73 byteout(cs->hw.hfcsx.base + 1, regnum); Read_hfc()
74 ret = bytein(cs->hw.hfcsx.base); Read_hfc()
85 if (fifo == cs->hw.hfcsx.last_fifo) fifo_select()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); fifo_select()
90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ fifo_select()
92 byteout(cs->hw.hfcsx.base, fifo); fifo_select()
93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ fifo_select()
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM); reset_fifo()
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ reset_fifo()
107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ reset_fifo()
133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ write_fifo()
157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; write_fifo()
197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ write_fifo()
220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ read_fifo()
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ read_fifo()
314 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ release_io_hfcsx()
315 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); release_io_hfcsx()
319 del_timer(&cs->hw.hfcsx.timer); release_io_hfcsx()
320 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ release_io_hfcsx()
321 kfree(cs->hw.hfcsx.extra); release_io_hfcsx()
322 cs->hw.hfcsx.extra = NULL; release_io_hfcsx()
332 if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */ set_fifo_size()
334 if ((cs->hw.hfcsx.chip >> 4) == 9) { set_fifo_size()
335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; set_fifo_size()
339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; set_fifo_size()
340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ set_fifo_size()
352 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ reset_hfcsx()
353 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); reset_hfcsx()
357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */ reset_hfcsx()
359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ reset_hfcsx()
363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ reset_hfcsx()
368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ reset_hfcsx()
369 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); reset_hfcsx()
372 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; reset_hfcsx()
373 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ reset_hfcsx()
374 cs->hw.hfcsx.bswapped = 0; /* no exchange */ reset_hfcsx()
375 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ reset_hfcsx()
376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; reset_hfcsx()
377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); reset_hfcsx()
379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | reset_hfcsx()
381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); reset_hfcsx()
389 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ reset_hfcsx()
391 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); reset_hfcsx()
392 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ reset_hfcsx()
393 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); reset_hfcsx()
394 cs->hw.hfcsx.sctrl_r = 0; reset_hfcsx()
395 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); reset_hfcsx()
404 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ reset_hfcsx()
405 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); reset_hfcsx()
412 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; reset_hfcsx()
413 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); reset_hfcsx()
423 cs->hw.hfcsx.timer.expires = jiffies + 75; hfcsx_Timer()
425 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80); hfcsx_Timer()
426 add_timer(&cs->hw.hfcsx.timer); hfcsx_Timer()
488 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? main_rec_hfcsx()
536 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? hfcsx_fill_fifo()
601 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) { hfcsx_auxcmd()
605 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; hfcsx_auxcmd()
606 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ hfcsx_auxcmd()
612 cs->hw.hfcsx.nt_mode = 1; hfcsx_auxcmd()
613 cs->hw.hfcsx.nt_timer = 0; hfcsx_auxcmd()
619 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || hfcsx_auxcmd()
620 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) hfcsx_auxcmd()
625 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ hfcsx_auxcmd()
626 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; hfcsx_auxcmd()
630 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ hfcsx_auxcmd()
631 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; hfcsx_auxcmd()
633 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; hfcsx_auxcmd()
634 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; hfcsx_auxcmd()
635 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ hfcsx_auxcmd()
636 cs->hw.hfcsx.ctmt &= ~2; hfcsx_auxcmd()
638 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); hfcsx_auxcmd()
639 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); hfcsx_auxcmd()
640 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); hfcsx_auxcmd()
641 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); hfcsx_auxcmd()
642 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); hfcsx_auxcmd()
643 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_auxcmd()
703 if (!(cs->hw.hfcsx.int_m2 & 0x08)) hfcsx_interrupt()
719 val &= cs->hw.hfcsx.int_m1; hfcsx_interrupt()
730 if (cs->hw.hfcsx.nt_mode) { hfcsx_interrupt()
731 if ((--cs->hw.hfcsx.nt_timer) < 0) hfcsx_interrupt()
735 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); hfcsx_interrupt()
739 cs->hw.hfcsx.int_s1 |= val; hfcsx_interrupt()
743 if (cs->hw.hfcsx.int_s1 & 0x18) { hfcsx_interrupt()
745 val = cs->hw.hfcsx.int_s1; hfcsx_interrupt()
746 cs->hw.hfcsx.int_s1 = exval; hfcsx_interrupt()
749 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { hfcsx_interrupt()
765 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { hfcsx_interrupt()
847 if (cs->hw.hfcsx.int_s1 && count--) { hfcsx_interrupt()
848 val = cs->hw.hfcsx.int_s1; hfcsx_interrupt()
849 cs->hw.hfcsx.int_s1 = 0; hfcsx_interrupt()
948 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; HFCSX_l1hw()
949 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); HFCSX_l1hw()
961 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; HFCSX_l1hw()
962 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); HFCSX_l1hw()
967 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; HFCSX_l1hw()
968 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); HFCSX_l1hw()
977 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; HFCSX_l1hw()
978 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); HFCSX_l1hw()
983 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; HFCSX_l1hw()
984 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); HFCSX_l1hw()
992 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ HFCSX_l1hw()
993 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); HFCSX_l1hw()
1043 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1044 cs->hw.hfcsx.sctrl_e &= ~0x80; mode_hfcsx()
1048 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcsx()
1049 cs->hw.hfcsx.sctrl_e |= 0x80; mode_hfcsx()
1051 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1052 cs->hw.hfcsx.sctrl_e &= ~0x80; mode_hfcsx()
1056 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1057 cs->hw.hfcsx.sctrl_e &= ~0x80; mode_hfcsx()
1063 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; mode_hfcsx()
1064 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; mode_hfcsx()
1066 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; mode_hfcsx()
1067 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; mode_hfcsx()
1070 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1072 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1077 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; mode_hfcsx()
1078 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; mode_hfcsx()
1080 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; mode_hfcsx()
1081 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; mode_hfcsx()
1084 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1085 cs->hw.hfcsx.ctmt |= 2; mode_hfcsx()
1086 cs->hw.hfcsx.conn &= ~0x18; mode_hfcsx()
1088 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1089 cs->hw.hfcsx.ctmt |= 1; mode_hfcsx()
1090 cs->hw.hfcsx.conn &= ~0x03; mode_hfcsx()
1095 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; mode_hfcsx()
1096 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; mode_hfcsx()
1098 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; mode_hfcsx()
1099 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; mode_hfcsx()
1102 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1103 cs->hw.hfcsx.ctmt &= ~2; mode_hfcsx()
1104 cs->hw.hfcsx.conn &= ~0x18; mode_hfcsx()
1106 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1107 cs->hw.hfcsx.ctmt &= ~1; mode_hfcsx()
1108 cs->hw.hfcsx.conn &= ~0x03; mode_hfcsx()
1113 cs->hw.hfcsx.conn |= 0x10; mode_hfcsx()
1114 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; mode_hfcsx()
1115 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; mode_hfcsx()
1116 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1118 cs->hw.hfcsx.conn |= 0x02; mode_hfcsx()
1119 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; mode_hfcsx()
1120 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; mode_hfcsx()
1121 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1125 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); mode_hfcsx()
1126 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); mode_hfcsx()
1127 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); mode_hfcsx()
1128 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); mode_hfcsx()
1129 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); mode_hfcsx()
1130 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); mode_hfcsx()
1262 if (!cs->hw.hfcsx.nt_mode) hfcsx_bh()
1285 if (cs->hw.hfcsx.nt_timer < 0) { hfcsx_bh()
1286 cs->hw.hfcsx.nt_timer = 0; hfcsx_bh()
1287 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; hfcsx_bh()
1288 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_bh()
1297 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; hfcsx_bh()
1298 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_bh()
1299 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; hfcsx_bh()
1300 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; hfcsx_bh()
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); hfcsx_bh()
1302 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); hfcsx_bh()
1303 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; hfcsx_bh()
1312 cs->hw.hfcsx.nt_timer = 0; hfcsx_bh()
1313 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; hfcsx_bh()
1314 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_bh()
1372 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; hfcsx_card_msg()
1373 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_card_msg()
1375 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); hfcsx_card_msg()
1445 cs->hw.hfcsx.base = card->para[1] & 0xfffe; setup_hfcsx()
1447 cs->hw.hfcsx.int_s1 = 0; setup_hfcsx()
1449 cs->hw.hfcsx.fifo = 255; setup_hfcsx()
1452 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { setup_hfcsx()
1455 cs->hw.hfcsx.base); setup_hfcsx()
1458 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); setup_hfcsx()
1459 byteout(cs->hw.hfcsx.base + 1, setup_hfcsx()
1460 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); setup_hfcsx()
1462 cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID); setup_hfcsx()
1463 switch (cs->hw.hfcsx.chip >> 4) { setup_hfcsx()
1473 cs->hw.hfcsx.chip >> 4); setup_hfcsx()
1474 release_region(cs->hw.hfcsx.base, 2); setup_hfcsx()
1480 release_region(cs->hw.hfcsx.base, 2); setup_hfcsx()
1483 if (!(cs->hw.hfcsx.extra = setup_hfcsx()
1485 release_region(cs->hw.hfcsx.base, 2); setup_hfcsx()
1490 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); setup_hfcsx()
1491 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ setup_hfcsx()
1492 cs->hw.hfcsx.int_m1 = 0; setup_hfcsx()
1493 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); setup_hfcsx()
1494 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); setup_hfcsx()
1510 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer; setup_hfcsx()
1511 cs->hw.hfcsx.timer.data = (long) cs; setup_hfcsx()
1512 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ setup_hfcsx()
1513 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ setup_hfcsx()
1514 init_timer(&cs->hw.hfcsx.timer); setup_hfcsx()
/linux-4.4.14/drivers/net/fjes/
H A Dfjes_hw.c37 u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg) fjes_hw_rd32() argument
39 u8 *base = hw->base; fjes_hw_rd32()
47 static u8 *fjes_hw_iomap(struct fjes_hw *hw) fjes_hw_iomap() argument
51 if (!request_mem_region(hw->hw_res.start, hw->hw_res.size, fjes_hw_iomap()
57 base = (u8 *)ioremap_nocache(hw->hw_res.start, hw->hw_res.size); fjes_hw_iomap()
62 static void fjes_hw_iounmap(struct fjes_hw *hw) fjes_hw_iounmap() argument
64 iounmap(hw->base); fjes_hw_iounmap()
65 release_mem_region(hw->hw_res.start, hw->hw_res.size); fjes_hw_iounmap()
68 int fjes_hw_reset(struct fjes_hw *hw) fjes_hw_reset() argument
88 static int fjes_hw_get_max_epid(struct fjes_hw *hw) fjes_hw_get_max_epid() argument
97 static int fjes_hw_get_my_epid(struct fjes_hw *hw) fjes_hw_get_my_epid() argument
106 static int fjes_hw_alloc_shared_status_region(struct fjes_hw *hw) fjes_hw_alloc_shared_status_region() argument
111 (sizeof(u8) * hw->max_epid); fjes_hw_alloc_shared_status_region()
112 hw->hw_info.share = kzalloc(size, GFP_KERNEL); fjes_hw_alloc_shared_status_region()
113 if (!hw->hw_info.share) fjes_hw_alloc_shared_status_region()
116 hw->hw_info.share->epnum = hw->max_epid; fjes_hw_alloc_shared_status_region()
121 static void fjes_hw_free_shared_status_region(struct fjes_hw *hw) fjes_hw_free_shared_status_region() argument
123 kfree(hw->hw_info.share); fjes_hw_free_shared_status_region()
124 hw->hw_info.share = NULL; fjes_hw_free_shared_status_region()
185 fjes_hw_init_command_registers(struct fjes_hw *hw, fjes_hw_init_command_registers() argument
212 static int fjes_hw_setup(struct fjes_hw *hw) fjes_hw_setup() argument
222 hw->hw_info.max_epid = &hw->max_epid; fjes_hw_setup()
223 hw->hw_info.my_epid = &hw->my_epid; fjes_hw_setup()
225 buf = kcalloc(hw->max_epid, sizeof(struct ep_share_mem_info), fjes_hw_setup()
230 hw->ep_shm_info = (struct ep_share_mem_info *)buf; fjes_hw_setup()
232 mem_size = FJES_DEV_REQ_BUF_SIZE(hw->max_epid); fjes_hw_setup()
233 hw->hw_info.req_buf = kzalloc(mem_size, GFP_KERNEL); fjes_hw_setup()
234 if (!(hw->hw_info.req_buf)) fjes_hw_setup()
237 hw->hw_info.req_buf_size = mem_size; fjes_hw_setup()
239 mem_size = FJES_DEV_RES_BUF_SIZE(hw->max_epid); fjes_hw_setup()
240 hw->hw_info.res_buf = kzalloc(mem_size, GFP_KERNEL); fjes_hw_setup()
241 if (!(hw->hw_info.res_buf)) fjes_hw_setup()
244 hw->hw_info.res_buf_size = mem_size; fjes_hw_setup()
246 result = fjes_hw_alloc_shared_status_region(hw); fjes_hw_setup()
250 hw->hw_info.buffer_share_bit = 0; fjes_hw_setup()
251 hw->hw_info.buffer_unshare_reserve_bit = 0; fjes_hw_setup()
253 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_hw_setup()
254 if (epidx != hw->my_epid) { fjes_hw_setup()
255 buf_pair = &hw->ep_shm_info[epidx]; fjes_hw_setup()
274 param.req_len = hw->hw_info.req_buf_size; fjes_hw_setup()
275 param.req_start = __pa(hw->hw_info.req_buf); fjes_hw_setup()
276 param.res_len = hw->hw_info.res_buf_size; fjes_hw_setup()
277 param.res_start = __pa(hw->hw_info.res_buf); fjes_hw_setup()
279 param.share_start = __pa(hw->hw_info.share->ep_status); fjes_hw_setup()
281 fjes_hw_init_command_registers(hw, &param); fjes_hw_setup()
286 static void fjes_hw_cleanup(struct fjes_hw *hw) fjes_hw_cleanup() argument
290 if (!hw->ep_shm_info) fjes_hw_cleanup()
293 fjes_hw_free_shared_status_region(hw); fjes_hw_cleanup()
295 kfree(hw->hw_info.req_buf); fjes_hw_cleanup()
296 hw->hw_info.req_buf = NULL; fjes_hw_cleanup()
298 kfree(hw->hw_info.res_buf); fjes_hw_cleanup()
299 hw->hw_info.res_buf = NULL; fjes_hw_cleanup()
301 for (epidx = 0; epidx < hw->max_epid ; epidx++) { fjes_hw_cleanup()
302 if (epidx == hw->my_epid) fjes_hw_cleanup()
304 fjes_hw_free_epbuf(&hw->ep_shm_info[epidx].tx); fjes_hw_cleanup()
305 fjes_hw_free_epbuf(&hw->ep_shm_info[epidx].rx); fjes_hw_cleanup()
308 kfree(hw->ep_shm_info); fjes_hw_cleanup()
309 hw->ep_shm_info = NULL; fjes_hw_cleanup()
312 int fjes_hw_init(struct fjes_hw *hw) fjes_hw_init() argument
316 hw->base = fjes_hw_iomap(hw); fjes_hw_init()
317 if (!hw->base) fjes_hw_init()
320 ret = fjes_hw_reset(hw); fjes_hw_init()
324 fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, true); fjes_hw_init()
326 INIT_WORK(&hw->update_zone_task, fjes_hw_update_zone_task); fjes_hw_init()
327 INIT_WORK(&hw->epstop_task, fjes_hw_epstop_task); fjes_hw_init()
329 mutex_init(&hw->hw_info.lock); fjes_hw_init()
331 hw->max_epid = fjes_hw_get_max_epid(hw); fjes_hw_init()
332 hw->my_epid = fjes_hw_get_my_epid(hw); fjes_hw_init()
334 if ((hw->max_epid == 0) || (hw->my_epid >= hw->max_epid)) fjes_hw_init()
337 ret = fjes_hw_setup(hw); fjes_hw_init()
342 void fjes_hw_exit(struct fjes_hw *hw) fjes_hw_exit() argument
346 if (hw->base) { fjes_hw_exit()
347 ret = fjes_hw_reset(hw); fjes_hw_exit()
351 fjes_hw_iounmap(hw); fjes_hw_exit()
352 hw->base = NULL; fjes_hw_exit()
355 fjes_hw_cleanup(hw); fjes_hw_exit()
357 cancel_work_sync(&hw->update_zone_task); fjes_hw_exit()
358 cancel_work_sync(&hw->epstop_task); fjes_hw_exit()
362 fjes_hw_issue_request_command(struct fjes_hw *hw, fjes_hw_issue_request_command() argument
408 int fjes_hw_request_info(struct fjes_hw *hw) fjes_hw_request_info() argument
410 union fjes_device_command_req *req_buf = hw->hw_info.req_buf; fjes_hw_request_info()
411 union fjes_device_command_res *res_buf = hw->hw_info.res_buf; fjes_hw_request_info()
415 memset(req_buf, 0, hw->hw_info.req_buf_size); fjes_hw_request_info()
416 memset(res_buf, 0, hw->hw_info.res_buf_size); fjes_hw_request_info()
423 ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_INFO); fjes_hw_request_info()
427 if (FJES_DEV_COMMAND_INFO_RES_LEN((*hw->hw_info.max_epid)) != fjes_hw_request_info()
462 int fjes_hw_register_buff_addr(struct fjes_hw *hw, int dest_epid, fjes_hw_register_buff_addr() argument
465 union fjes_device_command_req *req_buf = hw->hw_info.req_buf; fjes_hw_register_buff_addr()
466 union fjes_device_command_res *res_buf = hw->hw_info.res_buf; fjes_hw_register_buff_addr()
474 if (test_bit(dest_epid, &hw->hw_info.buffer_share_bit)) fjes_hw_register_buff_addr()
477 memset(req_buf, 0, hw->hw_info.req_buf_size); fjes_hw_register_buff_addr()
478 memset(res_buf, 0, hw->hw_info.res_buf_size); fjes_hw_register_buff_addr()
509 ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_SHARE_BUFFER); fjes_hw_register_buff_addr()
517 msleep(200 + hw->my_epid * 20); fjes_hw_register_buff_addr()
518 timeout -= (200 + hw->my_epid * 20); fjes_hw_register_buff_addr()
524 hw, FJES_CMD_REQ_SHARE_BUFFER); fjes_hw_register_buff_addr()
536 set_bit(dest_epid, &hw->hw_info.buffer_share_bit); fjes_hw_register_buff_addr()
564 int fjes_hw_unregister_buff_addr(struct fjes_hw *hw, int dest_epid) fjes_hw_unregister_buff_addr() argument
566 union fjes_device_command_req *req_buf = hw->hw_info.req_buf; fjes_hw_unregister_buff_addr()
567 union fjes_device_command_res *res_buf = hw->hw_info.res_buf; fjes_hw_unregister_buff_addr()
568 struct fjes_device_shared_info *share = hw->hw_info.share; fjes_hw_unregister_buff_addr()
573 if (!hw->base) fjes_hw_unregister_buff_addr()
579 if (!test_bit(dest_epid, &hw->hw_info.buffer_share_bit)) fjes_hw_unregister_buff_addr()
582 memset(req_buf, 0, hw->hw_info.req_buf_size); fjes_hw_unregister_buff_addr()
583 memset(res_buf, 0, hw->hw_info.res_buf_size); fjes_hw_unregister_buff_addr()
592 ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_UNSHARE_BUFFER); fjes_hw_unregister_buff_addr()
601 msleep(200 + hw->my_epid * 20); fjes_hw_unregister_buff_addr()
602 timeout -= (200 + hw->my_epid * 20); fjes_hw_unregister_buff_addr()
608 fjes_hw_issue_request_command(hw, FJES_CMD_REQ_UNSHARE_BUFFER); fjes_hw_unregister_buff_addr()
620 clear_bit(dest_epid, &hw->hw_info.buffer_share_bit); fjes_hw_unregister_buff_addr()
648 int fjes_hw_raise_interrupt(struct fjes_hw *hw, int dest_epid, fjes_hw_raise_interrupt() argument
658 u32 fjes_hw_capture_interrupt_status(struct fjes_hw *hw) fjes_hw_capture_interrupt_status() argument
667 void fjes_hw_set_irqmask(struct fjes_hw *hw, fjes_hw_set_irqmask() argument
676 bool fjes_hw_epid_is_same_zone(struct fjes_hw *hw, int epid) fjes_hw_epid_is_same_zone() argument
678 if (epid >= hw->max_epid) fjes_hw_epid_is_same_zone()
681 if ((hw->ep_shm_info[epid].es_status != fjes_hw_epid_is_same_zone()
683 (hw->ep_shm_info[hw->my_epid].zone == fjes_hw_epid_is_same_zone()
687 return (hw->ep_shm_info[epid].zone == fjes_hw_epid_is_same_zone()
688 hw->ep_shm_info[hw->my_epid].zone); fjes_hw_epid_is_same_zone()
702 static bool fjes_hw_epid_is_stop_requested(struct fjes_hw *hw, int src_epid) fjes_hw_epid_is_stop_requested() argument
704 return test_bit(src_epid, &hw->txrx_stop_req_bit); fjes_hw_epid_is_stop_requested()
707 static bool fjes_hw_epid_is_stop_process_done(struct fjes_hw *hw, int src_epid) fjes_hw_epid_is_stop_process_done() argument
709 return (hw->ep_shm_info[src_epid].tx.info->v1i.rx_status & fjes_hw_epid_is_stop_process_done()
714 fjes_hw_get_partner_ep_status(struct fjes_hw *hw, int epid) fjes_hw_get_partner_ep_status() argument
718 if (fjes_hw_epid_is_shared(hw->hw_info.share, epid)) { fjes_hw_get_partner_ep_status()
719 if (fjes_hw_epid_is_stop_requested(hw, epid)) { fjes_hw_get_partner_ep_status()
722 if (fjes_hw_epid_is_stop_process_done(hw, epid)) fjes_hw_get_partner_ep_status()
734 void fjes_hw_raise_epstop(struct fjes_hw *hw) fjes_hw_raise_epstop() argument
739 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_hw_raise_epstop()
740 if (epidx == hw->my_epid) fjes_hw_raise_epstop()
743 status = fjes_hw_get_partner_ep_status(hw, epidx); fjes_hw_raise_epstop()
746 fjes_hw_raise_interrupt(hw, epidx, fjes_hw_raise_epstop()
753 set_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit); fjes_hw_raise_epstop()
754 set_bit(epidx, &hw->txrx_stop_req_bit); fjes_hw_raise_epstop()
756 hw->ep_shm_info[epidx].tx.info->v1i.rx_status |= fjes_hw_raise_epstop()
761 int fjes_hw_wait_epstop(struct fjes_hw *hw) fjes_hw_wait_epstop() argument
768 while (hw->hw_info.buffer_unshare_reserve_bit && fjes_hw_wait_epstop()
770 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_hw_wait_epstop()
771 if (epidx == hw->my_epid) fjes_hw_wait_epstop()
773 status = fjes_hw_epid_is_shared(hw->hw_info.share, fjes_hw_wait_epstop()
775 info = hw->ep_shm_info[epidx].rx.info; fjes_hw_wait_epstop()
780 &hw->hw_info.buffer_unshare_reserve_bit)) { fjes_hw_wait_epstop()
782 &hw->hw_info.buffer_unshare_reserve_bit); fjes_hw_wait_epstop()
790 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_hw_wait_epstop()
791 if (epidx == hw->my_epid) fjes_hw_wait_epstop()
793 if (test_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit)) fjes_hw_wait_epstop()
795 &hw->hw_info.buffer_unshare_reserve_bit); fjes_hw_wait_epstop()
926 struct fjes_hw *hw = container_of(work, fjes_hw_update_zone_task() local
943 adapter = (struct fjes_adapter *)hw->back; fjes_hw_update_zone_task()
945 res_buf = hw->hw_info.res_buf; fjes_hw_update_zone_task()
948 mutex_lock(&hw->hw_info.lock); fjes_hw_update_zone_task()
950 ret = fjes_hw_request_info(hw); fjes_hw_update_zone_task()
963 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_hw_update_zone_task()
964 if (epidx == hw->my_epid) { fjes_hw_update_zone_task()
965 hw->ep_shm_info[epidx].es_status = fjes_hw_update_zone_task()
967 hw->ep_shm_info[epidx].zone = fjes_hw_update_zone_task()
972 pstatus = fjes_hw_get_partner_ep_status(hw, epidx); fjes_hw_update_zone_task()
981 info[hw->my_epid].zone)) fjes_hw_update_zone_task()
994 info[hw->my_epid].zone)) { fjes_hw_update_zone_task()
998 &hw->hw_info.buffer_unshare_reserve_bit); fjes_hw_update_zone_task()
1008 info[hw->my_epid].zone)) fjes_hw_update_zone_task()
1013 hw->ep_shm_info[epidx].es_status = fjes_hw_update_zone_task()
1015 hw->ep_shm_info[epidx].zone = info[epidx].zone; fjes_hw_update_zone_task()
1020 mutex_unlock(&hw->hw_info.lock); fjes_hw_update_zone_task()
1022 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_hw_update_zone_task()
1023 if (epidx == hw->my_epid) fjes_hw_update_zone_task()
1027 fjes_hw_setup_epbuf(&hw->ep_shm_info[epidx].tx, fjes_hw_update_zone_task()
1030 mutex_lock(&hw->hw_info.lock); fjes_hw_update_zone_task()
1033 hw, epidx, &hw->ep_shm_info[epidx]); fjes_hw_update_zone_task()
1048 mutex_unlock(&hw->hw_info.lock); fjes_hw_update_zone_task()
1052 mutex_lock(&hw->hw_info.lock); fjes_hw_update_zone_task()
1054 ret = fjes_hw_unregister_buff_addr(hw, epidx); fjes_hw_update_zone_task()
1070 mutex_unlock(&hw->hw_info.lock); fjes_hw_update_zone_task()
1074 &hw->ep_shm_info[epidx].tx, fjes_hw_update_zone_task()
1079 fjes_hw_raise_interrupt(hw, epidx, fjes_hw_update_zone_task()
1082 set_bit(epidx, &hw->txrx_stop_req_bit); fjes_hw_update_zone_task()
1083 hw->ep_shm_info[epidx].tx. fjes_hw_update_zone_task()
1086 set_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit); fjes_hw_update_zone_task()
1099 struct fjes_hw *hw = container_of(work, struct fjes_hw, epstop_task); fjes_hw_epstop_task() local
1100 struct fjes_adapter *adapter = (struct fjes_adapter *)hw->back; fjes_hw_epstop_task()
1105 while ((remain_bit = hw->epstop_req_bit)) { fjes_hw_epstop_task()
1108 hw->ep_shm_info[epid_bit]. fjes_hw_epstop_task()
1112 clear_bit(epid_bit, &hw->epstop_req_bit); fjes_hw_epstop_task()
H A Dfjes_main.c210 result = request_irq(adapter->hw.hw_res.irq, fjes_intr, fjes_request_irq()
223 struct fjes_hw *hw = &adapter->hw; fjes_free_irq() local
228 fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, true); fjes_free_irq()
231 free_irq(adapter->hw.hw_res.irq, adapter); fjes_free_irq()
251 struct fjes_hw *hw = &adapter->hw; fjes_open() local
261 hw->txrx_stop_req_bit = 0; fjes_open()
262 hw->epstop_req_bit = 0; fjes_open()
266 fjes_hw_capture_interrupt_status(hw); fjes_open()
272 fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, false); fjes_open()
292 struct fjes_hw *hw = &adapter->hw; fjes_close() local
298 fjes_hw_raise_epstop(hw); fjes_close()
302 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_close()
303 if (epidx == hw->my_epid) fjes_close()
306 adapter->hw.ep_shm_info[epidx].tx.info->v1i.rx_status &= fjes_close()
318 cancel_work_sync(&hw->update_zone_task); fjes_close()
319 cancel_work_sync(&hw->epstop_task); fjes_close()
321 fjes_hw_wait_epstop(hw); fjes_close()
332 struct fjes_hw *hw = &adapter->hw; fjes_setup_resources() local
336 mutex_lock(&hw->hw_info.lock); fjes_setup_resources()
337 result = fjes_hw_request_info(hw); fjes_setup_resources()
340 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_setup_resources()
341 hw->ep_shm_info[epidx].es_status = fjes_setup_resources()
342 hw->hw_info.res_buf->info.info[epidx].es_status; fjes_setup_resources()
343 hw->ep_shm_info[epidx].zone = fjes_setup_resources()
344 hw->hw_info.res_buf->info.info[epidx].zone; fjes_setup_resources()
352 mutex_unlock(&hw->hw_info.lock); fjes_setup_resources()
355 mutex_unlock(&hw->hw_info.lock); fjes_setup_resources()
357 for (epidx = 0; epidx < (hw->max_epid); epidx++) { fjes_setup_resources()
358 if ((epidx != hw->my_epid) && fjes_setup_resources()
359 (hw->ep_shm_info[epidx].es_status == fjes_setup_resources()
361 fjes_hw_raise_interrupt(hw, epidx, fjes_setup_resources()
366 msleep(FJES_OPEN_ZONE_UPDATE_WAIT * hw->max_epid); fjes_setup_resources()
368 for (epidx = 0; epidx < (hw->max_epid); epidx++) { fjes_setup_resources()
369 if (epidx == hw->my_epid) fjes_setup_resources()
372 buf_pair = &hw->ep_shm_info[epidx]; fjes_setup_resources()
377 if (fjes_hw_epid_is_same_zone(hw, epidx)) { fjes_setup_resources()
378 mutex_lock(&hw->hw_info.lock); fjes_setup_resources()
380 fjes_hw_register_buff_addr(hw, epidx, buf_pair); fjes_setup_resources()
381 mutex_unlock(&hw->hw_info.lock); fjes_setup_resources()
403 struct fjes_hw *hw = &adapter->hw; fjes_free_resources() local
408 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_free_resources()
409 if (epidx == hw->my_epid) fjes_free_resources()
412 mutex_lock(&hw->hw_info.lock); fjes_free_resources()
413 result = fjes_hw_unregister_buff_addr(hw, epidx); fjes_free_resources()
414 mutex_unlock(&hw->hw_info.lock); fjes_free_resources()
419 buf_pair = &hw->ep_shm_info[epidx]; fjes_free_resources()
424 clear_bit(epidx, &hw->txrx_stop_req_bit); fjes_free_resources()
428 result = fjes_hw_reset(hw); fjes_free_resources()
435 hw->hw_info.buffer_share_bit = 0; fjes_free_resources()
439 param.req_len = hw->hw_info.req_buf_size; fjes_free_resources()
440 param.req_start = __pa(hw->hw_info.req_buf); fjes_free_resources()
441 param.res_len = hw->hw_info.res_buf_size; fjes_free_resources()
442 param.res_start = __pa(hw->hw_info.res_buf); fjes_free_resources()
443 param.share_start = __pa(hw->hw_info.share->ep_status); fjes_free_resources()
445 fjes_hw_init_command_registers(hw, &param); fjes_free_resources()
454 struct fjes_hw *hw = &adapter->hw; fjes_tx_stall_task() local
467 my_epid = hw->my_epid; fjes_tx_stall_task()
468 max_epid = hw->max_epid; fjes_tx_stall_task()
477 pstatus = fjes_hw_get_partner_ep_status(hw, epid); fjes_tx_stall_task()
482 info = adapter->hw.ep_shm_info[epid].tx.info; fjes_tx_stall_task()
517 struct fjes_hw *hw = &adapter->hw; fjes_raise_intr_rxdata_task() local
521 my_epid = hw->my_epid; fjes_raise_intr_rxdata_task()
522 max_epid = hw->max_epid; fjes_raise_intr_rxdata_task()
525 hw->ep_shm_info[epid].tx_status_work = 0; fjes_raise_intr_rxdata_task()
531 pstatus = fjes_hw_get_partner_ep_status(hw, epid); fjes_raise_intr_rxdata_task()
533 hw->ep_shm_info[epid].tx_status_work = fjes_raise_intr_rxdata_task()
534 hw->ep_shm_info[epid].tx.info->v1i.tx_status; fjes_raise_intr_rxdata_task()
536 if (hw->ep_shm_info[epid].tx_status_work == fjes_raise_intr_rxdata_task()
538 hw->ep_shm_info[epid].tx.info->v1i.tx_status = fjes_raise_intr_rxdata_task()
548 pstatus = fjes_hw_get_partner_ep_status(hw, epid); fjes_raise_intr_rxdata_task()
549 if ((hw->ep_shm_info[epid].tx_status_work == fjes_raise_intr_rxdata_task()
552 !(hw->ep_shm_info[epid].rx.info->v1i.rx_status)) { fjes_raise_intr_rxdata_task()
553 fjes_hw_raise_interrupt(hw, epid, fjes_raise_intr_rxdata_task()
566 retval = fjes_hw_epbuf_tx_pkt_send(&adapter->hw.ep_shm_info[dest].tx, fjes_tx_send()
571 adapter->hw.ep_shm_info[dest].tx.info->v1i.tx_status = fjes_tx_send()
585 struct fjes_hw *hw = &adapter->hw; fjes_xmit_frame() local
604 my_epid = hw->my_epid; fjes_xmit_frame()
613 max_epid = hw->max_epid; fjes_xmit_frame()
622 (dest_epid < hw->max_epid)) { fjes_xmit_frame()
630 hw->ep_shm_info[my_epid].net_stats.tx_packets += 1; fjes_xmit_frame()
632 hw->ep_shm_info[my_epid].net_stats.tx_bytes += len; fjes_xmit_frame()
640 hw->ep_shm_info[my_epid].net_stats.tx_packets += 1; fjes_xmit_frame()
642 hw->ep_shm_info[my_epid].net_stats.tx_bytes += len; fjes_xmit_frame()
649 pstatus = fjes_hw_get_partner_ep_status(hw, dest_epid); fjes_xmit_frame()
653 &adapter->hw.ep_shm_info[dest_epid].rx, 0)) { fjes_xmit_frame()
656 hw->ep_shm_info[my_epid].net_stats fjes_xmit_frame()
661 &adapter->hw.ep_shm_info[dest_epid].rx, fjes_xmit_frame()
664 hw->ep_shm_info[my_epid].net_stats.tx_dropped += 1; fjes_xmit_frame()
666 hw->ep_shm_info[my_epid].net_stats.tx_errors += 1; fjes_xmit_frame()
671 &adapter->hw.ep_shm_info[dest_epid].rx, fjes_xmit_frame()
697 hw->ep_shm_info[my_epid].net_stats fjes_xmit_frame()
700 hw->ep_shm_info[my_epid].net_stats fjes_xmit_frame()
717 hw->ep_shm_info[my_epid].net_stats fjes_xmit_frame()
720 hw->ep_shm_info[my_epid].net_stats fjes_xmit_frame()
734 hw->ep_shm_info[my_epid].net_stats.tx_packets += 1; fjes_xmit_frame()
736 hw->ep_shm_info[my_epid].net_stats.tx_bytes += len; fjes_xmit_frame()
794 for (epid = 0; epid < adapter->hw.max_epid; epid++) { fjes_vlan_rx_add_vid()
795 if (epid == adapter->hw.my_epid) fjes_vlan_rx_add_vid()
799 &adapter->hw.ep_shm_info[epid].tx, vid)) fjes_vlan_rx_add_vid()
801 &adapter->hw.ep_shm_info[epid].tx, vid); fjes_vlan_rx_add_vid()
813 for (epid = 0; epid < adapter->hw.max_epid; epid++) { fjes_vlan_rx_kill_vid()
814 if (epid == adapter->hw.my_epid) fjes_vlan_rx_kill_vid()
817 fjes_hw_del_vlan_id(&adapter->hw.ep_shm_info[epid].tx, vid); fjes_vlan_rx_kill_vid()
826 struct fjes_hw *hw = &adapter->hw; fjes_txrx_stop_req_irq() local
829 status = fjes_hw_get_partner_ep_status(hw, src_epid); fjes_txrx_stop_req_irq()
836 if (src_epid < hw->my_epid) { fjes_txrx_stop_req_irq()
837 hw->ep_shm_info[src_epid].tx.info->v1i.rx_status |= fjes_txrx_stop_req_irq()
840 clear_bit(src_epid, &hw->txrx_stop_req_bit); fjes_txrx_stop_req_irq()
849 if (hw->ep_shm_info[src_epid].rx.info->v1i.rx_status & fjes_txrx_stop_req_irq()
851 set_bit(src_epid, &hw->epstop_req_bit); fjes_txrx_stop_req_irq()
852 if (!work_pending(&hw->epstop_task)) fjes_txrx_stop_req_irq()
854 &hw->epstop_task); fjes_txrx_stop_req_irq()
862 struct fjes_hw *hw = &adapter->hw; fjes_stop_req_irq() local
865 set_bit(src_epid, &hw->hw_info.buffer_unshare_reserve_bit); fjes_stop_req_irq()
867 status = fjes_hw_get_partner_ep_status(hw, src_epid); fjes_stop_req_irq()
870 hw->ep_shm_info[src_epid].tx.info->v1i.rx_status |= fjes_stop_req_irq()
872 clear_bit(src_epid, &hw->txrx_stop_req_bit); fjes_stop_req_irq()
883 set_bit(src_epid, &hw->epstop_req_bit); fjes_stop_req_irq()
885 if (!work_pending(&hw->epstop_task)) fjes_stop_req_irq()
886 queue_work(adapter->control_wq, &hw->epstop_task); fjes_stop_req_irq()
894 struct fjes_hw *hw = &adapter->hw; fjes_update_zone_irq() local
896 if (!work_pending(&hw->update_zone_task)) fjes_update_zone_irq()
897 queue_work(adapter->control_wq, &hw->update_zone_task); fjes_update_zone_irq()
903 struct fjes_hw *hw = &adapter->hw; fjes_intr() local
907 icr = fjes_hw_capture_interrupt_status(hw); fjes_intr()
920 fjes_hw_set_irqmask(hw, fjes_intr()
937 struct fjes_hw *hw = &adapter->hw; fjes_rxframe_search_exist() local
942 max_epid = hw->max_epid; fjes_rxframe_search_exist()
947 if (cur_epid == hw->my_epid) fjes_rxframe_search_exist()
950 pstatus = fjes_hw_get_partner_ep_status(hw, cur_epid); fjes_rxframe_search_exist()
953 &hw->ep_shm_info[cur_epid].rx)) fjes_rxframe_search_exist()
971 &adapter->hw.ep_shm_info[*cur_epid].rx, psize); fjes_rxframe_get()
978 fjes_hw_epbuf_rx_curpkt_drop(&adapter->hw.ep_shm_info[cur_epid].rx); fjes_rxframe_release()
983 struct fjes_hw *hw = &adapter->hw; fjes_rx_irq() local
985 fjes_hw_set_irqmask(hw, REG_ICTL_MASK_RX_DATA, true); fjes_rx_irq()
996 struct fjes_hw *hw = &adapter->hw; fjes_poll() local
1004 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_poll()
1005 if (epidx == hw->my_epid) fjes_poll()
1008 adapter->hw.ep_shm_info[epidx].tx.info->v1i.rx_status |= fjes_poll()
1013 prefetch(&adapter->hw); fjes_poll()
1020 hw->ep_shm_info[cur_epid].net_stats fjes_poll()
1023 hw->ep_shm_info[cur_epid].net_stats fjes_poll()
1036 hw->ep_shm_info[cur_epid].net_stats fjes_poll()
1039 hw->ep_shm_info[cur_epid].net_stats fjes_poll()
1045 hw->ep_shm_info[cur_epid].net_stats fjes_poll()
1068 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_poll()
1069 if (epidx == hw->my_epid) fjes_poll()
1071 adapter->hw.ep_shm_info[epidx] fjes_poll()
1076 fjes_hw_set_irqmask(hw, REG_ICTL_MASK_RX_DATA, false); fjes_poll()
1089 struct fjes_hw *hw; fjes_probe() local
1106 hw = &adapter->hw; fjes_probe()
1107 hw->back = adapter; fjes_probe()
1131 hw->hw_res.start = res->start; fjes_probe()
1132 hw->hw_res.size = res->end - res->start + 1; fjes_probe()
1133 hw->hw_res.irq = platform_get_irq(plat_dev, 0); fjes_probe()
1134 err = fjes_hw_init(&adapter->hw); fjes_probe()
1144 netdev->dev_addr[5] = hw->my_epid; /* EPID */ fjes_probe()
1155 fjes_hw_exit(&adapter->hw); fjes_probe()
1167 struct fjes_hw *hw = &adapter->hw; fjes_remove() local
1180 fjes_hw_exit(hw); fjes_remove()
1217 fjes_intr(adapter->hw.hw_res.irq, adapter); fjes_irq_watch_task()
1237 struct fjes_hw *hw = &adapter->hw; fjes_watch_unshare_task() local
1247 my_epid = hw->my_epid; fjes_watch_unshare_task()
1248 max_epid = hw->max_epid; fjes_watch_unshare_task()
1253 while ((unshare_watch_bitmask || hw->txrx_stop_req_bit) && fjes_watch_unshare_task()
1255 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_watch_unshare_task()
1256 if (epidx == hw->my_epid) fjes_watch_unshare_task()
1259 is_shared = fjes_hw_epid_is_shared(hw->hw_info.share, fjes_watch_unshare_task()
1262 stop_req = test_bit(epidx, &hw->txrx_stop_req_bit); fjes_watch_unshare_task()
1264 stop_req_done = hw->ep_shm_info[epidx].rx.info->v1i.rx_status & fjes_watch_unshare_task()
1270 &hw->hw_info.buffer_unshare_reserve_bit); fjes_watch_unshare_task()
1277 mutex_lock(&hw->hw_info.lock); fjes_watch_unshare_task()
1278 ret = fjes_hw_unregister_buff_addr(hw, epidx); fjes_watch_unshare_task()
1293 mutex_unlock(&hw->hw_info.lock); fjes_watch_unshare_task()
1295 fjes_hw_setup_epbuf(&hw->ep_shm_info[epidx].tx, fjes_watch_unshare_task()
1298 clear_bit(epidx, &hw->txrx_stop_req_bit); fjes_watch_unshare_task()
1301 &hw->hw_info.buffer_unshare_reserve_bit); fjes_watch_unshare_task()
1308 if (hw->hw_info.buffer_unshare_reserve_bit) { fjes_watch_unshare_task()
1309 for (epidx = 0; epidx < hw->max_epid; epidx++) { fjes_watch_unshare_task()
1310 if (epidx == hw->my_epid) fjes_watch_unshare_task()
1314 &hw->hw_info.buffer_unshare_reserve_bit)) { fjes_watch_unshare_task()
1315 mutex_lock(&hw->hw_info.lock); fjes_watch_unshare_task()
1317 ret = fjes_hw_unregister_buff_addr(hw, epidx); fjes_watch_unshare_task()
1332 mutex_unlock(&hw->hw_info.lock); fjes_watch_unshare_task()
1335 &hw->ep_shm_info[epidx].tx, fjes_watch_unshare_task()
1338 clear_bit(epidx, &hw->txrx_stop_req_bit); fjes_watch_unshare_task()
1340 clear_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit); fjes_watch_unshare_task()
1344 hw->ep_shm_info[epidx].tx.info->v1i.rx_status &= fjes_watch_unshare_task()
/linux-4.4.14/drivers/net/ethernet/intel/i40evf/
H A Di40e_adminq.c45 * @hw: pointer to the hardware structure
49 static void i40e_adminq_init_regs(struct i40e_hw *hw) i40e_adminq_init_regs() argument
52 if (i40e_is_vf(hw)) { i40e_adminq_init_regs()
53 hw->aq.asq.tail = I40E_VF_ATQT1; i40e_adminq_init_regs()
54 hw->aq.asq.head = I40E_VF_ATQH1; i40e_adminq_init_regs()
55 hw->aq.asq.len = I40E_VF_ATQLEN1; i40e_adminq_init_regs()
56 hw->aq.asq.bal = I40E_VF_ATQBAL1; i40e_adminq_init_regs()
57 hw->aq.asq.bah = I40E_VF_ATQBAH1; i40e_adminq_init_regs()
58 hw->aq.arq.tail = I40E_VF_ARQT1; i40e_adminq_init_regs()
59 hw->aq.arq.head = I40E_VF_ARQH1; i40e_adminq_init_regs()
60 hw->aq.arq.len = I40E_VF_ARQLEN1; i40e_adminq_init_regs()
61 hw->aq.arq.bal = I40E_VF_ARQBAL1; i40e_adminq_init_regs()
62 hw->aq.arq.bah = I40E_VF_ARQBAH1; i40e_adminq_init_regs()
68 * @hw: pointer to the hardware structure
70 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) i40e_alloc_adminq_asq_ring() argument
74 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, i40e_alloc_adminq_asq_ring()
76 (hw->aq.num_asq_entries * i40e_alloc_adminq_asq_ring()
82 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, i40e_alloc_adminq_asq_ring()
83 (hw->aq.num_asq_entries * i40e_alloc_adminq_asq_ring()
86 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); i40e_alloc_adminq_asq_ring()
95 * @hw: pointer to the hardware structure
97 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) i40e_alloc_adminq_arq_ring() argument
101 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, i40e_alloc_adminq_arq_ring()
103 (hw->aq.num_arq_entries * i40e_alloc_adminq_arq_ring()
112 * @hw: pointer to the hardware structure
117 static void i40e_free_adminq_asq(struct i40e_hw *hw) i40e_free_adminq_asq() argument
119 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); i40e_free_adminq_asq()
124 * @hw: pointer to the hardware structure
129 static void i40e_free_adminq_arq(struct i40e_hw *hw) i40e_free_adminq_arq() argument
131 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); i40e_free_adminq_arq()
136 * @hw: pointer to the hardware structure
138 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) i40e_alloc_arq_bufs() argument
150 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, i40e_alloc_arq_bufs()
151 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); i40e_alloc_arq_bufs()
154 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; i40e_alloc_arq_bufs()
157 for (i = 0; i < hw->aq.num_arq_entries; i++) { i40e_alloc_arq_bufs()
158 bi = &hw->aq.arq.r.arq_bi[i]; i40e_alloc_arq_bufs()
159 ret_code = i40e_allocate_dma_mem(hw, bi, i40e_alloc_arq_bufs()
161 hw->aq.arq_buf_size, i40e_alloc_arq_bufs()
167 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); i40e_alloc_arq_bufs()
170 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) i40e_alloc_arq_bufs()
195 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); i40e_alloc_arq_bufs()
196 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); i40e_alloc_arq_bufs()
203 * @hw: pointer to the hardware structure
205 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) i40e_alloc_asq_bufs() argument
212 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, i40e_alloc_asq_bufs()
213 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); i40e_alloc_asq_bufs()
216 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; i40e_alloc_asq_bufs()
219 for (i = 0; i < hw->aq.num_asq_entries; i++) { i40e_alloc_asq_bufs()
220 bi = &hw->aq.asq.r.asq_bi[i]; i40e_alloc_asq_bufs()
221 ret_code = i40e_allocate_dma_mem(hw, bi, i40e_alloc_asq_bufs()
223 hw->aq.asq_buf_size, i40e_alloc_asq_bufs()
235 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); i40e_alloc_asq_bufs()
236 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); i40e_alloc_asq_bufs()
243 * @hw: pointer to the hardware structure
245 static void i40e_free_arq_bufs(struct i40e_hw *hw) i40e_free_arq_bufs() argument
250 for (i = 0; i < hw->aq.num_arq_entries; i++) i40e_free_arq_bufs()
251 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); i40e_free_arq_bufs()
254 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); i40e_free_arq_bufs()
257 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); i40e_free_arq_bufs()
262 * @hw: pointer to the hardware structure
264 static void i40e_free_asq_bufs(struct i40e_hw *hw) i40e_free_asq_bufs() argument
269 for (i = 0; i < hw->aq.num_asq_entries; i++) i40e_free_asq_bufs()
270 if (hw->aq.asq.r.asq_bi[i].pa) i40e_free_asq_bufs()
271 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); i40e_free_asq_bufs()
274 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); i40e_free_asq_bufs()
277 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); i40e_free_asq_bufs()
280 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); i40e_free_asq_bufs()
285 * @hw: pointer to the hardware structure
289 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) i40e_config_asq_regs() argument
295 wr32(hw, hw->aq.asq.head, 0); i40e_config_asq_regs()
296 wr32(hw, hw->aq.asq.tail, 0); i40e_config_asq_regs()
299 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | i40e_config_asq_regs()
301 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); i40e_config_asq_regs()
302 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); i40e_config_asq_regs()
305 reg = rd32(hw, hw->aq.asq.bal); i40e_config_asq_regs()
306 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) i40e_config_asq_regs()
314 * @hw: pointer to the hardware structure
318 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) i40e_config_arq_regs() argument
324 wr32(hw, hw->aq.arq.head, 0); i40e_config_arq_regs()
325 wr32(hw, hw->aq.arq.tail, 0); i40e_config_arq_regs()
328 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | i40e_config_arq_regs()
330 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); i40e_config_arq_regs()
331 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); i40e_config_arq_regs()
334 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); i40e_config_arq_regs()
337 reg = rd32(hw, hw->aq.arq.bal); i40e_config_arq_regs()
338 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) i40e_config_arq_regs()
346 * @hw: pointer to the hardware structure
350 * in the hw->aq structure:
351 * - hw->aq.num_asq_entries
352 * - hw->aq.arq_buf_size
357 static i40e_status i40e_init_asq(struct i40e_hw *hw) i40e_init_asq() argument
361 if (hw->aq.asq.count > 0) { i40e_init_asq()
368 if ((hw->aq.num_asq_entries == 0) || i40e_init_asq()
369 (hw->aq.asq_buf_size == 0)) { i40e_init_asq()
374 hw->aq.asq.next_to_use = 0; i40e_init_asq()
375 hw->aq.asq.next_to_clean = 0; i40e_init_asq()
378 ret_code = i40e_alloc_adminq_asq_ring(hw); i40e_init_asq()
383 ret_code = i40e_alloc_asq_bufs(hw); i40e_init_asq()
388 ret_code = i40e_config_asq_regs(hw); i40e_init_asq()
393 hw->aq.asq.count = hw->aq.num_asq_entries; i40e_init_asq()
397 i40e_free_adminq_asq(hw); i40e_init_asq()
405 * @hw: pointer to the hardware structure
409 * in the hw->aq structure:
410 * - hw->aq.num_asq_entries
411 * - hw->aq.arq_buf_size
416 static i40e_status i40e_init_arq(struct i40e_hw *hw) i40e_init_arq() argument
420 if (hw->aq.arq.count > 0) { i40e_init_arq()
427 if ((hw->aq.num_arq_entries == 0) || i40e_init_arq()
428 (hw->aq.arq_buf_size == 0)) { i40e_init_arq()
433 hw->aq.arq.next_to_use = 0; i40e_init_arq()
434 hw->aq.arq.next_to_clean = 0; i40e_init_arq()
437 ret_code = i40e_alloc_adminq_arq_ring(hw); i40e_init_arq()
442 ret_code = i40e_alloc_arq_bufs(hw); i40e_init_arq()
447 ret_code = i40e_config_arq_regs(hw); i40e_init_arq()
452 hw->aq.arq.count = hw->aq.num_arq_entries; i40e_init_arq()
456 i40e_free_adminq_arq(hw); i40e_init_arq()
464 * @hw: pointer to the hardware structure
468 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) i40e_shutdown_asq() argument
472 mutex_lock(&hw->aq.asq_mutex); i40e_shutdown_asq()
474 if (hw->aq.asq.count == 0) { i40e_shutdown_asq()
480 wr32(hw, hw->aq.asq.head, 0); i40e_shutdown_asq()
481 wr32(hw, hw->aq.asq.tail, 0); i40e_shutdown_asq()
482 wr32(hw, hw->aq.asq.len, 0); i40e_shutdown_asq()
483 wr32(hw, hw->aq.asq.bal, 0); i40e_shutdown_asq()
484 wr32(hw, hw->aq.asq.bah, 0); i40e_shutdown_asq()
486 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ i40e_shutdown_asq()
489 i40e_free_asq_bufs(hw); i40e_shutdown_asq()
492 mutex_unlock(&hw->aq.asq_mutex); i40e_shutdown_asq()
498 * @hw: pointer to the hardware structure
502 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) i40e_shutdown_arq() argument
506 mutex_lock(&hw->aq.arq_mutex); i40e_shutdown_arq()
508 if (hw->aq.arq.count == 0) { i40e_shutdown_arq()
514 wr32(hw, hw->aq.arq.head, 0); i40e_shutdown_arq()
515 wr32(hw, hw->aq.arq.tail, 0); i40e_shutdown_arq()
516 wr32(hw, hw->aq.arq.len, 0); i40e_shutdown_arq()
517 wr32(hw, hw->aq.arq.bal, 0); i40e_shutdown_arq()
518 wr32(hw, hw->aq.arq.bah, 0); i40e_shutdown_arq()
520 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ i40e_shutdown_arq()
523 i40e_free_arq_bufs(hw); i40e_shutdown_arq()
526 mutex_unlock(&hw->aq.arq_mutex); i40e_shutdown_arq()
532 * @hw: pointer to the hardware structure
535 * in the hw->aq structure:
536 * - hw->aq.num_asq_entries
537 * - hw->aq.num_arq_entries
538 * - hw->aq.arq_buf_size
539 * - hw->aq.asq_buf_size
541 i40e_status i40evf_init_adminq(struct i40e_hw *hw) i40evf_init_adminq() argument
546 if ((hw->aq.num_arq_entries == 0) || i40evf_init_adminq()
547 (hw->aq.num_asq_entries == 0) || i40evf_init_adminq()
548 (hw->aq.arq_buf_size == 0) || i40evf_init_adminq()
549 (hw->aq.asq_buf_size == 0)) { i40evf_init_adminq()
555 i40e_adminq_init_regs(hw); i40evf_init_adminq()
558 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; i40evf_init_adminq()
561 ret_code = i40e_init_asq(hw); i40evf_init_adminq()
566 ret_code = i40e_init_arq(hw); i40evf_init_adminq()
574 i40e_shutdown_asq(hw); i40evf_init_adminq()
583 * @hw: pointer to the hardware structure
585 i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw) i40evf_shutdown_adminq() argument
589 if (i40evf_check_asq_alive(hw)) i40evf_shutdown_adminq()
590 i40evf_aq_queue_shutdown(hw, true); i40evf_shutdown_adminq()
592 i40e_shutdown_asq(hw); i40evf_shutdown_adminq()
593 i40e_shutdown_arq(hw); i40evf_shutdown_adminq()
595 if (hw->nvm_buff.va) i40evf_shutdown_adminq()
596 i40e_free_virt_mem(hw, &hw->nvm_buff); i40evf_shutdown_adminq()
603 * @hw: pointer to the hardware structure
607 static u16 i40e_clean_asq(struct i40e_hw *hw) i40e_clean_asq() argument
609 struct i40e_adminq_ring *asq = &(hw->aq.asq); i40e_clean_asq()
617 while (rd32(hw, hw->aq.asq.head) != ntc) { i40e_clean_asq()
618 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_clean_asq()
619 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); i40e_clean_asq()
625 cb_func(hw, &desc_cb); i40e_clean_asq()
644 * @hw: pointer to the hw struct
649 bool i40evf_asq_done(struct i40e_hw *hw) i40evf_asq_done() argument
654 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; i40evf_asq_done()
660 * @hw: pointer to the hw struct
669 i40e_status i40evf_asq_send_command(struct i40e_hw *hw, i40evf_asq_send_command() argument
683 mutex_lock(&hw->aq.asq_mutex); i40evf_asq_send_command()
685 if (hw->aq.asq.count == 0) { i40evf_asq_send_command()
686 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40evf_asq_send_command()
692 hw->aq.asq_last_status = I40E_AQ_RC_OK; i40evf_asq_send_command()
694 val = rd32(hw, hw->aq.asq.head); i40evf_asq_send_command()
695 if (val >= hw->aq.num_asq_entries) { i40evf_asq_send_command()
696 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40evf_asq_send_command()
702 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); i40evf_asq_send_command()
724 if (buff_size > hw->aq.asq_buf_size) { i40evf_asq_send_command()
725 i40e_debug(hw, i40evf_asq_send_command()
734 i40e_debug(hw, i40evf_asq_send_command()
748 if (i40e_clean_asq(hw) == 0) { i40evf_asq_send_command()
749 i40e_debug(hw, i40evf_asq_send_command()
757 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); i40evf_asq_send_command()
764 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); i40evf_asq_send_command()
779 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n"); i40evf_asq_send_command()
780 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, i40evf_asq_send_command()
782 (hw->aq.asq.next_to_use)++; i40evf_asq_send_command()
783 if (hw->aq.asq.next_to_use == hw->aq.asq.count) i40evf_asq_send_command()
784 hw->aq.asq.next_to_use = 0; i40evf_asq_send_command()
786 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); i40evf_asq_send_command()
798 if (i40evf_asq_done(hw)) i40evf_asq_send_command()
802 } while (total_delay < hw->aq.asq_cmd_timeout); i40evf_asq_send_command()
806 if (i40evf_asq_done(hw)) { i40evf_asq_send_command()
812 i40e_debug(hw, i40evf_asq_send_command()
825 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; i40evf_asq_send_command()
828 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40evf_asq_send_command()
830 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, i40evf_asq_send_command()
840 i40e_debug(hw, i40evf_asq_send_command()
847 mutex_unlock(&hw->aq.asq_mutex); i40evf_asq_send_command()
869 * @hw: pointer to the hw struct
877 i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, i40evf_clean_arq_element() argument
882 u16 ntc = hw->aq.arq.next_to_clean; i40evf_clean_arq_element()
891 mutex_lock(&hw->aq.arq_mutex); i40evf_clean_arq_element()
893 if (hw->aq.arq.count == 0) { i40evf_clean_arq_element()
894 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40evf_clean_arq_element()
901 ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK); i40evf_clean_arq_element()
909 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); i40evf_clean_arq_element()
915 hw->aq.arq_last_status = i40evf_clean_arq_element()
917 i40e_debug(hw, i40evf_clean_arq_element()
920 hw->aq.arq_last_status); i40evf_clean_arq_element()
927 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, i40evf_clean_arq_element()
930 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n"); i40evf_clean_arq_element()
931 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, i40evf_clean_arq_element()
932 hw->aq.arq_buf_size); i40evf_clean_arq_element()
938 bi = &hw->aq.arq.r.arq_bi[ntc]; i40evf_clean_arq_element()
942 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) i40evf_clean_arq_element()
949 wr32(hw, hw->aq.arq.tail, ntc); i40evf_clean_arq_element()
952 if (ntc == hw->aq.num_arq_entries) i40evf_clean_arq_element()
954 hw->aq.arq.next_to_clean = ntc; i40evf_clean_arq_element()
955 hw->aq.arq.next_to_use = ntu; i40evf_clean_arq_element()
960 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); i40evf_clean_arq_element()
963 mutex_unlock(&hw->aq.arq_mutex); i40evf_clean_arq_element()
968 void i40evf_resume_aq(struct i40e_hw *hw) i40evf_resume_aq() argument
971 hw->aq.asq.next_to_use = 0; i40evf_resume_aq()
972 hw->aq.asq.next_to_clean = 0; i40evf_resume_aq()
974 i40e_config_asq_regs(hw); i40evf_resume_aq()
976 hw->aq.arq.next_to_use = 0; i40evf_resume_aq()
977 hw->aq.arq.next_to_clean = 0; i40evf_resume_aq()
979 i40e_config_arq_regs(hw); i40evf_resume_aq()
H A Di40e_prototype.h42 i40e_status i40evf_init_adminq(struct i40e_hw *hw);
43 i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw);
44 void i40e_adminq_init_ring_data(struct i40e_hw *hw);
45 i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
48 i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
53 bool i40evf_asq_done(struct i40e_hw *hw);
56 void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
59 void i40e_idle_aq(struct i40e_hw *hw);
60 void i40evf_resume_aq(struct i40e_hw *hw);
61 bool i40evf_check_asq_alive(struct i40e_hw *hw);
62 i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
63 const char *i40evf_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
64 const char *i40evf_stat_str(struct i40e_hw *hw, i40e_status stat_err);
66 i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
68 i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
70 i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw,
73 i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,
77 i40e_status i40e_set_mac_type(struct i40e_hw *hw);
89 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
91 i40e_status i40e_vf_reset(struct i40e_hw *hw);
92 i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
97 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
99 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
104 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dhw.h29 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
30 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw);
31 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
33 int rtl92ee_hw_init(struct ieee80211_hw *hw);
34 void rtl92ee_card_disable(struct ieee80211_hw *hw);
35 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw);
36 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw);
37 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
38 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
39 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci);
40 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw);
41 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw);
42 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
44 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
45 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
47 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw);
48 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
49 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw);
50 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
53 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
55 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw);
56 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw);
57 void rtl92ee_suspend(struct ieee80211_hw *hw);
58 void rtl92ee_resume(struct ieee80211_hw *hw);
59 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, bool allow_all_da,
H A Dphy.c36 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
38 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
42 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw);
43 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
46 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
48 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw);
54 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
57 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
60 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw);
61 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw);
63 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl92ee_phy_query_bb_reg() argument
65 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_query_bb_reg()
81 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, rtl92ee_phy_set_bb_reg() argument
84 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_bb_reg()
104 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw, rtl92ee_phy_query_rf_reg() argument
107 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_query_rf_reg()
117 original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr); rtl92ee_phy_query_rf_reg()
130 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw, rtl92ee_phy_set_rf_reg() argument
134 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_rf_reg()
145 original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr); rtl92ee_phy_set_rf_reg()
150 _rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data); rtl92ee_phy_set_rf_reg()
159 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw, _rtl92ee_phy_rf_serial_read() argument
162 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_rf_serial_read()
172 if (RT_CANNOT_IO(hw)) { _rtl92ee_phy_rf_serial_read()
176 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92ee_phy_rf_serial_read()
180 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92ee_phy_rf_serial_read()
183 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92ee_phy_rf_serial_read()
186 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92ee_phy_rf_serial_read()
189 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, _rtl92ee_phy_rf_serial_read()
192 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, _rtl92ee_phy_rf_serial_read()
195 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, _rtl92ee_phy_rf_serial_read()
198 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, _rtl92ee_phy_rf_serial_read()
206 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw, _rtl92ee_phy_rf_serial_write() argument
212 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_rf_serial_write()
216 if (RT_CANNOT_IO(hw)) { _rtl92ee_phy_rf_serial_write()
223 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92ee_phy_rf_serial_write()
240 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw) rtl92ee_phy_mac_config() argument
242 return _rtl92ee_phy_config_mac_with_headerfile(hw); rtl92ee_phy_mac_config()
245 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw) rtl92ee_phy_bb_config() argument
247 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_bb_config()
253 phy_init_bb_rf_register_def(hw); rtl92ee_phy_bb_config()
268 rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw); rtl92ee_phy_bb_config()
271 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, rtl92ee_phy_bb_config()
276 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw) rtl92ee_phy_rf_config() argument
278 return rtl92ee_phy_rf6052_config(hw); rtl92ee_phy_rf_config()
281 static bool _check_condition(struct ieee80211_hw *hw, _check_condition() argument
284 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _check_condition()
285 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _check_condition()
311 static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data, _rtl92ee_config_rf_reg() argument
317 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); _rtl92ee_config_rf_reg()
324 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); _rtl92ee_config_rf_reg()
329 rtl_set_rfreg(hw, rfpath, regaddr, _rtl92ee_config_rf_reg()
332 getvalue = rtl_get_rfreg(hw, rfpath, addr, _rtl92ee_config_rf_reg()
343 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); _rtl92ee_config_rf_reg()
348 rtl_set_rfreg(hw, rfpath, regaddr, _rtl92ee_config_rf_reg()
351 rtl_set_rfreg(hw, rfpath, 0x18, _rtl92ee_config_rf_reg()
354 getvalue = rtl_get_rfreg(hw, rfpath, addr, _rtl92ee_config_rf_reg()
363 static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw, _rtl92ee_config_rf_radio_a() argument
369 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A, _rtl92ee_config_rf_radio_a()
373 static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw, _rtl92ee_config_rf_radio_b() argument
379 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B, _rtl92ee_config_rf_radio_b()
383 static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw, _rtl92ee_config_bb_reg() argument
399 rtl_set_bbreg(hw, addr, MASKDWORD , data); _rtl92ee_config_bb_reg()
404 static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) _rtl92ee_phy_init_tx_power_by_rate() argument
406 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_init_tx_power_by_rate()
419 static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, _rtl92ee_phy_set_txpower_by_rate_base() argument
424 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_set_txpower_by_rate_base()
459 static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, _rtl92ee_phy_get_txpower_by_rate_base() argument
463 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_get_txpower_by_rate_base()
500 static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) _rtl92ee_phy_store_txpower_by_rate_base() argument
502 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_store_txpower_by_rate_base()
513 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl92ee_phy_store_txpower_by_rate_base()
521 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl92ee_phy_store_txpower_by_rate_base()
528 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, _rtl92ee_phy_store_txpower_by_rate_base()
534 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, _rtl92ee_phy_store_txpower_by_rate_base()
541 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, _rtl92ee_phy_store_txpower_by_rate_base()
571 static void phy_convert_txpwr_dbm_to_rel_val(struct ieee80211_hw *hw) phy_convert_txpwr_dbm_to_rel_val() argument
573 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_convert_txpwr_dbm_to_rel_val()
579 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, phy_convert_txpwr_dbm_to_rel_val()
591 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, phy_convert_txpwr_dbm_to_rel_val()
603 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, phy_convert_txpwr_dbm_to_rel_val()
612 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, phy_convert_txpwr_dbm_to_rel_val()
622 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, phy_convert_txpwr_dbm_to_rel_val()
638 static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw) _rtl92ee_phy_txpower_by_rate_configuration() argument
640 _rtl92ee_phy_store_txpower_by_rate_base(hw); _rtl92ee_phy_txpower_by_rate_configuration()
641 phy_convert_txpwr_dbm_to_rel_val(hw); _rtl92ee_phy_txpower_by_rate_configuration()
644 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw) _rtl92ee_phy_bb8192ee_config_parafile() argument
646 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_bb8192ee_config_parafile()
648 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92ee_phy_bb8192ee_config_parafile()
651 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_PHY_REG); _rtl92ee_phy_bb8192ee_config_parafile()
657 _rtl92ee_phy_init_tx_power_by_rate(hw); _rtl92ee_phy_bb8192ee_config_parafile()
661 phy_config_bb_with_pghdrfile(hw, BASEBAND_CONFIG_PHY_REG); _rtl92ee_phy_bb8192ee_config_parafile()
663 _rtl92ee_phy_txpower_by_rate_configuration(hw); _rtl92ee_phy_bb8192ee_config_parafile()
668 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_AGC_TAB); _rtl92ee_phy_bb8192ee_config_parafile()
673 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, _rtl92ee_phy_bb8192ee_config_parafile()
680 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl92ee_phy_config_mac_with_headerfile() argument
682 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_config_mac_with_headerfile()
704 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw, phy_config_bb_with_hdr_file() argument
710 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_config_bb_with_hdr_file()
721 _rtl92ee_config_bb_reg(hw, v1, v2); phy_config_bb_with_hdr_file()
727 if (!_check_condition(hw , array[i])) { phy_config_bb_with_hdr_file()
744 _rtl92ee_config_bb_reg(hw, v1, phy_config_bb_with_hdr_file()
762 rtl_set_bbreg(hw, array[i], MASKDWORD, phy_config_bb_with_hdr_file()
771 if (!_check_condition(hw , array[i])) { phy_config_bb_with_hdr_file()
790 rtl_set_bbreg(hw, phy_config_bb_with_hdr_file()
860 static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw, _rtl92ee_store_tx_power_by_rate() argument
866 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_store_tx_power_by_rate()
888 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw, phy_config_bb_with_pghdrfile() argument
891 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_config_bb_with_pghdrfile()
910 _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3, phy_config_bb_with_pghdrfile()
929 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl92ee_phy_config_rf_with_headerfile() argument
932 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_config_rf_with_headerfile()
949 _rtl92ee_config_rf_radio_a(hw, v1, v2); rtl92ee_phy_config_rf_with_headerfile()
956 if (!_check_condition(hw , array[i])) { rtl92ee_phy_config_rf_with_headerfile()
973 _rtl92ee_config_rf_radio_a(hw, rtl92ee_phy_config_rf_with_headerfile()
996 _rtl92ee_config_rf_radio_b(hw, v1, v2); rtl92ee_phy_config_rf_with_headerfile()
1003 if (!_check_condition(hw , array[i])) { rtl92ee_phy_config_rf_with_headerfile()
1020 _rtl92ee_config_rf_radio_b(hw, rtl92ee_phy_config_rf_with_headerfile()
1039 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl92ee_phy_get_hw_reg_originalvalue() argument
1041 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_get_hw_reg_originalvalue()
1045 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl92ee_phy_get_hw_reg_originalvalue()
1047 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl92ee_phy_get_hw_reg_originalvalue()
1049 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl92ee_phy_get_hw_reg_originalvalue()
1051 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl92ee_phy_get_hw_reg_originalvalue()
1060 rtlphy->framesync = (u8)rtl_get_bbreg(hw, rtl92ee_phy_get_hw_reg_originalvalue()
1062 rtlphy->framesync_c34 = rtl_get_bbreg(hw, rtl92ee_phy_get_hw_reg_originalvalue()
1070 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw) phy_init_bb_rf_register_def() argument
1072 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_init_bb_rf_register_def()
1099 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) rtl92ee_phy_get_txpower_level() argument
1101 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_get_txpower_level()
1107 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, rtl92ee_phy_get_txpower_level()
1110 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > rtl92ee_phy_get_txpower_level()
1112 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, rtl92ee_phy_get_txpower_level()
1115 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, rtl92ee_phy_get_txpower_level()
1117 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, rtl92ee_phy_get_txpower_level()
1185 static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw, _rtl92ee_get_txpower_by_rate() argument
1189 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_get_txpower_by_rate()
1252 static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw, _rtl92ee_get_txpower_index() argument
1256 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_get_txpower_index()
1292 diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G, _rtl92ee_get_txpower_index()
1303 static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx, _rtl92ee_set_txpower_index() argument
1306 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_set_txpower_index()
1311 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, _rtl92ee_set_txpower_index()
1315 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1, _rtl92ee_set_txpower_index()
1319 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2, _rtl92ee_set_txpower_index()
1323 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3, _rtl92ee_set_txpower_index()
1327 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0, _rtl92ee_set_txpower_index()
1331 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1, _rtl92ee_set_txpower_index()
1335 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2, _rtl92ee_set_txpower_index()
1339 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3, _rtl92ee_set_txpower_index()
1343 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0, _rtl92ee_set_txpower_index()
1347 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1, _rtl92ee_set_txpower_index()
1351 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2, _rtl92ee_set_txpower_index()
1355 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3, _rtl92ee_set_txpower_index()
1359 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, _rtl92ee_set_txpower_index()
1363 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, _rtl92ee_set_txpower_index()
1367 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, _rtl92ee_set_txpower_index()
1371 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, _rtl92ee_set_txpower_index()
1375 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, _rtl92ee_set_txpower_index()
1379 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, _rtl92ee_set_txpower_index()
1383 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, _rtl92ee_set_txpower_index()
1387 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, _rtl92ee_set_txpower_index()
1391 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, _rtl92ee_set_txpower_index()
1395 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, _rtl92ee_set_txpower_index()
1399 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, _rtl92ee_set_txpower_index()
1403 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, _rtl92ee_set_txpower_index()
1407 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, _rtl92ee_set_txpower_index()
1411 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, _rtl92ee_set_txpower_index()
1415 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, _rtl92ee_set_txpower_index()
1419 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, _rtl92ee_set_txpower_index()
1430 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1, _rtl92ee_set_txpower_index()
1434 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2, _rtl92ee_set_txpower_index()
1438 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3, _rtl92ee_set_txpower_index()
1442 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, _rtl92ee_set_txpower_index()
1446 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0, _rtl92ee_set_txpower_index()
1450 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1, _rtl92ee_set_txpower_index()
1454 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2, _rtl92ee_set_txpower_index()
1458 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3, _rtl92ee_set_txpower_index()
1462 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0, _rtl92ee_set_txpower_index()
1466 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1, _rtl92ee_set_txpower_index()
1470 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2, _rtl92ee_set_txpower_index()
1474 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3, _rtl92ee_set_txpower_index()
1478 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, _rtl92ee_set_txpower_index()
1482 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, _rtl92ee_set_txpower_index()
1486 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, _rtl92ee_set_txpower_index()
1490 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, _rtl92ee_set_txpower_index()
1494 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, _rtl92ee_set_txpower_index()
1498 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, _rtl92ee_set_txpower_index()
1502 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, _rtl92ee_set_txpower_index()
1506 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, _rtl92ee_set_txpower_index()
1510 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, _rtl92ee_set_txpower_index()
1514 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, _rtl92ee_set_txpower_index()
1518 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, _rtl92ee_set_txpower_index()
1522 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, _rtl92ee_set_txpower_index()
1526 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, _rtl92ee_set_txpower_index()
1530 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, _rtl92ee_set_txpower_index()
1534 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, _rtl92ee_set_txpower_index()
1538 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, _rtl92ee_set_txpower_index()
1551 static void phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw, phy_set_txpower_index_by_rate_array() argument
1559 power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i], phy_set_txpower_index_by_rate_array()
1561 _rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]); phy_set_txpower_index_by_rate_array()
1565 static void phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw, phy_set_txpower_index_by_rate_section() argument
1570 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_set_txpower_index_by_rate_section()
1578 phy_set_txpower_index_by_rate_array(hw, rfpath, phy_set_txpower_index_by_rate_section()
1586 phy_set_txpower_index_by_rate_array(hw, rfpath, phy_set_txpower_index_by_rate_section()
1594 phy_set_txpower_index_by_rate_array(hw, rfpath, phy_set_txpower_index_by_rate_section()
1602 phy_set_txpower_index_by_rate_array(hw, rfpath, phy_set_txpower_index_by_rate_section()
1610 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl92ee_phy_set_txpower_level() argument
1612 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92ee_phy_set_txpower_level()
1613 struct rtl_phy *rtlphy = &rtl_priv(hw)->phy; rtl92ee_phy_set_txpower_level()
1620 phy_set_txpower_index_by_rate_section(hw, rfpath, rtl92ee_phy_set_txpower_level()
1622 phy_set_txpower_index_by_rate_section(hw, rfpath, rtl92ee_phy_set_txpower_level()
1624 phy_set_txpower_index_by_rate_section(hw, rfpath, rtl92ee_phy_set_txpower_level()
1629 phy_set_txpower_index_by_rate_section(hw, rtl92ee_phy_set_txpower_level()
1635 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, _rtl92ee_phy_txpwr_idx_to_dbm() argument
1658 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) rtl92ee_phy_scan_operation_backup() argument
1660 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_scan_operation_backup()
1661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_phy_scan_operation_backup()
1668 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, rtl92ee_phy_scan_operation_backup()
1674 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, rtl92ee_phy_scan_operation_backup()
1685 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl92ee_phy_set_bw_mode_callback() argument
1687 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_bw_mode_callback()
1688 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_phy_set_bw_mode_callback()
1690 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_phy_set_bw_mode_callback()
1727 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl92ee_phy_set_bw_mode_callback()
1728 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl92ee_phy_set_bw_mode_callback()
1729 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT, rtl92ee_phy_set_bw_mode_callback()
1733 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl92ee_phy_set_bw_mode_callback()
1734 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl92ee_phy_set_bw_mode_callback()
1735 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, rtl92ee_phy_set_bw_mode_callback()
1737 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, rtl92ee_phy_set_bw_mode_callback()
1740 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl92ee_phy_set_bw_mode_callback()
1749 rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl92ee_phy_set_bw_mode_callback()
1754 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw, rtl92ee_phy_set_bw_mode() argument
1757 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_bw_mode()
1759 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_phy_set_bw_mode()
1765 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl92ee_phy_set_bw_mode()
1766 rtl92ee_phy_set_bw_mode_callback(hw); rtl92ee_phy_set_bw_mode()
1775 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw) rtl92ee_phy_sw_chnl_callback() argument
1777 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_sw_chnl_callback()
1778 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_phy_sw_chnl_callback()
1790 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, rtl92ee_phy_sw_chnl_callback()
1804 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw) rtl92ee_phy_sw_chnl() argument
1806 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_sw_chnl()
1808 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_phy_sw_chnl()
1819 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl92ee_phy_sw_chnl()
1820 rtl92ee_phy_sw_chnl_callback(hw); rtl92ee_phy_sw_chnl()
1833 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, _rtl92ee_phy_sw_chnl_step_by_step() argument
1837 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_sw_chnl_step_by_step()
1902 rtl92ee_phy_set_txpower_level(hw, channel); _rtl92ee_phy_sw_chnl_step_by_step()
1922 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl92ee_phy_sw_chnl_step_by_step()
1965 static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl92ee_phy_path_a_iqk() argument
1971 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_iqk()
1972 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); _rtl92ee_phy_path_a_iqk()
1973 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_iqk()
1975 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_a_iqk()
1976 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_iqk()
1977 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_iqk()
1978 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_iqk()
1980 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); _rtl92ee_phy_path_a_iqk()
1981 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); _rtl92ee_phy_path_a_iqk()
1984 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl92ee_phy_path_a_iqk()
1987 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl92ee_phy_path_a_iqk()
1988 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_a_iqk()
1992 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92ee_phy_path_a_iqk()
1993 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92ee_phy_path_a_iqk()
1994 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92ee_phy_path_a_iqk()
2006 static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw) _rtl92ee_phy_path_b_iqk() argument
2012 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_iqk()
2013 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); _rtl92ee_phy_path_b_iqk()
2014 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_iqk()
2016 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_iqk()
2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_iqk()
2019 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_iqk()
2020 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_iqk()
2021 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_b_iqk()
2022 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_iqk()
2024 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); _rtl92ee_phy_path_b_iqk()
2025 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); _rtl92ee_phy_path_b_iqk()
2028 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl92ee_phy_path_b_iqk()
2031 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_b_iqk()
2032 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_b_iqk()
2036 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92ee_phy_path_b_iqk()
2037 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92ee_phy_path_b_iqk()
2038 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92ee_phy_path_b_iqk()
2050 static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl92ee_phy_path_a_rx_iqk() argument
2057 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk()
2059 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl92ee_phy_path_a_rx_iqk()
2060 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl92ee_phy_path_a_rx_iqk()
2061 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); _rtl92ee_phy_path_a_rx_iqk()
2062 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); _rtl92ee_phy_path_a_rx_iqk()
2065 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); _rtl92ee_phy_path_a_rx_iqk()
2066 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); _rtl92ee_phy_path_a_rx_iqk()
2069 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_rx_iqk()
2072 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_path_a_rx_iqk()
2073 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_a_rx_iqk()
2076 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_a_rx_iqk()
2077 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk()
2078 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk()
2079 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk()
2081 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_a_rx_iqk()
2082 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); _rtl92ee_phy_path_a_rx_iqk()
2085 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl92ee_phy_path_a_rx_iqk()
2088 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_a_rx_iqk()
2089 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_a_rx_iqk()
2094 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk()
2095 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk()
2096 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk()
2104 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); _rtl92ee_phy_path_a_rx_iqk()
2111 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); _rtl92ee_phy_path_a_rx_iqk()
2114 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk()
2116 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl92ee_phy_path_a_rx_iqk()
2118 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl92ee_phy_path_a_rx_iqk()
2119 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); _rtl92ee_phy_path_a_rx_iqk()
2120 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); _rtl92ee_phy_path_a_rx_iqk()
2123 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); _rtl92ee_phy_path_a_rx_iqk()
2124 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); _rtl92ee_phy_path_a_rx_iqk()
2127 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_rx_iqk()
2130 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_a_rx_iqk()
2133 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk()
2134 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_a_rx_iqk()
2135 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk()
2136 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk()
2138 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_a_rx_iqk()
2139 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); _rtl92ee_phy_path_a_rx_iqk()
2142 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); _rtl92ee_phy_path_a_rx_iqk()
2144 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_a_rx_iqk()
2145 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_a_rx_iqk()
2149 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk()
2150 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk()
2154 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk()
2155 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); _rtl92ee_phy_path_a_rx_iqk()
2165 static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl92ee_phy_path_b_rx_iqk() argument
2167 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_path_b_rx_iqk()
2173 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk()
2175 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl92ee_phy_path_b_rx_iqk()
2176 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl92ee_phy_path_b_rx_iqk()
2177 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); _rtl92ee_phy_path_b_rx_iqk()
2178 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); _rtl92ee_phy_path_b_rx_iqk()
2181 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); _rtl92ee_phy_path_b_rx_iqk()
2182 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); _rtl92ee_phy_path_b_rx_iqk()
2184 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_rx_iqk()
2187 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_path_b_rx_iqk()
2188 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_b_rx_iqk()
2191 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk()
2192 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk()
2193 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_b_rx_iqk()
2194 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk()
2196 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_b_rx_iqk()
2197 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl92ee_phy_path_b_rx_iqk()
2203 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_b_rx_iqk()
2204 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_b_rx_iqk()
2209 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk()
2210 reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk()
2211 reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk()
2220 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); _rtl92ee_phy_path_b_rx_iqk()
2226 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); _rtl92ee_phy_path_b_rx_iqk()
2229 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk()
2230 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl92ee_phy_path_b_rx_iqk()
2232 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl92ee_phy_path_b_rx_iqk()
2233 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); _rtl92ee_phy_path_b_rx_iqk()
2234 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); _rtl92ee_phy_path_b_rx_iqk()
2237 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); _rtl92ee_phy_path_b_rx_iqk()
2238 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); _rtl92ee_phy_path_b_rx_iqk()
2241 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_rx_iqk()
2244 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_b_rx_iqk()
2247 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk()
2248 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk()
2249 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk()
2250 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_b_rx_iqk()
2252 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_b_rx_iqk()
2253 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); _rtl92ee_phy_path_b_rx_iqk()
2256 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); _rtl92ee_phy_path_b_rx_iqk()
2258 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_b_rx_iqk()
2259 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_b_rx_iqk()
2263 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk()
2264 reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk()
2265 reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk()
2268 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk()
2269 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); _rtl92ee_phy_path_b_rx_iqk()
2281 static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl92ee_phy_path_a_fill_iqk_matrix() argument
2292 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, _rtl92ee_phy_path_a_fill_iqk_matrix()
2298 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); _rtl92ee_phy_path_a_fill_iqk_matrix()
2299 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), _rtl92ee_phy_path_a_fill_iqk_matrix()
2305 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, _rtl92ee_phy_path_a_fill_iqk_matrix()
2307 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, _rtl92ee_phy_path_a_fill_iqk_matrix()
2309 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), _rtl92ee_phy_path_a_fill_iqk_matrix()
2316 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); _rtl92ee_phy_path_a_fill_iqk_matrix()
2319 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); _rtl92ee_phy_path_a_fill_iqk_matrix()
2322 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); _rtl92ee_phy_path_a_fill_iqk_matrix()
2326 static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl92ee_phy_path_b_fill_iqk_matrix() argument
2337 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, _rtl92ee_phy_path_b_fill_iqk_matrix()
2343 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); _rtl92ee_phy_path_b_fill_iqk_matrix()
2344 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), _rtl92ee_phy_path_b_fill_iqk_matrix()
2350 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, _rtl92ee_phy_path_b_fill_iqk_matrix()
2352 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, _rtl92ee_phy_path_b_fill_iqk_matrix()
2354 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), _rtl92ee_phy_path_b_fill_iqk_matrix()
2361 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); _rtl92ee_phy_path_b_fill_iqk_matrix()
2364 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); _rtl92ee_phy_path_b_fill_iqk_matrix()
2367 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); _rtl92ee_phy_path_b_fill_iqk_matrix()
2371 static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw, _rtl92ee_phy_save_adda_registers() argument
2378 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); _rtl92ee_phy_save_adda_registers()
2381 static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw, _rtl92ee_phy_save_mac_registers() argument
2384 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_save_mac_registers()
2393 static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw, _rtl92ee_phy_reload_adda_registers() argument
2400 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); _rtl92ee_phy_reload_adda_registers()
2403 static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw, _rtl92ee_phy_reload_mac_registers() argument
2406 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_reload_mac_registers()
2414 static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, _rtl92ee_phy_path_adda_on() argument
2423 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616); _rtl92ee_phy_path_adda_on()
2425 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); _rtl92ee_phy_path_adda_on()
2429 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); _rtl92ee_phy_path_adda_on()
2432 static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw, _rtl92ee_phy_mac_setting_calibration() argument
2435 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); _rtl92ee_phy_mac_setting_calibration()
2438 static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw) _rtl92ee_phy_path_a_standby() argument
2440 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl92ee_phy_path_a_standby()
2441 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); _rtl92ee_phy_path_a_standby()
2442 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_standby()
2445 static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw, _rtl92ee_phy_simularity_compare() argument
2520 static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, _rtl92ee_phy_iq_calibrate() argument
2523 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_iq_calibrate()
2527 u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0); _rtl92ee_phy_iq_calibrate()
2528 u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0); _rtl92ee_phy_iq_calibrate()
2547 _rtl92ee_phy_save_adda_registers(hw, adda_reg, _rtl92ee_phy_iq_calibrate()
2550 _rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg, _rtl92ee_phy_iq_calibrate()
2552 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg, _rtl92ee_phy_iq_calibrate()
2557 _rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl92ee_phy_iq_calibrate()
2560 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); _rtl92ee_phy_iq_calibrate()
2561 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); _rtl92ee_phy_iq_calibrate()
2562 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); _rtl92ee_phy_iq_calibrate()
2563 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); _rtl92ee_phy_iq_calibrate()
2565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); _rtl92ee_phy_iq_calibrate()
2566 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); _rtl92ee_phy_iq_calibrate()
2567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); _rtl92ee_phy_iq_calibrate()
2568 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); _rtl92ee_phy_iq_calibrate()
2570 _rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl92ee_phy_iq_calibrate()
2574 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_iq_calibrate()
2575 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_iq_calibrate()
2576 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_iq_calibrate()
2579 patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t); _rtl92ee_phy_iq_calibrate()
2584 result[t][0] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2588 result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, _rtl92ee_phy_iq_calibrate()
2599 patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t); _rtl92ee_phy_iq_calibrate()
2604 result[t][2] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2608 result[t][3] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2623 _rtl92ee_phy_path_a_standby(hw); _rtl92ee_phy_iq_calibrate()
2625 _rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t); _rtl92ee_phy_iq_calibrate()
2628 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_iq_calibrate()
2629 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_iq_calibrate()
2630 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_iq_calibrate()
2633 pathb_ok = _rtl92ee_phy_path_b_iqk(hw); _rtl92ee_phy_iq_calibrate()
2637 result[t][4] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2641 result[t][5] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2653 pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t); _rtl92ee_phy_iq_calibrate()
2657 result[t][6] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2661 result[t][7] = (rtl_get_bbreg(hw, _rtl92ee_phy_iq_calibrate()
2679 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); _rtl92ee_phy_iq_calibrate()
2683 _rtl92ee_phy_reload_adda_registers(hw, adda_reg, _rtl92ee_phy_iq_calibrate()
2688 _rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl92ee_phy_iq_calibrate()
2691 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl92ee_phy_iq_calibrate()
2696 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); _rtl92ee_phy_iq_calibrate()
2697 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); _rtl92ee_phy_iq_calibrate()
2699 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); _rtl92ee_phy_iq_calibrate()
2700 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); _rtl92ee_phy_iq_calibrate()
2704 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); _rtl92ee_phy_iq_calibrate()
2705 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); _rtl92ee_phy_iq_calibrate()
2709 static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl92ee_phy_lc_calibrate() argument
2713 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_lc_calibrate()
2723 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); _rtl92ee_phy_lc_calibrate()
2726 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, _rtl92ee_phy_lc_calibrate()
2729 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, _rtl92ee_phy_lc_calibrate()
2733 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl92ee_phy_lc_calibrate()
2736 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); _rtl92ee_phy_lc_calibrate()
2738 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); _rtl92ee_phy_lc_calibrate()
2744 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); _rtl92ee_phy_lc_calibrate()
2747 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl92ee_phy_lc_calibrate()
2754 static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, _rtl92ee_phy_set_rfpath_switch() argument
2757 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_set_rfpath_switch()
2758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_phy_set_rfpath_switch()
2759 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92ee_phy_set_rfpath_switch()
2768 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); _rtl92ee_phy_set_rfpath_switch()
2772 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl92ee_phy_set_rfpath_switch()
2775 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl92ee_phy_set_rfpath_switch()
2778 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); _rtl92ee_phy_set_rfpath_switch()
2779 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); _rtl92ee_phy_set_rfpath_switch()
2786 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, _rtl92ee_phy_set_rfpath_switch()
2788 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl92ee_phy_set_rfpath_switch()
2791 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); _rtl92ee_phy_set_rfpath_switch()
2793 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, _rtl92ee_phy_set_rfpath_switch()
2795 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl92ee_phy_set_rfpath_switch()
2798 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); _rtl92ee_phy_set_rfpath_switch()
2828 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl92ee_phy_iq_calibrate() argument
2830 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_iq_calibrate()
2852 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg, rtl92ee_phy_iq_calibrate()
2874 _rtl92ee_phy_iq_calibrate(hw, result, i, true); rtl92ee_phy_iq_calibrate()
2876 is12simular = _rtl92ee_phy_simularity_compare(hw, rtl92ee_phy_iq_calibrate()
2886 is13simular = _rtl92ee_phy_simularity_compare(hw, rtl92ee_phy_iq_calibrate()
2893 is23simular = _rtl92ee_phy_simularity_compare(hw, rtl92ee_phy_iq_calibrate()
2937 _rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, rtl92ee_phy_iq_calibrate()
2941 _rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result, rtl92ee_phy_iq_calibrate()
2955 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg, rtl92ee_phy_iq_calibrate()
2959 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw) rtl92ee_phy_lc_calibrate() argument
2961 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_lc_calibrate()
2976 _rtl92ee_phy_lc_calibrate(hw, false); rtl92ee_phy_lc_calibrate()
2981 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) rtl92ee_phy_ap_calibrate() argument
2985 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) rtl92ee_phy_set_rfpath_switch() argument
2987 _rtl92ee_phy_set_rfpath_switch(hw, bmain, false); rtl92ee_phy_set_rfpath_switch()
2990 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl92ee_phy_set_io_cmd() argument
2992 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_io_cmd()
3023 rtl92ee_phy_set_io(hw); rtl92ee_phy_set_io_cmd()
3028 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw) rtl92ee_phy_set_io() argument
3030 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_io()
3039 rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); rtl92ee_phy_set_io()
3040 rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca); rtl92ee_phy_set_io()
3042 rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel); rtl92ee_phy_set_io()
3047 rtl92ee_dm_write_dig(hw, 0x17); rtl92ee_phy_set_io()
3049 rtl92ee_dm_write_cck_cca_thres(hw, 0x40); rtl92ee_phy_set_io()
3061 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw) rtl92ee_phy_set_rf_on() argument
3063 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_set_rf_on()
3073 static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw) _rtl92ee_phy_set_rf_sleep() argument
3075 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_set_rf_sleep()
3078 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92ee_phy_set_rf_sleep()
3084 static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl92ee_phy_set_rf_power_state() argument
3087 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_set_rf_power_state()
3088 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92ee_phy_set_rf_power_state()
3089 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl92ee_phy_set_rf_power_state()
3090 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92ee_phy_set_rf_power_state()
3106 rtstatus = rtl_ps_enable_nic(hw); _rtl92ee_phy_set_rf_power_state()
3115 rtl92ee_phy_set_rf_on(hw); _rtl92ee_phy_set_rf_power_state()
3118 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); _rtl92ee_phy_set_rf_power_state()
3120 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); _rtl92ee_phy_set_rf_power_state()
3152 rtl_ps_disable_nic(hw); _rtl92ee_phy_set_rf_power_state()
3156 rtlpriv->cfg->ops->led_control(hw, _rtl92ee_phy_set_rf_power_state()
3159 rtlpriv->cfg->ops->led_control(hw, _rtl92ee_phy_set_rf_power_state()
3195 _rtl92ee_phy_set_rf_sleep(hw); _rtl92ee_phy_set_rf_power_state()
3208 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl92ee_phy_set_rf_power_state() argument
3211 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ee_phy_set_rf_power_state()
3217 bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state); rtl92ee_phy_set_rf_power_state()
H A Dphy.h46 #define RT_CANNOT_IO(hw) false
119 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
121 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
123 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
126 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
129 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
130 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
131 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
132 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
133 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
135 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
136 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
138 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
139 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
141 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
142 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
143 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
144 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
145 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
146 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
147 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
149 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
150 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
H A Drf.c33 static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
35 void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) rtl92ee_phy_rf6052_set_bandwidth() argument
37 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_rf6052_set_bandwidth()
44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, rtl92ee_phy_rf6052_set_bandwidth()
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, rtl92ee_phy_rf6052_set_bandwidth()
52 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, rtl92ee_phy_rf6052_set_bandwidth()
54 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, rtl92ee_phy_rf6052_set_bandwidth()
64 bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw) rtl92ee_phy_rf6052_config() argument
66 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_phy_rf6052_config()
74 return _rtl92ee_phy_rf6052_config_parafile(hw); rtl92ee_phy_rf6052_config()
77 static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw) _rtl92ee_phy_rf6052_config_parafile() argument
79 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_phy_rf6052_config_parafile()
92 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, _rtl92ee_phy_rf6052_config_parafile()
97 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, _rtl92ee_phy_rf6052_config_parafile()
102 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); _rtl92ee_phy_rf6052_config_parafile()
105 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); _rtl92ee_phy_rf6052_config_parafile()
108 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, _rtl92ee_phy_rf6052_config_parafile()
112 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); _rtl92ee_phy_rf6052_config_parafile()
117 rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw, _rtl92ee_phy_rf6052_config_parafile()
121 rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw, _rtl92ee_phy_rf6052_config_parafile()
133 rtl_set_bbreg(hw, pphyreg->rfintfs, _rtl92ee_phy_rf6052_config_parafile()
138 rtl_set_bbreg(hw, pphyreg->rfintfs, _rtl92ee_phy_rf6052_config_parafile()
H A DMakefile4 hw.o \
H A Dled.c31 static void _rtl92ee_init_led(struct ieee80211_hw *hw, _rtl92ee_init_led() argument
34 pled->hw = hw; _rtl92ee_init_led()
39 void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92ee_sw_led_on() argument
42 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_sw_led_on()
70 void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92ee_sw_led_off() argument
72 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_sw_led_off()
100 void rtl92ee_init_sw_leds(struct ieee80211_hw *hw) rtl92ee_init_sw_leds() argument
102 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl92ee_init_sw_leds()
104 _rtl92ee_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0); rtl92ee_init_sw_leds()
105 _rtl92ee_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1); rtl92ee_init_sw_leds()
108 static void _rtl92ee_sw_led_control(struct ieee80211_hw *hw, _rtl92ee_sw_led_control() argument
111 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92ee_sw_led_control()
118 rtl92ee_sw_led_on(hw, pLed0); _rtl92ee_sw_led_control()
121 rtl92ee_sw_led_off(hw, pLed0); _rtl92ee_sw_led_control()
128 void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction) rtl92ee_led_control() argument
130 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_led_control()
131 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ee_led_control()
144 _rtl92ee_sw_led_control(hw, ledaction); rtl92ee_led_control()
H A Dhw.c39 #include "hw.h"
45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw, _rtl92ee_set_bcn_ctrl_reg() argument
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl92ee_set_bcn_ctrl_reg()
49 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_set_bcn_ctrl_reg()
57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw) _rtl92ee_stop_tx_beacon() argument
59 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_stop_tx_beacon()
70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw) _rtl92ee_resume_tx_beacon() argument
72 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_resume_tx_beacon()
83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw) _rtl92ee_enable_bcn_sub_func() argument
85 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); _rtl92ee_enable_bcn_sub_func()
88 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw) _rtl92ee_disable_bcn_sub_func() argument
90 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); _rtl92ee_disable_bcn_sub_func()
93 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw, _rtl92ee_set_fw_clock_on() argument
96 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_set_fw_clock_on()
97 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_set_fw_clock_on()
102 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, _rtl92ee_set_fw_clock_on()
130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, _rtl92ee_set_fw_clock_on()
164 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val) _rtl92ee_set_fw_clock_off() argument
166 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_set_fw_clock_off()
167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_set_fw_clock_off()
168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl92ee_set_fw_clock_off()
181 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); _rtl92ee_set_fw_clock_off()
206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl92ee_set_fw_clock_off()
219 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw) _rtl92ee_set_fw_ps_rf_on() argument
224 _rtl92ee_set_fw_clock_on(hw, rpwm_val, true); _rtl92ee_set_fw_ps_rf_on()
227 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw) _rtl92ee_set_fw_ps_rf_off_low_power() argument
232 _rtl92ee_set_fw_clock_off(hw, rpwm_val); _rtl92ee_set_fw_ps_rf_off_low_power()
237 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; rtl92ee_fw_clk_off_timer_callback() local
239 _rtl92ee_set_fw_ps_rf_off_low_power(hw); rtl92ee_fw_clk_off_timer_callback()
242 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw) _rtl92ee_fwlps_leave() argument
244 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_fwlps_leave()
245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92ee_fwlps_leave()
246 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_fwlps_leave()
252 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false); _rtl92ee_fwlps_leave()
254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl92ee_fwlps_leave()
256 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl92ee_fwlps_leave()
260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl92ee_fwlps_leave()
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl92ee_fwlps_leave()
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl92ee_fwlps_leave()
269 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw) _rtl92ee_fwlps_enter() argument
271 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_fwlps_enter()
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92ee_fwlps_enter()
273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_fwlps_enter()
279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl92ee_fwlps_enter()
281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl92ee_fwlps_enter()
284 _rtl92ee_set_fw_clock_off(hw, rpwm_val); _rtl92ee_fwlps_enter()
287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl92ee_fwlps_enter()
289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl92ee_fwlps_enter()
291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl92ee_fwlps_enter()
296 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) rtl92ee_get_hw_reg() argument
298 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_get_hw_reg()
299 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ee_get_hw_reg()
300 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_get_hw_reg()
313 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, rtl92ee_get_hw_reg()
348 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw) _rtl92ee_download_rsvd_page() argument
350 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_download_rsvd_page()
365 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); _rtl92ee_download_rsvd_page()
366 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); _rtl92ee_download_rsvd_page()
384 rtl92ee_set_fw_rsvdpagepkt(hw, false); _rtl92ee_download_rsvd_page()
417 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); _rtl92ee_download_rsvd_page()
418 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); _rtl92ee_download_rsvd_page()
427 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) rtl92ee_set_hw_reg() argument
429 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_hw_reg()
430 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_set_hw_reg()
431 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_set_hw_reg()
432 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw)); rtl92ee_set_hw_reg()
433 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ee_set_hw_reg()
476 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, rtl92ee_set_hw_reg()
526 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, rtl92ee_set_hw_reg()
603 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val)); rtl92ee_set_hw_reg()
620 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); rtl92ee_set_hw_reg()
626 _rtl92ee_set_fw_ps_rf_on(hw); rtl92ee_set_hw_reg()
632 _rtl92ee_fwlps_enter(hw); rtl92ee_set_hw_reg()
634 _rtl92ee_fwlps_leave(hw); rtl92ee_set_hw_reg()
641 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); rtl92ee_set_hw_reg()
642 _rtl92ee_download_rsvd_page(hw); rtl92ee_set_hw_reg()
644 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus); rtl92ee_set_hw_reg()
648 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); rtl92ee_set_hw_reg()
663 _rtl92ee_stop_tx_beacon(hw); rtl92ee_set_hw_reg()
665 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); rtl92ee_set_hw_reg()
672 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl92ee_set_hw_reg()
675 _rtl92ee_resume_tx_beacon(hw); rtl92ee_set_hw_reg()
683 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array); rtl92ee_set_hw_reg()
693 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw) _rtl92ee_llt_table_init() argument
695 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_llt_table_init()
732 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw) _rtl92ee_gen_refresh_led_state() argument
734 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_gen_refresh_led_state()
735 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92ee_gen_refresh_led_state()
736 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92ee_gen_refresh_led_state()
743 rtl92ee_sw_led_on(hw, pled0); _rtl92ee_gen_refresh_led_state()
745 rtl92ee_sw_led_on(hw, pled0); _rtl92ee_gen_refresh_led_state()
747 rtl92ee_sw_led_off(hw, pled0); _rtl92ee_gen_refresh_led_state()
750 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw) _rtl92ee_init_mac() argument
752 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_init_mac()
753 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl92ee_init_mac()
754 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_init_mac()
817 if (_rtl92ee_llt_table_init(hw) == false) { _rtl92ee_init_mac()
926 _rtl92ee_gen_refresh_led_state(hw); _rtl92ee_init_mac()
930 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw) _rtl92ee_hw_configure() argument
932 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_hw_configure()
933 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl92ee_hw_configure()
1017 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw) _rtl92ee_enable_aspm_back_door() argument
1019 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_enable_aspm_back_door()
1020 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92ee_enable_aspm_back_door()
1105 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw) rtl92ee_enable_hw_security_config() argument
1107 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_enable_hw_security_config()
1118 "not open hw encryption\n"); rtl92ee_enable_hw_security_config()
1137 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); rtl92ee_enable_hw_security_config()
1273 int rtl92ee_hw_init(struct ieee80211_hw *hw) rtl92ee_hw_init() argument
1275 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_hw_init()
1276 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_hw_init()
1277 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_hw_init()
1279 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ee_hw_init()
1285 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n"); rtl92ee_hw_init()
1287 rtlpriv->intf_ops->disable_aspm(hw); rtl92ee_hw_init()
1305 rtstatus = _rtl92ee_init_mac(hw); rtl92ee_hw_init()
1326 err = rtl92ee_download_fw(hw, false); rtl92ee_hw_init()
1342 rtl92ee_phy_mac_config(hw); rtl92ee_hw_init()
1344 rtl92ee_phy_bb_config(hw); rtl92ee_hw_init()
1346 rtl92ee_phy_rf_config(hw); rtl92ee_hw_init()
1348 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A, rtl92ee_hw_init()
1350 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B, rtl92ee_hw_init()
1352 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1, rtl92ee_hw_init()
1357 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, rtl92ee_hw_init()
1359 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, rtl92ee_hw_init()
1363 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); rtl92ee_hw_init()
1364 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); rtl92ee_hw_init()
1369 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418); rtl92ee_hw_init()
1372 _rtl92ee_hw_configure(hw); rtl92ee_hw_init()
1376 rtl_cam_reset_all_entry(hw); rtl92ee_hw_init()
1377 rtl92ee_enable_hw_security_config(hw); rtl92ee_hw_init()
1381 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); rtl92ee_hw_init()
1382 _rtl92ee_enable_aspm_back_door(hw); rtl92ee_hw_init()
1383 rtlpriv->intf_ops->enable_aspm(hw); rtl92ee_hw_init()
1385 rtl92ee_bt_hw_init(hw); rtl92ee_hw_init()
1391 rtl92ee_phy_iq_calibrate(hw, true); rtl92ee_hw_init()
1393 rtl92ee_phy_iq_calibrate(hw, false); rtl92ee_hw_init()
1402 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b); rtl92ee_hw_init()
1404 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); rtl92ee_hw_init()
1409 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); rtl92ee_hw_init()
1421 rtl92ee_dm_init(hw); rtl92ee_hw_init()
1426 "end of Rtl8192EE hw init %x\n", err); rtl92ee_hw_init()
1430 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw) _rtl92ee_read_chip_version() argument
1432 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_read_chip_version()
1452 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw, _rtl92ee_set_media_status() argument
1455 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_set_media_status()
1502 _rtl92ee_stop_tx_beacon(hw); _rtl92ee_set_media_status()
1503 _rtl92ee_enable_bcn_sub_func(hw); _rtl92ee_set_media_status()
1505 _rtl92ee_resume_tx_beacon(hw); _rtl92ee_set_media_status()
1506 _rtl92ee_disable_bcn_sub_func(hw); _rtl92ee_set_media_status()
1514 rtlpriv->cfg->ops->led_control(hw, ledaction); _rtl92ee_set_media_status()
1522 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) rtl92ee_set_check_bssid() argument
1524 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_check_bssid()
1525 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_set_check_bssid()
1533 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, rtl92ee_set_check_bssid()
1535 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); rtl92ee_set_check_bssid()
1538 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); rtl92ee_set_check_bssid()
1539 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, rtl92ee_set_check_bssid()
1544 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) rtl92ee_set_network_type() argument
1546 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_network_type()
1548 if (_rtl92ee_set_media_status(hw, type)) rtl92ee_set_network_type()
1554 rtl92ee_set_check_bssid(hw, true); rtl92ee_set_network_type()
1556 rtl92ee_set_check_bssid(hw, false); rtl92ee_set_network_type()
1563 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci) rtl92ee_set_qos() argument
1565 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_qos()
1567 rtl92ee_dm_init_edca_turbo(hw); rtl92ee_set_qos()
1587 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw) rtl92ee_enable_interrupt() argument
1589 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_enable_interrupt()
1590 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_enable_interrupt()
1597 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw) rtl92ee_disable_interrupt() argument
1599 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_disable_interrupt()
1600 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_disable_interrupt()
1608 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw) _rtl92ee_poweroff_adapter() argument
1610 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_poweroff_adapter()
1611 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_poweroff_adapter()
1626 rtl92ee_firmware_selfreset(hw); _rtl92ee_poweroff_adapter()
1649 void rtl92ee_card_disable(struct ieee80211_hw *hw) rtl92ee_card_disable() argument
1651 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_card_disable()
1652 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ee_card_disable()
1653 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_card_disable()
1663 _rtl92ee_set_media_status(hw, opmode); rtl92ee_card_disable()
1667 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); rtl92ee_card_disable()
1669 _rtl92ee_poweroff_adapter(hw); rtl92ee_card_disable()
1675 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw, rtl92ee_interrupt_recognized() argument
1678 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_interrupt_recognized()
1679 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_interrupt_recognized()
1688 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw) rtl92ee_set_beacon_related_registers() argument
1690 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_beacon_related_registers()
1691 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_set_beacon_related_registers()
1692 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_set_beacon_related_registers()
1697 rtl92ee_disable_interrupt(hw); rtl92ee_set_beacon_related_registers()
1708 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw) rtl92ee_set_beacon_interval() argument
1710 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_beacon_interval()
1711 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_set_beacon_interval()
1719 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw, rtl92ee_update_interrupt_mask() argument
1722 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_update_interrupt_mask()
1723 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_update_interrupt_mask()
1732 rtl92ee_disable_interrupt(hw); rtl92ee_update_interrupt_mask()
1733 rtl92ee_enable_interrupt(hw); rtl92ee_update_interrupt_mask()
1784 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw, _rtl8192ee_read_power_value_fromprom() argument
1789 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8192ee_read_power_value_fromprom()
1841 rtl_priv(hw)->efuse.txpwr_fromeprom = true; _rtl8192ee_read_power_value_fromprom()
2014 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, _rtl92ee_read_txpower_info_from_hwpg() argument
2017 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_read_txpower_info_from_hwpg()
2018 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw)); _rtl92ee_read_txpower_info_from_hwpg()
2036 _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g, _rtl92ee_read_txpower_info_from_hwpg()
2108 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw) _rtl92ee_read_adapter_info() argument
2110 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_read_adapter_info()
2111 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92ee_read_adapter_info()
2112 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_read_adapter_info()
2118 rtl_efuse_shadow_map_update(hw); _rtl92ee_read_adapter_info()
2183 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, _rtl92ee_read_adapter_info()
2186 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag, _rtl92ee_read_adapter_info()
2223 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw) _rtl92ee_hal_customized_behavior() argument
2225 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ee_hal_customized_behavior()
2226 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92ee_hal_customized_behavior()
2227 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ee_hal_customized_behavior()
2235 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw) rtl92ee_read_eeprom_info() argument
2237 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_read_eeprom_info()
2238 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92ee_read_eeprom_info()
2240 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ee_read_eeprom_info()
2243 rtlhal->version = _rtl92ee_read_chip_version(hw); rtl92ee_read_eeprom_info()
2263 _rtl92ee_read_adapter_info(hw); rtl92ee_read_eeprom_info()
2267 _rtl92ee_hal_customized_behavior(hw); rtl92ee_read_eeprom_info()
2274 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index) _rtl92ee_mrate_idx_to_arfr_id() argument
2305 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw, rtl92ee_update_hal_rate_mask() argument
2309 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_update_hal_rate_mask()
2311 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_update_hal_rate_mask()
2417 ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index); rtl92ee_update_hal_rate_mask()
2436 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask); rtl92ee_update_hal_rate_mask()
2437 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl92ee_update_hal_rate_mask()
2440 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw, rtl92ee_update_hal_rate_tbl() argument
2443 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_update_hal_rate_tbl()
2446 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level); rtl92ee_update_hal_rate_tbl()
2449 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw) rtl92ee_update_channel_access_setting() argument
2451 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_update_channel_access_setting()
2452 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_update_channel_access_setting()
2455 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, rtl92ee_update_channel_access_setting()
2461 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); rtl92ee_update_channel_access_setting()
2464 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) rtl92ee_gpio_radio_on_off_checking() argument
2470 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index, rtl92ee_set_key() argument
2474 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_set_key()
2475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ee_set_key()
2476 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92ee_set_key()
2499 rtl_cam_mark_invalid(hw, cam_offset + idx); rtl92ee_set_key()
2500 rtl_cam_empty_entry(hw, cam_offset + idx); rtl92ee_set_key()
2540 entry_id = rtl_cam_get_free_entry(hw, rtl92ee_set_key()
2545 "Can not find free hw security cam entry\n"); rtl92ee_set_key()
2563 rtl_cam_del_entry(hw, p_macaddr); rtl92ee_set_key()
2564 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); rtl92ee_set_key()
2572 rtl_cam_add_one_entry(hw, macaddr, key_index, rtl92ee_set_key()
2581 rtl_cam_add_one_entry(hw, rtl92ee_set_key()
2589 rtl_cam_add_one_entry(hw, macaddr, key_index, rtl92ee_set_key()
2598 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, rtl92ee_read_bt_coexist_info_from_hwpg() argument
2601 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_read_bt_coexist_info_from_hwpg()
2620 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw) rtl92ee_bt_reg_init() argument
2622 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_bt_reg_init()
2632 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw) rtl92ee_bt_hw_init() argument
2634 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_bt_hw_init()
2640 void rtl92ee_suspend(struct ieee80211_hw *hw) rtl92ee_suspend() argument
2644 void rtl92ee_resume(struct ieee80211_hw *hw) rtl92ee_resume() argument
2649 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, rtl92ee_allow_all_destaddr() argument
2652 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ee_allow_all_destaddr()
2653 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92ee_allow_all_destaddr()
/linux-4.4.14/sound/pci/ctxfi/
H A Dctsrc.c40 struct hw *hw; src_set_state() local
42 hw = src->rsc.hw; src_set_state()
43 hw->src_set_state(src->rsc.ctrl_blk, state); src_set_state()
50 struct hw *hw; src_set_bm() local
52 hw = src->rsc.hw; src_set_bm()
53 hw->src_set_bm(src->rsc.ctrl_blk, bm); src_set_bm()
60 struct hw *hw; src_set_sf() local
62 hw = src->rsc.hw; src_set_sf()
63 hw->src_set_sf(src->rsc.ctrl_blk, sf); src_set_sf()
70 struct hw *hw; src_set_pm() local
72 hw = src->rsc.hw; src_set_pm()
73 hw->src_set_pm(src->rsc.ctrl_blk, pm); src_set_pm()
80 struct hw *hw; src_set_rom() local
82 hw = src->rsc.hw; src_set_rom()
83 hw->src_set_rom(src->rsc.ctrl_blk, rom); src_set_rom()
90 struct hw *hw; src_set_vo() local
92 hw = src->rsc.hw; src_set_vo()
93 hw->src_set_vo(src->rsc.ctrl_blk, vo); src_set_vo()
100 struct hw *hw; src_set_st() local
102 hw = src->rsc.hw; src_set_st()
103 hw->src_set_st(src->rsc.ctrl_blk, st); src_set_st()
110 struct hw *hw; src_set_bp() local
112 hw = src->rsc.hw; src_set_bp()
113 hw->src_set_bp(src->rsc.ctrl_blk, bp); src_set_bp()
120 struct hw *hw; src_set_cisz() local
122 hw = src->rsc.hw; src_set_cisz()
123 hw->src_set_cisz(src->rsc.ctrl_blk, cisz); src_set_cisz()
130 struct hw *hw; src_set_ca() local
132 hw = src->rsc.hw; src_set_ca()
133 hw->src_set_ca(src->rsc.ctrl_blk, ca); src_set_ca()
140 struct hw *hw; src_set_sa() local
142 hw = src->rsc.hw; src_set_sa()
143 hw->src_set_sa(src->rsc.ctrl_blk, sa); src_set_sa()
150 struct hw *hw; src_set_la() local
152 hw = src->rsc.hw; src_set_la()
153 hw->src_set_la(src->rsc.ctrl_blk, la); src_set_la()
160 struct hw *hw; src_set_pitch() local
162 hw = src->rsc.hw; src_set_pitch()
163 hw->src_set_pitch(src->rsc.ctrl_blk, pitch); src_set_pitch()
170 struct hw *hw; src_set_clear_zbufs() local
172 hw = src->rsc.hw; src_set_clear_zbufs()
173 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); src_set_clear_zbufs()
180 struct hw *hw; src_commit_write() local
184 hw = src->rsc.hw; src_commit_write()
188 dirty = hw->src_get_dirty(src->rsc.ctrl_blk) & conj_mask; src_commit_write()
190 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src_commit_write()
199 hw->src_set_dirty(src->rsc.ctrl_blk, dirty); src_commit_write()
200 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src_commit_write()
210 struct hw *hw; src_get_ca() local
212 hw = src->rsc.hw; src_get_ca()
213 return hw->src_get_ca(hw, src->rsc.ops->index(&src->rsc), src_get_ca()
231 struct hw *hw = src->rsc.hw; src_default_config_memrd() local
234 hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF); src_default_config_memrd()
235 hw->src_set_bm(src->rsc.ctrl_blk, 1); src_default_config_memrd()
239 hw->src_set_rsr(src->rsc.ctrl_blk, rsr); src_default_config_memrd()
240 hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_S16); src_default_config_memrd()
241 hw->src_set_wr(src->rsc.ctrl_blk, 0); src_default_config_memrd()
242 hw->src_set_pm(src->rsc.ctrl_blk, 0); src_default_config_memrd()
243 hw->src_set_rom(src->rsc.ctrl_blk, 0); src_default_config_memrd()
244 hw->src_set_vo(src->rsc.ctrl_blk, 0); src_default_config_memrd()
245 hw->src_set_st(src->rsc.ctrl_blk, 0); src_default_config_memrd()
246 hw->src_set_ilsz(src->rsc.ctrl_blk, src->multi - 1); src_default_config_memrd()
247 hw->src_set_cisz(src->rsc.ctrl_blk, 0x80); src_default_config_memrd()
248 hw->src_set_sa(src->rsc.ctrl_blk, 0x0); src_default_config_memrd()
249 hw->src_set_la(src->rsc.ctrl_blk, 0x1000); src_default_config_memrd()
250 hw->src_set_ca(src->rsc.ctrl_blk, 0x80); src_default_config_memrd()
251 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); src_default_config_memrd()
252 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); src_default_config_memrd()
255 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src_default_config_memrd()
260 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); src_default_config_memrd()
261 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src_default_config_memrd()
271 struct hw *hw = src->rsc.hw; src_default_config_memwr() local
273 hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF); src_default_config_memwr()
274 hw->src_set_bm(src->rsc.ctrl_blk, 1); src_default_config_memwr()
275 hw->src_set_rsr(src->rsc.ctrl_blk, 0); src_default_config_memwr()
276 hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_S16); src_default_config_memwr()
277 hw->src_set_wr(src->rsc.ctrl_blk, 1); src_default_config_memwr()
278 hw->src_set_pm(src->rsc.ctrl_blk, 0); src_default_config_memwr()
279 hw->src_set_rom(src->rsc.ctrl_blk, 0); src_default_config_memwr()
280 hw->src_set_vo(src->rsc.ctrl_blk, 0); src_default_config_memwr()
281 hw->src_set_st(src->rsc.ctrl_blk, 0); src_default_config_memwr()
282 hw->src_set_ilsz(src->rsc.ctrl_blk, 0); src_default_config_memwr()
283 hw->src_set_cisz(src->rsc.ctrl_blk, 0x80); src_default_config_memwr()
284 hw->src_set_sa(src->rsc.ctrl_blk, 0x0); src_default_config_memwr()
285 hw->src_set_la(src->rsc.ctrl_blk, 0x1000); src_default_config_memwr()
286 hw->src_set_ca(src->rsc.ctrl_blk, 0x80); src_default_config_memwr()
287 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); src_default_config_memwr()
288 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); src_default_config_memwr()
291 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src_default_config_memwr()
299 struct hw *hw = src->rsc.hw; src_default_config_arcrw() local
303 hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF); src_default_config_arcrw()
304 hw->src_set_bm(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
308 hw->src_set_rsr(src->rsc.ctrl_blk, rsr); src_default_config_arcrw()
309 hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_F32); src_default_config_arcrw()
310 hw->src_set_wr(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
311 hw->src_set_pm(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
312 hw->src_set_rom(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
313 hw->src_set_vo(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
314 hw->src_set_st(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
315 hw->src_set_ilsz(src->rsc.ctrl_blk, 0); src_default_config_arcrw()
316 hw->src_set_cisz(src->rsc.ctrl_blk, 0x80); src_default_config_arcrw()
317 hw->src_set_sa(src->rsc.ctrl_blk, 0x0); src_default_config_arcrw()
318 /*hw->src_set_sa(src->rsc.ctrl_blk, 0x100);*/ src_default_config_arcrw()
319 hw->src_set_la(src->rsc.ctrl_blk, 0x1000); src_default_config_arcrw()
320 /*hw->src_set_la(src->rsc.ctrl_blk, 0x03ffffe0);*/ src_default_config_arcrw()
321 hw->src_set_ca(src->rsc.ctrl_blk, 0x80); src_default_config_arcrw()
322 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000); src_default_config_arcrw()
323 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1); src_default_config_arcrw()
325 dirty = hw->src_get_dirty(src->rsc.ctrl_blk); src_default_config_arcrw()
328 hw->src_set_dirty(src->rsc.ctrl_blk, dirty); src_default_config_arcrw()
329 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc), src_default_config_arcrw()
369 err = rsc_init(&p->rsc, idx + i, SRC, desc->msr, mgr->mgr.hw); src_rsc_init()
492 struct hw *hw = mgr->mgr.hw; src_enable_s() local
497 hw->src_mgr_enbs_src(mgr->mgr.ctrl_blk, src_enable_s()
508 struct hw *hw = mgr->mgr.hw; src_enable() local
513 hw->src_mgr_enb_src(mgr->mgr.ctrl_blk, src_enable()
524 struct hw *hw = mgr->mgr.hw; src_disable() local
529 hw->src_mgr_dsb_src(mgr->mgr.ctrl_blk, src_disable()
540 struct hw *hw = mgr->mgr.hw; src_mgr_commit_write() local
542 hw->src_mgr_commit_write(hw, mgr->mgr.ctrl_blk); src_mgr_commit_write()
547 int src_mgr_create(struct hw *hw, struct src_mgr **rsrc_mgr) src_mgr_create() argument
557 err = rsc_mgr_init(&src_mgr->mgr, SRC, SRC_RESOURCE_NUM, hw); src_mgr_create()
562 conj_mask = hw->src_dirty_conj_mask(); src_mgr_create()
570 src_mgr->card = hw->card; src_mgr_create()
574 hw->src_mgr_dsb_src(src_mgr->mgr.ctrl_blk, i); src_mgr_create()
576 hw->src_mgr_commit_write(hw, src_mgr->mgr.ctrl_blk); src_mgr_create()
677 SRCIMP, desc->msr, mgr->mgr.hw); srcimp_rsc_init()
786 struct hw *hw = mgr->hw; srcimp_map_op() local
788 hw->srcimp_mgr_set_imaparc(mgr->ctrl_blk, entry->slot); srcimp_map_op()
789 hw->srcimp_mgr_set_imapuser(mgr->ctrl_blk, entry->user); srcimp_map_op()
790 hw->srcimp_mgr_set_imapnxt(mgr->ctrl_blk, entry->next); srcimp_map_op()
791 hw->srcimp_mgr_set_imapaddr(mgr->ctrl_blk, entry->addr); srcimp_map_op()
792 hw->srcimp_mgr_commit_write(mgr->hw, mgr->ctrl_blk); srcimp_map_op()
831 int srcimp_mgr_create(struct hw *hw, struct srcimp_mgr **rsrcimp_mgr) srcimp_mgr_create() argument
842 err = rsc_mgr_init(&srcimp_mgr->mgr, SRCIMP, SRCIMP_RESOURCE_NUM, hw); srcimp_mgr_create()
863 srcimp_mgr->card = hw->card; srcimp_mgr_create()
H A Dcthardware.h72 struct hw { struct
73 int (*card_init)(struct hw *hw, struct card_conf *info);
74 int (*card_stop)(struct hw *hw);
75 int (*pll_init)(struct hw *hw, unsigned int rsr);
77 int (*suspend)(struct hw *hw);
78 int (*resume)(struct hw *hw, struct card_conf *info);
80 int (*is_adc_source_selected)(struct hw *hw, enum ADCSRC source);
81 int (*select_adc_source)(struct hw *hw, enum ADCSRC source);
82 struct capabilities (*capabilities)(struct hw *hw);
83 int (*output_switch_get)(struct hw *hw);
84 int (*output_switch_put)(struct hw *hw, int position);
85 int (*mic_source_switch_get)(struct hw *hw);
86 int (*mic_source_switch_put)(struct hw *hw, int position);
111 int (*src_commit_write)(struct hw *hw, unsigned int idx, void *blk);
112 int (*src_get_ca)(struct hw *hw, unsigned int idx, void *blk);
123 int (*src_mgr_commit_write)(struct hw *hw, void *blk);
132 int (*srcimp_mgr_commit_write)(struct hw *hw, void *blk);
147 int (*amixer_commit_write)(struct hw *hw, unsigned int idx, void *blk);
160 int (*dai_commit_write)(struct hw *hw, unsigned int idx, void *blk);
164 int (*dao_commit_write)(struct hw *hw, unsigned int idx, void *blk);
167 int (*daio_mgr_get_ctrl_blk)(struct hw *hw, void **rblk);
178 int (*daio_mgr_commit_write)(struct hw *hw, void *blk);
180 int (*set_timer_irq)(struct hw *hw, int enable);
181 int (*set_timer_tick)(struct hw *hw, unsigned int tick);
182 unsigned int (*get_wc)(struct hw *hw);
198 enum CTCARDS model, struct hw **rhw);
199 int destroy_hw_obj(struct hw *hw);
H A Dcthw20k2.c36 struct hw hw; member in struct:hw20k2
45 static u32 hw_read_20kx(struct hw *hw, u32 reg);
46 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
369 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) src_commit_write() argument
377 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0); src_commit_write()
380 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0); src_commit_write()
383 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0); src_commit_write()
393 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr); src_commit_write()
394 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3); src_commit_write()
395 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0); src_commit_write()
399 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa); src_commit_write()
403 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la); src_commit_write()
407 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca); src_commit_write()
412 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0); src_commit_write()
415 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr); src_commit_write()
419 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl); src_commit_write()
426 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) src_get_ca() argument
430 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100); src_get_ca()
468 static int src_mgr_commit_write(struct hw *hw, void *blk) src_mgr_commit_write() argument
476 ret = hw_read_20kx(hw, SRC_ENBSTAT); src_mgr_commit_write()
478 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa); src_mgr_commit_write()
483 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]); src_mgr_commit_write()
567 static int srcimp_mgr_commit_write(struct hw *hw, void *blk) srcimp_mgr_commit_write() argument
572 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100, srcimp_mgr_commit_write()
675 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) amixer_commit_write() argument
680 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo); amixer_commit_write()
682 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi); amixer_commit_write()
878 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) dai_commit_write() argument
883 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt); dai_commit_write()
918 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) dao_commit_write() argument
925 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx, dao_commit_write()
1061 static int daio_mgr_commit_write(struct hw *hw, void *blk) daio_mgr_commit_write() argument
1070 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); daio_mgr_commit_write()
1076 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); daio_mgr_commit_write()
1082 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4, daio_mgr_commit_write()
1090 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) daio_mgr_get_ctrl_blk() argument
1101 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i)); daio_mgr_get_ctrl_blk()
1102 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i)); daio_mgr_get_ctrl_blk()
1118 static int set_timer_irq(struct hw *hw, int enable) set_timer_irq() argument
1120 hw_write_20kx(hw, GIE, enable ? IT_INT : 0); set_timer_irq()
1124 static int set_timer_tick(struct hw *hw, unsigned int ticks) set_timer_tick() argument
1128 hw_write_20kx(hw, TIMR, ticks); set_timer_tick()
1132 static unsigned int get_wc(struct hw *hw) get_wc() argument
1134 return hw_read_20kx(hw, WC); get_wc()
1156 static int hw_daio_init(struct hw *hw, const struct daio_conf *info) hw_daio_init() argument
1164 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101); hw_daio_init()
1165 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101); hw_daio_init()
1166 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); hw_daio_init()
1168 if (hw->model != CTSB1270) { hw_daio_init()
1169 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111); hw_daio_init()
1172 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111); hw_daio_init()
1183 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111); hw_daio_init()
1184 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); hw_daio_init()
1185 } else if ((4 == info->msr) && (hw->model == CTSB1270)) { hw_daio_init()
1186 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111); hw_daio_init()
1187 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); hw_daio_init()
1188 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); hw_daio_init()
1190 dev_alert(hw->card->dev, hw_daio_init()
1205 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); hw_daio_init()
1206 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); hw_daio_init()
1218 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i), hw_daio_init()
1221 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B); hw_daio_init()
1226 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data); hw_daio_init()
1234 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data); hw_daio_init()
1242 static int hw_trn_init(struct hw *hw, const struct trn_conf *info) hw_trn_init() argument
1250 dev_alert(hw->card->dev, hw_trn_init()
1262 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low); hw_trn_init()
1263 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high); hw_trn_init()
1266 hw_write_20kx(hw, VMEM_CTL, vmctl); hw_trn_init()
1268 hw_write_20kx(hw, TRANSPORT_CTL, 0x03); hw_trn_init()
1269 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01); hw_trn_init()
1271 data = hw_read_20kx(hw, TRANSPORT_ENB); hw_trn_init()
1272 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03)); hw_trn_init()
1311 static int hw_pll_init(struct hw *hw, unsigned int rsr) hw_pll_init() argument
1319 hw_write_20kx(hw, PLL_ENB, pllenb); hw_pll_init()
1324 hw_write_20kx(hw, PLL_CTL, pllctl); hw_pll_init()
1327 pllctl = hw_read_20kx(hw, PLL_CTL); hw_pll_init()
1329 hw_write_20kx(hw, PLL_CTL, pllctl); hw_pll_init()
1333 pllstat = hw_read_20kx(hw, PLL_STAT); hw_pll_init()
1356 dev_alert(hw->card->dev, hw_pll_init()
1364 static int hw_auto_init(struct hw *hw) hw_auto_init() argument
1369 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); hw_auto_init()
1371 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); hw_auto_init()
1373 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); hw_auto_init()
1376 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); hw_auto_init()
1381 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); hw_auto_init()
1449 static int hw20k2_i2c_unlock_full_access(struct hw *hw) hw20k2_i2c_unlock_full_access() argument
1454 hw_write_20kx(hw, I2C_IF_WLOCK, hw20k2_i2c_unlock_full_access()
1456 hw_write_20kx(hw, I2C_IF_WLOCK, hw20k2_i2c_unlock_full_access()
1459 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED) hw20k2_i2c_unlock_full_access()
1465 static int hw20k2_i2c_lock_chip(struct hw *hw) hw20k2_i2c_lock_chip() argument
1468 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); hw20k2_i2c_lock_chip()
1469 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); hw20k2_i2c_lock_chip()
1470 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED) hw20k2_i2c_lock_chip()
1476 static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size) hw20k2_i2c_init() argument
1478 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; hw20k2_i2c_init()
1483 err = hw20k2_i2c_unlock_full_access(hw); hw20k2_i2c_init()
1494 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr); hw20k2_i2c_init()
1496 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); hw20k2_i2c_init()
1500 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); hw20k2_i2c_init()
1505 static int hw20k2_i2c_uninit(struct hw *hw) hw20k2_i2c_uninit() argument
1513 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr); hw20k2_i2c_uninit()
1515 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); hw20k2_i2c_uninit()
1519 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); hw20k2_i2c_uninit()
1521 return hw20k2_i2c_lock_chip(hw); hw20k2_i2c_uninit()
1524 static int hw20k2_i2c_wait_data_ready(struct hw *hw) hw20k2_i2c_wait_data_ready() argument
1530 ret = hw_read_20kx(hw, I2C_IF_STATUS); hw20k2_i2c_wait_data_ready()
1536 static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap) hw20k2_i2c_read() argument
1538 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; hw20k2_i2c_read()
1541 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); hw20k2_i2c_read()
1544 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); hw20k2_i2c_read()
1545 if (!hw20k2_i2c_wait_data_ready(hw)) hw20k2_i2c_read()
1548 hw_write_20kx(hw, I2C_IF_WDATA, addr); hw20k2_i2c_read()
1549 if (!hw20k2_i2c_wait_data_ready(hw)) hw20k2_i2c_read()
1553 hw_write_20kx(hw, I2C_IF_RDATA, 0); hw20k2_i2c_read()
1554 if (!hw20k2_i2c_wait_data_ready(hw)) hw20k2_i2c_read()
1557 *datap = hw_read_20kx(hw, I2C_IF_RDATA); hw20k2_i2c_read()
1562 static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data) hw20k2_i2c_write() argument
1564 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; hw20k2_i2c_write()
1568 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); hw20k2_i2c_write()
1574 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); hw20k2_i2c_write()
1575 hw20k2_i2c_wait_data_ready(hw); hw20k2_i2c_write()
1577 hw_write_20kx(hw, I2C_IF_WDATA, 0); hw20k2_i2c_write()
1578 hw20k2_i2c_wait_data_ready(hw); hw20k2_i2c_write()
1581 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data); hw20k2_i2c_write()
1582 hw20k2_i2c_wait_data_ready(hw); hw20k2_i2c_write()
1587 static void hw_dac_stop(struct hw *hw) hw_dac_stop() argument
1590 data = hw_read_20kx(hw, GPIO_DATA); hw_dac_stop()
1592 hw_write_20kx(hw, GPIO_DATA, data); hw_dac_stop()
1596 static void hw_dac_start(struct hw *hw) hw_dac_start() argument
1599 data = hw_read_20kx(hw, GPIO_DATA); hw_dac_start()
1601 hw_write_20kx(hw, GPIO_DATA, data); hw_dac_start()
1605 static void hw_dac_reset(struct hw *hw) hw_dac_reset() argument
1607 hw_dac_stop(hw); hw_dac_reset()
1608 hw_dac_start(hw); hw_dac_reset()
1611 static int hw_dac_init(struct hw *hw, const struct dac_conf *info) hw_dac_init() argument
1637 if (hw->model == CTSB1270) { hw_dac_init()
1638 hw_dac_stop(hw); hw_dac_init()
1639 data = hw_read_20kx(hw, GPIO_DATA); hw_dac_init()
1647 hw_write_20kx(hw, GPIO_DATA, data); hw_dac_init()
1648 hw_dac_start(hw); hw_dac_init()
1653 data = hw_read_20kx(hw, GPIO_CTRL); hw_dac_init()
1655 hw_write_20kx(hw, GPIO_CTRL, data); hw_dac_init()
1657 err = hw20k2_i2c_init(hw, 0x18, 1, 1); hw_dac_init()
1664 hw_dac_reset(hw); hw_dac_init()
1665 hw_dac_reset(hw); hw_dac_init()
1667 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1)) hw_dac_init()
1670 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2)) hw_dac_init()
1673 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3)) hw_dac_init()
1676 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control)) hw_dac_init()
1679 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control)) hw_dac_init()
1682 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1)) hw_dac_init()
1685 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1)) hw_dac_init()
1688 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1)) hw_dac_init()
1691 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2)) hw_dac_init()
1694 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2)) hw_dac_init()
1697 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2)) hw_dac_init()
1700 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3)) hw_dac_init()
1703 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3)) hw_dac_init()
1706 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3)) hw_dac_init()
1709 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4)) hw_dac_init()
1712 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4)) hw_dac_init()
1715 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4)) hw_dac_init()
1729 hw20k2_i2c_write(hw, CS4382_MC1, 0x80); hw_dac_init()
1730 hw20k2_i2c_write(hw, CS4382_MC2, 0x10); hw_dac_init()
1732 hw20k2_i2c_write(hw, CS4382_XC1, 0x24); hw_dac_init()
1733 hw20k2_i2c_write(hw, CS4382_XC2, 0x24); hw_dac_init()
1734 hw20k2_i2c_write(hw, CS4382_XC3, 0x24); hw_dac_init()
1735 hw20k2_i2c_write(hw, CS4382_XC4, 0x24); hw_dac_init()
1737 hw20k2_i2c_write(hw, CS4382_XC1, 0x25); hw_dac_init()
1738 hw20k2_i2c_write(hw, CS4382_XC2, 0x25); hw_dac_init()
1739 hw20k2_i2c_write(hw, CS4382_XC3, 0x25); hw_dac_init()
1740 hw20k2_i2c_write(hw, CS4382_XC4, 0x25); hw_dac_init()
1742 hw20k2_i2c_write(hw, CS4382_XC1, 0x26); hw_dac_init()
1743 hw20k2_i2c_write(hw, CS4382_XC2, 0x26); hw_dac_init()
1744 hw20k2_i2c_write(hw, CS4382_XC3, 0x26); hw_dac_init()
1745 hw20k2_i2c_write(hw, CS4382_XC4, 0x26); hw_dac_init()
1751 hw20k2_i2c_uninit(hw); hw_dac_init()
1766 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) hw_is_adc_input_selected() argument
1769 if (hw->model == CTSB1270) { hw_is_adc_input_selected()
1774 data = hw_read_20kx(hw, GPIO_DATA); hw_is_adc_input_selected()
1791 static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db) hw_wm8775_input_select() argument
1800 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc), hw_wm8775_input_select()
1810 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain), hw_wm8775_input_select()
1813 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain), hw_wm8775_input_select()
1817 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) hw_adc_input_select() argument
1820 data = hw_read_20kx(hw, GPIO_DATA); hw_adc_input_select()
1824 hw_write_20kx(hw, GPIO_DATA, data); hw_adc_input_select()
1825 hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */ hw_adc_input_select()
1829 hw_write_20kx(hw, GPIO_DATA, data); hw_adc_input_select()
1830 hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */ hw_adc_input_select()
1839 static int hw_adc_init(struct hw *hw, const struct adc_conf *info) hw_adc_init() argument
1845 data = hw_read_20kx(hw, GPIO_CTRL); hw_adc_init()
1847 hw_write_20kx(hw, GPIO_CTRL, data); hw_adc_init()
1850 err = hw20k2_i2c_init(hw, 0x1A, 1, 1); hw_adc_init()
1852 dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n"); hw_adc_init()
1857 data = hw_read_20kx(hw, GPIO_DATA); hw_adc_init()
1859 hw_write_20kx(hw, GPIO_DATA, data); hw_adc_init()
1861 if (hw->model == CTSB1270) { hw_adc_init()
1870 hw_write_20kx(hw, GPIO_DATA, data); hw_adc_init()
1876 hw_write_20kx(hw, GPIO_DATA, data); hw_adc_init()
1882 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26), hw_adc_init()
1888 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02), hw_adc_init()
1892 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), hw_adc_init()
1895 dev_alert(hw->card->dev, hw_adc_init()
1902 if (hw->model != CTSB1270) { hw_adc_init()
1904 ctl = hw_read_20kx(hw, GPIO_CTRL); hw_adc_init()
1906 hw_write_20kx(hw, GPIO_CTRL, ctl); hw_adc_init()
1907 hw_adc_input_select(hw, ADC_LINEIN); hw_adc_init()
1909 hw_wm8775_input_select(hw, 0, 0); hw_adc_init()
1914 hw20k2_i2c_uninit(hw); hw_adc_init()
1918 static struct capabilities hw_capabilities(struct hw *hw) hw_capabilities() argument
1923 cap.dedicated_mic = hw->model == CTSB1270; hw_capabilities()
1924 cap.output_switch = hw->model == CTSB1270; hw_capabilities()
1925 cap.mic_source_switch = hw->model == CTSB1270; hw_capabilities()
1930 static int hw_output_switch_get(struct hw *hw) hw_output_switch_get() argument
1932 u32 data = hw_read_20kx(hw, GPIO_EXT_DATA); hw_output_switch_get()
1946 static int hw_output_switch_put(struct hw *hw, int position) hw_output_switch_put() argument
1950 if (position == hw_output_switch_get(hw)) hw_output_switch_put()
1954 data = hw_read_20kx(hw, GPIO_DATA); hw_output_switch_put()
1956 hw_write_20kx(hw, GPIO_DATA, data); hw_output_switch_put()
1958 data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30; hw_output_switch_put()
1968 hw_write_20kx(hw, GPIO_EXT_DATA, data); hw_output_switch_put()
1971 data = hw_read_20kx(hw, GPIO_DATA); hw_output_switch_put()
1973 hw_write_20kx(hw, GPIO_DATA, data); hw_output_switch_put()
1978 static int hw_mic_source_switch_get(struct hw *hw) hw_mic_source_switch_get() argument
1980 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; hw_mic_source_switch_get()
1985 static int hw_mic_source_switch_put(struct hw *hw, int position) hw_mic_source_switch_put() argument
1987 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; hw_mic_source_switch_put()
1994 hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */ hw_mic_source_switch_put()
1997 hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */ hw_mic_source_switch_put()
2000 hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */ hw_mic_source_switch_put()
2013 struct hw *hw = dev_id; ct_20k2_interrupt() local
2016 status = hw_read_20kx(hw, GIP); ct_20k2_interrupt()
2020 if (hw->irq_callback) ct_20k2_interrupt()
2021 hw->irq_callback(hw->irq_callback_data, status); ct_20k2_interrupt()
2023 hw_write_20kx(hw, GIP, status); ct_20k2_interrupt()
2027 static int hw_card_start(struct hw *hw) hw_card_start() argument
2030 struct pci_dev *pci = hw->pci; hw_card_start()
2040 dev_err(hw->card->dev, hw_card_start()
2047 if (!hw->io_base) { hw_card_start()
2052 hw->io_base = pci_resource_start(hw->pci, 2); hw_card_start()
2053 hw->mem_base = ioremap(hw->io_base, hw_card_start()
2054 pci_resource_len(hw->pci, 2)); hw_card_start()
2055 if (!hw->mem_base) { hw_card_start()
2062 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); hw_card_start()
2064 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); hw_card_start()
2066 if (hw->irq < 0) { hw_card_start()
2068 KBUILD_MODNAME, hw); hw_card_start()
2070 dev_err(hw->card->dev, hw_card_start()
2074 hw->irq = pci->irq; hw_card_start()
2082 iounmap((void *)hw->mem_base); hw_card_start()
2083 hw->mem_base = (unsigned long)NULL;*/ hw_card_start()
2086 hw->io_base = 0; hw_card_start()
2092 static int hw_card_stop(struct hw *hw) hw_card_stop() argument
2097 hw_write_20kx(hw, TRANSPORT_CTL, 0x00); hw_card_stop()
2100 data = hw_read_20kx(hw, PLL_ENB); hw_card_stop()
2101 hw_write_20kx(hw, PLL_ENB, (data & (~0x07))); hw_card_stop()
2107 static int hw_card_shutdown(struct hw *hw) hw_card_shutdown() argument
2109 if (hw->irq >= 0) hw_card_shutdown()
2110 free_irq(hw->irq, hw); hw_card_shutdown()
2112 hw->irq = -1; hw_card_shutdown()
2113 iounmap(hw->mem_base); hw_card_shutdown()
2114 hw->mem_base = NULL; hw_card_shutdown()
2116 if (hw->io_base) hw_card_shutdown()
2117 pci_release_regions(hw->pci); hw_card_shutdown()
2119 hw->io_base = 0; hw_card_shutdown()
2121 pci_disable_device(hw->pci); hw_card_shutdown()
2126 static int hw_card_init(struct hw *hw, struct card_conf *info) hw_card_init() argument
2138 err = hw_card_start(hw); hw_card_init()
2143 err = hw_pll_init(hw, info->rsr); hw_card_init()
2148 err = hw_auto_init(hw); hw_card_init()
2152 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); hw_card_init()
2157 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); hw_card_init()
2160 hw_write_20kx(hw, GIE, 0); hw_card_init()
2162 hw_write_20kx(hw, SRC_IP, 0); hw_card_init()
2164 if (hw->model != CTSB1270) { hw_card_init()
2167 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/ hw_card_init()
2169 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/ hw_card_init()
2170 hw_write_20kx(hw, GPIO_CTRL, 0xD802); hw_card_init()
2172 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F); hw_card_init()
2175 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01); hw_card_init()
2178 err = hw_trn_init(hw, &trn_info); hw_card_init()
2183 err = hw_daio_init(hw, &daio_info); hw_card_init()
2188 err = hw_dac_init(hw, &dac_info); hw_card_init()
2195 err = hw_adc_init(hw, &adc_info); hw_card_init()
2199 data = hw_read_20kx(hw, SRC_MCTL); hw_card_init()
2201 hw_write_20kx(hw, SRC_MCTL, data); hw_card_init()
2207 static int hw_suspend(struct hw *hw) hw_suspend() argument
2209 hw_card_stop(hw); hw_suspend()
2213 static int hw_resume(struct hw *hw, struct card_conf *info) hw_resume() argument
2216 return hw_card_init(hw, info); hw_resume()
2220 static u32 hw_read_20kx(struct hw *hw, u32 reg) hw_read_20kx() argument
2222 return readl(hw->mem_base + reg); hw_read_20kx()
2225 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) hw_write_20kx() argument
2227 writel(data, hw->mem_base + reg); hw_write_20kx()
2230 static struct hw ct20k2_preset = {
2338 int create_20k2_hw_obj(struct hw **rhw) create_20k2_hw_obj()
2347 hw20k2->hw = ct20k2_preset; create_20k2_hw_obj()
2348 *rhw = &hw20k2->hw; create_20k2_hw_obj()
2353 int destroy_20k2_hw_obj(struct hw *hw) destroy_20k2_hw_obj() argument
2355 if (hw->io_base) destroy_20k2_hw_obj()
2356 hw_card_shutdown(hw); destroy_20k2_hw_obj()
2358 kfree(hw); destroy_20k2_hw_obj()
H A Dcthw20k1.c37 struct hw hw; member in struct:hw20k1
42 static u32 hw_read_20kx(struct hw *hw, u32 reg);
43 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
44 static u32 hw_read_pci(struct hw *hw, u32 reg);
45 static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
369 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) src_commit_write() argument
377 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0); src_commit_write()
380 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0); src_commit_write()
383 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0); src_commit_write()
393 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr); src_commit_write()
394 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3); src_commit_write()
395 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0); src_commit_write()
399 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa); src_commit_write()
403 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la); src_commit_write()
407 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca); src_commit_write()
412 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0); src_commit_write()
415 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr); src_commit_write()
419 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl); src_commit_write()
426 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) src_get_ca() argument
430 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100); src_get_ca()
468 static int src_mgr_commit_write(struct hw *hw, void *blk) src_mgr_commit_write() argument
476 ret = hw_read_20kx(hw, SRCENBSTAT); src_mgr_commit_write()
478 hw_write_20kx(hw, SRCENBS, ctl->enbsa); src_mgr_commit_write()
483 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]); src_mgr_commit_write()
569 static int srcimp_mgr_commit_write(struct hw *hw, void *blk) srcimp_mgr_commit_write() argument
574 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100, srcimp_mgr_commit_write()
673 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) amixer_commit_write() argument
678 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo); amixer_commit_write()
680 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi); amixer_commit_write()
888 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) dai_commit_write() argument
895 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl); dai_commit_write()
898 hw_write_20kx(hw, SRTICTL, ctl->srtctl); dai_commit_write()
934 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) dao_commit_write() argument
941 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos); dao_commit_write()
1108 static int daio_mgr_commit_write(struct hw *hw, void *blk) daio_mgr_commit_write() argument
1121 hw_write_20kx(hw, I2SCTL, ctl->i2sctl); daio_mgr_commit_write()
1129 hw_write_20kx(hw, SPOCTL, ctl->spoctl); daio_mgr_commit_write()
1137 hw_write_20kx(hw, SPICTL, ctl->spictl); daio_mgr_commit_write()
1141 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4, daio_mgr_commit_write()
1149 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) daio_mgr_get_ctrl_blk() argument
1158 blk->i2sctl = hw_read_20kx(hw, I2SCTL); daio_mgr_get_ctrl_blk()
1159 blk->spoctl = hw_read_20kx(hw, SPOCTL); daio_mgr_get_ctrl_blk()
1160 blk->spictl = hw_read_20kx(hw, SPICTL); daio_mgr_get_ctrl_blk()
1175 static int set_timer_irq(struct hw *hw, int enable) set_timer_irq() argument
1177 hw_write_20kx(hw, GIE, enable ? IT_INT : 0); set_timer_irq()
1181 static int set_timer_tick(struct hw *hw, unsigned int ticks) set_timer_tick() argument
1185 hw_write_20kx(hw, TIMR, ticks); set_timer_tick()
1189 static unsigned int get_wc(struct hw *hw) get_wc() argument
1191 return hw_read_20kx(hw, WC); get_wc()
1213 static int hw_daio_init(struct hw *hw, const struct daio_conf *info) hw_daio_init() argument
1219 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/ hw_daio_init()
1228 hw_write_20kx(hw, SPOCTL, 0x0); hw_daio_init()
1249 hw_write_20kx(hw, I2SCTL, i2sorg); hw_daio_init()
1250 hw_write_20kx(hw, SPOCTL, spdorg); hw_daio_init()
1254 hw_write_20kx(hw, SPICTL, 0x0); hw_daio_init()
1257 hw_write_20kx(hw, SPICTL, spdorg); hw_daio_init()
1264 static int hw_trn_init(struct hw *hw, const struct trn_conf *info) hw_trn_init() argument
1271 dev_err(hw->card->dev, hw_trn_init()
1286 hw_write_20kx(hw, PTPALX, ptp_phys_low); hw_trn_init()
1287 hw_write_20kx(hw, PTPAHX, ptp_phys_high); hw_trn_init()
1288 hw_write_20kx(hw, TRNCTL, trnctl); hw_trn_init()
1289 hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */ hw_trn_init()
1317 static int hw_pll_init(struct hw *hw, unsigned int rsr) hw_pll_init() argument
1324 if (hw_read_20kx(hw, PLLCTL) == pllctl) hw_pll_init()
1327 hw_write_20kx(hw, PLLCTL, pllctl); hw_pll_init()
1331 dev_alert(hw->card->dev, "PLL initialization failed!!!\n"); hw_pll_init()
1338 static int hw_auto_init(struct hw *hw) hw_auto_init() argument
1343 gctl = hw_read_20kx(hw, GCTL); hw_auto_init()
1345 hw_write_20kx(hw, GCTL, gctl); hw_auto_init()
1347 hw_write_20kx(hw, GCTL, gctl); hw_auto_init()
1350 gctl = hw_read_20kx(hw, GCTL); hw_auto_init()
1355 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); hw_auto_init()
1362 static int i2c_unlock(struct hw *hw) i2c_unlock() argument
1364 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) i2c_unlock()
1367 hw_write_pci(hw, 0xcc, 0x8c); i2c_unlock()
1368 hw_write_pci(hw, 0xcc, 0x0e); i2c_unlock()
1369 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) i2c_unlock()
1372 hw_write_pci(hw, 0xcc, 0xee); i2c_unlock()
1373 hw_write_pci(hw, 0xcc, 0xaa); i2c_unlock()
1374 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) i2c_unlock()
1380 static void i2c_lock(struct hw *hw) i2c_lock() argument
1382 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) i2c_lock()
1383 hw_write_pci(hw, 0xcc, 0x00); i2c_lock()
1386 static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data) i2c_write() argument
1391 ret = hw_read_pci(hw, 0xEC); i2c_write()
1393 hw_write_pci(hw, 0xE0, device); i2c_write()
1394 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff)); i2c_write()
1399 static int hw_reset_dac(struct hw *hw) hw_reset_dac() argument
1405 if (i2c_unlock(hw)) hw_reset_dac()
1409 ret = hw_read_pci(hw, 0xEC); hw_reset_dac()
1411 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ hw_reset_dac()
1417 gpioorg = (u16)hw_read_20kx(hw, GPIO); hw_reset_dac()
1419 hw_write_20kx(hw, GPIO, gpioorg); hw_reset_dac()
1421 hw_write_20kx(hw, GPIO, gpioorg | 0x2); hw_reset_dac()
1424 i2c_write(hw, 0x00180080, 0x01, 0x80); hw_reset_dac()
1425 i2c_write(hw, 0x00180080, 0x02, 0x10); hw_reset_dac()
1427 i2c_lock(hw); hw_reset_dac()
1432 static int hw_dac_init(struct hw *hw, const struct dac_conf *info) hw_dac_init() argument
1438 if (hw->model == CTSB055X) { hw_dac_init()
1440 gpioorg = (u16)hw_read_20kx(hw, GPIO); hw_dac_init()
1443 hw_write_20kx(hw, GPIO, gpioorg); hw_dac_init()
1448 gpioorg = (u16)hw_read_20kx(hw, GPIO); hw_dac_init()
1450 hw_write_20kx(hw, GPIO, gpioorg); hw_dac_init()
1452 hw_reset_dac(hw); hw_dac_init()
1454 if (i2c_unlock(hw)) hw_dac_init()
1457 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ hw_dac_init()
1459 ret = hw_read_pci(hw, 0xEC); hw_dac_init()
1477 i2c_write(hw, 0x00180080, 0x06, data); hw_dac_init()
1478 i2c_write(hw, 0x00180080, 0x09, data); hw_dac_init()
1479 i2c_write(hw, 0x00180080, 0x0c, data); hw_dac_init()
1480 i2c_write(hw, 0x00180080, 0x0f, data); hw_dac_init()
1482 i2c_lock(hw); hw_dac_init()
1485 gpioorg = (u16)hw_read_20kx(hw, GPIO); hw_dac_init()
1487 hw_write_20kx(hw, GPIO, gpioorg); hw_dac_init()
1494 static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type) is_adc_input_selected_SB055x() argument
1499 static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type) is_adc_input_selected_SBx() argument
1503 data = hw_read_20kx(hw, GPIO); is_adc_input_selected_SBx()
1520 static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type) is_adc_input_selected_hendrix() argument
1524 data = hw_read_20kx(hw, GPIO); is_adc_input_selected_hendrix()
1538 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) hw_is_adc_input_selected() argument
1540 switch (hw->model) { hw_is_adc_input_selected()
1542 return is_adc_input_selected_SB055x(hw, type); hw_is_adc_input_selected()
1544 return is_adc_input_selected_hendrix(hw, type); hw_is_adc_input_selected()
1546 return is_adc_input_selected_hendrix(hw, type); hw_is_adc_input_selected()
1548 return is_adc_input_selected_SBx(hw, type); hw_is_adc_input_selected()
1553 adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost) adc_input_select_SB055x() argument
1566 data = hw_read_20kx(hw, GPIO); adc_input_select_SB055x()
1586 hw_write_20kx(hw, GPIO, data); adc_input_select_SB055x()
1593 adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost) adc_input_select_SBx() argument
1599 if (i2c_unlock(hw)) adc_input_select_SBx()
1603 ret = hw_read_pci(hw, 0xEC); adc_input_select_SBx()
1606 hw_write_pci(hw, 0xEC, 0x05); adc_input_select_SBx()
1608 data = hw_read_20kx(hw, GPIO); adc_input_select_SBx()
1624 i2c_lock(hw); adc_input_select_SBx()
1627 hw_write_20kx(hw, GPIO, data); adc_input_select_SBx()
1628 i2c_write(hw, 0x001a0080, 0x2a, i2c_data); adc_input_select_SBx()
1630 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ adc_input_select_SBx()
1631 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ adc_input_select_SBx()
1633 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ adc_input_select_SBx()
1634 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ adc_input_select_SBx()
1637 i2c_lock(hw); adc_input_select_SBx()
1643 adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost) adc_input_select_hendrix() argument
1649 if (i2c_unlock(hw)) adc_input_select_hendrix()
1653 ret = hw_read_pci(hw, 0xEC); adc_input_select_hendrix()
1656 hw_write_pci(hw, 0xEC, 0x05); adc_input_select_hendrix()
1658 data = hw_read_20kx(hw, GPIO); adc_input_select_hendrix()
1669 i2c_lock(hw); adc_input_select_hendrix()
1672 hw_write_20kx(hw, GPIO, data); adc_input_select_hendrix()
1673 i2c_write(hw, 0x001a0080, 0x2a, i2c_data); adc_input_select_hendrix()
1675 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ adc_input_select_hendrix()
1676 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ adc_input_select_hendrix()
1678 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ adc_input_select_hendrix()
1679 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ adc_input_select_hendrix()
1682 i2c_lock(hw); adc_input_select_hendrix()
1687 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) hw_adc_input_select() argument
1691 switch (hw->model) { hw_adc_input_select()
1693 return adc_input_select_SB055x(hw, type, state); hw_adc_input_select()
1695 return adc_input_select_hendrix(hw, type, state); hw_adc_input_select()
1697 return adc_input_select_hendrix(hw, type, state); hw_adc_input_select()
1699 return adc_input_select_SBx(hw, type, state); hw_adc_input_select()
1703 static int adc_init_SB055x(struct hw *hw, int input, int mic20db) adc_init_SB055x() argument
1705 return adc_input_select_SB055x(hw, input, mic20db); adc_init_SB055x()
1708 static int adc_init_SBx(struct hw *hw, int input, int mic20db) adc_init_SBx() argument
1739 if (i2c_unlock(hw)) adc_init_SBx()
1743 ret = hw_read_pci(hw, 0xEC); adc_init_SBx()
1745 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ adc_init_SBx()
1747 i2c_write(hw, 0x001a0080, 0x0e, 0x08); adc_init_SBx()
1748 i2c_write(hw, 0x001a0080, 0x18, 0x0a); adc_init_SBx()
1749 i2c_write(hw, 0x001a0080, 0x28, 0x86); adc_init_SBx()
1750 i2c_write(hw, 0x001a0080, 0x2a, adcdata); adc_init_SBx()
1753 i2c_write(hw, 0x001a0080, 0x1c, 0xf7); adc_init_SBx()
1754 i2c_write(hw, 0x001a0080, 0x1e, 0xf7); adc_init_SBx()
1756 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); adc_init_SBx()
1757 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); adc_init_SBx()
1760 if (!(hw_read_20kx(hw, ID0) & 0x100)) adc_init_SBx()
1761 i2c_write(hw, 0x001a0080, 0x16, 0x26); adc_init_SBx()
1763 i2c_lock(hw); adc_init_SBx()
1765 gpioorg = (u16)hw_read_20kx(hw, GPIO); adc_init_SBx()
1768 hw_write_20kx(hw, GPIO, gpioorg); adc_init_SBx()
1773 static int hw_adc_init(struct hw *hw, const struct adc_conf *info) hw_adc_init() argument
1775 if (hw->model == CTSB055X) hw_adc_init()
1776 return adc_init_SB055x(hw, info->input, info->mic20db); hw_adc_init()
1778 return adc_init_SBx(hw, info->input, info->mic20db); hw_adc_init()
1781 static struct capabilities hw_capabilities(struct hw *hw) hw_capabilities() argument
1786 cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA); hw_capabilities()
1889 struct hw *hw = dev_id; ct_20k1_interrupt() local
1892 status = hw_read_20kx(hw, GIP); ct_20k1_interrupt()
1896 if (hw->irq_callback) ct_20k1_interrupt()
1897 hw->irq_callback(hw->irq_callback_data, status); ct_20k1_interrupt()
1899 hw_write_20kx(hw, GIP, status); ct_20k1_interrupt()
1903 static int hw_card_start(struct hw *hw) hw_card_start() argument
1906 struct pci_dev *pci = hw->pci; hw_card_start()
1915 dev_err(hw->card->dev, hw_card_start()
1922 if (!hw->io_base) { hw_card_start()
1927 if (hw->model == CTUAA) hw_card_start()
1928 hw->io_base = pci_resource_start(pci, 5); hw_card_start()
1930 hw->io_base = pci_resource_start(pci, 0); hw_card_start()
1935 if (hw->model == CTUAA) { hw_card_start()
1942 if (hw->irq < 0) { hw_card_start()
1944 KBUILD_MODNAME, hw); hw_card_start()
1946 dev_err(hw->card->dev, hw_card_start()
1950 hw->irq = pci->irq; hw_card_start()
1959 hw->io_base = 0; hw_card_start()
1965 static int hw_card_stop(struct hw *hw) hw_card_stop() argument
1970 hw_write_20kx(hw, TRNCTL, 0x00); hw_card_stop()
1973 data = hw_read_20kx(hw, PLLCTL); hw_card_stop()
1974 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12)))); hw_card_stop()
1977 if (hw->irq >= 0) hw_card_stop()
1978 synchronize_irq(hw->irq); hw_card_stop()
1982 static int hw_card_shutdown(struct hw *hw) hw_card_shutdown() argument
1984 if (hw->irq >= 0) hw_card_shutdown()
1985 free_irq(hw->irq, hw); hw_card_shutdown()
1987 hw->irq = -1; hw_card_shutdown()
1988 iounmap(hw->mem_base); hw_card_shutdown()
1989 hw->mem_base = NULL; hw_card_shutdown()
1991 if (hw->io_base) hw_card_shutdown()
1992 pci_release_regions(hw->pci); hw_card_shutdown()
1994 hw->io_base = 0; hw_card_shutdown()
1996 pci_disable_device(hw->pci); hw_card_shutdown()
2001 static int hw_card_init(struct hw *hw, struct card_conf *info) hw_card_init() argument
2012 err = hw_card_start(hw); hw_card_init()
2017 err = hw_pll_init(hw, info->rsr); hw_card_init()
2022 err = hw_auto_init(hw); hw_card_init()
2027 gctl = hw_read_20kx(hw, GCTL); hw_card_init()
2033 hw_write_20kx(hw, GCTL, gctl); hw_card_init()
2037 hw_write_20kx(hw, GIE, 0); hw_card_init()
2039 hw_write_20kx(hw, SRCIP, 0); hw_card_init()
2043 switch (hw->model) { hw_card_init()
2045 hw_write_20kx(hw, GPIOCTL, 0x13fe); hw_card_init()
2048 hw_write_20kx(hw, GPIOCTL, 0x00e6); hw_card_init()
2051 hw_write_20kx(hw, GPIOCTL, 0x00c2); hw_card_init()
2054 hw_write_20kx(hw, GPIOCTL, 0x01e6); hw_card_init()
2059 err = hw_trn_init(hw, &trn_info); hw_card_init()
2064 err = hw_daio_init(hw, &daio_info); hw_card_init()
2069 err = hw_dac_init(hw, &dac_info); hw_card_init()
2076 err = hw_adc_init(hw, &adc_info); hw_card_init()
2080 data = hw_read_20kx(hw, SRCMCTL); hw_card_init()
2082 hw_write_20kx(hw, SRCMCTL, data); hw_card_init()
2088 static int hw_suspend(struct hw *hw) hw_suspend() argument
2090 struct pci_dev *pci = hw->pci; hw_suspend()
2092 hw_card_stop(hw); hw_suspend()
2094 if (hw->model == CTUAA) { hw_suspend()
2102 static int hw_resume(struct hw *hw, struct card_conf *info) hw_resume() argument
2105 return hw_card_init(hw, info); hw_resume()
2109 static u32 hw_read_20kx(struct hw *hw, u32 reg) hw_read_20kx() argument
2115 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); hw_read_20kx()
2116 outl(reg, hw->io_base + 0x0); hw_read_20kx()
2117 value = inl(hw->io_base + 0x4); hw_read_20kx()
2119 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); hw_read_20kx()
2124 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) hw_write_20kx() argument
2129 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); hw_write_20kx()
2130 outl(reg, hw->io_base + 0x0); hw_write_20kx()
2131 outl(data, hw->io_base + 0x4); hw_write_20kx()
2133 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); hw_write_20kx()
2137 static u32 hw_read_pci(struct hw *hw, u32 reg) hw_read_pci() argument
2143 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); hw_read_pci()
2144 outl(reg, hw->io_base + 0x10); hw_read_pci()
2145 value = inl(hw->io_base + 0x14); hw_read_pci()
2147 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); hw_read_pci()
2152 static void hw_write_pci(struct hw *hw, u32 reg, u32 data) hw_write_pci() argument
2157 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); hw_write_pci()
2158 outl(reg, hw->io_base + 0x10); hw_write_pci()
2159 outl(data, hw->io_base + 0x14); hw_write_pci()
2161 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); hw_write_pci()
2164 static struct hw ct20k1_preset = {
2268 int create_20k1_hw_obj(struct hw **rhw) create_20k1_hw_obj()
2280 hw20k1->hw = ct20k1_preset; create_20k1_hw_obj()
2282 *rhw = &hw20k1->hw; create_20k1_hw_obj()
2287 int destroy_20k1_hw_obj(struct hw *hw) destroy_20k1_hw_obj() argument
2289 if (hw->io_base) destroy_20k1_hw_obj()
2290 hw_card_shutdown(hw); destroy_20k1_hw_obj()
2292 kfree(container_of(hw, struct hw20k1, hw)); destroy_20k1_hw_obj()
H A Dctamixer.c61 struct hw *hw; amixer_set_input() local
63 hw = amixer->rsc.hw; amixer_set_input()
64 hw->amixer_set_mode(amixer->rsc.ctrl_blk, AMIXER_Y_IMMEDIATE); amixer_set_input()
67 hw->amixer_set_x(amixer->rsc.ctrl_blk, BLANK_SLOT); amixer_set_input()
69 hw->amixer_set_x(amixer->rsc.ctrl_blk, amixer_set_input()
78 struct hw *hw; amixer_set_y() local
80 hw = amixer->rsc.hw; amixer_set_y()
81 hw->amixer_set_y(amixer->rsc.ctrl_blk, y); amixer_set_y()
88 struct hw *hw; amixer_set_invalid_squash() local
90 hw = amixer->rsc.hw; amixer_set_invalid_squash()
91 hw->amixer_set_iv(amixer->rsc.ctrl_blk, iv); amixer_set_invalid_squash()
98 struct hw *hw; amixer_set_sum() local
100 hw = amixer->rsc.hw; amixer_set_sum()
103 hw->amixer_set_se(amixer->rsc.ctrl_blk, 0); amixer_set_sum()
105 hw->amixer_set_se(amixer->rsc.ctrl_blk, 1); amixer_set_sum()
106 hw->amixer_set_sadr(amixer->rsc.ctrl_blk, amixer_set_sum()
115 struct hw *hw; amixer_commit_write() local
121 hw = amixer->rsc.hw; amixer_commit_write()
134 hw->amixer_set_dirty_all(amixer->rsc.ctrl_blk); amixer_commit_write()
136 hw->amixer_set_x(amixer->rsc.ctrl_blk, amixer_commit_write()
141 hw->amixer_set_sadr(amixer->rsc.ctrl_blk, amixer_commit_write()
146 hw->amixer_commit_write(hw, index, amixer->rsc.ctrl_blk); amixer_commit_write()
161 struct hw *hw; amixer_commit_raw_write() local
164 hw = amixer->rsc.hw; amixer_commit_raw_write()
166 hw->amixer_commit_write(hw, index, amixer->rsc.ctrl_blk); amixer_commit_raw_write()
173 struct hw *hw; amixer_get_y() local
175 hw = amixer->rsc.hw; amixer_get_y()
176 return hw->amixer_get_y(amixer->rsc.ctrl_blk); amixer_get_y()
207 AMIXER, desc->msr, mgr->mgr.hw); amixer_rsc_init()
300 int amixer_mgr_create(struct hw *hw, struct amixer_mgr **ramixer_mgr) amixer_mgr_create() argument
310 err = rsc_mgr_init(&amixer_mgr->mgr, AMIXER, AMIXER_RESOURCE_NUM, hw); amixer_mgr_create()
318 amixer_mgr->card = hw->card; amixer_mgr_create()
373 err = rsc_init(&sum->rsc, sum->idx[0], SUM, desc->msr, mgr->mgr.hw); sum_rsc_init()
455 int sum_mgr_create(struct hw *hw, struct sum_mgr **rsum_mgr) sum_mgr_create() argument
465 err = rsc_mgr_init(&sum_mgr->mgr, SUM, SUM_RESOURCE_NUM, hw); sum_mgr_create()
473 sum_mgr->card = hw->card; sum_mgr_create()
H A Dcthw20k1.h23 int create_20k1_hw_obj(struct hw **rhw);
24 int destroy_20k1_hw_obj(struct hw *hw);
/linux-4.4.14/sound/isa/sb/
H A Demu8000_synth.c40 struct snd_emu8000 *hw; snd_emu8000_probe() local
43 hw = *(struct snd_emu8000**)SNDRV_SEQ_DEVICE_ARGPTR(dev); snd_emu8000_probe()
44 if (hw == NULL) snd_emu8000_probe()
47 if (hw->emu) snd_emu8000_probe()
53 hw->emu = emu; snd_emu8000_probe()
54 snd_emu8000_ops_setup(hw); snd_emu8000_probe()
56 emu->hw = hw; snd_emu8000_probe()
58 emu->num_ports = hw->seq_ports; snd_emu8000_probe()
60 if (hw->memhdr) { snd_emu8000_probe()
62 snd_util_memhdr_free(hw->memhdr); snd_emu8000_probe()
64 hw->memhdr = snd_util_memhdr_new(hw->mem_size); snd_emu8000_probe()
65 if (hw->memhdr == NULL) { snd_emu8000_probe()
67 hw->emu = NULL; snd_emu8000_probe()
71 emu->memhdr = hw->memhdr; snd_emu8000_probe()
72 emu->midi_ports = hw->seq_ports < 2 ? hw->seq_ports : 2; /* number of virmidi ports */ snd_emu8000_probe()
77 if (snd_emux_register(emu, dev->card, hw->index, "Emu8000") < 0) { snd_emu8000_probe()
79 snd_util_memhdr_free(hw->memhdr); snd_emu8000_probe()
80 hw->emu = NULL; snd_emu8000_probe()
81 hw->memhdr = NULL; snd_emu8000_probe()
85 if (hw->mem_size > 0) snd_emu8000_probe()
86 snd_emu8000_pcm_new(dev->card, hw, 1); snd_emu8000_probe()
88 dev->driver_data = hw; snd_emu8000_probe()
100 struct snd_emu8000 *hw; snd_emu8000_remove() local
105 hw = dev->driver_data; snd_emu8000_remove()
106 if (hw->pcm) snd_emu8000_remove()
107 snd_device_free(dev->card, hw->pcm); snd_emu8000_remove()
108 snd_emux_free(hw->emu); snd_emu8000_remove()
109 snd_util_memhdr_free(hw->memhdr); snd_emu8000_remove()
110 hw->emu = NULL; snd_emu8000_remove()
111 hw->memhdr = NULL; snd_emu8000_remove()
H A Demu8000_callback.c45 static void set_pitch(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
46 static void set_volume(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
47 static void set_pan(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
48 static void set_fmmod(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
49 static void set_tremfreq(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
50 static void set_fm2frq2(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
51 static void set_filterQ(struct snd_emu8000 *hw, struct snd_emux_voice *vp);
85 snd_emu8000_ops_setup(struct snd_emu8000 *hw) snd_emu8000_ops_setup() argument
87 hw->emu->ops = emu8000_ops; snd_emu8000_ops_setup()
99 struct snd_emu8000 *hw; release_voice() local
101 hw = vp->hw; release_voice()
103 EMU8000_DCYSUS_WRITE(hw, vp->ch, dcysusv); release_voice()
105 EMU8000_DCYSUSV_WRITE(hw, vp->ch, dcysusv); release_voice()
114 struct snd_emu8000 *hw; terminate_voice() local
116 hw = vp->hw; terminate_voice()
117 EMU8000_DCYSUSV_WRITE(hw, vp->ch, 0x807F); terminate_voice()
126 struct snd_emu8000 *hw; update_voice() local
128 hw = vp->hw; update_voice()
130 set_volume(hw, vp); update_voice()
132 set_pitch(hw, vp); update_voice()
135 set_pan(hw, vp); update_voice()
137 set_fmmod(hw, vp); update_voice()
139 set_tremfreq(hw, vp); update_voice()
141 set_fm2frq2(hw, vp); update_voice()
143 set_filterQ(hw, vp); update_voice()
161 struct snd_emu8000 *hw; get_voice() local
175 hw = emu->hw; get_voice()
196 val = (EMU8000_CVCF_READ(hw, vp->ch) >> 16) & 0xffff; get_voice()
208 val = EMU8000_CCCA_READ(hw, vp->ch) & 0xffffff; get_voice()
240 struct snd_emu8000 *hw; start_voice() local
242 hw = vp->hw; start_voice()
247 EMU8000_DCYSUSV_WRITE(hw, ch, 0x0080); start_voice()
248 EMU8000_VTFT_WRITE(hw, ch, 0x0000FFFF); start_voice()
249 EMU8000_CVCF_WRITE(hw, ch, 0x0000FFFF); start_voice()
250 EMU8000_PTRX_WRITE(hw, ch, 0); start_voice()
251 EMU8000_CPF_WRITE(hw, ch, 0); start_voice()
254 set_pitch(hw, vp); start_voice()
257 EMU8000_ENVVAL_WRITE(hw, ch, vp->reg.parm.moddelay); start_voice()
258 EMU8000_ATKHLD_WRITE(hw, ch, vp->reg.parm.modatkhld); start_voice()
259 EMU8000_DCYSUS_WRITE(hw, ch, vp->reg.parm.moddcysus); start_voice()
260 EMU8000_ENVVOL_WRITE(hw, ch, vp->reg.parm.voldelay); start_voice()
261 EMU8000_ATKHLDV_WRITE(hw, ch, vp->reg.parm.volatkhld); start_voice()
266 set_volume(hw, vp); start_voice()
269 EMU8000_PEFE_WRITE(hw, ch, vp->reg.parm.pefe); start_voice()
272 EMU8000_LFO1VAL_WRITE(hw, ch, vp->reg.parm.lfo1delay); start_voice()
273 EMU8000_LFO2VAL_WRITE(hw, ch, vp->reg.parm.lfo2delay); start_voice()
276 set_fmmod(hw, vp); start_voice()
278 set_tremfreq(hw, vp); start_voice()
280 set_fm2frq2(hw, vp); start_voice()
282 set_pan(hw, vp); start_voice()
290 EMU8000_CSL_WRITE(hw, ch, temp); start_voice()
296 EMU8000_CCCA_WRITE(hw, ch, temp); start_voice()
299 EMU8000_00A0_WRITE(hw, ch, 0); start_voice()
300 EMU8000_0080_WRITE(hw, ch, 0); start_voice()
304 EMU8000_VTFT_WRITE(hw, ch, temp | vp->ftarget); start_voice()
305 EMU8000_CVCF_WRITE(hw, ch, temp | 0xff00); start_voice()
318 struct snd_emu8000 *hw; trigger_voice() local
320 hw = vp->hw; trigger_voice()
327 EMU8000_PTRX_WRITE(hw, ch, temp); trigger_voice()
328 EMU8000_CPF_WRITE(hw, ch, vp->ptarget << 16); trigger_voice()
329 EMU8000_DCYSUSV_WRITE(hw, ch, vp->reg.parm.voldcysus); trigger_voice()
338 struct snd_emu8000 *hw; reset_voice() local
340 hw = emu->hw; reset_voice()
341 EMU8000_DCYSUSV_WRITE(hw, ch, 0x807F); reset_voice()
342 snd_emu8000_tweak_voice(hw, ch); reset_voice()
349 set_pitch(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_pitch() argument
351 EMU8000_IP_WRITE(hw, vp->ch, vp->apitch); set_pitch()
358 set_volume(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_volume() argument
365 EMU8000_IFATN_WRITE(hw, vp->ch, ifatn); set_volume()
372 set_pan(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_pan() argument
377 EMU8000_PSST_WRITE(hw, vp->ch, temp); set_pan()
383 set_fmmod(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_fmmod() argument
396 EMU8000_FMMOD_WRITE(hw, vp->ch, fmmod); set_fmmod()
401 set_tremfreq(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_tremfreq() argument
403 EMU8000_TREMFRQ_WRITE(hw, vp->ch, vp->reg.parm.tremfrq); set_tremfreq()
408 set_fm2frq2(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_fm2frq2() argument
421 EMU8000_FM2FRQ2_WRITE(hw, vp->ch, fm2frq2); set_fm2frq2()
426 set_filterQ(struct snd_emu8000 *hw, struct snd_emux_voice *vp) set_filterQ() argument
429 addr = EMU8000_CCCA_READ(hw, vp->ch) & 0xffffff; set_filterQ()
431 EMU8000_CCCA_WRITE(hw, vp->ch, addr); set_filterQ()
462 struct snd_emu8000 *hw; sysex() local
464 hw = emu->hw; sysex()
468 hw->chorus_mode = chset->gs_chorus_mode; sysex()
469 snd_emu8000_update_chorus_mode(hw); sysex()
473 hw->reverb_mode = chset->gs_reverb_mode; sysex()
474 snd_emu8000_update_reverb_mode(hw); sysex()
487 struct snd_emu8000 *hw; oss_ioctl() local
489 hw = emu->hw; oss_ioctl()
493 hw->reverb_mode = p1; oss_ioctl()
494 snd_emu8000_update_reverb_mode(hw); oss_ioctl()
498 hw->chorus_mode = p1; oss_ioctl()
499 snd_emu8000_update_chorus_mode(hw); oss_ioctl()
503 /* snd_emu8000_init(hw); */ /*ignored*/ oss_ioctl()
507 hw->bass_level = p1; oss_ioctl()
508 hw->treble_level = p2; oss_ioctl()
509 snd_emu8000_update_equalizer(hw); oss_ioctl()
532 struct snd_emu8000 *hw; load_fx() local
533 hw = emu->hw; load_fx()
541 return snd_emu8000_load_chorus_fx(hw, mode, buf, len); load_fx()
543 return snd_emu8000_load_reverb_fx(hw, mode, buf, len); load_fx()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dhw.h33 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw);
35 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
37 int rtl88ee_hw_init(struct ieee80211_hw *hw);
38 void rtl88ee_card_disable(struct ieee80211_hw *hw);
39 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw);
40 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw);
41 int rtl88ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
42 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
43 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci);
44 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw);
45 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw);
46 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
48 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
49 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
51 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw);
52 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
53 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw);
54 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
58 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
60 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw);
61 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw);
62 void rtl88ee_suspend(struct ieee80211_hw *hw);
63 void rtl88ee_resume(struct ieee80211_hw *hw);
H A Dphy.c36 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
38 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
42 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw);
43 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
46 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw,
48 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
53 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
57 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
60 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw);
61 static void rtl88e_phy_set_io(struct ieee80211_hw *hw);
63 u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl88e_phy_query_bb_reg() argument
65 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_query_bb_reg()
82 void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw, rtl88e_phy_set_bb_reg() argument
85 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_set_bb_reg()
105 u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw, rtl88e_phy_query_rf_reg() argument
108 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_query_rf_reg()
119 original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr); rtl88e_phy_query_rf_reg()
131 void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw, rtl88e_phy_set_rf_reg() argument
135 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_set_rf_reg()
146 original_value = _rtl88e_phy_rf_serial_read(hw, rtl88e_phy_set_rf_reg()
155 _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data); rtl88e_phy_set_rf_reg()
165 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw, _rtl88e_phy_rf_serial_read() argument
168 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_rf_serial_read()
178 if (RT_CANNOT_IO(hw)) { _rtl88e_phy_rf_serial_read()
182 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl88e_phy_rf_serial_read()
186 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl88e_phy_rf_serial_read()
189 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl88e_phy_rf_serial_read()
192 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl88e_phy_rf_serial_read()
195 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, _rtl88e_phy_rf_serial_read()
198 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, _rtl88e_phy_rf_serial_read()
201 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, _rtl88e_phy_rf_serial_read()
204 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, _rtl88e_phy_rf_serial_read()
212 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw, _rtl88e_phy_rf_serial_write() argument
218 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_rf_serial_write()
222 if (RT_CANNOT_IO(hw)) { _rtl88e_phy_rf_serial_write()
229 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl88e_phy_rf_serial_write()
246 bool rtl88e_phy_mac_config(struct ieee80211_hw *hw) rtl88e_phy_mac_config() argument
248 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_mac_config()
249 bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw); rtl88e_phy_mac_config()
255 bool rtl88e_phy_bb_config(struct ieee80211_hw *hw) rtl88e_phy_bb_config() argument
258 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_bb_config()
262 _rtl88e_phy_init_bb_rf_register_definition(hw); rtl88e_phy_bb_config()
274 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw); rtl88e_phy_bb_config()
278 bool rtl88e_phy_rf_config(struct ieee80211_hw *hw) rtl88e_phy_rf_config() argument
280 return rtl88e_phy_rf6052_config(hw); rtl88e_phy_rf_config()
283 static bool _rtl88e_check_condition(struct ieee80211_hw *hw, _rtl88e_check_condition() argument
286 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88e_check_condition()
287 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl88e_check_condition()
312 static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr, _rtl8188e_config_rf_reg() argument
329 rtl_set_rfreg(hw, rfpath, regaddr, _rtl8188e_config_rf_reg()
336 static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw, _rtl8188e_config_rf_radio_a() argument
342 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A, _rtl8188e_config_rf_radio_a()
346 static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw, _rtl8188e_config_bb_reg() argument
362 rtl_set_bbreg(hw, addr, MASKDWORD, data); _rtl8188e_config_bb_reg()
367 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw) _rtl88e_phy_bb8188e_config_parafile() argument
369 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_bb8188e_config_parafile()
371 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl88e_phy_bb8188e_config_parafile()
374 rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG); _rtl88e_phy_bb8188e_config_parafile()
383 phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG); _rtl88e_phy_bb8188e_config_parafile()
390 phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB); _rtl88e_phy_bb8188e_config_parafile()
396 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); _rtl88e_phy_bb8188e_config_parafile()
401 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl88e_phy_config_mac_with_headerfile() argument
403 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_config_mac_with_headerfile()
424 static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen, handle_branch1() argument
435 _rtl8188e_config_bb_reg(hw, v1, v2); handle_branch1()
441 if (!_rtl88e_check_condition(hw, array_table[i])) { handle_branch1()
456 _rtl8188e_config_bb_reg(hw, v1, v2); handle_branch1()
467 static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen, handle_branch2() argument
470 struct rtl_priv *rtlpriv = rtl_priv(hw); handle_branch2()
479 rtl_set_bbreg(hw, array_table[i], MASKDWORD, handle_branch2()
488 if (!_rtl88e_check_condition(hw, array_table[i])) { handle_branch2()
503 rtl_set_bbreg(hw, array_table[i], handle_branch2()
520 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw, phy_config_bb_with_headerfile() argument
529 handle_branch1(hw, arraylen, array_table); phy_config_bb_with_headerfile()
533 handle_branch2(hw, arraylen, array_table); phy_config_bb_with_headerfile()
538 static void store_pwrindex_rate_offset(struct ieee80211_hw *hw, store_pwrindex_rate_offset() argument
542 struct rtl_priv *rtlpriv = rtl_priv(hw); store_pwrindex_rate_offset()
668 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype) phy_config_bb_with_pghdr() argument
670 struct rtl_priv *rtlpriv = rtl_priv(hw); phy_config_bb_with_pghdr()
699 store_pwrindex_rate_offset(hw, phy_reg_page[i], phy_config_bb_with_pghdr()
704 if (!_rtl88e_check_condition(hw, phy_config_bb_with_pghdr()
739 static void process_path_a(struct ieee80211_hw *hw, process_path_a() argument
743 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); process_path_a()
751 _rtl8188e_config_rf_radio_a(hw, v1, v2); process_path_a()
757 if (!_rtl88e_check_condition(hw, radioa_array_table[i])) { process_path_a()
775 _rtl8188e_config_rf_radio_a(hw, v1, v2); process_path_a()
787 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD); process_path_a()
790 bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl88e_phy_config_rf_with_headerfile() argument
793 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_config_rf_with_headerfile()
806 process_path_a(hw, radioa_arraylen, radioa_array_table); rtl88e_phy_config_rf_with_headerfile()
816 void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl88e_phy_get_hw_reg_originalvalue() argument
818 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_get_hw_reg_originalvalue()
822 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl88e_phy_get_hw_reg_originalvalue()
824 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl88e_phy_get_hw_reg_originalvalue()
826 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl88e_phy_get_hw_reg_originalvalue()
828 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl88e_phy_get_hw_reg_originalvalue()
837 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, rtl88e_phy_get_hw_reg_originalvalue()
839 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, rtl88e_phy_get_hw_reg_originalvalue()
847 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) _rtl88e_phy_init_bb_rf_register_definition() argument
849 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_init_bb_rf_register_definition()
933 void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) rtl88e_phy_get_txpower_level() argument
935 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_get_txpower_level()
941 txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw, rtl88e_phy_get_txpower_level()
944 if (_rtl88e_phy_txpwr_idx_to_dbm(hw, rtl88e_phy_get_txpower_level()
948 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, rtl88e_phy_get_txpower_level()
951 if (_rtl88e_phy_txpwr_idx_to_dbm(hw, rtl88e_phy_get_txpower_level()
955 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, rtl88e_phy_get_txpower_level()
987 static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel, _rtl88e_get_txpower_index() argument
991 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl88e_get_txpower_index()
1016 static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw, _rtl88e_ccxpower_index_check() argument
1021 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_ccxpower_index_check()
1031 void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl88e_phy_set_txpower_level() argument
1033 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_phy_set_txpower_level()
1041 _rtl88e_get_txpower_index(hw, channel, rtl88e_phy_set_txpower_level()
1044 _rtl88e_ccxpower_index_check(hw, channel, rtl88e_phy_set_txpower_level()
1047 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); rtl88e_phy_set_txpower_level()
1048 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], rtl88e_phy_set_txpower_level()
1053 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, _rtl88e_phy_txpwr_idx_to_dbm() argument
1076 void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) rtl88e_phy_scan_operation_backup() argument
1078 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_scan_operation_backup()
1079 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_phy_scan_operation_backup()
1086 rtlpriv->cfg->ops->set_hw_reg(hw, rtl88e_phy_scan_operation_backup()
1093 rtlpriv->cfg->ops->set_hw_reg(hw, rtl88e_phy_scan_operation_backup()
1105 void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl88e_phy_set_bw_mode_callback() argument
1107 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_set_bw_mode_callback()
1108 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_phy_set_bw_mode_callback()
1110 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88e_phy_set_bw_mode_callback()
1147 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl88e_phy_set_bw_mode_callback()
1148 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl88e_phy_set_bw_mode_callback()
1149 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/ rtl88e_phy_set_bw_mode_callback()
1152 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl88e_phy_set_bw_mode_callback()
1153 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl88e_phy_set_bw_mode_callback()
1155 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, rtl88e_phy_set_bw_mode_callback()
1157 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); rtl88e_phy_set_bw_mode_callback()
1158 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ rtl88e_phy_set_bw_mode_callback()
1160 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl88e_phy_set_bw_mode_callback()
1169 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl88e_phy_set_bw_mode_callback()
1174 void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw, rtl88e_phy_set_bw_mode() argument
1177 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_set_bw_mode()
1179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_phy_set_bw_mode()
1185 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl88e_phy_set_bw_mode()
1186 rtl88e_phy_set_bw_mode_callback(hw); rtl88e_phy_set_bw_mode()
1195 void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw) rtl88e_phy_sw_chnl_callback() argument
1197 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_sw_chnl_callback()
1198 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_phy_sw_chnl_callback()
1210 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, rtl88e_phy_sw_chnl_callback()
1224 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw) rtl88e_phy_sw_chnl() argument
1226 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_sw_chnl()
1228 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_phy_sw_chnl()
1239 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl88e_phy_sw_chnl()
1240 rtl88e_phy_sw_chnl_callback(hw); rtl88e_phy_sw_chnl()
1253 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, _rtl88e_phy_sw_chnl_step_by_step() argument
1257 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_sw_chnl_step_by_step()
1321 rtl88e_phy_set_txpower_level(hw, channel); _rtl88e_phy_sw_chnl_step_by_step()
1341 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl88e_phy_sw_chnl_step_by_step()
1384 static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl88e_phy_path_a_iqk() argument
1389 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); _rtl88e_phy_path_a_iqk()
1390 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); _rtl88e_phy_path_a_iqk()
1391 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); _rtl88e_phy_path_a_iqk()
1392 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); _rtl88e_phy_path_a_iqk()
1394 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl88e_phy_path_a_iqk()
1395 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl88e_phy_path_a_iqk()
1396 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl88e_phy_path_a_iqk()
1400 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl88e_phy_path_a_iqk()
1401 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl88e_phy_path_a_iqk()
1402 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl88e_phy_path_a_iqk()
1403 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl88e_phy_path_a_iqk()
1412 static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw) _rtl88e_phy_path_b_iqk() argument
1417 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl88e_phy_path_b_iqk()
1418 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl88e_phy_path_b_iqk()
1420 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl88e_phy_path_b_iqk()
1421 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl88e_phy_path_b_iqk()
1422 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl88e_phy_path_b_iqk()
1423 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl88e_phy_path_b_iqk()
1424 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl88e_phy_path_b_iqk()
1439 static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl88e_phy_path_a_rx_iqk() argument
1446 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl88e_phy_path_a_rx_iqk()
1447 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl88e_phy_path_a_rx_iqk()
1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl88e_phy_path_a_rx_iqk()
1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); _rtl88e_phy_path_a_rx_iqk()
1450 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); _rtl88e_phy_path_a_rx_iqk()
1451 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl88e_phy_path_a_rx_iqk()
1454 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl88e_phy_path_a_rx_iqk()
1455 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); _rtl88e_phy_path_a_rx_iqk()
1458 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); _rtl88e_phy_path_a_rx_iqk()
1459 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); _rtl88e_phy_path_a_rx_iqk()
1460 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); _rtl88e_phy_path_a_rx_iqk()
1461 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); _rtl88e_phy_path_a_rx_iqk()
1464 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl88e_phy_path_a_rx_iqk()
1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl88e_phy_path_a_rx_iqk()
1467 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl88e_phy_path_a_rx_iqk()
1471 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1472 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1473 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1485 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); _rtl88e_phy_path_a_rx_iqk()
1488 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl88e_phy_path_a_rx_iqk()
1489 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl88e_phy_path_a_rx_iqk()
1490 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl88e_phy_path_a_rx_iqk()
1491 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); _rtl88e_phy_path_a_rx_iqk()
1492 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); _rtl88e_phy_path_a_rx_iqk()
1493 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl88e_phy_path_a_rx_iqk()
1496 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl88e_phy_path_a_rx_iqk()
1499 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); _rtl88e_phy_path_a_rx_iqk()
1500 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); _rtl88e_phy_path_a_rx_iqk()
1501 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); _rtl88e_phy_path_a_rx_iqk()
1502 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); _rtl88e_phy_path_a_rx_iqk()
1505 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl88e_phy_path_a_rx_iqk()
1507 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl88e_phy_path_a_rx_iqk()
1508 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl88e_phy_path_a_rx_iqk()
1512 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1513 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1514 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1515 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl88e_phy_path_a_rx_iqk()
1524 static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl88e_phy_path_a_fill_iqk_matrix() argument
1534 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, _rtl88e_phy_path_a_fill_iqk_matrix()
1540 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); _rtl88e_phy_path_a_fill_iqk_matrix()
1541 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), _rtl88e_phy_path_a_fill_iqk_matrix()
1547 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, _rtl88e_phy_path_a_fill_iqk_matrix()
1549 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, _rtl88e_phy_path_a_fill_iqk_matrix()
1551 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), _rtl88e_phy_path_a_fill_iqk_matrix()
1556 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); _rtl88e_phy_path_a_fill_iqk_matrix()
1558 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); _rtl88e_phy_path_a_fill_iqk_matrix()
1560 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); _rtl88e_phy_path_a_fill_iqk_matrix()
1564 static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw, _rtl88e_phy_save_adda_registers() argument
1571 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); _rtl88e_phy_save_adda_registers()
1574 static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw, _rtl88e_phy_save_mac_registers() argument
1577 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_save_mac_registers()
1585 static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw, _rtl88e_phy_reload_adda_registers() argument
1592 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); _rtl88e_phy_reload_adda_registers()
1595 static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw, _rtl88e_phy_reload_mac_registers() argument
1598 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_reload_mac_registers()
1606 static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw, _rtl88e_phy_path_adda_on() argument
1615 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); _rtl88e_phy_path_adda_on()
1617 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); _rtl88e_phy_path_adda_on()
1621 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); _rtl88e_phy_path_adda_on()
1624 static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw, _rtl88e_phy_mac_setting_calibration() argument
1627 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_mac_setting_calibration()
1638 static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw) _rtl88e_phy_path_a_standby() argument
1640 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl88e_phy_path_a_standby()
1641 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl88e_phy_path_a_standby()
1642 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl88e_phy_path_a_standby()
1645 static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) _rtl88e_phy_pi_mode_switch() argument
1650 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); _rtl88e_phy_pi_mode_switch()
1651 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); _rtl88e_phy_pi_mode_switch()
1654 static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw, _rtl88e_phy_simularity_compare() argument
1658 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88e_phy_simularity_compare()
1714 static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, _rtl88e_phy_iq_calibrate() argument
1717 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_iq_calibrate()
1738 _rtl88e_phy_save_adda_registers(hw, adda_reg, _rtl88e_phy_iq_calibrate()
1740 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg, _rtl88e_phy_iq_calibrate()
1742 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg, _rtl88e_phy_iq_calibrate()
1746 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl88e_phy_iq_calibrate()
1749 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8)); _rtl88e_phy_iq_calibrate()
1753 _rtl88e_phy_pi_mode_switch(hw, true); _rtl88e_phy_iq_calibrate()
1755 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); _rtl88e_phy_iq_calibrate()
1756 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl88e_phy_iq_calibrate()
1757 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl88e_phy_iq_calibrate()
1758 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl88e_phy_iq_calibrate()
1760 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); _rtl88e_phy_iq_calibrate()
1761 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); _rtl88e_phy_iq_calibrate()
1762 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); _rtl88e_phy_iq_calibrate()
1763 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); _rtl88e_phy_iq_calibrate()
1766 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl88e_phy_iq_calibrate()
1767 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); _rtl88e_phy_iq_calibrate()
1769 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl88e_phy_iq_calibrate()
1771 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); _rtl88e_phy_iq_calibrate()
1773 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); _rtl88e_phy_iq_calibrate()
1775 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl88e_phy_iq_calibrate()
1776 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl88e_phy_iq_calibrate()
1777 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); _rtl88e_phy_iq_calibrate()
1779 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t); _rtl88e_phy_iq_calibrate()
1783 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1785 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1792 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t); _rtl88e_phy_iq_calibrate()
1796 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1798 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1811 _rtl88e_phy_path_a_standby(hw); _rtl88e_phy_iq_calibrate()
1812 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t); _rtl88e_phy_iq_calibrate()
1814 pathb_ok = _rtl88e_phy_path_b_iqk(hw); _rtl88e_phy_iq_calibrate()
1816 result[t][4] = (rtl_get_bbreg(hw, _rtl88e_phy_iq_calibrate()
1821 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1824 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1827 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1831 result[t][4] = (rtl_get_bbreg(hw, _rtl88e_phy_iq_calibrate()
1836 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl88e_phy_iq_calibrate()
1841 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl88e_phy_iq_calibrate()
1845 _rtl88e_phy_pi_mode_switch(hw, false); _rtl88e_phy_iq_calibrate()
1846 _rtl88e_phy_reload_adda_registers(hw, adda_reg, _rtl88e_phy_iq_calibrate()
1848 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl88e_phy_iq_calibrate()
1850 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl88e_phy_iq_calibrate()
1854 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); _rtl88e_phy_iq_calibrate()
1856 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); _rtl88e_phy_iq_calibrate()
1857 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); _rtl88e_phy_iq_calibrate()
1858 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); _rtl88e_phy_iq_calibrate()
1863 static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl88e_phy_lc_calibrate() argument
1867 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_lc_calibrate()
1877 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); _rtl88e_phy_lc_calibrate()
1880 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, _rtl88e_phy_lc_calibrate()
1883 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, _rtl88e_phy_lc_calibrate()
1887 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl88e_phy_lc_calibrate()
1890 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); _rtl88e_phy_lc_calibrate()
1892 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); _rtl88e_phy_lc_calibrate()
1898 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); _rtl88e_phy_lc_calibrate()
1901 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl88e_phy_lc_calibrate()
1910 static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, _rtl88e_phy_set_rfpath_switch() argument
1913 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88e_phy_set_rfpath_switch()
1914 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88e_phy_set_rfpath_switch()
1915 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl88e_phy_set_rfpath_switch()
1922 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); _rtl88e_phy_set_rfpath_switch()
1926 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl88e_phy_set_rfpath_switch()
1929 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl88e_phy_set_rfpath_switch()
1932 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); _rtl88e_phy_set_rfpath_switch()
1933 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); _rtl88e_phy_set_rfpath_switch()
1940 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, _rtl88e_phy_set_rfpath_switch()
1942 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl88e_phy_set_rfpath_switch()
1945 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); _rtl88e_phy_set_rfpath_switch()
1947 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, _rtl88e_phy_set_rfpath_switch()
1949 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl88e_phy_set_rfpath_switch()
1952 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); _rtl88e_phy_set_rfpath_switch()
1960 void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl88e_phy_iq_calibrate() argument
1962 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_iq_calibrate()
1983 _rtl88e_phy_reload_adda_registers(hw, rtl88e_phy_iq_calibrate()
2003 _rtl88e_phy_iq_calibrate(hw, result, i, true); rtl88e_phy_iq_calibrate()
2005 _rtl88e_phy_iq_calibrate(hw, result, i, false); rtl88e_phy_iq_calibrate()
2008 _rtl88e_phy_simularity_compare(hw, result, 0, 1); rtl88e_phy_iq_calibrate()
2016 _rtl88e_phy_simularity_compare(hw, result, 0, 2); rtl88e_phy_iq_calibrate()
2022 _rtl88e_phy_simularity_compare(hw, result, 1, 2); rtl88e_phy_iq_calibrate()
2068 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, rtl88e_phy_iq_calibrate()
2078 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg, rtl88e_phy_iq_calibrate()
2082 void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw) rtl88e_phy_lc_calibrate() argument
2084 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_lc_calibrate()
2099 _rtl88e_phy_lc_calibrate(hw, false); rtl88e_phy_lc_calibrate()
2104 void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) rtl88e_phy_set_rfpath_switch() argument
2106 _rtl88e_phy_set_rfpath_switch(hw, bmain, false); rtl88e_phy_set_rfpath_switch()
2109 bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl88e_phy_set_io_cmd() argument
2111 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_set_io_cmd()
2142 rtl88e_phy_set_io(hw); rtl88e_phy_set_io_cmd()
2147 static void rtl88e_phy_set_io(struct ieee80211_hw *hw) rtl88e_phy_set_io() argument
2149 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_phy_set_io()
2159 /*rtl92c_dm_write_dig(hw);*/ rtl88e_phy_set_io()
2160 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); rtl88e_phy_set_io()
2161 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); rtl88e_phy_set_io()
2166 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); rtl88e_phy_set_io()
2178 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw) rtl88ee_phy_set_rf_on() argument
2180 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_phy_set_rf_on()
2190 static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw) _rtl88ee_phy_set_rf_sleep() argument
2192 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_phy_set_rf_sleep()
2195 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl88ee_phy_set_rf_sleep()
2200 static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl88ee_phy_set_rf_power_state() argument
2203 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_phy_set_rf_power_state()
2204 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl88ee_phy_set_rf_power_state()
2205 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl88ee_phy_set_rf_power_state()
2206 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl88ee_phy_set_rf_power_state()
2222 rtstatus = rtl_ps_enable_nic(hw); _rtl88ee_phy_set_rf_power_state()
2234 rtl88ee_phy_set_rf_on(hw); _rtl88ee_phy_set_rf_power_state()
2237 rtlpriv->cfg->ops->led_control(hw, _rtl88ee_phy_set_rf_power_state()
2240 rtlpriv->cfg->ops->led_control(hw, _rtl88ee_phy_set_rf_power_state()
2274 rtl_ps_disable_nic(hw); _rtl88ee_phy_set_rf_power_state()
2278 rtlpriv->cfg->ops->led_control(hw, _rtl88ee_phy_set_rf_power_state()
2281 rtlpriv->cfg->ops->led_control(hw, _rtl88ee_phy_set_rf_power_state()
2318 _rtl88ee_phy_set_rf_sleep(hw); _rtl88ee_phy_set_rf_power_state()
2332 bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl88e_phy_set_rf_power_state() argument
2335 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88e_phy_set_rf_power_state()
2341 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state); rtl88e_phy_set_rf_power_state()
H A Ddm.c168 static void rtl88e_set_iqk_matrix(struct ieee80211_hw *hw, rtl88e_set_iqk_matrix() argument
188 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, rtl88e_set_iqk_matrix()
191 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, rtl88e_set_iqk_matrix()
194 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), rtl88e_set_iqk_matrix()
199 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, rtl88e_set_iqk_matrix()
202 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32); rtl88e_set_iqk_matrix()
204 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), rtl88e_set_iqk_matrix()
213 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, rtl88e_set_iqk_matrix()
215 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, rtl88e_set_iqk_matrix()
217 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl88e_set_iqk_matrix()
221 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, rtl88e_set_iqk_matrix()
223 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, rtl88e_set_iqk_matrix()
225 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl88e_set_iqk_matrix()
234 void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw, rtl88e_dm_txpower_track_adjust() argument
237 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_txpower_track_adjust()
238 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_txpower_track_adjust()
270 static void dm_tx_pwr_track_set_pwr(struct ieee80211_hw *hw, dm_tx_pwr_track_set_pwr() argument
274 struct rtl_priv *rtlpriv = rtl_priv(hw); dm_tx_pwr_track_set_pwr()
276 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); dm_tx_pwr_track_set_pwr()
281 rtl88e_phy_set_txpower_level(hw, dm_tx_pwr_track_set_pwr()
324 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath], dm_tx_pwr_track_set_pwr()
332 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath], dm_tx_pwr_track_set_pwr()
345 static u8 rtl88e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) rtl88e_dm_initial_gain_min_pwdb() argument
347 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_initial_gain_min_pwdb()
372 static void rtl88e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) rtl88e_dm_false_alarm_counter_statistics() argument
375 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_false_alarm_counter_statistics()
378 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); rtl88e_dm_false_alarm_counter_statistics()
379 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); rtl88e_dm_false_alarm_counter_statistics()
381 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics()
385 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics()
389 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics()
393 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics()
402 ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics()
406 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1); rtl88e_dm_false_alarm_counter_statistics()
407 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); rtl88e_dm_false_alarm_counter_statistics()
409 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); rtl88e_dm_false_alarm_counter_statistics()
412 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); rtl88e_dm_false_alarm_counter_statistics()
415 ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics()
429 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1); rtl88e_dm_false_alarm_counter_statistics()
430 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0); rtl88e_dm_false_alarm_counter_statistics()
431 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1); rtl88e_dm_false_alarm_counter_statistics()
432 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0); rtl88e_dm_false_alarm_counter_statistics()
433 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); rtl88e_dm_false_alarm_counter_statistics()
434 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); rtl88e_dm_false_alarm_counter_statistics()
435 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0); rtl88e_dm_false_alarm_counter_statistics()
436 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2); rtl88e_dm_false_alarm_counter_statistics()
437 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0); rtl88e_dm_false_alarm_counter_statistics()
438 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2); rtl88e_dm_false_alarm_counter_statistics()
452 static void rtl88e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) rtl88e_dm_cck_packet_detection_thresh() argument
454 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_cck_packet_detection_thresh()
459 dm_dig->rssi_val_min = rtl88e_dm_initial_gain_min_pwdb(hw); rtl88e_dm_cck_packet_detection_thresh()
480 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh); rtl88e_dm_cck_packet_detection_thresh()
488 static void rtl88e_dm_dig(struct ieee80211_hw *hw) rtl88e_dm_dig() argument
490 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_dig()
491 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88e_dm_dig()
492 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_dig()
522 rtl88e_dm_initial_gain_min_pwdb(hw); rtl88e_dm_dig()
614 rtl88e_dm_write_dig(hw); rtl88e_dm_dig()
619 rtl88e_dm_cck_packet_detection_thresh(hw); rtl88e_dm_dig()
622 static void rtl88e_dm_init_dynamic_txpower(struct ieee80211_hw *hw) rtl88e_dm_init_dynamic_txpower() argument
624 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_init_dynamic_txpower()
632 static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw) rtl92c_dm_dynamic_txpower() argument
634 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_dynamic_txpower()
636 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_dynamic_txpower()
704 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); rtl92c_dm_dynamic_txpower()
710 void rtl88e_dm_write_dig(struct ieee80211_hw *hw) rtl88e_dm_write_dig() argument
712 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_write_dig()
723 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, rtl88e_dm_write_dig()
730 static void rtl88e_dm_pwdb_monitor(struct ieee80211_hw *hw) rtl88e_dm_pwdb_monitor() argument
732 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_pwdb_monitor()
733 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_dm_pwdb_monitor()
794 void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw) rtl88e_dm_init_edca_turbo() argument
796 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_init_edca_turbo()
803 static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw) rtl88e_dm_check_edca_turbo() argument
805 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_check_edca_turbo()
806 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88e_dm_check_edca_turbo()
867 rtlpriv->cfg->ops->set_hw_reg(hw, rtl88e_dm_check_edca_turbo()
879 static void dm_txpower_track_cb_therm(struct ieee80211_hw *hw) dm_txpower_track_cb_therm() argument
881 struct rtl_priv *rtlpriv = rtl_priv(hw); dm_txpower_track_cb_therm()
882 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); dm_txpower_track_cb_therm()
883 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); dm_txpower_track_cb_therm()
884 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); dm_txpower_track_cb_therm()
915 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, dm_txpower_track_cb_therm()
925 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & dm_txpower_track_cb_therm()
940 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; dm_txpower_track_cb_therm()
1026 rtl88e_phy_lc_calibrate(hw); dm_txpower_track_cb_therm()
1091 dm_tx_pwr_track_set_pwr(hw, TXAGC, 0, 0); dm_txpower_track_cb_therm()
1097 rtl88e_phy_iq_calibrate(hw, false); dm_txpower_track_cb_therm()
1106 static void rtl88e_dm_init_txpower_tracking(struct ieee80211_hw *hw) rtl88e_dm_init_txpower_tracking() argument
1108 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_init_txpower_tracking()
1123 void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw) rtl88e_dm_check_txpower_tracking() argument
1125 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_check_txpower_tracking()
1131 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16), rtl88e_dm_check_txpower_tracking()
1140 dm_txpower_track_cb_therm(hw); rtl88e_dm_check_txpower_tracking()
1145 void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) rtl88e_dm_init_rate_adaptive_mask() argument
1147 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_init_rate_adaptive_mask()
1159 static void rtl88e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw) rtl88e_dm_refresh_rate_adaptive_mask() argument
1161 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_refresh_rate_adaptive_mask()
1162 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88e_dm_refresh_rate_adaptive_mask()
1163 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88e_dm_refresh_rate_adaptive_mask()
1221 sta = rtl_find_sta(hw, mac->bssid); rtl88e_dm_refresh_rate_adaptive_mask()
1223 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, rtl88e_dm_refresh_rate_adaptive_mask()
1232 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw) rtl92c_dm_init_dynamic_bb_powersaving() argument
1234 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_init_dynamic_bb_powersaving()
1244 static void rtl88e_dm_update_rx_idle_ant(struct ieee80211_hw *hw, rtl88e_dm_update_rx_idle_ant() argument
1247 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_update_rx_idle_ant()
1248 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_update_rx_idle_ant()
1249 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_update_rx_idle_ant()
1273 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_update_rx_idle_ant()
1275 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_update_rx_idle_ant()
1277 rtl_set_bbreg(hw, DM_REG_ANTSEL_CTRL_11N, rtl88e_dm_update_rx_idle_ant()
1280 rtl_set_bbreg(hw, DM_REG_RESP_TX_11N, rtl88e_dm_update_rx_idle_ant()
1283 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_update_rx_idle_ant()
1285 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_update_rx_idle_ant()
1294 static void rtl88e_dm_update_tx_ant(struct ieee80211_hw *hw, rtl88e_dm_update_tx_ant() argument
1297 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_update_tx_ant()
1298 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_update_tx_ant()
1318 static void rtl88e_dm_rx_hw_antena_div_init(struct ieee80211_hw *hw) rtl88e_dm_rx_hw_antena_div_init() argument
1323 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); rtl88e_dm_rx_hw_antena_div_init()
1324 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, rtl88e_dm_rx_hw_antena_div_init()
1327 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); rtl88e_dm_rx_hw_antena_div_init()
1328 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); rtl88e_dm_rx_hw_antena_div_init()
1329 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1); rtl88e_dm_rx_hw_antena_div_init()
1330 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); rtl88e_dm_rx_hw_antena_div_init()
1332 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); rtl88e_dm_rx_hw_antena_div_init()
1334 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1); rtl88e_dm_rx_hw_antena_div_init()
1335 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); rtl88e_dm_rx_hw_antena_div_init()
1336 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT); rtl88e_dm_rx_hw_antena_div_init()
1337 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201); rtl88e_dm_rx_hw_antena_div_init()
1340 static void rtl88e_dm_trx_hw_antenna_div_init(struct ieee80211_hw *hw) rtl88e_dm_trx_hw_antenna_div_init() argument
1345 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); rtl88e_dm_trx_hw_antenna_div_init()
1346 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD, rtl88e_dm_trx_hw_antenna_div_init()
1349 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); rtl88e_dm_trx_hw_antenna_div_init()
1350 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); rtl88e_dm_trx_hw_antenna_div_init()
1351 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0); rtl88e_dm_trx_hw_antenna_div_init()
1352 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); rtl88e_dm_trx_hw_antenna_div_init()
1354 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); rtl88e_dm_trx_hw_antenna_div_init()
1356 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1); rtl88e_dm_trx_hw_antenna_div_init()
1357 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); rtl88e_dm_trx_hw_antenna_div_init()
1359 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0); rtl88e_dm_trx_hw_antenna_div_init()
1360 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT); rtl88e_dm_trx_hw_antenna_div_init()
1361 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201); rtl88e_dm_trx_hw_antenna_div_init()
1364 static void rtl88e_dm_fast_training_init(struct ieee80211_hw *hw) rtl88e_dm_fast_training_init() argument
1366 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_fast_training_init()
1381 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); rtl88e_dm_fast_training_init()
1382 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, rtl88e_dm_fast_training_init()
1384 value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, MASKDWORD); rtl88e_dm_fast_training_init()
1385 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, rtl88e_dm_fast_training_init()
1387 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, rtl88e_dm_fast_training_init()
1389 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N, rtl88e_dm_fast_training_init()
1393 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); rtl88e_dm_fast_training_init()
1394 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); rtl88e_dm_fast_training_init()
1395 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0); rtl88e_dm_fast_training_init()
1396 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); rtl88e_dm_fast_training_init()
1399 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); rtl88e_dm_fast_training_init()
1401 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1); rtl88e_dm_fast_training_init()
1402 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2); rtl88e_dm_fast_training_init()
1405 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1); rtl88e_dm_fast_training_init()
1406 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_fast_training_init()
1408 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_fast_training_init()
1410 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, rtl88e_dm_fast_training_init()
1413 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); rtl88e_dm_fast_training_init()
1416 static void rtl88e_dm_antenna_div_init(struct ieee80211_hw *hw) rtl88e_dm_antenna_div_init() argument
1418 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_antenna_div_init()
1421 rtl88e_dm_rx_hw_antena_div_init(hw); rtl88e_dm_antenna_div_init()
1423 rtl88e_dm_trx_hw_antenna_div_init(hw); rtl88e_dm_antenna_div_init()
1425 rtl88e_dm_fast_training_init(hw); rtl88e_dm_antenna_div_init()
1429 void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, rtl88e_dm_set_tx_ant_by_tx_info() argument
1432 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_set_tx_ant_by_tx_info()
1433 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_set_tx_ant_by_tx_info()
1444 void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw, rtl88e_dm_ant_sel_statistics() argument
1448 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_ant_sel_statistics()
1449 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_ant_sel_statistics()
1471 static void rtl88e_dm_hw_ant_div(struct ieee80211_hw *hw) rtl88e_dm_hw_ant_div() argument
1473 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_hw_ant_div()
1474 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_hw_ant_div()
1475 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_hw_ant_div()
1519 rtl88e_dm_update_tx_ant(hw, target_ant, i); rtl88e_dm_hw_ant_div()
1558 rtl88e_dm_update_tx_ant(hw, target_ant, i); rtl88e_dm_hw_ant_div()
1570 rtl88e_dm_update_rx_idle_ant(hw, rx_idle_ant); rtl88e_dm_hw_ant_div()
1576 static void rtl88e_set_next_mac_address_target(struct ieee80211_hw *hw) rtl88e_set_next_mac_address_target() argument
1578 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_set_next_mac_address_target()
1579 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88e_set_next_mac_address_target()
1580 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_set_next_mac_address_target()
1595 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, rtl88e_set_next_mac_address_target()
1602 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N, rtl88e_set_next_mac_address_target()
1618 rtl_set_bbreg(hw, rtl88e_set_next_mac_address_target()
1626 rtl_set_bbreg(hw, rtl88e_set_next_mac_address_target()
1640 static void rtl88e_dm_fast_ant_training(struct ieee80211_hw *hw) rtl88e_dm_fast_ant_training() argument
1642 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_fast_ant_training()
1643 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_fast_ant_training()
1667 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, rtl88e_dm_fast_ant_training()
1669 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); rtl88e_dm_fast_ant_training()
1671 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, rtl88e_dm_fast_ant_training()
1673 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) | rtl88e_dm_fast_ant_training()
1675 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, rtl88e_dm_fast_ant_training()
1686 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); rtl88e_dm_fast_ant_training()
1699 rtl88e_set_next_mac_address_target(hw); rtl88e_dm_fast_ant_training()
1702 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1); rtl88e_dm_fast_ant_training()
1703 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); rtl88e_dm_fast_ant_training()
1712 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; rtl88e_dm_fast_antenna_training_callback() local
1714 rtl88e_dm_fast_ant_training(hw); rtl88e_dm_fast_antenna_training_callback()
1717 static void rtl88e_dm_antenna_diversity(struct ieee80211_hw *hw) rtl88e_dm_antenna_diversity() argument
1719 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_antenna_diversity()
1720 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88e_dm_antenna_diversity()
1721 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88e_dm_antenna_diversity()
1722 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); rtl88e_dm_antenna_diversity()
1730 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); rtl88e_dm_antenna_diversity()
1731 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N, rtl88e_dm_antenna_diversity()
1734 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, rtl88e_dm_antenna_diversity()
1745 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); rtl88e_dm_antenna_diversity()
1746 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N, rtl88e_dm_antenna_diversity()
1749 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, rtl88e_dm_antenna_diversity()
1759 rtl88e_dm_hw_ant_div(hw); rtl88e_dm_antenna_diversity()
1761 rtl88e_dm_fast_ant_training(hw); rtl88e_dm_antenna_diversity()
1764 void rtl88e_dm_init(struct ieee80211_hw *hw) rtl88e_dm_init() argument
1766 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_init()
1767 u32 cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f); rtl88e_dm_init()
1770 rtl_dm_diginit(hw, cur_igvalue); rtl88e_dm_init()
1771 rtl88e_dm_init_dynamic_txpower(hw); rtl88e_dm_init()
1772 rtl88e_dm_init_edca_turbo(hw); rtl88e_dm_init()
1773 rtl88e_dm_init_rate_adaptive_mask(hw); rtl88e_dm_init()
1774 rtl88e_dm_init_txpower_tracking(hw); rtl88e_dm_init()
1775 rtl92c_dm_init_dynamic_bb_powersaving(hw); rtl88e_dm_init()
1776 rtl88e_dm_antenna_div_init(hw); rtl88e_dm_init()
1779 void rtl88e_dm_watchdog(struct ieee80211_hw *hw) rtl88e_dm_watchdog() argument
1781 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88e_dm_watchdog()
1782 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88e_dm_watchdog()
1786 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, rtl88e_dm_watchdog()
1788 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, rtl88e_dm_watchdog()
1796 rtl88e_dm_pwdb_monitor(hw); rtl88e_dm_watchdog()
1797 rtl88e_dm_dig(hw); rtl88e_dm_watchdog()
1798 rtl88e_dm_false_alarm_counter_statistics(hw); rtl88e_dm_watchdog()
1799 rtl92c_dm_dynamic_txpower(hw); rtl88e_dm_watchdog()
1800 rtl88e_dm_check_txpower_tracking(hw); rtl88e_dm_watchdog()
1801 rtl88e_dm_refresh_rate_adaptive_mask(hw); rtl88e_dm_watchdog()
1802 rtl88e_dm_check_edca_turbo(hw); rtl88e_dm_watchdog()
1803 rtl88e_dm_antenna_diversity(hw); rtl88e_dm_watchdog()
H A Dled.c35 static void _rtl88ee_init_led(struct ieee80211_hw *hw, _rtl88ee_init_led() argument
38 pled->hw = hw; _rtl88ee_init_led()
43 void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl88ee_sw_led_on() argument
46 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_sw_led_on()
71 void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl88ee_sw_led_off() argument
73 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_sw_led_off()
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl88ee_sw_led_off()
109 void rtl88ee_init_sw_leds(struct ieee80211_hw *hw) rtl88ee_init_sw_leds() argument
111 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl88ee_init_sw_leds()
112 _rtl88ee_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0); rtl88ee_init_sw_leds()
113 _rtl88ee_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1); rtl88ee_init_sw_leds()
116 static void _rtl88ee_sw_led_control(struct ieee80211_hw *hw, _rtl88ee_sw_led_control() argument
119 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl88ee_sw_led_control()
125 rtl88ee_sw_led_on(hw, pLed0); _rtl88ee_sw_led_control()
128 rtl88ee_sw_led_off(hw, pLed0); _rtl88ee_sw_led_control()
135 void rtl88ee_led_control(struct ieee80211_hw *hw, rtl88ee_led_control() argument
138 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_led_control()
139 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88ee_led_control()
153 _rtl88ee_sw_led_control(hw, ledaction); rtl88ee_led_control()
H A Dhw.c40 #include "hw.h"
45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw, _rtl88ee_set_bcn_ctrl_reg() argument
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl88ee_set_bcn_ctrl_reg()
49 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_set_bcn_ctrl_reg()
57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw) _rtl88ee_stop_tx_beacon() argument
59 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_stop_tx_beacon()
70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw) _rtl88ee_resume_tx_beacon() argument
72 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_resume_tx_beacon()
83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw) _rtl88ee_enable_bcn_sub_func() argument
85 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); _rtl88ee_enable_bcn_sub_func()
88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw) _rtl88ee_return_beacon_queue_skb() argument
90 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_return_beacon_queue_skb()
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl88ee_return_beacon_queue_skb()
110 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw) _rtl88ee_disable_bcn_sub_func() argument
112 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0); _rtl88ee_disable_bcn_sub_func()
115 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw, _rtl88ee_set_fw_clock_on() argument
118 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_set_fw_clock_on()
119 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_set_fw_clock_on()
123 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, _rtl88ee_set_fw_clock_on()
151 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); _rtl88ee_set_fw_clock_on()
185 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw, _rtl88ee_set_fw_clock_off() argument
188 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_set_fw_clock_off()
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_set_fw_clock_off()
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl88ee_set_fw_clock_off()
202 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); _rtl88ee_set_fw_clock_off()
228 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl88ee_set_fw_clock_off()
241 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw) _rtl88ee_set_fw_ps_rf_on() argument
246 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true); _rtl88ee_set_fw_ps_rf_on()
249 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw) _rtl88ee_set_fw_ps_rf_off_low_power() argument
253 _rtl88ee_set_fw_clock_off(hw, rpwm_val); _rtl88ee_set_fw_ps_rf_off_low_power()
257 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; rtl88ee_fw_clk_off_timer_callback() local
259 _rtl88ee_set_fw_ps_rf_off_low_power(hw); rtl88ee_fw_clk_off_timer_callback()
262 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw) _rtl88ee_fwlps_leave() argument
264 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_fwlps_leave()
265 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl88ee_fwlps_leave()
266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_fwlps_leave()
272 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false); _rtl88ee_fwlps_leave()
274 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl88ee_fwlps_leave()
276 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl88ee_fwlps_leave()
280 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); _rtl88ee_fwlps_leave()
281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl88ee_fwlps_leave()
283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl88ee_fwlps_leave()
288 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw) _rtl88ee_fwlps_enter() argument
290 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_fwlps_enter()
291 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl88ee_fwlps_enter()
292 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_fwlps_enter()
298 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl88ee_fwlps_enter()
300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl88ee_fwlps_enter()
303 _rtl88ee_set_fw_clock_off(hw, rpwm_val); _rtl88ee_fwlps_enter()
306 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl88ee_fwlps_enter()
308 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl88ee_fwlps_enter()
310 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val); _rtl88ee_fwlps_enter()
314 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) rtl88ee_get_hw_reg() argument
316 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_get_hw_reg()
317 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88ee_get_hw_reg()
318 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_get_hw_reg()
331 rtlpriv->cfg->ops->get_hw_reg(hw, rtl88ee_get_hw_reg()
365 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) rtl88ee_set_hw_reg() argument
367 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_hw_reg()
368 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_set_hw_reg()
369 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_set_hw_reg()
370 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88ee_set_hw_reg()
371 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88ee_set_hw_reg()
426 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, rtl88ee_set_hw_reg()
527 rtl88e_dm_init_edca_turbo(hw); rtl88ee_set_hw_reg()
530 rtlpriv->cfg->ops->set_hw_reg(hw, rtl88ee_set_hw_reg()
605 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val)); rtl88ee_set_hw_reg()
620 rtl88e_set_fw_pwrmode_cmd(hw, *val); rtl88ee_set_hw_reg()
626 _rtl88ee_set_fw_ps_rf_on(hw); rtl88ee_set_hw_reg()
632 _rtl88ee_fwlps_enter(hw); rtl88ee_set_hw_reg()
634 _rtl88ee_fwlps_leave(hw); rtl88ee_set_hw_reg()
644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, rtl88ee_set_hw_reg()
651 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); rtl88ee_set_hw_reg()
652 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); rtl88ee_set_hw_reg()
667 _rtl88ee_return_beacon_queue_skb(hw); rtl88ee_set_hw_reg()
669 rtl88e_set_fw_rsvdpagepkt(hw, 0); rtl88ee_set_hw_reg()
685 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl88ee_set_hw_reg()
686 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); rtl88ee_set_hw_reg()
697 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); rtl88ee_set_hw_reg()
700 rtl88e_set_p2p_ps_offload_cmd(hw, *val); rtl88ee_set_hw_reg()
714 _rtl88ee_stop_tx_beacon(hw); rtl88ee_set_hw_reg()
716 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); rtl88ee_set_hw_reg()
723 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl88ee_set_hw_reg()
726 _rtl88ee_resume_tx_beacon(hw); rtl88ee_set_hw_reg()
733 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL, rtl88ee_set_hw_reg()
743 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) _rtl88ee_llt_write() argument
745 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_llt_write()
770 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw) _rtl88ee_llt_table_init() argument
772 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_llt_table_init()
796 status = _rtl88ee_llt_write(hw, i, i + 1); _rtl88ee_llt_table_init()
801 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); _rtl88ee_llt_table_init()
806 status = _rtl88ee_llt_write(hw, i, (i + 1)); _rtl88ee_llt_table_init()
811 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy); _rtl88ee_llt_table_init()
818 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw) _rtl88ee_gen_refresh_led_state() argument
820 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_gen_refresh_led_state()
821 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl88ee_gen_refresh_led_state()
822 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl88ee_gen_refresh_led_state()
829 rtl88ee_sw_led_on(hw, pLed0); _rtl88ee_gen_refresh_led_state()
831 rtl88ee_sw_led_on(hw, pLed0); _rtl88ee_gen_refresh_led_state()
833 rtl88ee_sw_led_off(hw, pLed0); _rtl88ee_gen_refresh_led_state()
836 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw) _rtl88ee_init_mac() argument
838 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_init_mac()
839 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl88ee_init_mac()
840 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_init_mac()
892 if (_rtl88ee_llt_table_init(hw) == false) { _rtl88ee_init_mac()
945 _rtl88ee_gen_refresh_led_state(hw); _rtl88ee_init_mac()
949 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw) _rtl88ee_hw_configure() argument
951 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_hw_configure()
964 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw) _rtl88ee_enable_aspm_back_door() argument
966 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_enable_aspm_back_door()
967 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl88ee_enable_aspm_back_door()
1024 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw) rtl88ee_enable_hw_security_config() argument
1026 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_enable_hw_security_config()
1036 "not open hw encryption\n"); rtl88ee_enable_hw_security_config()
1054 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); rtl88ee_enable_hw_security_config()
1057 int rtl88ee_hw_init(struct ieee80211_hw *hw) rtl88ee_hw_init() argument
1059 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_hw_init()
1060 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88ee_hw_init()
1061 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_hw_init()
1063 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88ee_hw_init()
1064 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_hw_init()
1065 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88ee_hw_init()
1083 rtlpriv->intf_ops->disable_aspm(hw); rtl88ee_hw_init()
1094 rtstatus = _rtl88ee_init_mac(hw); rtl88ee_hw_init()
1101 err = rtl88e_download_fw(hw, false); rtl88ee_hw_init()
1116 rtl88e_phy_mac_config(hw); rtl88ee_hw_init()
1125 rtl88e_phy_bb_config(hw); rtl88ee_hw_init()
1126 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); rtl88ee_hw_init()
1127 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); rtl88ee_hw_init()
1130 rtl88e_phy_rf_config(hw); rtl88ee_hw_init()
1132 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, rtl88ee_hw_init()
1136 _rtl88ee_hw_configure(hw); rtl88ee_hw_init()
1137 rtl_cam_reset_all_entry(hw); rtl88ee_hw_init()
1138 rtl88ee_enable_hw_security_config(hw); rtl88ee_hw_init()
1143 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); rtl88ee_hw_init()
1144 _rtl88ee_enable_aspm_back_door(hw); rtl88ee_hw_init()
1145 rtlpriv->intf_ops->enable_aspm(hw); rtl88ee_hw_init()
1151 rtl88e_phy_set_rfpath_switch(hw, true); rtl88ee_hw_init()
1154 rtl88e_phy_set_rfpath_switch(hw, false); rtl88ee_hw_init()
1162 rtl88e_phy_iq_calibrate(hw, true); rtl88ee_hw_init()
1164 rtl88e_phy_iq_calibrate(hw, false); rtl88ee_hw_init()
1168 rtl88e_dm_check_txpower_tracking(hw); rtl88ee_hw_init()
1169 rtl88e_phy_lc_calibrate(hw); rtl88ee_hw_init()
1172 tmp_u1b = efuse_read_1byte(hw, 0x1FA); rtl88ee_hw_init()
1174 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); rtl88ee_hw_init()
1187 rtl88e_dm_init(hw); rtl88ee_hw_init()
1194 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw) _rtl88ee_read_chip_version() argument
1196 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_read_chip_version()
1219 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw, _rtl88ee_set_media_status() argument
1222 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_set_media_status()
1270 _rtl88ee_stop_tx_beacon(hw); _rtl88ee_set_media_status()
1271 _rtl88ee_enable_bcn_sub_func(hw); _rtl88ee_set_media_status()
1273 _rtl88ee_resume_tx_beacon(hw); _rtl88ee_set_media_status()
1274 _rtl88ee_disable_bcn_sub_func(hw); _rtl88ee_set_media_status()
1282 rtlpriv->cfg->ops->led_control(hw, ledaction); _rtl88ee_set_media_status()
1290 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) rtl88ee_set_check_bssid() argument
1292 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_check_bssid()
1293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_set_check_bssid()
1301 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, rtl88ee_set_check_bssid()
1303 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); rtl88ee_set_check_bssid()
1306 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0); rtl88ee_set_check_bssid()
1307 rtlpriv->cfg->ops->set_hw_reg(hw, rtl88ee_set_check_bssid()
1313 int rtl88ee_set_network_type(struct ieee80211_hw *hw, rtl88ee_set_network_type() argument
1316 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_network_type()
1318 if (_rtl88ee_set_media_status(hw, type)) rtl88ee_set_network_type()
1324 rtl88ee_set_check_bssid(hw, true); rtl88ee_set_network_type()
1326 rtl88ee_set_check_bssid(hw, false); rtl88ee_set_network_type()
1335 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci) rtl88ee_set_qos() argument
1337 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_qos()
1338 rtl88e_dm_init_edca_turbo(hw); rtl88ee_set_qos()
1357 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw) rtl88ee_enable_interrupt() argument
1359 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_enable_interrupt()
1360 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_enable_interrupt()
1378 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw) rtl88ee_disable_interrupt() argument
1380 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_disable_interrupt()
1381 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_disable_interrupt()
1389 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw) _rtl88ee_poweroff_adapter() argument
1391 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_poweroff_adapter()
1392 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_poweroff_adapter()
1396 rtlpriv->intf_ops->enable_aspm(hw); _rtl88ee_poweroff_adapter()
1417 rtl88e_firmware_selfreset(hw); _rtl88ee_poweroff_adapter()
1448 void rtl88ee_card_disable(struct ieee80211_hw *hw) rtl88ee_card_disable() argument
1450 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_card_disable()
1451 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88ee_card_disable()
1452 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_card_disable()
1460 _rtl88ee_set_media_status(hw, opmode); rtl88ee_card_disable()
1464 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); rtl88ee_card_disable()
1467 _rtl88ee_poweroff_adapter(hw); rtl88ee_card_disable()
1473 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw, rtl88ee_interrupt_recognized() argument
1476 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_interrupt_recognized()
1477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_interrupt_recognized()
1487 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw) rtl88ee_set_beacon_related_registers() argument
1489 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_beacon_related_registers()
1490 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_set_beacon_related_registers()
1491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_set_beacon_related_registers()
1496 rtl88ee_disable_interrupt(hw); rtl88ee_set_beacon_related_registers()
1505 /*rtl88ee_enable_interrupt(hw);*/ rtl88ee_set_beacon_related_registers()
1508 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw) rtl88ee_set_beacon_interval() argument
1510 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_beacon_interval()
1511 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_set_beacon_interval()
1516 /*rtl88ee_disable_interrupt(hw);*/ rtl88ee_set_beacon_interval()
1518 /*rtl88ee_enable_interrupt(hw);*/ rtl88ee_set_beacon_interval()
1521 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw, rtl88ee_update_interrupt_mask() argument
1524 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_update_interrupt_mask()
1525 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl88ee_update_interrupt_mask()
1534 rtl88ee_disable_interrupt(hw); rtl88ee_update_interrupt_mask()
1535 rtl88ee_enable_interrupt(hw); rtl88ee_update_interrupt_mask()
1579 static void read_power_value_fromprom(struct ieee80211_hw *hw, read_power_value_fromprom() argument
1584 struct rtl_priv *rtlpriv = rtl_priv(hw); read_power_value_fromprom()
1769 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, _rtl88ee_read_txpower_info_from_hwpg() argument
1773 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_read_txpower_info_from_hwpg()
1774 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl88ee_read_txpower_info_from_hwpg()
1780 read_power_value_fromprom(hw, &pwrinfo24g, _rtl88ee_read_txpower_info_from_hwpg()
1833 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw) _rtl88ee_read_adapter_info() argument
1835 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_read_adapter_info()
1836 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl88ee_read_adapter_info()
1837 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_read_adapter_info()
1843 rtl_efuse_shadow_map_update(hw); _rtl88ee_read_adapter_info()
1909 _rtl88ee_read_txpower_info_from_hwpg(hw, _rtl88ee_read_adapter_info()
1914 rtl8188ee_read_bt_coexist_info_from_hwpg(hw, _rtl88ee_read_adapter_info()
1981 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw) _rtl88ee_hal_customized_behavior() argument
1983 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl88ee_hal_customized_behavior()
1984 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl88ee_hal_customized_behavior()
1985 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl88ee_hal_customized_behavior()
2006 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw) rtl88ee_read_eeprom_info() argument
2008 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_read_eeprom_info()
2009 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88ee_read_eeprom_info()
2011 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88ee_read_eeprom_info()
2014 rtlhal->version = _rtl88ee_read_chip_version(hw); rtl88ee_read_eeprom_info()
2033 _rtl88ee_read_adapter_info(hw); rtl88ee_read_eeprom_info()
2037 _rtl88ee_hal_customized_behavior(hw); rtl88ee_read_eeprom_info()
2040 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw, rtl88ee_update_hal_rate_table() argument
2043 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_update_hal_rate_table()
2045 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_update_hal_rate_table()
2046 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88ee_update_hal_rate_table()
2130 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw, rtl88ee_update_hal_rate_mask() argument
2133 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_update_hal_rate_mask()
2135 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_update_hal_rate_mask()
2136 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl88ee_update_hal_rate_mask()
2257 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask); rtl88ee_update_hal_rate_mask()
2258 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl88ee_update_hal_rate_mask()
2261 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw, rtl88ee_update_hal_rate_tbl() argument
2264 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_update_hal_rate_tbl()
2267 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level); rtl88ee_update_hal_rate_tbl()
2269 rtl88ee_update_hal_rate_table(hw, sta); rtl88ee_update_hal_rate_tbl()
2272 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw) rtl88ee_update_channel_access_setting() argument
2274 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_update_channel_access_setting()
2275 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_update_channel_access_setting()
2278 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); rtl88ee_update_channel_access_setting()
2283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); rtl88ee_update_channel_access_setting()
2286 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) rtl88ee_gpio_radio_on_off_checking() argument
2288 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_gpio_radio_on_off_checking()
2289 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl88ee_gpio_radio_on_off_checking()
2349 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index, rtl88ee_set_key() argument
2353 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl88ee_set_key()
2354 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl88ee_set_key()
2355 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl88ee_set_key()
2377 rtl_cam_mark_invalid(hw, cam_offset + idx); rtl88ee_set_key()
2378 rtl_cam_empty_entry(hw, cam_offset + idx); rtl88ee_set_key()
2419 rtl_cam_get_free_entry(hw, p_macaddr); rtl88ee_set_key()
2423 "Can not find free hw security cam entry\n"); rtl88ee_set_key()
2440 rtl_cam_del_entry(hw, p_macaddr); rtl88ee_set_key()
2441 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); rtl88ee_set_key()
2449 rtl_cam_add_one_entry(hw, macaddr, key_index, rtl88ee_set_key()
2458 rtl_cam_add_one_entry(hw, rtl88ee_set_key()
2468 rtl_cam_add_one_entry(hw, macaddr, key_index, rtl88ee_set_key()
2478 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw) rtl8188ee_bt_var_init() argument
2480 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8188ee_bt_var_init()
2515 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, rtl8188ee_read_bt_coexist_info_from_hwpg() argument
2518 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8188ee_read_bt_coexist_info_from_hwpg()
2540 rtl8188ee_bt_var_init(hw); rtl8188ee_read_bt_coexist_info_from_hwpg()
2543 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw) rtl8188ee_bt_reg_init() argument
2545 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8188ee_bt_reg_init()
2555 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw) rtl8188ee_bt_hw_init() argument
2557 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8188ee_bt_hw_init()
2593 void rtl88ee_suspend(struct ieee80211_hw *hw) rtl88ee_suspend() argument
2597 void rtl88ee_resume(struct ieee80211_hw *hw) rtl88ee_resume() argument
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dhw.h33 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw);
35 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
37 int rtl92de_hw_init(struct ieee80211_hw *hw);
38 void rtl92de_card_disable(struct ieee80211_hw *hw);
39 void rtl92de_enable_interrupt(struct ieee80211_hw *hw);
40 void rtl92de_disable_interrupt(struct ieee80211_hw *hw);
41 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
42 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
43 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci);
44 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw);
45 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw);
46 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
48 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
49 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
51 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw);
52 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
53 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw);
54 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
58 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, u16 offset, u32 value,
60 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct);
61 void rtl92de_suspend(struct ieee80211_hw *hw);
62 void rtl92de_resume(struct ieee80211_hw *hw);
63 void rtl92d_linked_set_reg(struct ieee80211_hw *hw);
H A DMakefile4 hw.o \
H A Dphy.c41 #include "hw.h"
201 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl92d_phy_query_bb_reg() argument
203 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_query_bb_reg()
218 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr, rtl92d_phy_query_bb_reg()
231 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, rtl92d_phy_set_bb_reg() argument
234 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_bb_reg()
250 originalvalue = rtl92de_read_dword_dbi(hw, rtl92d_phy_set_bb_reg()
259 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct); rtl92d_phy_set_bb_reg()
267 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, _rtl92d_phy_rf_serial_read() argument
271 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_rf_serial_read()
280 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92d_phy_rf_serial_read()
284 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92d_phy_rf_serial_read()
287 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92d_phy_rf_serial_read()
290 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92d_phy_rf_serial_read()
293 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92d_phy_rf_serial_read()
297 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, _rtl92d_phy_rf_serial_read()
300 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, _rtl92d_phy_rf_serial_read()
303 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, _rtl92d_phy_rf_serial_read()
306 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, _rtl92d_phy_rf_serial_read()
313 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, _rtl92d_phy_rf_serial_write() argument
319 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_rf_serial_write()
326 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92d_phy_rf_serial_write()
331 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, rtl92d_phy_query_rf_reg() argument
334 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_query_rf_reg()
342 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); rtl92d_phy_query_rf_reg()
352 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, rtl92d_phy_set_rf_reg() argument
355 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_rf_reg()
368 original_value = _rtl92d_phy_rf_serial_read(hw, rtl92d_phy_set_rf_reg()
374 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); rtl92d_phy_set_rf_reg()
382 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) rtl92d_phy_mac_config() argument
384 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_mac_config()
408 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) _rtl92d_phy_init_bb_rf_register_definition() argument
410 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_init_bb_rf_register_definition()
535 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, _rtl92d_phy_config_bb_with_headerfile() argument
543 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_config_bb_with_headerfile()
544 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92d_phy_config_bb_with_headerfile()
573 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl92d_phy_config_bb_with_headerfile()
584 rtl_set_bbreg(hw, agctab_array_table[i], _rtl92d_phy_config_bb_with_headerfile()
600 rtl_set_bbreg(hw, agctab_array_table[i], _rtl92d_phy_config_bb_with_headerfile()
615 rtl_set_bbreg(hw, _rtl92d_phy_config_bb_with_headerfile()
635 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, _rtl92d_store_pwrindex_diffrate_offset() argument
639 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_store_pwrindex_diffrate_offset()
687 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, _rtl92d_phy_config_bb_with_pgheaderfile() argument
690 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_config_bb_with_pgheaderfile()
700 _rtl92d_store_pwrindex_diffrate_offset(hw, _rtl92d_phy_config_bb_with_pgheaderfile()
712 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw) _rtl92d_phy_bb_config() argument
714 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_bb_config()
716 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92d_phy_bb_config()
720 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, _rtl92d_phy_bb_config()
728 * _rtl92c_phy_bb_config_1t(hw); _rtl92d_phy_bb_config()
734 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw, _rtl92d_phy_bb_config()
741 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, _rtl92d_phy_bb_config()
747 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, _rtl92d_phy_bb_config()
753 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) rtl92d_phy_bb_config() argument
755 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_bb_config()
760 _rtl92d_phy_init_bb_rf_register_definition(hw); rtl92d_phy_bb_config()
778 return _rtl92d_phy_bb_config(hw); rtl92d_phy_bb_config()
781 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw) rtl92d_phy_rf_config() argument
783 return rtl92d_phy_rf6052_config(hw); rtl92d_phy_rf_config()
786 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl92d_phy_config_rf_with_headerfile() argument
794 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_config_rf_with_headerfile()
826 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], rtl92d_phy_config_rf_with_headerfile()
833 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], rtl92d_phy_config_rf_with_headerfile()
850 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl92d_phy_get_hw_reg_originalvalue() argument
852 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_get_hw_reg_originalvalue()
856 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl92d_phy_get_hw_reg_originalvalue()
858 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl92d_phy_get_hw_reg_originalvalue()
860 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl92d_phy_get_hw_reg_originalvalue()
862 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl92d_phy_get_hw_reg_originalvalue()
869 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, rtl92d_phy_get_hw_reg_originalvalue()
871 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, rtl92d_phy_get_hw_reg_originalvalue()
878 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, _rtl92d_get_txpower_index() argument
881 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_get_txpower_index()
884 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92d_get_txpower_index()
915 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, _rtl92d_ccxpower_index_check() argument
918 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_ccxpower_index_check()
948 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl92d_phy_set_txpower_level() argument
950 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92d_phy_set_txpower_level()
951 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_txpower_level()
957 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], rtl92d_phy_set_txpower_level()
960 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], rtl92d_phy_set_txpower_level()
963 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); rtl92d_phy_set_txpower_level()
964 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); rtl92d_phy_set_txpower_level()
967 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, rtl92d_phy_set_bw_mode() argument
970 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_bw_mode()
972 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_set_bw_mode()
973 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92d_phy_set_bw_mode()
980 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { rtl92d_phy_set_bw_mode()
1011 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl92d_phy_set_bw_mode()
1012 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl92d_phy_set_bw_mode()
1014 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | rtl92d_phy_set_bw_mode()
1018 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl92d_phy_set_bw_mode()
1019 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl92d_phy_set_bw_mode()
1023 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); rtl92d_phy_set_bw_mode()
1024 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, rtl92d_phy_set_bw_mode()
1026 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); rtl92d_phy_set_bw_mode()
1028 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); rtl92d_phy_set_bw_mode()
1030 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | rtl92d_phy_set_bw_mode()
1032 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl92d_phy_set_bw_mode()
1042 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl92d_phy_set_bw_mode()
1047 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) _rtl92d_phy_stop_trx_before_changeband() argument
1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); _rtl92d_phy_stop_trx_before_changeband()
1050 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); _rtl92d_phy_stop_trx_before_changeband()
1051 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); _rtl92d_phy_stop_trx_before_changeband()
1052 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); _rtl92d_phy_stop_trx_before_changeband()
1055 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) rtl92d_phy_switch_wirelessband() argument
1057 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_switch_wirelessband()
1058 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_switch_wirelessband()
1067 _rtl92d_phy_stop_trx_before_changeband(hw); rtl92d_phy_switch_wirelessband()
1073 _rtl92d_phy_config_bb_with_headerfile(hw, rtl92d_phy_switch_wirelessband()
1079 _rtl92d_phy_config_bb_with_headerfile(hw, rtl92d_phy_switch_wirelessband()
1082 rtl92d_update_bbrf_configuration(hw); rtl92d_phy_switch_wirelessband()
1084 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); rtl92d_phy_switch_wirelessband()
1085 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); rtl92d_phy_switch_wirelessband()
1088 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ rtl92d_phy_switch_wirelessband()
1108 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, _rtl92d_phy_reload_imr_setting() argument
1111 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_reload_imr_setting()
1120 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); _rtl92d_phy_reload_imr_setting()
1121 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); _rtl92d_phy_reload_imr_setting()
1124 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | _rtl92d_phy_reload_imr_setting()
1127 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | _rtl92d_phy_reload_imr_setting()
1133 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl92d_phy_reload_imr_setting()
1136 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); _rtl92d_phy_reload_imr_setting()
1137 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); _rtl92d_phy_reload_imr_setting()
1148 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); _rtl92d_phy_reload_imr_setting()
1149 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); _rtl92d_phy_reload_imr_setting()
1150 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, _rtl92d_phy_reload_imr_setting()
1154 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl92d_phy_reload_imr_setting()
1159 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, _rtl92d_phy_reload_imr_setting()
1161 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); _rtl92d_phy_reload_imr_setting()
1162 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); _rtl92d_phy_reload_imr_setting()
1168 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, _rtl92d_phy_enable_rf_env() argument
1171 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_enable_rf_env()
1180 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); _rtl92d_phy_enable_rf_env()
1185 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); _rtl92d_phy_enable_rf_env()
1189 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); _rtl92d_phy_enable_rf_env()
1192 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); _rtl92d_phy_enable_rf_env()
1196 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); _rtl92d_phy_enable_rf_env()
1199 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); _rtl92d_phy_enable_rf_env()
1204 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, _rtl92d_phy_restore_rf_env() argument
1207 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_restore_rf_env()
1216 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); _rtl92d_phy_restore_rf_env()
1220 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, _rtl92d_phy_restore_rf_env()
1227 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) _rtl92d_phy_switch_rf_setting() argument
1229 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_switch_rf_setting()
1263 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false); _rtl92d_phy_switch_rf_setting()
1267 _rtl92d_phy_enable_rf_env(hw, path, _rtl92d_phy_switch_rf_setting()
1272 rtl_set_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1280 rtl_set_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1284 rtl_set_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1294 rtl_get_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1299 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); _rtl92d_phy_switch_rf_setting()
1301 rtl92d_phy_powerdown_anotherphy(hw, false); _rtl92d_phy_switch_rf_setting()
1324 rtl_set_rfreg(hw, rfpath, _rtl92d_phy_switch_rf_setting()
1335 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, _rtl92d_phy_switch_rf_setting()
1355 rtl92d_phy_enable_anotherphy(hw, true); _rtl92d_phy_switch_rf_setting()
1359 _rtl92d_phy_enable_rf_env(hw, path, _rtl92d_phy_switch_rf_setting()
1365 rtl_set_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1371 rtl_set_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1381 rtl_get_rfreg(hw, (enum radio_path)path, _rtl92d_phy_switch_rf_setting()
1389 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, _rtl92d_phy_switch_rf_setting()
1393 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); _rtl92d_phy_switch_rf_setting()
1395 rtl92d_phy_powerdown_anotherphy(hw, true); _rtl92d_phy_switch_rf_setting()
1427 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) _rtl92d_phy_patha_iqk() argument
1429 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_patha_iqk()
1430 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92d_phy_patha_iqk()
1438 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); _rtl92d_phy_patha_iqk()
1439 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); _rtl92d_phy_patha_iqk()
1441 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk()
1442 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk()
1444 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); _rtl92d_phy_patha_iqk()
1445 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); _rtl92d_phy_patha_iqk()
1448 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk()
1449 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk()
1450 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); _rtl92d_phy_patha_iqk()
1451 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); _rtl92d_phy_patha_iqk()
1455 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl92d_phy_patha_iqk()
1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl92d_phy_patha_iqk()
1459 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92d_phy_patha_iqk()
1466 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_patha_iqk()
1468 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92d_phy_patha_iqk()
1470 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92d_phy_patha_iqk()
1472 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl92d_phy_patha_iqk()
1489 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, _rtl92d_phy_patha_iqk_5g_normal() argument
1492 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_patha_iqk_5g_normal()
1493 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92d_phy_patha_iqk_5g_normal()
1508 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); _rtl92d_phy_patha_iqk_5g_normal()
1509 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); _rtl92d_phy_patha_iqk_5g_normal()
1510 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); _rtl92d_phy_patha_iqk_5g_normal()
1511 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); _rtl92d_phy_patha_iqk_5g_normal()
1514 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); _rtl92d_phy_patha_iqk_5g_normal()
1515 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); _rtl92d_phy_patha_iqk_5g_normal()
1516 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); _rtl92d_phy_patha_iqk_5g_normal()
1517 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); _rtl92d_phy_patha_iqk_5g_normal()
1521 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl92d_phy_patha_iqk_5g_normal()
1523 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); _rtl92d_phy_patha_iqk_5g_normal()
1524 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); _rtl92d_phy_patha_iqk_5g_normal()
1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl92d_phy_patha_iqk_5g_normal()
1530 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92d_phy_patha_iqk_5g_normal()
1537 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal()
1539 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal()
1541 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal()
1543 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal()
1565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, _rtl92d_phy_patha_iqk_5g_normal()
1567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, _rtl92d_phy_patha_iqk_5g_normal()
1573 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw) _rtl92d_phy_pathb_iqk() argument
1575 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_pathb_iqk()
1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl92d_phy_pathb_iqk()
1583 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl92d_phy_pathb_iqk()
1589 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_pathb_iqk()
1591 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92d_phy_pathb_iqk()
1593 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92d_phy_pathb_iqk()
1595 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl92d_phy_pathb_iqk()
1597 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl92d_phy_pathb_iqk()
1613 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) _rtl92d_phy_pathb_iqk_5g_normal() argument
1615 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_pathb_iqk_5g_normal()
1625 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); _rtl92d_phy_pathb_iqk_5g_normal()
1626 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); _rtl92d_phy_pathb_iqk_5g_normal()
1627 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); _rtl92d_phy_pathb_iqk_5g_normal()
1628 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); _rtl92d_phy_pathb_iqk_5g_normal()
1631 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); _rtl92d_phy_pathb_iqk_5g_normal()
1632 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); _rtl92d_phy_pathb_iqk_5g_normal()
1633 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); _rtl92d_phy_pathb_iqk_5g_normal()
1634 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); _rtl92d_phy_pathb_iqk_5g_normal()
1638 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl92d_phy_pathb_iqk_5g_normal()
1641 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); _rtl92d_phy_pathb_iqk_5g_normal()
1642 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); _rtl92d_phy_pathb_iqk_5g_normal()
1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); _rtl92d_phy_pathb_iqk_5g_normal()
1649 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92d_phy_pathb_iqk_5g_normal()
1657 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal()
1659 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal()
1661 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal()
1663 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal()
1665 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal()
1683 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, _rtl92d_phy_pathb_iqk_5g_normal()
1685 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, _rtl92d_phy_pathb_iqk_5g_normal()
1690 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, _rtl92d_phy_save_adda_registers() argument
1694 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_save_adda_registers()
1699 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); _rtl92d_phy_save_adda_registers()
1702 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, _rtl92d_phy_save_mac_registers() argument
1705 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_save_mac_registers()
1714 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, _rtl92d_phy_reload_adda_registers() argument
1718 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_reload_adda_registers()
1724 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); _rtl92d_phy_reload_adda_registers()
1727 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, _rtl92d_phy_reload_mac_registers() argument
1730 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_reload_mac_registers()
1739 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, _rtl92d_phy_path_adda_on() argument
1742 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_path_adda_on()
1752 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); _rtl92d_phy_path_adda_on()
1755 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, _rtl92d_phy_mac_setting_calibration() argument
1758 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_mac_setting_calibration()
1770 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) _rtl92d_phy_patha_standby() argument
1772 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_patha_standby()
1775 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl92d_phy_patha_standby()
1776 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); _rtl92d_phy_patha_standby()
1777 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92d_phy_patha_standby()
1780 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) _rtl92d_phy_pimode_switch() argument
1782 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_pimode_switch()
1788 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); _rtl92d_phy_pimode_switch()
1789 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); _rtl92d_phy_pimode_switch()
1792 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], _rtl92d_phy_iq_calibrate() argument
1795 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_iq_calibrate()
1820 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); _rtl92d_phy_iq_calibrate()
1826 _rtl92d_phy_save_adda_registers(hw, adda_reg, _rtl92d_phy_iq_calibrate()
1828 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, _rtl92d_phy_iq_calibrate()
1830 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate()
1833 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl92d_phy_iq_calibrate()
1835 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, _rtl92d_phy_iq_calibrate()
1840 _rtl92d_phy_pimode_switch(hw, true); _rtl92d_phy_iq_calibrate()
1842 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); _rtl92d_phy_iq_calibrate()
1843 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); _rtl92d_phy_iq_calibrate()
1844 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); _rtl92d_phy_iq_calibrate()
1845 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); _rtl92d_phy_iq_calibrate()
1846 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); _rtl92d_phy_iq_calibrate()
1848 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, _rtl92d_phy_iq_calibrate()
1850 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, _rtl92d_phy_iq_calibrate()
1854 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl92d_phy_iq_calibrate()
1857 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate()
1859 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate()
1862 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92d_phy_iq_calibrate()
1863 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl92d_phy_iq_calibrate()
1864 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl92d_phy_iq_calibrate()
1866 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); _rtl92d_phy_iq_calibrate()
1870 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate()
1872 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate()
1874 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl92d_phy_iq_calibrate()
1876 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl92d_phy_iq_calibrate()
1884 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate()
1886 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate()
1893 _rtl92d_phy_patha_standby(hw); _rtl92d_phy_iq_calibrate()
1895 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); _rtl92d_phy_iq_calibrate()
1897 pathb_ok = _rtl92d_phy_pathb_iqk(hw); _rtl92d_phy_iq_calibrate()
1901 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, _rtl92d_phy_iq_calibrate()
1903 result[t][5] = (rtl_get_bbreg(hw, 0xebc, _rtl92d_phy_iq_calibrate()
1905 result[t][6] = (rtl_get_bbreg(hw, 0xec4, _rtl92d_phy_iq_calibrate()
1907 result[t][7] = (rtl_get_bbreg(hw, 0xecc, _rtl92d_phy_iq_calibrate()
1914 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, _rtl92d_phy_iq_calibrate()
1916 result[t][5] = (rtl_get_bbreg(hw, 0xebc, _rtl92d_phy_iq_calibrate()
1929 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl92d_phy_iq_calibrate()
1933 _rtl92d_phy_pimode_switch(hw, false); _rtl92d_phy_iq_calibrate()
1935 _rtl92d_phy_reload_adda_registers(hw, adda_reg, _rtl92d_phy_iq_calibrate()
1938 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl92d_phy_iq_calibrate()
1941 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate()
1945 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate()
1949 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); _rtl92d_phy_iq_calibrate()
1950 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); _rtl92d_phy_iq_calibrate()
1955 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, _rtl92d_phy_iq_calibrate_5g_normal() argument
1958 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_iq_calibrate_5g_normal()
1987 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); _rtl92d_phy_iq_calibrate_5g_normal()
1992 _rtl92d_phy_save_adda_registers(hw, adda_reg, _rtl92d_phy_iq_calibrate_5g_normal()
1995 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, _rtl92d_phy_iq_calibrate_5g_normal()
1998 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2002 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2006 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl92d_phy_iq_calibrate_5g_normal()
2008 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2011 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, _rtl92d_phy_iq_calibrate_5g_normal()
2015 _rtl92d_phy_pimode_switch(hw, true); _rtl92d_phy_iq_calibrate_5g_normal()
2016 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); _rtl92d_phy_iq_calibrate_5g_normal()
2017 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); _rtl92d_phy_iq_calibrate_5g_normal()
2018 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); _rtl92d_phy_iq_calibrate_5g_normal()
2019 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); _rtl92d_phy_iq_calibrate_5g_normal()
2020 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); _rtl92d_phy_iq_calibrate_5g_normal()
2023 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate_5g_normal()
2025 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate_5g_normal()
2028 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92d_phy_iq_calibrate_5g_normal()
2029 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); _rtl92d_phy_iq_calibrate_5g_normal()
2030 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl92d_phy_iq_calibrate_5g_normal()
2031 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); _rtl92d_phy_iq_calibrate_5g_normal()
2034 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2036 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2038 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2040 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2046 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2048 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2054 /* _rtl92d_phy_patha_standby(hw); */ _rtl92d_phy_iq_calibrate_5g_normal()
2056 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); _rtl92d_phy_iq_calibrate_5g_normal()
2057 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); _rtl92d_phy_iq_calibrate_5g_normal()
2061 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2063 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2065 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2067 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2072 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2074 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal()
2085 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl92d_phy_iq_calibrate_5g_normal()
2088 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2092 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2096 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2100 _rtl92d_phy_pimode_switch(hw, false); _rtl92d_phy_iq_calibrate_5g_normal()
2102 _rtl92d_phy_reload_adda_registers(hw, adda_reg, _rtl92d_phy_iq_calibrate_5g_normal()
2109 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, _rtl92d_phy_simularity_compare() argument
2112 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_simularity_compare()
2168 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl92d_phy_patha_fill_iqk_matrix() argument
2172 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_patha_fill_iqk_matrix()
2184 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, _rtl92d_phy_patha_fill_iqk_matrix()
2193 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a); _rtl92d_phy_patha_fill_iqk_matrix()
2194 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), _rtl92d_phy_patha_fill_iqk_matrix()
2207 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, _rtl92d_phy_patha_fill_iqk_matrix()
2209 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000, _rtl92d_phy_patha_fill_iqk_matrix()
2212 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), _rtl92d_phy_patha_fill_iqk_matrix()
2215 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, _rtl92d_phy_patha_fill_iqk_matrix()
2222 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); _rtl92d_phy_patha_fill_iqk_matrix()
2224 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); _rtl92d_phy_patha_fill_iqk_matrix()
2226 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); _rtl92d_phy_patha_fill_iqk_matrix()
2230 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl92d_phy_pathb_fill_iqk_matrix() argument
2233 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_pathb_fill_iqk_matrix()
2243 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, _rtl92d_phy_pathb_fill_iqk_matrix()
2251 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a); _rtl92d_phy_pathb_fill_iqk_matrix()
2252 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), _rtl92d_phy_pathb_fill_iqk_matrix()
2262 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, _rtl92d_phy_pathb_fill_iqk_matrix()
2264 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000, _rtl92d_phy_pathb_fill_iqk_matrix()
2266 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), _rtl92d_phy_pathb_fill_iqk_matrix()
2271 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); _rtl92d_phy_pathb_fill_iqk_matrix()
2273 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); _rtl92d_phy_pathb_fill_iqk_matrix()
2275 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); _rtl92d_phy_pathb_fill_iqk_matrix()
2279 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw) rtl92d_phy_iq_calibrate() argument
2281 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_iq_calibrate()
2308 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); rtl92d_phy_iq_calibrate()
2311 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i); rtl92d_phy_iq_calibrate()
2314 _rtl92d_phy_iq_calibrate(hw, result, i, true); rtl92d_phy_iq_calibrate()
2316 _rtl92d_phy_iq_calibrate(hw, result, i, false); rtl92d_phy_iq_calibrate()
2319 is12simular = _rtl92d_phy_simularity_compare(hw, result, rtl92d_phy_iq_calibrate()
2327 is13simular = _rtl92d_phy_simularity_compare(hw, result, rtl92d_phy_iq_calibrate()
2333 is23simular = _rtl92d_phy_simularity_compare(hw, result, rtl92d_phy_iq_calibrate()
2348 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); rtl92d_phy_iq_calibrate()
2384 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result, rtl92d_phy_iq_calibrate()
2388 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, rtl92d_phy_iq_calibrate()
2406 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) rtl92d_phy_reload_iqk_setting() argument
2408 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_reload_iqk_setting()
2424 rtl92d_phy_iq_calibrate(hw); rtl92d_phy_reload_iqk_setting()
2436 _rtl92d_phy_patha_fill_iqk_matrix(hw, true, rtl92d_phy_reload_iqk_setting()
2445 _rtl92d_phy_pathb_fill_iqk_matrix(hw, rtl92d_phy_reload_iqk_setting()
2470 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) _rtl92d_is_legal_5g_channel() argument
2488 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, _rtl92d_phy_calc_curvindex() argument
2492 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_calc_curvindex()
2498 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) _rtl92d_phy_calc_curvindex()
2516 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, _rtl92d_phy_reload_lck_setting() argument
2519 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_reload_lck_setting()
2538 rtl92d_phy_enable_anotherphy(hw, false); _rtl92d_phy_reload_lck_setting()
2542 _rtl92d_phy_enable_rf_env(hw, erfpath, _rtl92d_phy_reload_lck_setting()
2545 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); _rtl92d_phy_reload_lck_setting()
2547 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); _rtl92d_phy_reload_lck_setting()
2549 rtl92d_phy_powerdown_anotherphy(hw, false); _rtl92d_phy_reload_lck_setting()
2557 rtl92d_phy_enable_anotherphy(hw, true); _rtl92d_phy_reload_lck_setting()
2560 _rtl92d_phy_enable_rf_env(hw, erfpath, _rtl92d_phy_reload_lck_setting()
2563 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); _rtl92d_phy_reload_lck_setting()
2566 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); _rtl92d_phy_reload_lck_setting()
2568 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); _rtl92d_phy_reload_lck_setting()
2570 rtl92d_phy_powerdown_anotherphy(hw, true); _rtl92d_phy_reload_lck_setting()
2575 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) _rtl92d_phy_lc_calibrate_sw() argument
2577 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_lc_calibrate_sw()
2579 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl92d_phy_lc_calibrate_sw()
2595 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); _rtl92d_phy_lc_calibrate_sw()
2601 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, _rtl92d_phy_lc_calibrate_sw()
2605 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, _rtl92d_phy_lc_calibrate_sw()
2608 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, _rtl92d_phy_lc_calibrate_sw()
2611 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, _rtl92d_phy_lc_calibrate_sw()
2616 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, _rtl92d_phy_lc_calibrate_sw()
2621 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); _rtl92d_phy_lc_calibrate_sw()
2631 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, _rtl92d_phy_lc_calibrate_sw()
2637 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, _rtl92d_phy_lc_calibrate_sw()
2640 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, _rtl92d_phy_lc_calibrate_sw()
2642 readval = rtl_get_rfreg(hw, (enum radio_path)index, _rtl92d_phy_lc_calibrate_sw()
2647 readval2 = rtl_get_rfreg(hw, (enum radio_path)index, _rtl92d_phy_lc_calibrate_sw()
2653 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, _rtl92d_phy_lc_calibrate_sw()
2657 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, _rtl92d_phy_lc_calibrate_sw()
2661 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, _rtl92d_phy_lc_calibrate_sw()
2675 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); _rtl92d_phy_lc_calibrate_sw()
2676 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); _rtl92d_phy_lc_calibrate_sw()
2679 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl92d_phy_lc_calibrate() argument
2681 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_lc_calibrate()
2684 _rtl92d_phy_lc_calibrate_sw(hw, is2t); _rtl92d_phy_lc_calibrate()
2687 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) rtl92d_phy_lc_calibrate() argument
2689 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_lc_calibrate()
2704 _rtl92d_phy_lc_calibrate(hw, true); rtl92d_phy_lc_calibrate()
2707 _rtl92d_phy_lc_calibrate(hw, false); rtl92d_phy_lc_calibrate()
2713 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) rtl92d_phy_ap_calibrate() argument
2739 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) rtl92d_phy_reset_iqk_result() argument
2741 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_reset_iqk_result()
2764 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, _rtl92d_phy_sw_chnl_step_by_step() argument
2768 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_sw_chnl_step_by_step()
2820 rtl92d_phy_set_txpower_level(hw, channel); _rtl92d_phy_sw_chnl_step_by_step()
2855 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl92d_phy_sw_chnl_step_by_step()
2859 _rtl92d_phy_reload_imr_setting(hw, channel, _rtl92d_phy_sw_chnl_step_by_step()
2862 _rtl92d_phy_switch_rf_setting(hw, channel); _rtl92d_phy_sw_chnl_step_by_step()
2864 rtl92d_phy_reload_iqk_setting(hw, channel); _rtl92d_phy_sw_chnl_step_by_step()
2878 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) rtl92d_phy_sw_chnl() argument
2880 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_sw_chnl()
2882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_sw_chnl()
2893 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { rtl92d_phy_sw_chnl()
2904 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, rtl92d_phy_sw_chnl()
2907 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); rtl92d_phy_sw_chnl()
2909 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G); rtl92d_phy_sw_chnl()
2942 if (!_rtl92d_phy_sw_chnl_step_by_step(hw, rtl92d_phy_sw_chnl()
2959 static void rtl92d_phy_set_io(struct ieee80211_hw *hw) rtl92d_phy_set_io() argument
2961 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_io()
2971 rtl92d_dm_write_dig(hw); rtl92d_phy_set_io()
2972 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); rtl92d_phy_set_io()
2977 rtl92d_dm_write_dig(hw); rtl92d_phy_set_io()
2989 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl92d_phy_set_io_cmd() argument
2991 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_io_cmd()
3022 rtl92d_phy_set_io(hw); rtl92d_phy_set_io_cmd()
3027 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) _rtl92d_phy_set_rfon() argument
3029 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_set_rfon()
3048 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw) _rtl92d_phy_set_rfsleep() argument
3050 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92d_phy_set_rfsleep()
3057 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92d_phy_set_rfsleep()
3065 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl92d_phy_set_rfsleep()
3068 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92d_phy_set_rfsleep()
3070 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl92d_phy_set_rfsleep()
3092 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl92d_phy_set_rf_power_state() argument
3097 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_rf_power_state()
3098 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl92d_phy_set_rf_power_state()
3099 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92d_phy_set_rf_power_state()
3100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92d_phy_set_rf_power_state()
3101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl92d_phy_set_rf_power_state()
3117 rtstatus = rtl_ps_enable_nic(hw); rtl92d_phy_set_rf_power_state()
3129 _rtl92d_phy_set_rfon(hw); rtl92d_phy_set_rf_power_state()
3133 rtlpriv->cfg->ops->led_control(hw, rtl92d_phy_set_rf_power_state()
3136 rtlpriv->cfg->ops->led_control(hw, rtl92d_phy_set_rf_power_state()
3143 rtl_ps_disable_nic(hw); rtl92d_phy_set_rf_power_state()
3147 rtlpriv->cfg->ops->led_control(hw, rtl92d_phy_set_rf_power_state()
3150 rtlpriv->cfg->ops->led_control(hw, rtl92d_phy_set_rf_power_state()
3196 _rtl92d_phy_set_rfsleep(hw); rtl92d_phy_set_rf_power_state()
3209 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) rtl92d_phy_config_macphymode() argument
3211 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_config_macphymode()
3212 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_config_macphymode()
3234 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) rtl92d_phy_config_macphymode_info() argument
3236 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_config_macphymode_info()
3237 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_config_macphymode_info()
3312 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) rtl92d_phy_set_poweron() argument
3314 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_set_poweron()
3315 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_set_poweron()
3363 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) rtl92d_phy_config_maccoexist_rfpage() argument
3365 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_config_maccoexist_rfpage()
3388 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) rtl92d_update_bbrf_configuration() argument
3390 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_update_bbrf_configuration()
3391 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_update_bbrf_configuration()
3393 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92d_update_bbrf_configuration()
3400 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); rtl92d_update_bbrf_configuration()
3401 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); rtl92d_update_bbrf_configuration()
3403 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); rtl92d_update_bbrf_configuration()
3404 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); rtl92d_update_bbrf_configuration()
3407 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); rtl92d_update_bbrf_configuration()
3409 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); rtl92d_update_bbrf_configuration()
3411 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); rtl92d_update_bbrf_configuration()
3413 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration()
3415 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration()
3418 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, rtl92d_update_bbrf_configuration()
3423 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, rtl92d_update_bbrf_configuration()
3428 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); rtl92d_update_bbrf_configuration()
3430 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, rtl92d_update_bbrf_configuration()
3439 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, rtl92d_update_bbrf_configuration()
3444 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, rtl92d_update_bbrf_configuration()
3449 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, rtl92d_update_bbrf_configuration()
3455 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); rtl92d_update_bbrf_configuration()
3456 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); rtl92d_update_bbrf_configuration()
3458 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); rtl92d_update_bbrf_configuration()
3459 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); rtl92d_update_bbrf_configuration()
3462 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); rtl92d_update_bbrf_configuration()
3464 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); rtl92d_update_bbrf_configuration()
3466 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); rtl92d_update_bbrf_configuration()
3469 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration()
3472 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration()
3475 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration()
3478 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration()
3481 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, rtl92d_update_bbrf_configuration()
3484 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), rtl92d_update_bbrf_configuration()
3486 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), rtl92d_update_bbrf_configuration()
3489 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, rtl92d_update_bbrf_configuration()
3494 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), rtl92d_update_bbrf_configuration()
3496 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), rtl92d_update_bbrf_configuration()
3498 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, rtl92d_update_bbrf_configuration()
3505 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); rtl92d_update_bbrf_configuration()
3506 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); rtl92d_update_bbrf_configuration()
3507 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); rtl92d_update_bbrf_configuration()
3508 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | rtl92d_update_bbrf_configuration()
3510 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00); rtl92d_update_bbrf_configuration()
3511 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); rtl92d_update_bbrf_configuration()
3512 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); rtl92d_update_bbrf_configuration()
3519 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | rtl92d_update_bbrf_configuration()
3522 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, rtl92d_update_bbrf_configuration()
3526 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | rtl92d_update_bbrf_configuration()
3535 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); rtl92d_update_bbrf_configuration()
3536 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); rtl92d_update_bbrf_configuration()
3540 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | rtl92d_update_bbrf_configuration()
3543 rtl92d_phy_enable_anotherphy(hw, false); rtl92d_update_bbrf_configuration()
3547 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN, rtl92d_update_bbrf_configuration()
3548 rtl92de_read_dword_dbi(hw, rtl92d_update_bbrf_configuration()
3552 rtl92d_phy_powerdown_anotherphy(hw, false); rtl92d_update_bbrf_configuration()
3557 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); rtl92d_update_bbrf_configuration()
3558 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); rtl92d_update_bbrf_configuration()
3560 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); rtl92d_update_bbrf_configuration()
3564 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, rtl92d_update_bbrf_configuration()
3566 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, rtl92d_update_bbrf_configuration()
3576 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw) rtl92d_phy_check_poweroff() argument
3578 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_phy_check_poweroff()
3579 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92d_phy_check_poweroff()
H A Dphy.h39 #define RT_CANNOT_IO(hw) false
109 static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, rtl92d_acquire_cckandrw_pagea_ctl() argument
112 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_acquire_cckandrw_pagea_ctl()
118 static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, rtl92d_release_cckandrw_pagea_ctl() argument
121 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92d_release_cckandrw_pagea_ctl()
128 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
130 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
132 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
135 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
138 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
139 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
140 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
141 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
143 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
144 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
145 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
147 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
148 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
151 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
152 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
155 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
156 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
158 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
159 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
160 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
161 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
162 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
163 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
164 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
165 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
166 void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
168 void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
171 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhw.h33 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw);
36 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
38 int rtl8723e_hw_init(struct ieee80211_hw *hw);
39 void rtl8723e_card_disable(struct ieee80211_hw *hw);
40 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw);
41 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw);
42 int rtl8723e_set_network_type(struct ieee80211_hw *hw,
44 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
45 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci);
46 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw);
47 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw);
48 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
50 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
51 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
53 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw);
54 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
55 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw);
56 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
60 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
62 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw);
63 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw);
64 void rtl8723e_suspend(struct ieee80211_hw *hw);
65 void rtl8723e_resume(struct ieee80211_hw *hw);
H A Dphy.c37 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
40 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
41 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
42 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
44 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
46 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
49 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
52 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw);
53 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw);
55 u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw, rtl8723e_phy_query_rf_reg() argument
59 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_query_rf_reg()
71 original_value = rtl8723_phy_rf_serial_read(hw, rtl8723e_phy_query_rf_reg()
87 void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw, rtl8723e_phy_set_rf_reg() argument
91 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_set_rf_reg()
104 original_value = rtl8723_phy_rf_serial_read(hw, rtl8723e_phy_set_rf_reg()
113 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data); rtl8723e_phy_set_rf_reg()
121 _rtl8723e_phy_fw_rf_serial_write(hw, rfpath, regaddr, data); rtl8723e_phy_set_rf_reg()
132 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw, _rtl8723e_phy_fw_rf_serial_write() argument
139 static void _rtl8723e_phy_bb_config_1t(struct ieee80211_hw *hw) _rtl8723e_phy_bb_config_1t() argument
141 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); _rtl8723e_phy_bb_config_1t()
142 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); _rtl8723e_phy_bb_config_1t()
143 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); _rtl8723e_phy_bb_config_1t()
144 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); _rtl8723e_phy_bb_config_1t()
145 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); _rtl8723e_phy_bb_config_1t()
146 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); _rtl8723e_phy_bb_config_1t()
147 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); _rtl8723e_phy_bb_config_1t()
148 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); _rtl8723e_phy_bb_config_1t()
149 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); _rtl8723e_phy_bb_config_1t()
150 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); _rtl8723e_phy_bb_config_1t()
153 bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw) rtl8723e_phy_mac_config() argument
155 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_mac_config()
156 bool rtstatus = _rtl8723e_phy_config_mac_with_headerfile(hw); rtl8723e_phy_mac_config()
161 bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw) rtl8723e_phy_bb_config() argument
164 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_bb_config()
168 rtl8723_phy_init_bb_rf_reg_def(hw); rtl8723e_phy_bb_config()
196 rtstatus = _rtl8723e_phy_bb8192c_config_parafile(hw); rtl8723e_phy_bb_config()
200 bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw) rtl8723e_phy_rf_config() argument
202 return rtl8723e_phy_rf6052_config(hw); rtl8723e_phy_rf_config()
205 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw) _rtl8723e_phy_bb8192c_config_parafile() argument
207 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_bb8192c_config_parafile()
209 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723e_phy_bb8192c_config_parafile()
213 rtstatus = _rtl8723e_phy_config_bb_with_headerfile(hw, _rtl8723e_phy_bb8192c_config_parafile()
221 _rtl8723e_phy_bb_config_1t(hw); _rtl8723e_phy_bb8192c_config_parafile()
226 rtstatus = _rtl8723e_phy_config_bb_with_pgheaderfile(hw, _rtl8723e_phy_bb8192c_config_parafile()
234 _rtl8723e_phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB); _rtl8723e_phy_bb8192c_config_parafile()
239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, _rtl8723e_phy_bb8192c_config_parafile()
246 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl8723e_phy_config_mac_with_headerfile() argument
248 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_config_mac_with_headerfile()
264 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, _rtl8723e_phy_config_bb_with_headerfile() argument
271 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_config_bb_with_headerfile()
291 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl8723e_phy_config_bb_with_headerfile()
301 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, _rtl8723e_phy_config_bb_with_headerfile()
313 static void store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, store_pwrindex_diffrate_offset() argument
317 struct rtl_priv *rtlpriv = rtl_priv(hw); store_pwrindex_diffrate_offset()
468 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, _rtl8723e_phy_config_bb_with_pgheaderfile() argument
471 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_config_bb_with_pgheaderfile()
494 store_pwrindex_diffrate_offset(hw, _rtl8723e_phy_config_bb_with_pgheaderfile()
506 bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl8723e_phy_config_rf_with_headerfile() argument
538 rtl_set_rfreg(hw, rfpath, radioa_array_table[i], rtl8723e_phy_config_rf_with_headerfile()
553 void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl8723e_phy_get_hw_reg_originalvalue() argument
555 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_get_hw_reg_originalvalue()
559 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl8723e_phy_get_hw_reg_originalvalue()
561 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl8723e_phy_get_hw_reg_originalvalue()
563 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl8723e_phy_get_hw_reg_originalvalue()
565 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl8723e_phy_get_hw_reg_originalvalue()
574 rtlphy->framesync = (u8) rtl_get_bbreg(hw, rtl8723e_phy_get_hw_reg_originalvalue()
576 rtlphy->framesync_c34 = rtl_get_bbreg(hw, rtl8723e_phy_get_hw_reg_originalvalue()
584 void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) rtl8723e_phy_get_txpower_level() argument
586 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_get_txpower_level()
588 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723e_phy_get_txpower_level()
593 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, rtl8723e_phy_get_txpower_level()
597 if (rtl8723_phy_txpwr_idx_to_dbm(hw, rtl8723e_phy_get_txpower_level()
601 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, rtl8723e_phy_get_txpower_level()
604 if (rtl8723_phy_txpwr_idx_to_dbm(hw, rtl8723e_phy_get_txpower_level()
608 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, rtl8723e_phy_get_txpower_level()
613 static void _rtl8723e_get_txpower_index(struct ieee80211_hw *hw, u8 channel, _rtl8723e_get_txpower_index() argument
616 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_get_txpower_index()
618 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723e_get_txpower_index()
638 static void _rtl8723e_ccxpower_index_check(struct ieee80211_hw *hw, _rtl8723e_ccxpower_index_check() argument
642 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_ccxpower_index_check()
650 void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl8723e_phy_set_txpower_level() argument
652 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723e_phy_set_txpower_level()
657 _rtl8723e_get_txpower_index(hw, channel, rtl8723e_phy_set_txpower_level()
659 _rtl8723e_ccxpower_index_check(hw, rtl8723e_phy_set_txpower_level()
662 rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); rtl8723e_phy_set_txpower_level()
663 rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); rtl8723e_phy_set_txpower_level()
666 bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm) rtl8723e_phy_update_txpower_dbm() argument
668 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_update_txpower_dbm()
670 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723e_phy_update_txpower_dbm()
673 u8 ccktxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw, rtl8723e_phy_update_txpower_dbm()
676 u8 ofdmtxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw, rtl8723e_phy_update_txpower_dbm()
695 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); rtl8723e_phy_update_txpower_dbm()
699 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw, _rtl8723e_phy_dbm_to_txpwr_idx() argument
730 void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) rtl8723e_phy_scan_operation_backup() argument
732 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_scan_operation_backup()
733 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723e_phy_scan_operation_backup()
740 rtlpriv->cfg->ops->set_hw_reg(hw, rtl8723e_phy_scan_operation_backup()
747 rtlpriv->cfg->ops->set_hw_reg(hw, rtl8723e_phy_scan_operation_backup()
759 void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl8723e_phy_set_bw_mode_callback() argument
761 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_set_bw_mode_callback()
762 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723e_phy_set_bw_mode_callback()
764 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723e_phy_set_bw_mode_callback()
801 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl8723e_phy_set_bw_mode_callback()
802 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl8723e_phy_set_bw_mode_callback()
803 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); rtl8723e_phy_set_bw_mode_callback()
806 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl8723e_phy_set_bw_mode_callback()
807 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl8723e_phy_set_bw_mode_callback()
809 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, rtl8723e_phy_set_bw_mode_callback()
811 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); rtl8723e_phy_set_bw_mode_callback()
812 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); rtl8723e_phy_set_bw_mode_callback()
814 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl8723e_phy_set_bw_mode_callback()
823 rtl8723e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl8723e_phy_set_bw_mode_callback()
828 void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw, rtl8723e_phy_set_bw_mode() argument
831 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_set_bw_mode()
833 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723e_phy_set_bw_mode()
839 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl8723e_phy_set_bw_mode()
840 rtl8723e_phy_set_bw_mode_callback(hw); rtl8723e_phy_set_bw_mode()
849 void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw) rtl8723e_phy_sw_chnl_callback() argument
851 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_sw_chnl_callback()
852 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723e_phy_sw_chnl_callback()
864 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, rtl8723e_phy_sw_chnl_callback()
878 u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw) rtl8723e_phy_sw_chnl() argument
880 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_sw_chnl()
882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723e_phy_sw_chnl()
893 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl8723e_phy_sw_chnl()
894 rtl8723e_phy_sw_chnl_callback(hw); rtl8723e_phy_sw_chnl()
906 static void _rtl8723e_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel) _rtl8723e_phy_sw_rf_seting() argument
908 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_sw_rf_seting()
910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723e_phy_sw_rf_seting()
915 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, _rtl8723e_phy_sw_rf_seting()
918 u32 backuprf0x1a = (u32)rtl_get_rfreg(hw, _rtl8723e_phy_sw_rf_seting()
921 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, _rtl8723e_phy_sw_rf_seting()
927 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, _rtl8723e_phy_sw_chnl_step_by_step() argument
931 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_sw_chnl_step_by_step()
997 rtl8723e_phy_set_txpower_level(hw, channel); _rtl8723e_phy_sw_chnl_step_by_step()
1017 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl8723e_phy_sw_chnl_step_by_step()
1022 _rtl8723e_phy_sw_rf_seting(hw, channel); _rtl8723e_phy_sw_chnl_step_by_step()
1038 static u8 _rtl8723e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl8723e_phy_path_a_iqk() argument
1043 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); _rtl8723e_phy_path_a_iqk()
1044 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); _rtl8723e_phy_path_a_iqk()
1045 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); _rtl8723e_phy_path_a_iqk()
1046 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, _rtl8723e_phy_path_a_iqk()
1050 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); _rtl8723e_phy_path_a_iqk()
1051 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); _rtl8723e_phy_path_a_iqk()
1052 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); _rtl8723e_phy_path_a_iqk()
1053 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); _rtl8723e_phy_path_a_iqk()
1056 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); _rtl8723e_phy_path_a_iqk()
1057 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl8723e_phy_path_a_iqk()
1058 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl8723e_phy_path_a_iqk()
1062 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl8723e_phy_path_a_iqk()
1063 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl8723e_phy_path_a_iqk()
1064 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl8723e_phy_path_a_iqk()
1065 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl8723e_phy_path_a_iqk()
1081 static u8 _rtl8723e_phy_path_b_iqk(struct ieee80211_hw *hw) _rtl8723e_phy_path_b_iqk() argument
1086 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl8723e_phy_path_b_iqk()
1087 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl8723e_phy_path_b_iqk()
1089 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl8723e_phy_path_b_iqk()
1090 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl8723e_phy_path_b_iqk()
1091 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl8723e_phy_path_b_iqk()
1092 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl8723e_phy_path_b_iqk()
1093 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl8723e_phy_path_b_iqk()
1108 static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw, _rtl8723e_phy_simularity_compare() argument
1160 static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, _rtl8723e_phy_iq_calibrate() argument
1163 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_iq_calibrate()
1183 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); _rtl8723e_phy_iq_calibrate()
1185 rtl8723_save_adda_registers(hw, adda_reg, _rtl8723e_phy_iq_calibrate()
1187 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg, _rtl8723e_phy_iq_calibrate()
1190 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl8723e_phy_iq_calibrate()
1192 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, _rtl8723e_phy_iq_calibrate()
1198 rtl8723_phy_pi_mode_switch(hw, true); _rtl8723e_phy_iq_calibrate()
1200 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); _rtl8723e_phy_iq_calibrate()
1201 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); _rtl8723e_phy_iq_calibrate()
1202 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); _rtl8723e_phy_iq_calibrate()
1204 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl8723e_phy_iq_calibrate()
1205 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl8723e_phy_iq_calibrate()
1206 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl8723e_phy_iq_calibrate()
1208 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl8723e_phy_iq_calibrate()
1209 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); _rtl8723e_phy_iq_calibrate()
1211 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl8723e_phy_iq_calibrate()
1213 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); _rtl8723e_phy_iq_calibrate()
1215 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); _rtl8723e_phy_iq_calibrate()
1216 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl8723e_phy_iq_calibrate()
1217 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl8723e_phy_iq_calibrate()
1218 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl8723e_phy_iq_calibrate()
1220 patha_ok = _rtl8723e_phy_path_a_iqk(hw, is2t); _rtl8723e_phy_iq_calibrate()
1222 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1224 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1226 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1228 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1233 result[t][0] = (rtl_get_bbreg(hw, 0xe94, _rtl8723e_phy_iq_calibrate()
1237 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; _rtl8723e_phy_iq_calibrate()
1242 rtl8723_phy_path_a_standby(hw); _rtl8723e_phy_iq_calibrate()
1243 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t); _rtl8723e_phy_iq_calibrate()
1245 pathb_ok = _rtl8723e_phy_path_b_iqk(hw); _rtl8723e_phy_iq_calibrate()
1247 result[t][4] = (rtl_get_bbreg(hw, _rtl8723e_phy_iq_calibrate()
1252 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1255 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1258 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1262 result[t][4] = (rtl_get_bbreg(hw, _rtl8723e_phy_iq_calibrate()
1267 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl8723e_phy_iq_calibrate()
1271 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); _rtl8723e_phy_iq_calibrate()
1272 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); _rtl8723e_phy_iq_calibrate()
1273 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); _rtl8723e_phy_iq_calibrate()
1274 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl8723e_phy_iq_calibrate()
1275 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); _rtl8723e_phy_iq_calibrate()
1277 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); _rtl8723e_phy_iq_calibrate()
1280 rtl8723_phy_pi_mode_switch(hw, false); _rtl8723e_phy_iq_calibrate()
1281 rtl8723_phy_reload_adda_registers(hw, adda_reg, _rtl8723e_phy_iq_calibrate()
1283 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl8723e_phy_iq_calibrate()
1288 static void _rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl8723e_phy_lc_calibrate() argument
1292 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_lc_calibrate()
1302 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); _rtl8723e_phy_lc_calibrate()
1305 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, _rtl8723e_phy_lc_calibrate()
1308 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, _rtl8723e_phy_lc_calibrate()
1312 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl8723e_phy_lc_calibrate()
1315 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); _rtl8723e_phy_lc_calibrate()
1317 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); _rtl8723e_phy_lc_calibrate()
1323 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); _rtl8723e_phy_lc_calibrate()
1326 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl8723e_phy_lc_calibrate()
1333 static void _rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, _rtl8723e_phy_set_rfpath_switch() argument
1336 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723e_phy_set_rfpath_switch()
1339 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); _rtl8723e_phy_set_rfpath_switch()
1340 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); _rtl8723e_phy_set_rfpath_switch()
1344 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl8723e_phy_set_rfpath_switch()
1347 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl8723e_phy_set_rfpath_switch()
1351 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); _rtl8723e_phy_set_rfpath_switch()
1353 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); _rtl8723e_phy_set_rfpath_switch()
1362 void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl8723e_phy_iq_calibrate() argument
1364 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_iq_calibrate()
1387 rtl8723_phy_reload_adda_registers(hw, rtl8723e_phy_iq_calibrate()
1405 _rtl8723e_phy_iq_calibrate(hw, result, i, false); rtl8723e_phy_iq_calibrate()
1408 _rtl8723e_phy_simularity_compare(hw, result, 0, 1); rtl8723e_phy_iq_calibrate()
1416 _rtl8723e_phy_simularity_compare(hw, result, 0, 2); rtl8723e_phy_iq_calibrate()
1422 _rtl8723e_phy_simularity_compare(hw, result, 1, 2); rtl8723e_phy_iq_calibrate()
1462 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, rtl8723e_phy_iq_calibrate()
1465 rtl8723_save_adda_registers(hw, iqk_bb_reg, rtl8723e_phy_iq_calibrate()
1469 void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw) rtl8723e_phy_lc_calibrate() argument
1471 _rtl8723e_phy_lc_calibrate(hw, false); rtl8723e_phy_lc_calibrate()
1474 void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) rtl8723e_phy_set_rfpath_switch() argument
1476 _rtl8723e_phy_set_rfpath_switch(hw, bmain, false); rtl8723e_phy_set_rfpath_switch()
1479 bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl8723e_phy_set_io_cmd() argument
1481 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_set_io_cmd()
1512 rtl8723e_phy_set_io(hw); rtl8723e_phy_set_io_cmd()
1517 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw) rtl8723e_phy_set_io() argument
1519 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_set_io()
1529 rtl8723e_dm_write_dig(hw); rtl8723e_phy_set_io()
1530 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); rtl8723e_phy_set_io()
1535 rtl8723e_dm_write_dig(hw); rtl8723e_phy_set_io()
1547 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw) rtl8723e_phy_set_rf_on() argument
1549 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_phy_set_rf_on()
1559 static void _rtl8723e_phy_set_rf_sleep(struct ieee80211_hw *hw) _rtl8723e_phy_set_rf_sleep() argument
1563 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_set_rf_sleep()
1566 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl8723e_phy_set_rf_sleep()
1568 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl8723e_phy_set_rf_sleep()
1571 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl8723e_phy_set_rf_sleep()
1573 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl8723e_phy_set_rf_sleep()
1589 static bool _rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl8723e_phy_set_rf_power_state() argument
1592 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_phy_set_rf_power_state()
1593 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8723e_phy_set_rf_power_state()
1594 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl8723e_phy_set_rf_power_state()
1595 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl8723e_phy_set_rf_power_state()
1611 rtstatus = rtl_ps_enable_nic(hw); _rtl8723e_phy_set_rf_power_state()
1622 rtl8723e_phy_set_rf_on(hw); _rtl8723e_phy_set_rf_power_state()
1625 rtlpriv->cfg->ops->led_control(hw, _rtl8723e_phy_set_rf_power_state()
1628 rtlpriv->cfg->ops->led_control(hw, _rtl8723e_phy_set_rf_power_state()
1636 rtl_ps_disable_nic(hw); _rtl8723e_phy_set_rf_power_state()
1640 rtlpriv->cfg->ops->led_control(hw, _rtl8723e_phy_set_rf_power_state()
1643 rtlpriv->cfg->ops->led_control(hw, _rtl8723e_phy_set_rf_power_state()
1681 _rtl8723e_phy_set_rf_sleep(hw); _rtl8723e_phy_set_rf_power_state()
1694 bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl8723e_phy_set_rf_power_state() argument
1697 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723e_phy_set_rf_power_state()
1703 bresult = _rtl8723e_phy_set_rf_power_state(hw, rfpwr_state); rtl8723e_phy_set_rf_power_state()
H A DMakefile6 hw.o \
H A Ddm.c150 static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) rtl8723e_dm_initial_gain_min_pwdb() argument
152 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_initial_gain_min_pwdb()
177 static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) rtl8723e_dm_false_alarm_counter_statistics() argument
180 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_false_alarm_counter_statistics()
183 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl8723e_dm_false_alarm_counter_statistics()
186 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl8723e_dm_false_alarm_counter_statistics()
190 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl8723e_dm_false_alarm_counter_statistics()
196 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); rtl8723e_dm_false_alarm_counter_statistics()
197 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); rtl8723e_dm_false_alarm_counter_statistics()
200 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); rtl8723e_dm_false_alarm_counter_statistics()
208 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); rtl8723e_dm_false_alarm_counter_statistics()
209 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); rtl8723e_dm_false_alarm_counter_statistics()
210 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); rtl8723e_dm_false_alarm_counter_statistics()
211 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); rtl8723e_dm_false_alarm_counter_statistics()
225 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw) rtl92c_dm_ctrl_initgain_by_fa() argument
227 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_ctrl_initgain_by_fa()
247 rtl8723e_dm_write_dig(hw); rtl92c_dm_ctrl_initgain_by_fa()
250 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) rtl92c_dm_ctrl_initgain_by_rssi() argument
252 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_ctrl_initgain_by_rssi()
285 rtl8723e_dm_write_dig(hw); rtl92c_dm_ctrl_initgain_by_rssi()
288 static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) rtl8723e_dm_initial_gain_multi_sta() argument
291 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_initial_gain_multi_sta()
292 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723e_dm_initial_gain_multi_sta()
308 rtl8723e_dm_write_dig(hw); rtl8723e_dm_initial_gain_multi_sta()
318 rtl8723e_dm_write_dig(hw); rtl8723e_dm_initial_gain_multi_sta()
324 rtl92c_dm_ctrl_initgain_by_fa(hw); rtl8723e_dm_initial_gain_multi_sta()
329 rtl8723e_dm_write_dig(hw); rtl8723e_dm_initial_gain_multi_sta()
338 static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw) rtl8723e_dm_initial_gain_sta() argument
340 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_initial_gain_sta()
353 rtl8723e_dm_initial_gain_min_pwdb(hw); rtl8723e_dm_initial_gain_sta()
354 rtl92c_dm_ctrl_initgain_by_rssi(hw); rtl8723e_dm_initial_gain_sta()
362 rtl8723e_dm_write_dig(hw); rtl8723e_dm_initial_gain_sta()
366 static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) rtl8723e_dm_cck_packet_detection_thresh() argument
368 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_cck_packet_detection_thresh()
372 dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw); rtl8723e_dm_cck_packet_detection_thresh()
405 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, rtl8723e_dm_cck_packet_detection_thresh()
408 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, rtl8723e_dm_cck_packet_detection_thresh()
415 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40); rtl8723e_dm_cck_packet_detection_thresh()
418 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); rtl8723e_dm_cck_packet_detection_thresh()
419 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47); rtl8723e_dm_cck_packet_detection_thresh()
430 static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) rtl8723e_dm_ctrl_initgain_by_twoport() argument
432 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723e_dm_ctrl_initgain_by_twoport()
433 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_ctrl_initgain_by_twoport()
444 rtl8723e_dm_initial_gain_sta(hw); rtl8723e_dm_ctrl_initgain_by_twoport()
445 rtl8723e_dm_initial_gain_multi_sta(hw); rtl8723e_dm_ctrl_initgain_by_twoport()
446 rtl8723e_dm_cck_packet_detection_thresh(hw); rtl8723e_dm_ctrl_initgain_by_twoport()
452 static void rtl8723e_dm_dig(struct ieee80211_hw *hw) rtl8723e_dm_dig() argument
454 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_dig()
462 rtl8723e_dm_ctrl_initgain_by_twoport(hw); rtl8723e_dm_dig()
466 static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw) rtl8723e_dm_dynamic_txpower() argument
468 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_dynamic_txpower()
470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723e_dm_dynamic_txpower()
537 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); rtl8723e_dm_dynamic_txpower()
543 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw) rtl8723e_dm_write_dig() argument
545 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_write_dig()
554 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, rtl8723e_dm_write_dig()
556 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, rtl8723e_dm_write_dig()
563 static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw) rtl8723e_dm_pwdb_monitor() argument
567 static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw) rtl8723e_dm_check_edca_turbo() argument
569 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_check_edca_turbo()
570 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723e_dm_check_edca_turbo()
630 rtlpriv->cfg->ops->set_hw_reg(hw, rtl8723e_dm_check_edca_turbo()
643 struct ieee80211_hw *hw) rtl8723e_dm_initialize_txpower_tracking_thermalmeter()
645 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_initialize_txpower_tracking_thermalmeter()
655 static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) rtl8723e_dm_initialize_txpower_tracking() argument
657 rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw); rtl8723e_dm_initialize_txpower_tracking()
660 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw) rtl8723e_dm_check_txpower_tracking() argument
665 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) rtl8723e_dm_init_rate_adaptive_mask() argument
667 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_init_rate_adaptive_mask()
680 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal) rtl8723e_dm_rf_saving() argument
682 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_rf_saving()
688 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl8723e_dm_rf_saving()
691 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, rtl8723e_dm_rf_saving()
694 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, rtl8723e_dm_rf_saving()
697 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12; rtl8723e_dm_rf_saving()
724 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl8723e_dm_rf_saving()
726 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl8723e_dm_rf_saving()
728 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); rtl8723e_dm_rf_saving()
729 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, rtl8723e_dm_rf_saving()
731 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl8723e_dm_rf_saving()
733 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3); rtl8723e_dm_rf_saving()
734 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); rtl8723e_dm_rf_saving()
735 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); rtl8723e_dm_rf_saving()
737 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl8723e_dm_rf_saving()
739 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), rtl8723e_dm_rf_saving()
741 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, rtl8723e_dm_rf_saving()
743 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74); rtl8723e_dm_rf_saving()
744 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); rtl8723e_dm_rf_saving()
745 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl8723e_dm_rf_saving()
753 static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw) rtl8723e_dm_dynamic_bb_powersaving() argument
755 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_dynamic_bb_powersaving()
756 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723e_dm_dynamic_bb_powersaving()
789 rtl8723e_dm_rf_saving(hw, false); rtl8723e_dm_dynamic_bb_powersaving()
792 void rtl8723e_dm_init(struct ieee80211_hw *hw) rtl8723e_dm_init() argument
794 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_init()
797 rtl_dm_diginit(hw, 0x20); rtl8723e_dm_init()
798 rtl8723_dm_init_dynamic_txpower(hw); rtl8723e_dm_init()
799 rtl8723_dm_init_edca_turbo(hw); rtl8723e_dm_init()
800 rtl8723e_dm_init_rate_adaptive_mask(hw); rtl8723e_dm_init()
801 rtl8723e_dm_initialize_txpower_tracking(hw); rtl8723e_dm_init()
802 rtl8723_dm_init_dynamic_bb_powersaving(hw); rtl8723e_dm_init()
805 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw) rtl8723e_dm_watchdog() argument
807 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_watchdog()
808 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723e_dm_watchdog()
811 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, rtl8723e_dm_watchdog()
813 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, rtl8723e_dm_watchdog()
822 rtl8723e_dm_pwdb_monitor(hw); rtl8723e_dm_watchdog()
823 rtl8723e_dm_dig(hw); rtl8723e_dm_watchdog()
824 rtl8723e_dm_false_alarm_counter_statistics(hw); rtl8723e_dm_watchdog()
825 rtl8723e_dm_dynamic_bb_powersaving(hw); rtl8723e_dm_watchdog()
826 rtl8723e_dm_dynamic_txpower(hw); rtl8723e_dm_watchdog()
827 rtl8723e_dm_check_txpower_tracking(hw); rtl8723e_dm_watchdog()
828 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */ rtl8723e_dm_watchdog()
829 rtl8723e_dm_bt_coexist(hw); rtl8723e_dm_watchdog()
830 rtl8723e_dm_check_edca_turbo(hw); rtl8723e_dm_watchdog()
836 static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw) rtl8723e_dm_init_bt_coexist() argument
838 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_init_bt_coexist()
841 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff); rtl8723e_dm_init_bt_coexist()
843 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0); rtl8723e_dm_init_bt_coexist()
859 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw) rtl8723e_dm_bt_coexist() argument
861 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_coexist()
872 rtl8723e_dm_init_bt_coexist(hw); rtl8723e_dm_bt_coexist()
880 rtl8723e_dm_bt_coexist_8723(hw); rtl8723e_dm_bt_coexist()
642 rtl8723e_dm_initialize_txpower_tracking_thermalmeter( struct ieee80211_hw *hw) rtl8723e_dm_initialize_txpower_tracking_thermalmeter() argument
H A Dhal_btc.c35 void rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps(struct ieee80211_hw *hw) rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps() argument
37 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps()
38 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps()
50 rtl8723e_btdm_coex_all_off(hw); rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps()
54 static enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw) mgnt_link_status_query() argument
56 struct rtl_priv *rtlpriv = rtl_priv(hw); mgnt_link_status_query()
57 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); mgnt_link_status_query()
66 void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw, rtl_8723e_bt_wifi_media_status_notify() argument
69 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_8723e_bt_wifi_media_status_notify()
82 if (mgnt_link_status_query(hw)) { rtl_8723e_bt_wifi_media_status_notify()
96 rtl8723e_fill_h2c_cmd(hw, 0x19, 3, h2c_parameter); rtl_8723e_bt_wifi_media_status_notify()
99 static bool rtl8723e_dm_bt_is_wifi_busy(struct ieee80211_hw *hw) rtl8723e_dm_bt_is_wifi_busy() argument
101 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_is_wifi_busy()
110 static void rtl8723e_dm_bt_set_fw_3a(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_3a() argument
114 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_3a()
127 rtl8723e_fill_h2c_cmd(hw, 0x3a, 5, h2c_parameter); rtl8723e_dm_bt_set_fw_3a()
130 static bool rtl8723e_dm_bt_need_to_dec_bt_pwr(struct ieee80211_hw *hw) rtl8723e_dm_bt_need_to_dec_bt_pwr() argument
132 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_need_to_dec_bt_pwr()
134 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) { rtl8723e_dm_bt_need_to_dec_bt_pwr()
146 static bool rtl8723e_dm_bt_is_same_coexist_state(struct ieee80211_hw *hw) rtl8723e_dm_bt_is_same_coexist_state() argument
148 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_is_same_coexist_state()
164 static void rtl8723e_dm_bt_set_coex_table(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_coex_table() argument
168 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_coex_table()
183 static void rtl8723e_dm_bt_set_hw_pta_mode(struct ieee80211_hw *hw, bool b_mode) rtl8723e_dm_bt_set_hw_pta_mode() argument
185 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_hw_pta_mode()
198 static void rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner() argument
201 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner()
207 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner()
214 rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, 0xfffff, rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner()
219 static void dm_bt_set_sw_penalty_tx_rate_adapt(struct ieee80211_hw *hw, dm_bt_set_sw_penalty_tx_rate_adapt() argument
222 struct rtl_priv *rtlpriv = rtl_priv(hw); dm_bt_set_sw_penalty_tx_rate_adapt()
241 static void rtl8723e_dm_bt_btdm_structure_reload(struct ieee80211_hw *hw, rtl8723e_dm_bt_btdm_structure_reload() argument
284 static void rtl8723e_dm_bt_btdm_structure_reload_all_off(struct ieee80211_hw *hw, rtl8723e_dm_bt_btdm_structure_reload_all_off() argument
287 rtl8723e_dm_bt_btdm_structure_reload(hw, btdm); rtl8723e_dm_bt_btdm_structure_reload_all_off()
293 static bool rtl8723e_dm_bt_is_2_ant_common_action(struct ieee80211_hw *hw) rtl8723e_dm_bt_is_2_ant_common_action() argument
295 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_is_2_ant_common_action()
299 rtl8723e_dm_bt_btdm_structure_reload(hw, &btdm8723); rtl8723e_dm_bt_is_2_ant_common_action()
301 if (!rtl8723e_dm_bt_is_wifi_busy(hw) && rtl8723e_dm_bt_is_2_ant_common_action()
305 rtl8723e_dm_bt_btdm_structure_reload_all_off(hw, &btdm8723); rtl8723e_dm_bt_is_2_ant_common_action()
307 } else if (rtl8723e_dm_bt_is_wifi_busy(hw) && rtl8723e_dm_bt_is_2_ant_common_action()
333 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) { rtl8723e_dm_bt_is_2_ant_common_action()
362 if (rtl8723e_dm_bt_need_to_dec_bt_pwr(hw)) rtl8723e_dm_bt_is_2_ant_common_action()
369 if (b_common && rtl8723e_dm_bt_is_coexist_state_changed(hw)) rtl8723e_dm_bt_is_2_ant_common_action()
370 rtl8723e_dm_bt_set_bt_dm(hw, &btdm8723); rtl8723e_dm_bt_is_2_ant_common_action()
376 struct ieee80211_hw *hw, rtl8723e_dm_bt_set_sw_full_time_dac_swing()
380 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_sw_full_time_dac_swing()
385 rtl8723_phy_set_bb_reg(hw, 0x880, 0xff000000, rtl8723e_dm_bt_set_sw_full_time_dac_swing()
391 rtl8723_phy_set_bb_reg(hw, 0x880, 0xff000000, 0xc0); rtl8723e_dm_bt_set_sw_full_time_dac_swing()
396 struct ieee80211_hw *hw, bool dec_bt_pwr) rtl8723e_dm_bt_set_fw_dec_bt_pwr()
398 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_dec_bt_pwr()
412 rtl8723e_fill_h2c_cmd(hw, 0x21, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_dec_bt_pwr()
415 static void rtl8723e_dm_bt_set_fw_2_ant_hid(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_2_ant_hid() argument
418 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_2_ant_hid()
433 rtl8723e_fill_h2c_cmd(hw, 0x15, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_2_ant_hid()
436 static void rtl8723e_dm_bt_set_fw_tdma_ctrl(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_tdma_ctrl() argument
440 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_tdma_ctrl()
495 rtl8723e_fill_h2c_cmd(hw, 0x26, 1, h2c_parameter1); rtl8723e_dm_bt_set_fw_tdma_ctrl()
500 rtl8723e_fill_h2c_cmd(hw, 0x14, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_tdma_ctrl()
503 static void rtl8723e_dm_bt_set_fw_ignore_wlan_act(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_ignore_wlan_act() argument
506 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_ignore_wlan_act()
523 rtl8723e_fill_h2c_cmd(hw, 0x25, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_ignore_wlan_act()
526 static void rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_tra_tdma_ctrl() argument
530 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_tra_tdma_ctrl()
531 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723e_dm_bt_set_fw_tra_tdma_ctrl()
577 rtl8723e_fill_h2c_cmd(hw, 0x33, 2, h2c_parameter); rtl8723e_dm_bt_set_fw_tra_tdma_ctrl()
580 static void rtl8723e_dm_bt_set_fw_dac_swing_level(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_dac_swing_level() argument
583 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_dac_swing_level()
592 rtl8723e_fill_h2c_cmd(hw, 0x29, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_dac_swing_level()
595 static void rtl8723e_dm_bt_set_fw_bt_hid_info(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_bt_hid_info() argument
598 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_bt_hid_info()
611 rtl8723e_fill_h2c_cmd(hw, 0x24, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_bt_hid_info()
614 static void rtl8723e_dm_bt_set_fw_bt_retry_index(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_bt_retry_index() argument
617 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_bt_retry_index()
626 rtl8723e_fill_h2c_cmd(hw, 0x23, 1, h2c_parameter); rtl8723e_dm_bt_set_fw_bt_retry_index()
629 static void rtl8723e_dm_bt_set_fw_wlan_act(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_fw_wlan_act() argument
632 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_fw_wlan_act()
647 rtl8723e_fill_h2c_cmd(hw, 0x22, 1, h2c_parameter_hi); rtl8723e_dm_bt_set_fw_wlan_act()
649 rtl8723e_fill_h2c_cmd(hw, 0x11, 1, h2c_parameter_lo); rtl8723e_dm_bt_set_fw_wlan_act()
652 void rtl8723e_dm_bt_set_bt_dm(struct ieee80211_hw *hw, rtl8723e_dm_bt_set_bt_dm() argument
655 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_set_bt_dm()
662 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, rtl8723e_dm_bt_set_bt_dm()
664 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, rtl8723e_dm_bt_set_bt_dm()
782 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, true); rtl8723e_dm_bt_set_bt_dm()
789 rtl8723e_btdm_coex_all_off(hw); rtl8723e_dm_bt_set_bt_dm()
793 rtl8723e_dm_bt_reject_ap_aggregated_packet(hw, btdm->reject_aggre_pkt); rtl8723e_dm_bt_set_bt_dm()
796 dm_bt_set_sw_penalty_tx_rate_adapt(hw, BT_TX_RATE_ADAPTIVE_LOW_PENALTY); rtl8723e_dm_bt_set_bt_dm()
798 dm_bt_set_sw_penalty_tx_rate_adapt(hw, rtl8723e_dm_bt_set_bt_dm()
802 rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(hw, rtl8723e_dm_bt_set_bt_dm()
805 rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(hw, rtl8723e_dm_bt_set_bt_dm()
809 rtl8723e_dm_bt_agc_table(hw, BT_AGCTABLE_ON); rtl8723e_dm_bt_set_bt_dm()
811 rtl8723e_dm_bt_agc_table(hw, BT_AGCTABLE_OFF); rtl8723e_dm_bt_set_bt_dm()
814 rtl8723e_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_ON); rtl8723e_dm_bt_set_bt_dm()
816 rtl8723e_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_OFF); rtl8723e_dm_bt_set_bt_dm()
818 rtl8723e_dm_bt_set_fw_bt_retry_index(hw, btdm->bt_retry_index); rtl8723e_dm_bt_set_bt_dm()
820 rtl8723e_dm_bt_set_fw_dac_swing_level(hw, btdm->fw_dac_swing_lvl); rtl8723e_dm_bt_set_bt_dm()
821 rtl8723e_dm_bt_set_fw_wlan_act(hw, btdm->wlan_act_hi, rtl8723e_dm_bt_set_bt_dm()
824 rtl8723e_dm_bt_set_coex_table(hw, btdm->val_0x6c0, rtl8723e_dm_bt_set_bt_dm()
826 rtl8723e_dm_bt_set_hw_pta_mode(hw, btdm->pta_on); rtl8723e_dm_bt_set_bt_dm()
835 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, rtl8723e_dm_bt_set_bt_dm()
838 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant, rtl8723e_dm_bt_set_bt_dm()
843 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, rtl8723e_dm_bt_set_bt_dm()
846 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); rtl8723e_dm_bt_set_bt_dm()
849 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, true); rtl8723e_dm_bt_set_bt_dm()
850 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, true, true); rtl8723e_dm_bt_set_bt_dm()
853 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false); rtl8723e_dm_bt_set_bt_dm()
854 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false); rtl8723e_dm_bt_set_bt_dm()
857 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, rtl8723e_dm_bt_set_bt_dm()
860 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); rtl8723e_dm_bt_set_bt_dm()
863 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, rtl8723e_dm_bt_set_bt_dm()
866 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, true, btdm->tdma_ant, rtl8723e_dm_bt_set_bt_dm()
871 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false); rtl8723e_dm_bt_set_bt_dm()
872 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false); rtl8723e_dm_bt_set_bt_dm()
875 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, rtl8723e_dm_bt_set_bt_dm()
878 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant, rtl8723e_dm_bt_set_bt_dm()
883 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, rtl8723e_dm_bt_set_bt_dm()
885 rtl8723e_dm_bt_set_fw_3a(hw, btdm->ps_tdma_byte[0], rtl8723e_dm_bt_set_bt_dm()
892 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false); rtl8723e_dm_bt_set_bt_dm()
893 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false); rtl8723e_dm_bt_set_bt_dm()
896 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, btdm->tra_tdma_on, rtl8723e_dm_bt_set_bt_dm()
899 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, btdm->tdma_ant, rtl8723e_dm_bt_set_bt_dm()
904 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, rtl8723e_dm_bt_set_bt_dm()
907 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); rtl8723e_dm_bt_set_bt_dm()
918 rtl8723e_dm_bt_set_sw_full_time_dac_swing(hw, btdm->sw_dac_swing_on, rtl8723e_dm_bt_set_bt_dm()
920 rtl8723e_dm_bt_set_fw_dec_bt_pwr(hw, btdm->dec_bt_pwr); rtl8723e_dm_bt_set_bt_dm()
927 static u32 rtl8723e_dm_bt_tx_rx_couter_h(struct ieee80211_hw *hw) rtl8723e_dm_bt_tx_rx_couter_h() argument
936 static u32 rtl8723e_dm_bt_tx_rx_couter_l(struct ieee80211_hw *hw) rtl8723e_dm_bt_tx_rx_couter_l() argument
945 static u8 rtl8723e_dm_bt_bt_tx_rx_counter_level(struct ieee80211_hw *hw) rtl8723e_dm_bt_bt_tx_rx_counter_level() argument
947 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_bt_tx_rx_counter_level()
951 bt_tx_rx_cnt = rtl8723e_dm_bt_tx_rx_couter_h(hw) rtl8723e_dm_bt_bt_tx_rx_counter_level()
952 + rtl8723e_dm_bt_tx_rx_couter_l(hw); rtl8723e_dm_bt_bt_tx_rx_counter_level()
988 static void rtl8723e_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw) rtl8723e_dm_bt_2_ant_hid_sco_esco() argument
990 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_2_ant_hid_sco_esco()
996 rtl8723e_dm_bt_btdm_structure_reload(hw, &btdm8723); rtl8723e_dm_bt_2_ant_hid_sco_esco()
1002 bt_tx_rx_cnt_lvl = rtl8723e_dm_bt_bt_tx_rx_counter_level(hw); rtl8723e_dm_bt_2_ant_hid_sco_esco()
1049 rtl8723e_dm_bt_check_coex_rssi_state(hw, 2, 47, 0); rtl8723e_dm_bt_2_ant_hid_sco_esco()
1051 rtl8723e_dm_bt_check_coex_rssi_state1(hw, 2, 27, 0); rtl8723e_dm_bt_2_ant_hid_sco_esco()
1139 if (rtl8723e_dm_bt_need_to_dec_bt_pwr(hw)) rtl8723e_dm_bt_2_ant_hid_sco_esco()
1159 if (rtl8723e_dm_bt_is_coexist_state_changed(hw)) rtl8723e_dm_bt_2_ant_hid_sco_esco()
1160 rtl8723e_dm_bt_set_bt_dm(hw, &btdm8723); rtl8723e_dm_bt_2_ant_hid_sco_esco()
1164 static void rtl8723e_dm_bt_2_ant_ftp_a2dp(struct ieee80211_hw *hw) rtl8723e_dm_bt_2_ant_ftp_a2dp() argument
1166 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1173 rtl8723e_dm_bt_btdm_structure_reload(hw, &btdm8723); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1179 bt_tx_rx_cnt_lvl = rtl8723e_dm_bt_bt_tx_rx_counter_level(hw); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1187 rtl8723e_dm_bt_check_coex_rssi_state(hw, 2, 37, 0); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1264 rtl8723e_dm_bt_check_coex_rssi_state(hw, 2, 47, 0); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1266 rtl8723e_dm_bt_check_coex_rssi_state1(hw, 2, 27, 0); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1354 if (rtl8723e_dm_bt_need_to_dec_bt_pwr(hw)) rtl8723e_dm_bt_2_ant_ftp_a2dp()
1373 if (rtl8723e_dm_bt_is_coexist_state_changed(hw)) rtl8723e_dm_bt_2_ant_ftp_a2dp()
1374 rtl8723e_dm_bt_set_bt_dm(hw, &btdm8723); rtl8723e_dm_bt_2_ant_ftp_a2dp()
1378 static void rtl8723e_dm_bt_inq_page_monitor(struct ieee80211_hw *hw) rtl8723e_dm_bt_inq_page_monitor() argument
1380 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_inq_page_monitor()
1412 static void rtl8723e_dm_bt_reset_action_profile_state(struct ieee80211_hw *hw) rtl8723e_dm_bt_reset_action_profile_state() argument
1414 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_reset_action_profile_state()
1426 static void _rtl8723e_dm_bt_coexist_2_ant(struct ieee80211_hw *hw) _rtl8723e_dm_bt_coexist_2_ant() argument
1428 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723e_dm_bt_coexist_2_ant()
1434 _rtl8723_dm_bt_check_wifi_state(hw); _rtl8723e_dm_bt_coexist_2_ant()
1446 rtl8723e_dm_bt_inq_page_monitor(hw); _rtl8723e_dm_bt_coexist_2_ant()
1447 rtl8723e_dm_bt_reset_action_profile_state(hw); _rtl8723e_dm_bt_coexist_2_ant()
1449 if (rtl8723e_dm_bt_is_2_ant_common_action(hw)) { _rtl8723e_dm_bt_coexist_2_ant()
1466 rtl8723e_dm_bt_2_ant_hid_sco_esco(hw); _rtl8723e_dm_bt_coexist_2_ant()
1477 rtl8723e_dm_bt_2_ant_ftp_a2dp(hw); _rtl8723e_dm_bt_coexist_2_ant()
1487 rtl8723e_dm_bt_2_ant_hid_sco_esco(hw); _rtl8723e_dm_bt_coexist_2_ant()
1492 static void _rtl8723e_dm_bt_coexist_1_ant(struct ieee80211_hw *hw) _rtl8723e_dm_bt_coexist_1_ant() argument
1497 void rtl8723e_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw) rtl8723e_dm_bt_hw_coex_all_off_8723a() argument
1499 rtl8723e_dm_bt_set_coex_table(hw, 0x5a5aaaaa, 0xcc, 0x3); rtl8723e_dm_bt_hw_coex_all_off_8723a()
1500 rtl8723e_dm_bt_set_hw_pta_mode(hw, true); rtl8723e_dm_bt_hw_coex_all_off_8723a()
1503 void rtl8723e_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw) rtl8723e_dm_bt_fw_coex_all_off_8723a() argument
1505 rtl8723e_dm_bt_set_fw_ignore_wlan_act(hw, false); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1506 rtl8723e_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1507 rtl8723e_dm_bt_set_fw_2_ant_hid(hw, false, false); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1508 rtl8723e_dm_bt_set_fw_tra_tdma_ctrl(hw, false, TDMA_2ANT, rtl8723e_dm_bt_fw_coex_all_off_8723a()
1510 rtl8723e_dm_bt_set_fw_tdma_ctrl(hw, false, TDMA_2ANT, TDMA_NAV_OFF, rtl8723e_dm_bt_fw_coex_all_off_8723a()
1512 rtl8723e_dm_bt_set_fw_dac_swing_level(hw, 0); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1513 rtl8723e_dm_bt_set_fw_bt_hid_info(hw, false); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1514 rtl8723e_dm_bt_set_fw_bt_retry_index(hw, 2); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1515 rtl8723e_dm_bt_set_fw_wlan_act(hw, 0x10, 0x10); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1516 rtl8723e_dm_bt_set_fw_dec_bt_pwr(hw, false); rtl8723e_dm_bt_fw_coex_all_off_8723a()
1519 void rtl8723e_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw) rtl8723e_dm_bt_sw_coex_all_off_8723a() argument
1521 rtl8723e_dm_bt_agc_table(hw, BT_AGCTABLE_OFF); rtl8723e_dm_bt_sw_coex_all_off_8723a()
1522 rtl8723e_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_OFF); rtl8723e_dm_bt_sw_coex_all_off_8723a()
1523 rtl8723e_dm_bt_reject_ap_aggregated_packet(hw, false); rtl8723e_dm_bt_sw_coex_all_off_8723a()
1525 dm_bt_set_sw_penalty_tx_rate_adapt(hw, BT_TX_RATE_ADAPTIVE_NORMAL); rtl8723e_dm_bt_sw_coex_all_off_8723a()
1526 rtl8723e_dm_bt_set_sw_rf_rx_lpf_corner(hw, BT_RF_RX_LPF_CORNER_RESUME); rtl8723e_dm_bt_sw_coex_all_off_8723a()
1527 rtl8723e_dm_bt_set_sw_full_time_dac_swing(hw, false, 0xc0); rtl8723e_dm_bt_sw_coex_all_off_8723a()
1530 static void rtl8723e_dm_bt_query_bt_information(struct ieee80211_hw *hw) rtl8723e_dm_bt_query_bt_information() argument
1532 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_query_bt_information()
1542 rtl8723e_fill_h2c_cmd(hw, 0x38, 1, h2c_parameter); rtl8723e_dm_bt_query_bt_information()
1545 static void rtl8723e_dm_bt_bt_hw_counters_monitor(struct ieee80211_hw *hw) rtl8723e_dm_bt_bt_hw_counters_monitor() argument
1547 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_bt_hw_counters_monitor()
1584 static void rtl8723e_dm_bt_bt_enable_disable_check(struct ieee80211_hw *hw) rtl8723e_dm_bt_bt_enable_disable_check() argument
1586 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_bt_enable_disable_check()
1637 void rtl8723e_dm_bt_coexist_8723(struct ieee80211_hw *hw) rtl8723e_dm_bt_coexist_8723() argument
1639 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_coexist_8723()
1641 rtl8723e_dm_bt_query_bt_information(hw); rtl8723e_dm_bt_coexist_8723()
1642 rtl8723e_dm_bt_bt_hw_counters_monitor(hw); rtl8723e_dm_bt_coexist_8723()
1643 rtl8723e_dm_bt_bt_enable_disable_check(hw); rtl8723e_dm_bt_coexist_8723()
1648 _rtl8723e_dm_bt_coexist_2_ant(hw); rtl8723e_dm_bt_coexist_8723()
1652 _rtl8723e_dm_bt_coexist_1_ant(hw); rtl8723e_dm_bt_coexist_8723()
1655 if (!rtl8723e_dm_bt_is_same_coexist_state(hw)) { rtl8723e_dm_bt_coexist_8723()
1669 static void rtl8723e_dm_bt_parse_bt_info(struct ieee80211_hw *hw, rtl8723e_dm_bt_parse_bt_info() argument
1672 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723e_dm_bt_parse_bt_info()
1714 void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw) rtl_8723e_c2h_command_handle() argument
1716 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_8723e_c2h_command_handle()
1768 rtl8723e_dm_bt_parse_bt_info(hw, ptmp_buf, c2h_event.cmd_len); rtl_8723e_c2h_command_handle()
375 rtl8723e_dm_bt_set_sw_full_time_dac_swing( struct ieee80211_hw *hw, bool sw_dac_swing_on, u32 sw_dac_swing_lvl) rtl8723e_dm_bt_set_sw_full_time_dac_swing() argument
395 rtl8723e_dm_bt_set_fw_dec_bt_pwr( struct ieee80211_hw *hw, bool dec_bt_pwr) rtl8723e_dm_bt_set_fw_dec_bt_pwr() argument
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dhw.h29 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
30 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw);
32 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
34 int rtl8723be_hw_init(struct ieee80211_hw *hw);
35 void rtl8723be_card_disable(struct ieee80211_hw *hw);
36 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw);
37 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw);
38 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
40 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
41 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci);
42 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw);
43 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw);
44 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
46 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
47 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
50 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw);
51 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
52 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw);
53 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
56 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
58 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw);
59 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw);
60 void rtl8723be_suspend(struct ieee80211_hw *hw);
61 void rtl8723be_resume(struct ieee80211_hw *hw);
H A Dphy.c39 static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw);
40 static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
41 static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
43 static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
45 static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
49 static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw);
50 static void rtl8723be_phy_set_io(struct ieee80211_hw *hw);
52 u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, rtl8723be_phy_query_rf_reg() argument
55 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_query_rf_reg()
65 original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr); rtl8723be_phy_query_rf_reg()
78 void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path path, rtl8723be_phy_set_rf_reg() argument
81 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_set_rf_reg()
92 original_value = rtl8723_phy_rf_serial_read(hw, path, rtl8723be_phy_set_rf_reg()
99 rtl8723_phy_rf_serial_write(hw, path, regaddr, data); rtl8723be_phy_set_rf_reg()
109 bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw) rtl8723be_phy_mac_config() argument
111 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_mac_config()
112 bool rtstatus = _rtl8723be_phy_config_mac_with_headerfile(hw); rtl8723be_phy_mac_config()
118 bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw) rtl8723be_phy_bb_config() argument
121 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_bb_config()
126 rtl8723_phy_init_bb_rf_reg_def(hw); rtl8723be_phy_bb_config()
141 rtstatus = _rtl8723be_phy_bb8723b_config_parafile(hw); rtl8723be_phy_bb_config()
144 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, rtl8723be_phy_bb_config()
150 bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw) rtl8723be_phy_rf_config() argument
152 return rtl8723be_phy_rf6052_config(hw); rtl8723be_phy_rf_config()
155 static bool _rtl8723be_check_condition(struct ieee80211_hw *hw, _rtl8723be_check_condition() argument
158 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_check_condition()
159 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723be_check_condition()
184 static void _rtl8723be_config_rf_reg(struct ieee80211_hw *hw, u32 addr, _rtl8723be_config_rf_reg() argument
194 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); _rtl8723be_config_rf_reg()
198 static void _rtl8723be_config_rf_radio_a(struct ieee80211_hw *hw, _rtl8723be_config_rf_radio_a() argument
204 _rtl8723be_config_rf_reg(hw, addr, data, RF90_PATH_A, _rtl8723be_config_rf_radio_a()
209 static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) _rtl8723be_phy_init_tx_power_by_rate() argument
211 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_init_tx_power_by_rate()
226 static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw, _rtl8723be_config_bb_reg() argument
242 rtl_set_bbreg(hw, addr, MASKDWORD, data); _rtl8723be_config_bb_reg()
247 static void _rtl8723be_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, _rtl8723be_phy_set_txpower_by_rate_base() argument
252 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_set_txpower_by_rate_base()
290 static u8 _rtl8723be_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, _rtl8723be_phy_get_txpower_by_rate_base() argument
294 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_get_txpower_by_rate_base()
333 static void _rtl8723be_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) _rtl8723be_phy_store_txpower_by_rate_base() argument
335 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_store_txpower_by_rate_base()
345 _rtl8723be_phy_set_txpower_by_rate_base(hw, _rtl8723be_phy_store_txpower_by_rate_base()
351 _rtl8723be_phy_set_txpower_by_rate_base(hw, _rtl8723be_phy_store_txpower_by_rate_base()
359 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl8723be_phy_store_txpower_by_rate_base()
366 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl8723be_phy_store_txpower_by_rate_base()
373 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl8723be_phy_store_txpower_by_rate_base()
406 struct ieee80211_hw *hw) _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
408 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
412 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
421 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
430 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
439 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
454 static void phy_txpower_by_rate_config(struct ieee80211_hw *hw) phy_txpower_by_rate_config() argument
456 _rtl8723be_phy_store_txpower_by_rate_base(hw); phy_txpower_by_rate_config()
457 _rtl8723be_phy_convert_txpower_dbm_to_relative_value(hw); phy_txpower_by_rate_config()
460 static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw) _rtl8723be_phy_bb8723b_config_parafile() argument
462 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_bb8723b_config_parafile()
464 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723be_phy_bb8723b_config_parafile()
467 rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw, _rtl8723be_phy_bb8723b_config_parafile()
473 _rtl8723be_phy_init_tx_power_by_rate(hw); _rtl8723be_phy_bb8723b_config_parafile()
476 rtstatus = _rtl8723be_phy_config_bb_with_pgheaderfile(hw, _rtl8723be_phy_bb8723b_config_parafile()
479 phy_txpower_by_rate_config(hw); _rtl8723be_phy_bb8723b_config_parafile()
484 rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw, _rtl8723be_phy_bb8723b_config_parafile()
490 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, _rtl8723be_phy_bb8723b_config_parafile()
496 static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl8723be_phy_config_mac_with_headerfile() argument
498 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_config_mac_with_headerfile()
513 static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, _rtl8723be_phy_config_bb_with_headerfile() argument
526 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_config_bb_with_headerfile()
537 _rtl8723be_config_bb_reg(hw, v1, v2); _rtl8723be_phy_config_bb_with_headerfile()
543 if (!_rtl8723be_check_condition(hw, _rtl8723be_phy_config_bb_with_headerfile()
565 _rtl8723be_config_bb_reg(hw, _rtl8723be_phy_config_bb_with_headerfile()
583 rtl_set_bbreg(hw, array_table[i], _rtl8723be_phy_config_bb_with_headerfile()
593 if (!_rtl8723be_check_condition(hw, _rtl8723be_phy_config_bb_with_headerfile()
615 rtl_set_bbreg(hw, array_table[i], _rtl8723be_phy_config_bb_with_headerfile()
695 static void _rtl8723be_store_tx_power_by_rate(struct ieee80211_hw *hw, _rtl8723be_store_tx_power_by_rate() argument
700 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_store_tx_power_by_rate()
723 static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, _rtl8723be_phy_config_bb_with_pgheaderfile() argument
726 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_config_bb_with_pgheaderfile()
749 _rtl8723be_store_tx_power_by_rate(hw, _rtl8723be_phy_config_bb_with_pgheaderfile()
761 bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl8723be_phy_config_rf_with_headerfile() argument
775 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_config_rf_with_headerfile()
776 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_phy_config_rf_with_headerfile()
791 _rtl8723be_config_rf_radio_a(hw, v1, v2); rtl8723be_phy_config_rf_with_headerfile()
797 if (!_rtl8723be_check_condition(hw, rtl8723be_phy_config_rf_with_headerfile()
819 _rtl8723be_config_rf_radio_a(hw, rtl8723be_phy_config_rf_with_headerfile()
833 _rtl8723be_config_rf_radio_a(hw, 0x52, 0x7E4BD); rtl8723be_phy_config_rf_with_headerfile()
846 void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl8723be_phy_get_hw_reg_originalvalue() argument
848 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_get_hw_reg_originalvalue()
852 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl8723be_phy_get_hw_reg_originalvalue()
854 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl8723be_phy_get_hw_reg_originalvalue()
856 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl8723be_phy_get_hw_reg_originalvalue()
858 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl8723be_phy_get_hw_reg_originalvalue()
867 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, rtl8723be_phy_get_hw_reg_originalvalue()
869 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, rtl8723be_phy_get_hw_reg_originalvalue()
949 static u8 _rtl8723be_get_txpower_by_rate(struct ieee80211_hw *hw, _rtl8723be_get_txpower_by_rate() argument
953 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_get_txpower_by_rate()
1016 static u8 _rtl8723be_get_txpower_index(struct ieee80211_hw *hw, u8 path, _rtl8723be_get_txpower_index() argument
1019 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_get_txpower_index()
1020 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723be_get_txpower_index()
1055 power_diff_byrate = _rtl8723be_get_txpower_by_rate(hw, _rtl8723be_get_txpower_index()
1067 static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw, _rtl8723be_phy_set_txpower_index() argument
1070 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_set_txpower_index()
1074 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_CCK1_MCS32, _rtl8723be_phy_set_txpower_index()
1078 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11, _rtl8723be_phy_set_txpower_index()
1082 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11, _rtl8723be_phy_set_txpower_index()
1086 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11, _rtl8723be_phy_set_txpower_index()
1091 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06, _rtl8723be_phy_set_txpower_index()
1095 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06, _rtl8723be_phy_set_txpower_index()
1099 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06, _rtl8723be_phy_set_txpower_index()
1103 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06, _rtl8723be_phy_set_txpower_index()
1108 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24, _rtl8723be_phy_set_txpower_index()
1112 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24, _rtl8723be_phy_set_txpower_index()
1116 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24, _rtl8723be_phy_set_txpower_index()
1120 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24, _rtl8723be_phy_set_txpower_index()
1125 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00, _rtl8723be_phy_set_txpower_index()
1129 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00, _rtl8723be_phy_set_txpower_index()
1133 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00, _rtl8723be_phy_set_txpower_index()
1137 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00, _rtl8723be_phy_set_txpower_index()
1142 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04, _rtl8723be_phy_set_txpower_index()
1146 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04, _rtl8723be_phy_set_txpower_index()
1150 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04, _rtl8723be_phy_set_txpower_index()
1154 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04, _rtl8723be_phy_set_txpower_index()
1159 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08, _rtl8723be_phy_set_txpower_index()
1163 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08, _rtl8723be_phy_set_txpower_index()
1167 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08, _rtl8723be_phy_set_txpower_index()
1171 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08, _rtl8723be_phy_set_txpower_index()
1184 void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl8723be_phy_set_txpower_level() argument
1186 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723be_phy_set_txpower_level()
1205 power_index = _rtl8723be_get_txpower_index(hw, RF90_PATH_A, rtl8723be_phy_set_txpower_level()
1207 rtl_priv(hw)->phy.current_chan_bw, rtl8723be_phy_set_txpower_level()
1209 _rtl8723be_phy_set_txpower_index(hw, power_index, RF90_PATH_A, rtl8723be_phy_set_txpower_level()
1214 power_index = _rtl8723be_get_txpower_index(hw, RF90_PATH_A, rtl8723be_phy_set_txpower_level()
1216 rtl_priv(hw)->phy.current_chan_bw, rtl8723be_phy_set_txpower_level()
1218 _rtl8723be_phy_set_txpower_index(hw, power_index, RF90_PATH_A, rtl8723be_phy_set_txpower_level()
1223 power_index = _rtl8723be_get_txpower_index(hw, RF90_PATH_A, rtl8723be_phy_set_txpower_level()
1225 rtl_priv(hw)->phy.current_chan_bw, rtl8723be_phy_set_txpower_level()
1227 _rtl8723be_phy_set_txpower_index(hw, power_index, RF90_PATH_A, rtl8723be_phy_set_txpower_level()
1232 void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) rtl8723be_phy_scan_operation_backup() argument
1234 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_scan_operation_backup()
1235 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_phy_scan_operation_backup()
1242 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, rtl8723be_phy_scan_operation_backup()
1248 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, rtl8723be_phy_scan_operation_backup()
1259 void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl8723be_phy_set_bw_mode_callback() argument
1261 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_set_bw_mode_callback()
1262 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_phy_set_bw_mode_callback()
1264 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_phy_set_bw_mode_callback()
1301 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl8723be_phy_set_bw_mode_callback()
1302 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl8723be_phy_set_bw_mode_callback()
1303 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/ rtl8723be_phy_set_bw_mode_callback()
1306 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl8723be_phy_set_bw_mode_callback()
1307 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl8723be_phy_set_bw_mode_callback()
1309 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, rtl8723be_phy_set_bw_mode_callback()
1311 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); rtl8723be_phy_set_bw_mode_callback()
1312 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ rtl8723be_phy_set_bw_mode_callback()
1314 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl8723be_phy_set_bw_mode_callback()
1323 rtl8723be_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl8723be_phy_set_bw_mode_callback()
1328 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw, rtl8723be_phy_set_bw_mode() argument
1331 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_set_bw_mode()
1333 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_phy_set_bw_mode()
1339 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl8723be_phy_set_bw_mode()
1340 rtl8723be_phy_set_bw_mode_callback(hw); rtl8723be_phy_set_bw_mode()
1349 void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw) rtl8723be_phy_sw_chnl_callback() argument
1351 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_sw_chnl_callback()
1352 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_phy_sw_chnl_callback()
1363 if (!_rtl8723be_phy_sw_chnl_step_by_step(hw, rtl8723be_phy_sw_chnl_callback()
1380 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw) rtl8723be_phy_sw_chnl() argument
1382 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_sw_chnl()
1384 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_phy_sw_chnl()
1395 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl8723be_phy_sw_chnl()
1396 rtl8723be_phy_sw_chnl_callback(hw); rtl8723be_phy_sw_chnl()
1409 static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, _rtl8723be_phy_sw_chnl_step_by_step() argument
1413 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_sw_chnl_step_by_step()
1482 rtl8723be_phy_set_txpower_level(hw, channel); _rtl8723be_phy_sw_chnl_step_by_step()
1502 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl8723be_phy_sw_chnl_step_by_step()
1522 static u8 _rtl8723be_phy_path_a_iqk(struct ieee80211_hw *hw) _rtl8723be_phy_path_a_iqk() argument
1528 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_iqk()
1530 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_iqk()
1532 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl8723be_phy_path_a_iqk()
1533 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x20000); _rtl8723be_phy_path_a_iqk()
1534 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0003f); _rtl8723be_phy_path_a_iqk()
1535 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xc7f87); _rtl8723be_phy_path_a_iqk()
1540 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_a_iqk()
1541 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_a_iqk()
1543 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_a_iqk()
1544 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_iqk()
1545 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_iqk()
1546 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_iqk()
1548 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); _rtl8723be_phy_path_a_iqk()
1549 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); _rtl8723be_phy_path_a_iqk()
1550 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_iqk()
1551 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_iqk()
1553 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl8723be_phy_path_a_iqk()
1555 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_iqk()
1558 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_a_iqk()
1559 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_a_iqk()
1564 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_iqk()
1567 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl8723be_phy_path_a_iqk()
1568 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl8723be_phy_path_a_iqk()
1569 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl8723be_phy_path_a_iqk()
1595 static u8 _rtl8723be_phy_path_a_rx_iqk(struct ieee80211_hw *hw) _rtl8723be_phy_path_a_rx_iqk() argument
1601 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk()
1604 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk()
1608 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1); _rtl8723be_phy_path_a_rx_iqk()
1609 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl8723be_phy_path_a_rx_iqk()
1610 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); _rtl8723be_phy_path_a_rx_iqk()
1612 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7fb7); _rtl8723be_phy_path_a_rx_iqk()
1613 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_rx_iqk()
1616 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_a_rx_iqk()
1617 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_a_rx_iqk()
1620 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_a_rx_iqk()
1621 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk()
1622 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk()
1623 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk()
1625 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); _rtl8723be_phy_path_a_rx_iqk()
1626 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_rx_iqk()
1627 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_rx_iqk()
1628 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_rx_iqk()
1631 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl8723be_phy_path_a_rx_iqk()
1634 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_rx_iqk()
1637 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_a_rx_iqk()
1638 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_a_rx_iqk()
1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk()
1646 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk()
1647 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk()
1648 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk()
1672 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); _rtl8723be_phy_path_a_rx_iqk()
1676 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk()
1677 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1); _rtl8723be_phy_path_a_rx_iqk()
1678 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl8723be_phy_path_a_rx_iqk()
1679 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); _rtl8723be_phy_path_a_rx_iqk()
1681 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77); _rtl8723be_phy_path_a_rx_iqk()
1684 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0xf80); _rtl8723be_phy_path_a_rx_iqk()
1685 rtl_set_rfreg(hw, RF90_PATH_A, 0x55, RFREG_OFFSET_MASK, 0x4021f); _rtl8723be_phy_path_a_rx_iqk()
1688 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_a_rx_iqk()
1691 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk()
1692 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_a_rx_iqk()
1693 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk()
1694 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk()
1696 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_rx_iqk()
1697 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); _rtl8723be_phy_path_a_rx_iqk()
1698 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_rx_iqk()
1699 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_rx_iqk()
1702 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); _rtl8723be_phy_path_a_rx_iqk()
1705 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_rx_iqk()
1708 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_a_rx_iqk()
1709 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_a_rx_iqk()
1714 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk()
1717 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk()
1718 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk()
1721 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk()
1722 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x780); _rtl8723be_phy_path_a_rx_iqk()
1742 static u8 _rtl8723be_phy_path_b_iqk(struct ieee80211_hw *hw) _rtl8723be_phy_path_b_iqk() argument
1748 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_iqk()
1750 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); _rtl8723be_phy_path_b_iqk()
1753 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020); _rtl8723be_phy_path_b_iqk()
1754 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x40fc1); _rtl8723be_phy_path_b_iqk()
1758 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_b_iqk()
1759 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_b_iqk()
1761 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_b_iqk()
1762 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_iqk()
1763 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_iqk()
1764 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_iqk()
1766 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); _rtl8723be_phy_path_b_iqk()
1767 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_iqk()
1768 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_iqk()
1769 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_iqk()
1772 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl8723be_phy_path_b_iqk()
1775 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_b_iqk()
1778 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_b_iqk()
1779 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_b_iqk()
1784 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_iqk()
1787 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_iqk()
1788 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_iqk()
1789 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_iqk()
1815 static u8 _rtl8723be_phy_path_b_rx_iqk(struct ieee80211_hw *hw) _rtl8723be_phy_path_b_rx_iqk() argument
1821 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk()
1823 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); _rtl8723be_phy_path_b_rx_iqk()
1827 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); _rtl8723be_phy_path_b_rx_iqk()
1828 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl8723be_phy_path_b_rx_iqk()
1829 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); _rtl8723be_phy_path_b_rx_iqk()
1830 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ff7); _rtl8723be_phy_path_b_rx_iqk()
1833 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020); _rtl8723be_phy_path_b_rx_iqk()
1834 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fed); _rtl8723be_phy_path_b_rx_iqk()
1837 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_b_rx_iqk()
1838 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_b_rx_iqk()
1841 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_b_rx_iqk()
1842 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk()
1843 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk()
1844 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk()
1846 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); _rtl8723be_phy_path_b_rx_iqk()
1847 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_rx_iqk()
1848 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_rx_iqk()
1849 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_rx_iqk()
1852 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl8723be_phy_path_b_rx_iqk()
1854 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_b_rx_iqk()
1857 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_b_rx_iqk()
1858 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_b_rx_iqk()
1863 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk()
1865 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk()
1866 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk()
1867 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk()
1891 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); _rtl8723be_phy_path_b_rx_iqk()
1896 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk()
1897 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1); _rtl8723be_phy_path_b_rx_iqk()
1898 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); _rtl8723be_phy_path_b_rx_iqk()
1899 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); _rtl8723be_phy_path_b_rx_iqk()
1900 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77); _rtl8723be_phy_path_b_rx_iqk()
1901 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x0); _rtl8723be_phy_path_b_rx_iqk()
1904 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020); _rtl8723be_phy_path_b_rx_iqk()
1905 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fbd); _rtl8723be_phy_path_b_rx_iqk()
1908 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_b_rx_iqk()
1911 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk()
1912 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_b_rx_iqk()
1913 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk()
1914 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk()
1916 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_rx_iqk()
1917 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); _rtl8723be_phy_path_b_rx_iqk()
1918 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_rx_iqk()
1919 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_rx_iqk()
1922 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); _rtl8723be_phy_path_b_rx_iqk()
1924 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_b_rx_iqk()
1927 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_b_rx_iqk()
1928 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_b_rx_iqk()
1933 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk()
1935 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk()
1936 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk()
1959 static void _rtl8723be_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl8723be_phy_path_b_fill_iqk_matrix() argument
1971 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, _rtl8723be_phy_path_b_fill_iqk_matrix()
1977 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); _rtl8723be_phy_path_b_fill_iqk_matrix()
1978 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), _rtl8723be_phy_path_b_fill_iqk_matrix()
1984 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, _rtl8723be_phy_path_b_fill_iqk_matrix()
1986 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, _rtl8723be_phy_path_b_fill_iqk_matrix()
1988 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), _rtl8723be_phy_path_b_fill_iqk_matrix()
1993 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); _rtl8723be_phy_path_b_fill_iqk_matrix()
1995 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); _rtl8723be_phy_path_b_fill_iqk_matrix()
1997 /* rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); */ _rtl8723be_phy_path_b_fill_iqk_matrix()
2001 static bool _rtl8723be_phy_simularity_compare(struct ieee80211_hw *hw, _rtl8723be_phy_simularity_compare() argument
2076 static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, _rtl8723be_phy_iq_calibrate() argument
2079 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_iq_calibrate()
2105 tmp_reg_c50 = rtl_get_bbreg(hw, 0xc50, MASKBYTE0); _rtl8723be_phy_iq_calibrate()
2106 tmp_reg_c58 = rtl_get_bbreg(hw, 0xc58, MASKBYTE0); _rtl8723be_phy_iq_calibrate()
2109 rtl8723_save_adda_registers(hw, adda_reg, _rtl8723be_phy_iq_calibrate()
2111 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg, _rtl8723be_phy_iq_calibrate()
2113 rtl8723_save_adda_registers(hw, iqk_bb_reg, _rtl8723be_phy_iq_calibrate()
2117 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl8723be_phy_iq_calibrate()
2119 rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw, _rtl8723be_phy_iq_calibrate()
2124 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); _rtl8723be_phy_iq_calibrate()
2126 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl8723be_phy_iq_calibrate()
2129 rtl_set_bbreg(hw, 0xa04, 0x0f000000, 0xf); _rtl8723be_phy_iq_calibrate()
2130 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl8723be_phy_iq_calibrate()
2131 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl8723be_phy_iq_calibrate()
2132 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl8723be_phy_iq_calibrate()
2136 patha_ok = _rtl8723be_phy_path_a_iqk(hw); _rtl8723be_phy_iq_calibrate()
2140 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl8723be_phy_iq_calibrate()
2142 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl8723be_phy_iq_calibrate()
2152 patha_ok = _rtl8723be_phy_path_a_rx_iqk(hw); _rtl8723be_phy_iq_calibrate()
2156 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl8723be_phy_iq_calibrate()
2158 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl8723be_phy_iq_calibrate()
2172 pathb_ok = _rtl8723be_phy_path_b_iqk(hw); _rtl8723be_phy_iq_calibrate()
2176 result[t][4] = (rtl_get_bbreg(hw, 0xe94, _rtl8723be_phy_iq_calibrate()
2179 result[t][5] = (rtl_get_bbreg(hw, 0xe9c, _rtl8723be_phy_iq_calibrate()
2189 pathb_ok = _rtl8723be_phy_path_b_rx_iqk(hw); _rtl8723be_phy_iq_calibrate()
2193 result[t][6] = (rtl_get_bbreg(hw, 0xea4, _rtl8723be_phy_iq_calibrate()
2196 result[t][7] = (rtl_get_bbreg(hw, 0xeac, _rtl8723be_phy_iq_calibrate()
2207 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); _rtl8723be_phy_iq_calibrate()
2210 rtl8723_phy_reload_adda_registers(hw, adda_reg, _rtl8723be_phy_iq_calibrate()
2212 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl8723be_phy_iq_calibrate()
2214 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg, _rtl8723be_phy_iq_calibrate()
2218 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); _rtl8723be_phy_iq_calibrate()
2219 /*rtl_set_rfreg(hw, RF90_PATH_B, 0xb0, 0xfffff, path_sel_rf);*/ _rtl8723be_phy_iq_calibrate()
2221 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); _rtl8723be_phy_iq_calibrate()
2222 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50); _rtl8723be_phy_iq_calibrate()
2224 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, 0x50); _rtl8723be_phy_iq_calibrate()
2225 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_reg_c58); _rtl8723be_phy_iq_calibrate()
2227 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); _rtl8723be_phy_iq_calibrate()
2228 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); _rtl8723be_phy_iq_calibrate()
2255 static void _rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl8723be_phy_lc_calibrate() argument
2259 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_lc_calibrate()
2269 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); _rtl8723be_phy_lc_calibrate()
2272 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, _rtl8723be_phy_lc_calibrate()
2275 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, _rtl8723be_phy_lc_calibrate()
2279 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl8723be_phy_lc_calibrate()
2282 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); _rtl8723be_phy_lc_calibrate()
2284 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0); _rtl8723be_phy_lc_calibrate()
2285 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a); _rtl8723be_phy_lc_calibrate()
2292 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0); _rtl8723be_phy_lc_calibrate()
2296 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); _rtl8723be_phy_lc_calibrate()
2299 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, _rtl8723be_phy_lc_calibrate()
2308 static void _rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, _rtl8723be_phy_set_rfpath_switch() argument
2311 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_set_rfpath_switch()
2315 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1); _rtl8723be_phy_set_rfpath_switch()
2317 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2); _rtl8723be_phy_set_rfpath_switch()
2323 void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl8723be_phy_iq_calibrate() argument
2325 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_iq_calibrate()
2354 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg, rtl8723be_phy_iq_calibrate()
2359 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); rtl8723be_phy_iq_calibrate()
2360 /* path_sel_rf = rtl_get_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff); */ rtl8723be_phy_iq_calibrate()
2375 _rtl8723be_phy_iq_calibrate(hw, result, i, true); rtl8723be_phy_iq_calibrate()
2377 is12simular = _rtl8723be_phy_simularity_compare(hw, rtl8723be_phy_iq_calibrate()
2386 is13simular = _rtl8723be_phy_simularity_compare(hw, rtl8723be_phy_iq_calibrate()
2393 is23simular = _rtl8723be_phy_simularity_compare(hw, rtl8723be_phy_iq_calibrate()
2441 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, rtl8723be_phy_iq_calibrate()
2445 _rtl8723be_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result, rtl8723be_phy_iq_calibrate()
2458 rtl8723_save_adda_registers(hw, iqk_bb_reg, rtl8723be_phy_iq_calibrate()
2461 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); rtl8723be_phy_iq_calibrate()
2462 /* rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff, path_sel_rf); */ rtl8723be_phy_iq_calibrate()
2469 void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw) rtl8723be_phy_lc_calibrate() argument
2471 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_lc_calibrate()
2486 _rtl8723be_phy_lc_calibrate(hw, false); rtl8723be_phy_lc_calibrate()
2491 void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) rtl8723be_phy_set_rfpath_switch() argument
2493 _rtl8723be_phy_set_rfpath_switch(hw, bmain, true); rtl8723be_phy_set_rfpath_switch()
2496 bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl8723be_phy_set_io_cmd() argument
2498 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_set_io_cmd()
2529 rtl8723be_phy_set_io(hw); rtl8723be_phy_set_io_cmd()
2534 static void rtl8723be_phy_set_io(struct ieee80211_hw *hw) rtl8723be_phy_set_io() argument
2536 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_set_io()
2546 /*rtl92c_dm_write_dig(hw);*/ rtl8723be_phy_set_io()
2547 rtl8723be_phy_set_txpower_level(hw, rtlphy->current_channel); rtl8723be_phy_set_io()
2548 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); rtl8723be_phy_set_io()
2553 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); rtl8723be_phy_set_io()
2565 static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw) rtl8723be_phy_set_rf_on() argument
2567 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_phy_set_rf_on()
2576 static void _rtl8723be_phy_set_rf_sleep(struct ieee80211_hw *hw) _rtl8723be_phy_set_rf_sleep() argument
2578 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_set_rf_sleep()
2581 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl8723be_phy_set_rf_sleep()
2586 static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl8723be_phy_set_rf_power_state() argument
2589 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_phy_set_rf_power_state()
2590 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8723be_phy_set_rf_power_state()
2591 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl8723be_phy_set_rf_power_state()
2592 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl8723be_phy_set_rf_power_state()
2607 rtstatus = rtl_ps_enable_nic(hw); _rtl8723be_phy_set_rf_power_state()
2617 rtl8723be_phy_set_rf_on(hw); _rtl8723be_phy_set_rf_power_state()
2620 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); _rtl8723be_phy_set_rf_power_state()
2622 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); _rtl8723be_phy_set_rf_power_state()
2660 rtl_ps_disable_nic(hw); _rtl8723be_phy_set_rf_power_state()
2664 rtlpriv->cfg->ops->led_control(hw, _rtl8723be_phy_set_rf_power_state()
2667 rtlpriv->cfg->ops->led_control(hw, _rtl8723be_phy_set_rf_power_state()
2705 _rtl8723be_phy_set_rf_sleep(hw); _rtl8723be_phy_set_rf_power_state()
2719 bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl8723be_phy_set_rf_power_state() argument
2722 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_phy_set_rf_power_state()
2728 bresult = _rtl8723be_phy_set_rf_power_state(hw, rfpwr_state); rtl8723be_phy_set_rf_power_state()
405 _rtl8723be_phy_convert_txpower_dbm_to_relative_value( struct ieee80211_hw *hw) _rtl8723be_phy_convert_txpower_dbm_to_relative_value() argument
H A DMakefile4 hw.o \
H A Dled.c31 static void _rtl8723be_init_led(struct ieee80211_hw *hw, struct rtl_led *pled, _rtl8723be_init_led() argument
34 pled->hw = hw; _rtl8723be_init_led()
39 void rtl8723be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl8723be_sw_led_on() argument
42 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_sw_led_on()
67 void rtl8723be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl8723be_sw_led_off() argument
69 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_sw_led_off()
70 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl8723be_sw_led_off()
109 void rtl8723be_init_sw_leds(struct ieee80211_hw *hw) rtl8723be_init_sw_leds() argument
111 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl8723be_init_sw_leds()
112 _rtl8723be_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0); rtl8723be_init_sw_leds()
113 _rtl8723be_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1); rtl8723be_init_sw_leds()
116 static void _rtl8723be_sw_led_control(struct ieee80211_hw *hw, _rtl8723be_sw_led_control() argument
119 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8723be_sw_led_control()
125 rtl8723be_sw_led_on(hw, pled0); _rtl8723be_sw_led_control()
128 rtl8723be_sw_led_off(hw, pled0); _rtl8723be_sw_led_control()
135 void rtl8723be_led_control(struct ieee80211_hw *hw, rtl8723be_led_control() argument
138 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_led_control()
139 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_led_control()
152 _rtl8723be_sw_led_control(hw, ledaction); rtl8723be_led_control()
H A Dphy.h46 #define RT_CANNOT_IO(hw) false
107 u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw,
110 void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw,
113 bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw);
114 bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw);
115 bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw);
116 void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
117 void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw,
119 void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw,
121 void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
122 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,
124 void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw);
125 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw);
126 void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
128 void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw);
129 void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
130 bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
132 bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
133 bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
H A Dhw.c42 #include "hw.h"
49 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw) _rtl8723be_return_beacon_queue_skb() argument
51 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_return_beacon_queue_skb()
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl8723be_return_beacon_queue_skb()
71 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw, _rtl8723be_set_bcn_ctrl_reg() argument
74 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl8723be_set_bcn_ctrl_reg()
75 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_set_bcn_ctrl_reg()
83 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw) _rtl8723be_stop_tx_beacon() argument
85 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_stop_tx_beacon()
96 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw) _rtl8723be_resume_tx_beacon() argument
98 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_resume_tx_beacon()
109 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw) _rtl8723be_enable_bcn_sub_func() argument
111 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1)); _rtl8723be_enable_bcn_sub_func()
114 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw) _rtl8723be_disable_bcn_sub_func() argument
116 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0); _rtl8723be_disable_bcn_sub_func()
119 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val, _rtl8723be_set_fw_clock_on() argument
122 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_set_fw_clock_on()
123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_set_fw_clock_on()
127 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, _rtl8723be_set_fw_clock_on()
155 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, _rtl8723be_set_fw_clock_on()
188 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val) _rtl8723be_set_fw_clock_off() argument
190 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_set_fw_clock_off()
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_set_fw_clock_off()
192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl8723be_set_fw_clock_off()
204 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); _rtl8723be_set_fw_clock_off()
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl8723be_set_fw_clock_off()
243 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw) _rtl8723be_set_fw_ps_rf_on() argument
247 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true); _rtl8723be_set_fw_ps_rf_on()
250 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw) _rtl8723be_fwlps_leave() argument
252 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_fwlps_leave()
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl8723be_fwlps_leave()
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_fwlps_leave()
260 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false); _rtl8723be_fwlps_leave()
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl8723be_fwlps_leave()
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl8723be_fwlps_leave()
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl8723be_fwlps_leave()
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl8723be_fwlps_leave()
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl8723be_fwlps_leave()
278 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw) _rtl8723be_fwlps_enter() argument
280 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_fwlps_enter()
281 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl8723be_fwlps_enter()
282 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_fwlps_enter()
288 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl8723be_fwlps_enter()
290 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl8723be_fwlps_enter()
293 _rtl8723be_set_fw_clock_off(hw, rpwm_val); _rtl8723be_fwlps_enter()
296 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, _rtl8723be_fwlps_enter()
298 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, _rtl8723be_fwlps_enter()
300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, _rtl8723be_fwlps_enter()
306 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) rtl8723be_get_hw_reg() argument
308 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_get_hw_reg()
309 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_get_hw_reg()
310 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_get_hw_reg()
323 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, rtl8723be_get_hw_reg()
358 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw) _rtl8723be_download_rsvd_page() argument
360 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_download_rsvd_page()
369 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3)); _rtl8723be_download_rsvd_page()
370 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0); _rtl8723be_download_rsvd_page()
381 _rtl8723be_return_beacon_queue_skb(hw); _rtl8723be_download_rsvd_page()
383 rtl8723be_set_fw_rsvdpagepkt(hw, 0); _rtl8723be_download_rsvd_page()
398 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); _rtl8723be_download_rsvd_page()
399 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4)); _rtl8723be_download_rsvd_page()
408 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) rtl8723be_set_hw_reg() argument
410 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_hw_reg()
411 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_set_hw_reg()
412 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_set_hw_reg()
413 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723be_set_hw_reg()
414 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_set_hw_reg()
463 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, rtl8723be_set_hw_reg()
563 rtl8723_dm_init_edca_turbo(hw); rtl8723be_set_hw_reg()
566 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, rtl8723be_set_hw_reg()
643 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val)); rtl8723be_set_hw_reg()
660 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); rtl8723be_set_hw_reg()
666 _rtl8723be_set_fw_ps_rf_on(hw); rtl8723be_set_hw_reg()
672 _rtl8723be_fwlps_enter(hw); rtl8723be_set_hw_reg()
674 _rtl8723be_fwlps_leave(hw); rtl8723be_set_hw_reg()
681 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); rtl8723be_set_hw_reg()
682 _rtl8723be_download_rsvd_page(hw); rtl8723be_set_hw_reg()
684 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus); rtl8723be_set_hw_reg()
688 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); rtl8723be_set_hw_reg()
702 _rtl8723be_stop_tx_beacon(hw); rtl8723be_set_hw_reg()
704 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3)); rtl8723be_set_hw_reg()
711 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl8723be_set_hw_reg()
714 _rtl8723be_resume_tx_beacon(hw); rtl8723be_set_hw_reg()
721 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array); rtl8723be_set_hw_reg()
732 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) _rtl8723be_llt_write() argument
734 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_llt_write()
759 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw) _rtl8723be_llt_table_init() argument
761 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_llt_table_init()
782 status = _rtl8723be_llt_write(hw, i, i + 1); _rtl8723be_llt_table_init()
787 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); _rtl8723be_llt_table_init()
793 status = _rtl8723be_llt_write(hw, i, (i + 1)); _rtl8723be_llt_table_init()
798 status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy); _rtl8723be_llt_table_init()
808 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw) _rtl8723be_gen_refresh_led_state() argument
810 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_gen_refresh_led_state()
811 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8723be_gen_refresh_led_state()
812 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl8723be_gen_refresh_led_state()
819 rtl8723be_sw_led_on(hw, pled0); _rtl8723be_gen_refresh_led_state()
821 rtl8723be_sw_led_on(hw, pled0); _rtl8723be_gen_refresh_led_state()
823 rtl8723be_sw_led_off(hw, pled0); _rtl8723be_gen_refresh_led_state()
826 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw) _rtl8723be_init_mac() argument
828 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_init_mac()
829 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl8723be_init_mac()
879 if (_rtl8723be_llt_table_init(hw) == false) _rtl8723be_init_mac()
935 rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */ _rtl8723be_init_mac()
936 rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */ _rtl8723be_init_mac()
937 rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */; _rtl8723be_init_mac()
938 rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */; _rtl8723be_init_mac()
939 rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */; _rtl8723be_init_mac()
940 rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */; _rtl8723be_init_mac()
941 rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */; _rtl8723be_init_mac()
942 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */; _rtl8723be_init_mac()
947 _rtl8723be_gen_refresh_led_state(hw); _rtl8723be_init_mac()
951 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw) _rtl8723be_hw_configure() argument
953 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_hw_configure()
954 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl8723be_hw_configure()
1082 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw) _rtl8723be_enable_aspm_back_door() argument
1084 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_enable_aspm_back_door()
1135 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw) rtl8723be_enable_hw_security_config() argument
1137 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_enable_hw_security_config()
1147 "not open hw encryption\n"); rtl8723be_enable_hw_security_config()
1165 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); rtl8723be_enable_hw_security_config()
1168 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw) _rtl8723be_poweroff_adapter() argument
1170 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_poweroff_adapter()
1171 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_poweroff_adapter()
1185 rtl8723be_firmware_selfreset(hw); _rtl8723be_poweroff_adapter()
1344 int rtl8723be_hw_init(struct ieee80211_hw *hw) rtl8723be_hw_init() argument
1346 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_hw_init()
1347 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_hw_init()
1348 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_hw_init()
1350 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_hw_init()
1351 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_hw_init()
1363 rtlpriv->intf_ops->disable_aspm(hw); rtl8723be_hw_init()
1379 _rtl8723be_poweroff_adapter(hw); rtl8723be_hw_init()
1382 rtstatus = _rtl8723be_init_mac(hw); rtl8723be_hw_init()
1392 err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT); rtl8723be_hw_init()
1402 rtl8723be_phy_mac_config(hw); rtl8723be_hw_init()
1412 rtl8723be_phy_bb_config(hw); rtl8723be_hw_init()
1413 rtl8723be_phy_rf_config(hw); rtl8723be_hw_init()
1415 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, rtl8723be_hw_init()
1417 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, rtl8723be_hw_init()
1422 _rtl8723be_hw_configure(hw); rtl8723be_hw_init()
1424 rtl_cam_reset_all_entry(hw); rtl8723be_hw_init()
1425 rtl8723be_enable_hw_security_config(hw); rtl8723be_hw_init()
1429 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); rtl8723be_hw_init()
1430 _rtl8723be_enable_aspm_back_door(hw); rtl8723be_hw_init()
1431 rtlpriv->intf_ops->enable_aspm(hw); rtl8723be_hw_init()
1433 rtl8723be_bt_hw_init(hw); rtl8723be_hw_init()
1436 rtl8723be_phy_set_rfpath_switch(hw, 1); rtl8723be_hw_init()
1443 rtl8723be_phy_iq_calibrate(hw, false); rtl8723be_hw_init()
1446 rtl8723be_dm_check_txpower_tracking(hw); rtl8723be_hw_init()
1447 rtl8723be_phy_lc_calibrate(hw); rtl8723be_hw_init()
1461 rtl8723be_dm_init(hw); rtl8723be_hw_init()
1468 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw) _rtl8723be_read_chip_version() argument
1470 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_read_chip_version()
1500 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw, _rtl8723be_set_media_status() argument
1503 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_set_media_status()
1550 _rtl8723be_stop_tx_beacon(hw); _rtl8723be_set_media_status()
1551 _rtl8723be_enable_bcn_sub_func(hw); _rtl8723be_set_media_status()
1553 _rtl8723be_resume_tx_beacon(hw); _rtl8723be_set_media_status()
1554 _rtl8723be_disable_bcn_sub_func(hw); _rtl8723be_set_media_status()
1562 rtlpriv->cfg->ops->led_control(hw, ledaction); _rtl8723be_set_media_status()
1570 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) rtl8723be_set_check_bssid() argument
1572 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_check_bssid()
1573 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_set_check_bssid()
1581 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, rtl8723be_set_check_bssid()
1583 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4)); rtl8723be_set_check_bssid()
1586 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0); rtl8723be_set_check_bssid()
1587 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, rtl8723be_set_check_bssid()
1593 int rtl8723be_set_network_type(struct ieee80211_hw *hw, rtl8723be_set_network_type() argument
1596 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_network_type()
1598 if (_rtl8723be_set_media_status(hw, type)) rtl8723be_set_network_type()
1603 rtl8723be_set_check_bssid(hw, true); rtl8723be_set_network_type()
1605 rtl8723be_set_check_bssid(hw, false); rtl8723be_set_network_type()
1614 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci) rtl8723be_set_qos() argument
1616 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_qos()
1618 rtl8723_dm_init_edca_turbo(hw); rtl8723be_set_qos()
1637 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw) rtl8723be_enable_interrupt() argument
1639 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_enable_interrupt()
1640 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_enable_interrupt()
1650 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw) rtl8723be_disable_interrupt() argument
1652 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_disable_interrupt()
1653 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_disable_interrupt()
1661 void rtl8723be_card_disable(struct ieee80211_hw *hw) rtl8723be_card_disable() argument
1663 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_card_disable()
1664 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_card_disable()
1665 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_card_disable()
1670 _rtl8723be_set_media_status(hw, opmode); rtl8723be_card_disable()
1673 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); rtl8723be_card_disable()
1675 _rtl8723be_poweroff_adapter(hw); rtl8723be_card_disable()
1681 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw, rtl8723be_interrupt_recognized() argument
1684 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_interrupt_recognized()
1685 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_interrupt_recognized()
1695 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw) rtl8723be_set_beacon_related_registers() argument
1697 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_beacon_related_registers()
1698 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_set_beacon_related_registers()
1703 rtl8723be_disable_interrupt(hw); rtl8723be_set_beacon_related_registers()
1710 rtl8723be_enable_interrupt(hw); rtl8723be_set_beacon_related_registers()
1713 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw) rtl8723be_set_beacon_interval() argument
1715 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_beacon_interval()
1716 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_set_beacon_interval()
1721 rtl8723be_disable_interrupt(hw); rtl8723be_set_beacon_interval()
1723 rtl8723be_enable_interrupt(hw); rtl8723be_set_beacon_interval()
1726 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw, rtl8723be_update_interrupt_mask() argument
1729 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_update_interrupt_mask()
1730 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl8723be_update_interrupt_mask()
1739 rtl8723be_disable_interrupt(hw); rtl8723be_update_interrupt_mask()
1740 rtl8723be_enable_interrupt(hw); rtl8723be_update_interrupt_mask()
1756 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw, _rtl8723be_read_power_value_fromprom() argument
1761 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_read_power_value_fromprom()
1955 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, _rtl8723be_read_txpower_info_from_hwpg() argument
1959 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_read_txpower_info_from_hwpg()
1960 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723be_read_txpower_info_from_hwpg()
1966 _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail, _rtl8723be_read_txpower_info_from_hwpg()
2023 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw, _rtl8723be_read_adapter_info() argument
2026 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_read_adapter_info()
2027 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl8723be_read_adapter_info()
2028 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_read_adapter_info()
2059 rtl_efuse_shadow_map_update(hw); _rtl8723be_read_adapter_info()
2110 _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, _rtl8723be_read_adapter_info()
2113 rtl8723be_read_bt_coexist_info_from_hwpg(hw, _rtl8723be_read_adapter_info()
2237 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw) _rtl8723be_hal_customized_behavior() argument
2239 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl8723be_hal_customized_behavior()
2240 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl8723be_hal_customized_behavior()
2241 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl8723be_hal_customized_behavior()
2261 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw) rtl8723be_read_eeprom_info() argument
2263 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_read_eeprom_info()
2264 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723be_read_eeprom_info()
2266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723be_read_eeprom_info()
2269 rtlhal->version = _rtl8723be_read_chip_version(hw); rtl8723be_read_eeprom_info()
2288 _rtl8723be_read_adapter_info(hw, false); rtl8723be_read_eeprom_info()
2292 _rtl8723be_hal_customized_behavior(hw); rtl8723be_read_eeprom_info()
2295 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, _rtl8723be_mrate_idx_to_arfr_id() argument
2326 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw, rtl8723be_update_hal_rate_mask() argument
2330 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_update_hal_rate_mask()
2332 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_update_hal_rate_mask()
2442 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) | rtl8723be_update_hal_rate_mask()
2458 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask); rtl8723be_update_hal_rate_mask()
2459 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0); rtl8723be_update_hal_rate_mask()
2462 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw, rtl8723be_update_hal_rate_tbl() argument
2466 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_update_hal_rate_tbl()
2468 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level); rtl8723be_update_hal_rate_tbl()
2471 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw) rtl8723be_update_channel_access_setting() argument
2473 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_update_channel_access_setting()
2474 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_update_channel_access_setting()
2477 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); rtl8723be_update_channel_access_setting()
2482 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); rtl8723be_update_channel_access_setting()
2485 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) rtl8723be_gpio_radio_on_off_checking() argument
2487 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_gpio_radio_on_off_checking()
2488 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl8723be_gpio_radio_on_off_checking()
2555 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index, rtl8723be_set_key() argument
2559 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_set_key()
2560 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl8723be_set_key()
2561 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl8723be_set_key()
2584 rtl_cam_mark_invalid(hw, cam_offset + idx); rtl8723be_set_key()
2585 rtl_cam_empty_entry(hw, cam_offset + idx); rtl8723be_set_key()
2624 entry_id = rtl_cam_get_free_entry(hw, rtl8723be_set_key()
2629 "Can not find free hw security cam entry\n"); rtl8723be_set_key()
2646 rtl_cam_del_entry(hw, p_macaddr); rtl8723be_set_key()
2647 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); rtl8723be_set_key()
2655 rtl_cam_add_one_entry(hw, macaddr, key_index, rtl8723be_set_key()
2664 rtl_cam_add_one_entry(hw, rtl8723be_set_key()
2674 rtl_cam_add_one_entry(hw, macaddr, key_index, rtl8723be_set_key()
2683 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, rtl8723be_read_bt_coexist_info_from_hwpg() argument
2686 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_read_bt_coexist_info_from_hwpg()
2712 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw) rtl8723be_bt_reg_init() argument
2714 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_bt_reg_init()
2724 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw) rtl8723be_bt_hw_init() argument
2726 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723be_bt_hw_init()
2733 void rtl8723be_suspend(struct ieee80211_hw *hw) rtl8723be_suspend() argument
2737 void rtl8723be_resume(struct ieee80211_hw *hw) rtl8723be_resume() argument
/linux-4.4.14/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_api.c51 * @hw: Pointer to the HW structure
53 static void pch_gbe_plat_get_bus_info(struct pch_gbe_hw *hw) pch_gbe_plat_get_bus_info() argument
55 hw->bus.type = pch_gbe_bus_type_pci_express; pch_gbe_plat_get_bus_info()
56 hw->bus.speed = pch_gbe_bus_speed_2500; pch_gbe_plat_get_bus_info()
57 hw->bus.width = pch_gbe_bus_width_pcie_x1; pch_gbe_plat_get_bus_info()
62 * @hw: Pointer to the HW structure
67 static s32 pch_gbe_plat_init_hw(struct pch_gbe_hw *hw) pch_gbe_plat_init_hw() argument
71 ret_val = pch_gbe_phy_get_id(hw); pch_gbe_plat_init_hw()
73 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_plat_init_hw()
78 pch_gbe_phy_init_setting(hw); pch_gbe_plat_init_hw()
81 pch_gbe_phy_set_rgmii(hw); pch_gbe_plat_init_hw()
100 * @hw: Pointer to the HW structure
102 static void pch_gbe_plat_init_function_pointers(struct pch_gbe_hw *hw) pch_gbe_plat_init_function_pointers() argument
105 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US; pch_gbe_plat_init_function_pointers()
107 hw->func = &pch_gbe_ops; pch_gbe_plat_init_function_pointers()
112 * @hw: Pointer to the HW structure
117 s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw) pch_gbe_hal_setup_init_funcs() argument
119 if (!hw->reg) { pch_gbe_hal_setup_init_funcs()
120 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_hal_setup_init_funcs()
125 pch_gbe_plat_init_function_pointers(hw); pch_gbe_hal_setup_init_funcs()
131 * @hw: Pointer to the HW structure
133 void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw) pch_gbe_hal_get_bus_info() argument
135 if (!hw->func->get_bus_info) { pch_gbe_hal_get_bus_info()
136 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_hal_get_bus_info()
141 hw->func->get_bus_info(hw); pch_gbe_hal_get_bus_info()
146 * @hw: Pointer to the HW structure
151 s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw) pch_gbe_hal_init_hw() argument
153 if (!hw->func->init_hw) { pch_gbe_hal_init_hw()
154 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_hal_init_hw()
159 return hw->func->init_hw(hw); pch_gbe_hal_init_hw()
164 * @hw: Pointer to the HW structure
171 s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset, pch_gbe_hal_read_phy_reg() argument
174 if (!hw->func->read_phy_reg) pch_gbe_hal_read_phy_reg()
176 return hw->func->read_phy_reg(hw, offset, data); pch_gbe_hal_read_phy_reg()
181 * @hw: Pointer to the HW structure
188 s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset, pch_gbe_hal_write_phy_reg() argument
191 if (!hw->func->write_phy_reg) pch_gbe_hal_write_phy_reg()
193 return hw->func->write_phy_reg(hw, offset, data); pch_gbe_hal_write_phy_reg()
198 * @hw: Pointer to the HW structure
200 void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw) pch_gbe_hal_phy_hw_reset() argument
202 if (!hw->func->reset_phy) { pch_gbe_hal_phy_hw_reset()
203 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_hal_phy_hw_reset()
208 hw->func->reset_phy(hw); pch_gbe_hal_phy_hw_reset()
213 * @hw: Pointer to the HW structure
215 void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw) pch_gbe_hal_phy_sw_reset() argument
217 if (!hw->func->sw_reset_phy) { pch_gbe_hal_phy_sw_reset()
218 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_hal_phy_sw_reset()
223 hw->func->sw_reset_phy(hw); pch_gbe_hal_phy_sw_reset()
228 * @hw: Pointer to the HW structure
233 s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw) pch_gbe_hal_read_mac_addr() argument
235 if (!hw->func->read_mac_addr) { pch_gbe_hal_read_mac_addr()
236 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_hal_read_mac_addr()
241 return hw->func->read_mac_addr(hw); pch_gbe_hal_read_mac_addr()
246 * @hw: Pointer to the HW structure
248 void pch_gbe_hal_power_up_phy(struct pch_gbe_hw *hw) pch_gbe_hal_power_up_phy() argument
250 if (hw->func->power_up_phy) pch_gbe_hal_power_up_phy()
251 hw->func->power_up_phy(hw); pch_gbe_hal_power_up_phy()
256 * @hw: Pointer to the HW structure
258 void pch_gbe_hal_power_down_phy(struct pch_gbe_hw *hw) pch_gbe_hal_power_down_phy() argument
260 if (hw->func->power_down_phy) pch_gbe_hal_power_down_phy()
261 hw->func->power_down_phy(hw); pch_gbe_hal_power_down_phy()
H A Dpch_gbe_phy.c101 * @hw: Pointer to the HW structure
106 s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw) pch_gbe_phy_get_id() argument
108 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_phy_get_id()
109 struct pch_gbe_phy_info *phy = &hw->phy; pch_gbe_phy_get_id()
114 ret = pch_gbe_phy_read_reg_miic(hw, PHY_ID1, &phy_id1); pch_gbe_phy_get_id()
117 ret = pch_gbe_phy_read_reg_miic(hw, PHY_ID2, &phy_id2); pch_gbe_phy_get_id()
135 * @hw: Pointer to the HW structure
142 s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data) pch_gbe_phy_read_reg_miic() argument
144 struct pch_gbe_phy_info *phy = &hw->phy; pch_gbe_phy_read_reg_miic()
147 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_phy_read_reg_miic()
153 *data = pch_gbe_mac_ctrl_miim(hw, phy->addr, PCH_GBE_HAL_MIIM_READ, pch_gbe_phy_read_reg_miic()
160 * @hw: Pointer to the HW structure
167 s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data) pch_gbe_phy_write_reg_miic() argument
169 struct pch_gbe_phy_info *phy = &hw->phy; pch_gbe_phy_write_reg_miic()
172 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_phy_write_reg_miic()
178 pch_gbe_mac_ctrl_miim(hw, phy->addr, PCH_GBE_HAL_MIIM_WRITE, pch_gbe_phy_write_reg_miic()
185 * @hw: Pointer to the HW structure
187 void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw) pch_gbe_phy_sw_reset() argument
191 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &phy_ctrl); pch_gbe_phy_sw_reset()
193 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, phy_ctrl); pch_gbe_phy_sw_reset()
199 * @hw: Pointer to the HW structure
201 void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw) pch_gbe_phy_hw_reset() argument
203 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, PHY_CONTROL_DEFAULT); pch_gbe_phy_hw_reset()
204 pch_gbe_phy_write_reg_miic(hw, PHY_AUTONEG_ADV, pch_gbe_phy_hw_reset()
206 pch_gbe_phy_write_reg_miic(hw, PHY_NEXT_PAGE_TX, pch_gbe_phy_hw_reset()
208 pch_gbe_phy_write_reg_miic(hw, PHY_1000T_CTRL, PHY_1000T_CTRL_DEFAULT); pch_gbe_phy_hw_reset()
209 pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, pch_gbe_phy_hw_reset()
215 * @hw: Pointer to the HW structure
217 void pch_gbe_phy_power_up(struct pch_gbe_hw *hw) pch_gbe_phy_power_up() argument
225 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); pch_gbe_phy_power_up()
227 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); pch_gbe_phy_power_up()
232 * @hw: Pointer to the HW structure
234 void pch_gbe_phy_power_down(struct pch_gbe_hw *hw) pch_gbe_phy_power_down() argument
244 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); pch_gbe_phy_power_down()
246 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); pch_gbe_phy_power_down()
252 * @hw: Pointer to the HW structure
254 void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw) pch_gbe_phy_set_rgmii() argument
256 pch_gbe_phy_sw_reset(hw); pch_gbe_phy_set_rgmii()
261 * @hw: Pointer to the HW structure
266 static int pch_gbe_phy_tx_clk_delay(struct pch_gbe_hw *hw) pch_gbe_phy_tx_clk_delay() argument
272 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_phy_tx_clk_delay()
276 switch (hw->phy.id) { pch_gbe_phy_tx_clk_delay()
280 pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_OFF, &mii_reg); pch_gbe_phy_tx_clk_delay()
281 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF, pch_gbe_phy_tx_clk_delay()
286 pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg); pch_gbe_phy_tx_clk_delay()
288 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT, pch_gbe_phy_tx_clk_delay()
294 hw->phy.id); pch_gbe_phy_tx_clk_delay()
306 * @hw: Pointer to the HW structure
308 void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw) pch_gbe_phy_init_setting() argument
310 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_phy_init_setting()
319 ethtool_cmd_speed_set(&cmd, hw->mac.link_speed); pch_gbe_phy_init_setting()
320 cmd.duplex = hw->mac.link_duplex; pch_gbe_phy_init_setting()
321 cmd.advertising = hw->phy.autoneg_advertised; pch_gbe_phy_init_setting()
322 cmd.autoneg = hw->mac.autoneg; pch_gbe_phy_init_setting()
323 pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET); pch_gbe_phy_init_setting()
328 pch_gbe_phy_sw_reset(hw); pch_gbe_phy_init_setting()
330 pch_gbe_phy_read_reg_miic(hw, PHY_PHYSP_CONTROL, &mii_reg); pch_gbe_phy_init_setting()
332 pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, mii_reg); pch_gbe_phy_init_setting()
336 pch_gbe_phy_tx_clk_delay(hw); pch_gbe_phy_init_setting()
341 * @hw: Pointer to the HW structure
346 int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw) pch_gbe_phy_disable_hibernate() argument
348 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); pch_gbe_phy_disable_hibernate()
352 switch (hw->phy.id) { pch_gbe_phy_disable_hibernate()
356 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF, pch_gbe_phy_disable_hibernate()
361 pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg); pch_gbe_phy_disable_hibernate()
363 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT, pch_gbe_phy_disable_hibernate()
369 hw->phy.id); pch_gbe_phy_disable_hibernate()
H A Dpch_gbe_api.h24 s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw);
25 void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw);
26 s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw);
27 s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 *data);
28 s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset, u16 data);
29 void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw);
30 void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw);
31 s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw);
32 void pch_gbe_hal_power_up_phy(struct pch_gbe_hw *hw);
33 void pch_gbe_hal_power_down_phy(struct pch_gbe_hw *hw);
H A Dpch_gbe_phy.h26 s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw);
27 s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data);
28 s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data);
29 void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw);
30 void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw);
31 void pch_gbe_phy_power_up(struct pch_gbe_hw *hw);
32 void pch_gbe_phy_power_down(struct pch_gbe_hw *hw);
33 void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw);
34 void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw);
35 int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw);
/linux-4.4.14/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.c32 int atl1e_check_eeprom_exist(struct atl1e_hw *hw) atl1e_check_eeprom_exist() argument
36 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); atl1e_check_eeprom_exist()
39 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); atl1e_check_eeprom_exist()
41 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST); atl1e_check_eeprom_exist()
45 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw) atl1e_hw_set_mac_addr() argument
53 value = (((u32)hw->mac_addr[2]) << 24) | atl1e_hw_set_mac_addr()
54 (((u32)hw->mac_addr[3]) << 16) | atl1e_hw_set_mac_addr()
55 (((u32)hw->mac_addr[4]) << 8) | atl1e_hw_set_mac_addr()
56 (((u32)hw->mac_addr[5])) ; atl1e_hw_set_mac_addr()
57 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); atl1e_hw_set_mac_addr()
59 value = (((u32)hw->mac_addr[0]) << 8) | atl1e_hw_set_mac_addr()
60 (((u32)hw->mac_addr[1])) ; atl1e_hw_set_mac_addr()
61 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); atl1e_hw_set_mac_addr()
68 static int atl1e_get_permanent_address(struct atl1e_hw *hw) atl1e_get_permanent_address() argument
75 if (is_valid_ether_addr(hw->perm_mac_addr)) atl1e_get_permanent_address()
81 if (!atl1e_check_eeprom_exist(hw)) { atl1e_get_permanent_address()
83 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); atl1e_get_permanent_address()
85 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); atl1e_get_permanent_address()
88 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); atl1e_get_permanent_address()
97 addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR); atl1e_get_permanent_address()
98 addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4); atl1e_get_permanent_address()
103 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); atl1e_get_permanent_address()
110 bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value) atl1e_write_eeprom() argument
115 bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value) atl1e_read_eeprom() argument
123 AT_WRITE_REG(hw, REG_VPD_DATA, 0); atl1e_read_eeprom()
125 AT_WRITE_REG(hw, REG_VPD_CAP, control); atl1e_read_eeprom()
129 control = AT_READ_REG(hw, REG_VPD_CAP); atl1e_read_eeprom()
134 *p_value = AT_READ_REG(hw, REG_VPD_DATA); atl1e_read_eeprom()
140 void atl1e_force_ps(struct atl1e_hw *hw) atl1e_force_ps() argument
142 AT_WRITE_REGW(hw, REG_GPHY_CTRL, atl1e_force_ps()
149 * hw - Struct containing variables accessed by shared code
151 int atl1e_read_mac_addr(struct atl1e_hw *hw) atl1e_read_mac_addr() argument
155 err = atl1e_get_permanent_address(hw); atl1e_read_mac_addr()
158 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); atl1e_read_mac_addr()
167 u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr) atl1e_hash_mc_addr() argument
182 * hw - Struct containing variables accessed by shared code
185 void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value) atl1e_hash_set() argument
202 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); atl1e_hash_set()
206 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); atl1e_hash_set()
210 * hw - Struct containing variables accessed by shared code
213 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data) atl1e_read_phy_reg() argument
222 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); atl1e_read_phy_reg()
228 val = AT_READ_REG(hw, REG_MDIO_CTRL); atl1e_read_phy_reg()
243 * hw - Struct containing variables accessed by shared code
247 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data) atl1e_write_phy_reg() argument
258 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); atl1e_write_phy_reg()
263 val = AT_READ_REG(hw, REG_MDIO_CTRL); atl1e_write_phy_reg()
278 static void atl1e_init_pcie(struct atl1e_hw *hw) atl1e_init_pcie() argument
283 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); atl1e_init_pcie()
287 value = AT_READ_REG(hw, 0x1008); atl1e_init_pcie()
289 AT_WRITE_REG(hw, 0x1008, value); atl1e_init_pcie()
294 * hw - Struct containing variables accessed by shared code
296 static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw) atl1e_phy_setup_autoneg_adv() argument
302 if (0 != hw->mii_autoneg_adv_reg) atl1e_phy_setup_autoneg_adv()
328 switch (hw->media_type) { atl1e_phy_setup_autoneg_adv()
331 hw->autoneg_advertised = ADVERTISE_ALL; atl1e_phy_setup_autoneg_adv()
332 if (hw->nic_type == athr_l1e) { atl1e_phy_setup_autoneg_adv()
334 hw->autoneg_advertised |= ADVERTISE_1000_FULL; atl1e_phy_setup_autoneg_adv()
340 hw->autoneg_advertised = ADVERTISE_100_FULL; atl1e_phy_setup_autoneg_adv()
345 hw->autoneg_advertised = ADVERTISE_100_HALF; atl1e_phy_setup_autoneg_adv()
350 hw->autoneg_advertised = ADVERTISE_10_FULL; atl1e_phy_setup_autoneg_adv()
355 hw->autoneg_advertised = ADVERTISE_10_HALF; atl1e_phy_setup_autoneg_adv()
362 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; atl1e_phy_setup_autoneg_adv()
363 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; atl1e_phy_setup_autoneg_adv()
365 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); atl1e_phy_setup_autoneg_adv()
369 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { atl1e_phy_setup_autoneg_adv()
370 ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000, atl1e_phy_setup_autoneg_adv()
383 * hw - Struct containing variables accessed by shared code
387 int atl1e_phy_commit(struct atl1e_hw *hw) atl1e_phy_commit() argument
389 struct atl1e_adapter *adapter = hw->adapter; atl1e_phy_commit()
395 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); atl1e_phy_commit()
404 val = AT_READ_REG(hw, REG_MDIO_CTRL); atl1e_phy_commit()
420 int atl1e_phy_init(struct atl1e_hw *hw) atl1e_phy_init() argument
422 struct atl1e_adapter *adapter = hw->adapter; atl1e_phy_init()
426 if (hw->phy_configured) { atl1e_phy_init()
427 if (hw->re_autoneg) { atl1e_phy_init()
428 hw->re_autoneg = false; atl1e_phy_init()
429 return atl1e_restart_autoneg(hw); atl1e_phy_init()
435 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT); atl1e_phy_init()
437 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT | atl1e_phy_init()
443 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB); atl1e_phy_init()
446 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00); atl1e_phy_init()
450 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0); atl1e_phy_init()
455 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */ atl1e_phy_init()
456 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val); atl1e_phy_init()
460 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12); atl1e_phy_init()
463 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04); atl1e_phy_init()
467 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4); atl1e_phy_init()
470 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB); atl1e_phy_init()
474 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5); atl1e_phy_init()
477 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46); atl1e_phy_init()
484 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00); atl1e_phy_init()
491 ret_val = atl1e_phy_setup_autoneg_adv(hw); atl1e_phy_init()
499 ret_val = atl1e_phy_commit(hw); atl1e_phy_init()
505 hw->phy_configured = true; atl1e_phy_init()
512 * hw - Struct containing variables accessed by shared code
515 int atl1e_reset_hw(struct atl1e_hw *hw) atl1e_reset_hw() argument
517 struct atl1e_adapter *adapter = hw->adapter; atl1e_reset_hw()
540 AT_WRITE_REG(hw, REG_MASTER_CTRL, atl1e_reset_hw()
547 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS); atl1e_reset_hw()
567 * hw - Struct containing variables accessed by shared code
573 int atl1e_init_hw(struct atl1e_hw *hw) atl1e_init_hw() argument
577 atl1e_init_pcie(hw); atl1e_init_hw()
581 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); atl1e_init_hw()
582 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); atl1e_init_hw()
584 ret_val = atl1e_phy_init(hw); atl1e_init_hw()
592 * hw - Struct containing variables accessed by shared code
596 int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex) atl1e_get_speed_and_duplex() argument
602 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); atl1e_get_speed_and_duplex()
631 int atl1e_restart_autoneg(struct atl1e_hw *hw) atl1e_restart_autoneg() argument
635 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); atl1e_restart_autoneg()
639 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { atl1e_restart_autoneg()
640 err = atl1e_write_phy_reg(hw, MII_CTRL1000, atl1e_restart_autoneg()
641 hw->mii_1000t_ctrl_reg); atl1e_restart_autoneg()
646 err = atl1e_write_phy_reg(hw, MII_BMCR, atl1e_restart_autoneg()
H A Datl1e_ethtool.c33 struct atl1e_hw *hw = &adapter->hw; atl1e_get_settings() local
41 if (hw->nic_type == athr_l1e) atl1e_get_settings()
47 ecmd->advertising |= hw->autoneg_advertised; atl1e_get_settings()
72 struct atl1e_hw *hw = &adapter->hw; atl1e_set_settings() local
81 if (hw->nic_type == athr_l1e) { atl1e_set_settings()
82 hw->autoneg_advertised = atl1e_set_settings()
92 hw->autoneg_advertised = atl1e_set_settings()
95 ecmd->advertising = hw->autoneg_advertised | atl1e_set_settings()
98 adv4 = hw->mii_autoneg_adv_reg & ~ADVERTISE_ALL; atl1e_set_settings()
99 adv9 = hw->mii_1000t_ctrl_reg & ~MII_AT001_CR_1000T_SPEED_MASK; atl1e_set_settings()
100 if (hw->autoneg_advertised & ADVERTISE_10_HALF) atl1e_set_settings()
102 if (hw->autoneg_advertised & ADVERTISE_10_FULL) atl1e_set_settings()
104 if (hw->autoneg_advertised & ADVERTISE_100_HALF) atl1e_set_settings()
106 if (hw->autoneg_advertised & ADVERTISE_100_FULL) atl1e_set_settings()
108 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) atl1e_set_settings()
111 if (adv4 != hw->mii_autoneg_adv_reg || atl1e_set_settings()
112 adv9 != hw->mii_1000t_ctrl_reg) { atl1e_set_settings()
113 hw->mii_autoneg_adv_reg = adv4; atl1e_set_settings()
114 hw->mii_1000t_ctrl_reg = adv9; atl1e_set_settings()
115 hw->re_autoneg = true; atl1e_set_settings()
129 atl1e_reset_hw(&adapter->hw); atl1e_set_settings()
153 struct atl1e_hw *hw = &adapter->hw; atl1e_get_regs() local
159 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; atl1e_get_regs()
161 regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP); atl1e_get_regs()
162 regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); atl1e_get_regs()
163 regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG); atl1e_get_regs()
164 regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL); atl1e_get_regs()
165 regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); atl1e_get_regs()
166 regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL); atl1e_get_regs()
167 regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT); atl1e_get_regs()
168 regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); atl1e_get_regs()
169 regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL); atl1e_get_regs()
170 regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER); atl1e_get_regs()
171 regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS); atl1e_get_regs()
172 regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL); atl1e_get_regs()
173 regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK); atl1e_get_regs()
174 regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL); atl1e_get_regs()
175 regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG); atl1e_get_regs()
176 regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR); atl1e_get_regs()
177 regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4); atl1e_get_regs()
178 regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE); atl1e_get_regs()
179 regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4); atl1e_get_regs()
180 regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); atl1e_get_regs()
181 regs_buff[20] = AT_READ_REG(hw, REG_MTU); atl1e_get_regs()
182 regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL); atl1e_get_regs()
183 regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR); atl1e_get_regs()
184 regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN); atl1e_get_regs()
185 regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR); atl1e_get_regs()
186 regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN); atl1e_get_regs()
187 regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR); atl1e_get_regs()
188 regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN); atl1e_get_regs()
189 regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR); atl1e_get_regs()
190 regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR); atl1e_get_regs()
192 atl1e_read_phy_reg(hw, MII_BMCR, &phy_data); atl1e_get_regs()
194 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); atl1e_get_regs()
202 if (!atl1e_check_eeprom_exist(&adapter->hw)) atl1e_get_eeprom_len()
212 struct atl1e_hw *hw = &adapter->hw; atl1e_get_eeprom() local
221 if (atl1e_check_eeprom_exist(hw)) /* not exist */ atl1e_get_eeprom()
224 eeprom->magic = hw->vendor_id | (hw->device_id << 16); atl1e_get_eeprom()
235 if (!atl1e_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) { atl1e_get_eeprom()
252 struct atl1e_hw *hw = &adapter->hw; atl1e_set_eeprom() local
262 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) atl1e_set_eeprom()
276 if (!atl1e_read_eeprom(hw, first_dword * 4, &(eeprom_buff[0]))) { atl1e_set_eeprom()
286 if (!atl1e_read_eeprom(hw, last_dword * 4, atl1e_set_eeprom()
297 if (!atl1e_write_eeprom(hw, ((first_dword + i) * 4), atl1e_set_eeprom()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dhw.h45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw,
47 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw);
48 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw,
50 int rtl92se_hw_init(struct ieee80211_hw *hw);
51 void rtl92se_card_disable(struct ieee80211_hw *hw);
52 void rtl92se_enable_interrupt(struct ieee80211_hw *hw);
53 void rtl92se_disable_interrupt(struct ieee80211_hw *hw);
54 int rtl92se_set_network_type(struct ieee80211_hw *hw,
56 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
58 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci);
59 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw);
60 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw);
61 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
63 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable,
65 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
67 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw);
68 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw,
70 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw);
71 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw);
72 void rtl92se_set_key(struct ieee80211_hw *hw,
75 void rtl92se_suspend(struct ieee80211_hw *hw);
76 void rtl92se_resume(struct ieee80211_hw *hw);
H A DMakefile4 hw.o \
H A Dled.c35 static void _rtl92se_init_led(struct ieee80211_hw *hw, _rtl92se_init_led() argument
38 pled->hw = hw; _rtl92se_init_led()
43 void rtl92se_init_sw_leds(struct ieee80211_hw *hw) rtl92se_init_sw_leds() argument
45 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl92se_init_sw_leds()
46 _rtl92se_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0); rtl92se_init_sw_leds()
47 _rtl92se_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1); rtl92se_init_sw_leds()
50 void rtl92se_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92se_sw_led_on() argument
53 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92se_sw_led_on()
77 void rtl92se_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92se_sw_led_off() argument
80 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl92se_sw_led_off()
83 rtlpriv = rtl_priv(hw); rtl92se_sw_led_off()
113 static void _rtl92se_sw_led_control(struct ieee80211_hw *hw, _rtl92se_sw_led_control() argument
116 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92se_sw_led_control()
122 rtl92se_sw_led_on(hw, pLed0); _rtl92se_sw_led_control()
125 rtl92se_sw_led_off(hw, pLed0); _rtl92se_sw_led_control()
132 void rtl92se_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction) rtl92se_led_control() argument
134 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92se_led_control()
135 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92se_led_control()
149 _rtl92se_sw_led_control(hw, ledaction); rtl92se_led_control()
H A Dphy.h77 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
78 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
80 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
81 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
83 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
85 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
87 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw);
88 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
90 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw);
91 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw);
92 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw);
93 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw);
94 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
95 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel);
96 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fwcmd_io);
97 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw);
98 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval);
99 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) ;
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dphy.h39 #define RT_CANNOT_IO(hw) false
81 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
82 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
83 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
85 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
87 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
89 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
90 bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
91 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
92 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
94 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
95 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel);
96 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
97 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
99 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
101 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
102 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
103 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
104 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval);
105 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
106 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
107 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
108 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
109 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
111 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
113 bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
115 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
116 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
117 void rtl92c_phy_set_io(struct ieee80211_hw *hw);
118 void rtl92c_bb_block_on(struct ieee80211_hw *hw);
119 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath,
121 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
124 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
126 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
129 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
131 bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
132 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
133 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
134 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
135 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
137 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
139 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
141 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
H A DMakefile3 hw.o \
H A Dhw.h46 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
47 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw);
48 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
50 int rtl92ce_hw_init(struct ieee80211_hw *hw);
51 void rtl92ce_card_disable(struct ieee80211_hw *hw);
52 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw);
53 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw);
54 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
55 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
56 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci);
57 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw);
58 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw);
59 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
61 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
62 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
64 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
66 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw);
67 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
68 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw);
69 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
73 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
75 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw);
76 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw);
77 void rtl92ce_suspend(struct ieee80211_hw *hw);
78 void rtl92ce_resume(struct ieee80211_hw *hw);
H A Dphy.c36 #include "hw.h"
45 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
47 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, rtl92c_phy_query_rf_reg() argument
50 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_query_rf_reg()
61 original_value = _rtl92c_phy_rf_serial_read(hw, rtl92c_phy_query_rf_reg()
64 original_value = _rtl92c_phy_fw_rf_serial_read(hw, rtl92c_phy_query_rf_reg()
80 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw) rtl92c_phy_mac_config() argument
82 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_mac_config()
83 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_mac_config()
85 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw); rtl92c_phy_mac_config()
94 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw) rtl92c_phy_bb_config() argument
97 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_bb_config()
102 _rtl92c_phy_init_bb_rf_register_definition(hw); rtl92c_phy_bb_config()
116 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw); rtl92c_phy_bb_config()
120 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, rtl92ce_phy_set_rf_reg() argument
124 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ce_phy_set_rf_reg()
136 original_value = _rtl92c_phy_rf_serial_read(hw, rtl92ce_phy_set_rf_reg()
145 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data); rtl92ce_phy_set_rf_reg()
148 original_value = _rtl92c_phy_fw_rf_serial_read(hw, rtl92ce_phy_set_rf_reg()
156 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data); rtl92ce_phy_set_rf_reg()
166 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl92c_phy_config_mac_with_headerfile() argument
168 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_config_mac_with_headerfile()
182 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, _rtl92ce_phy_config_bb_with_headerfile() argument
189 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ce_phy_config_bb_with_headerfile()
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92ce_phy_config_bb_with_headerfile()
206 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl92ce_phy_config_bb_with_headerfile()
216 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, _rtl92ce_phy_config_bb_with_headerfile()
228 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, _rtl92ce_phy_config_bb_with_pgheaderfile() argument
231 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ce_phy_config_bb_with_pgheaderfile()
243 _rtl92c_store_pwrIndex_diffrate_offset(hw, _rtl92ce_phy_config_bb_with_pgheaderfile()
256 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl92c_phy_config_rf_with_headerfile() argument
264 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_config_rf_with_headerfile()
265 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_config_rf_with_headerfile()
290 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], rtl92c_phy_config_rf_with_headerfile()
297 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], rtl92c_phy_config_rf_with_headerfile()
316 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl92ce_phy_set_bw_mode_callback() argument
318 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ce_phy_set_bw_mode_callback()
319 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92ce_phy_set_bw_mode_callback()
321 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92ce_phy_set_bw_mode_callback()
357 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl92ce_phy_set_bw_mode_callback()
358 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl92ce_phy_set_bw_mode_callback()
359 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); rtl92ce_phy_set_bw_mode_callback()
362 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl92ce_phy_set_bw_mode_callback()
363 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl92ce_phy_set_bw_mode_callback()
365 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, rtl92ce_phy_set_bw_mode_callback()
367 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); rtl92ce_phy_set_bw_mode_callback()
368 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); rtl92ce_phy_set_bw_mode_callback()
370 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl92ce_phy_set_bw_mode_callback()
379 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl92ce_phy_set_bw_mode_callback()
384 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl92ce_phy_lc_calibrate() argument
388 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ce_phy_lc_calibrate()
398 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); _rtl92ce_phy_lc_calibrate()
401 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, _rtl92ce_phy_lc_calibrate()
404 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, _rtl92ce_phy_lc_calibrate()
408 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl92ce_phy_lc_calibrate()
411 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); _rtl92ce_phy_lc_calibrate()
413 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); _rtl92ce_phy_lc_calibrate()
419 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); _rtl92ce_phy_lc_calibrate()
422 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl92ce_phy_lc_calibrate()
429 static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw) _rtl92ce_phy_set_rf_sleep() argument
433 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ce_phy_set_rf_sleep()
436 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92ce_phy_set_rf_sleep()
438 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl92ce_phy_set_rf_sleep()
441 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92ce_phy_set_rf_sleep()
443 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl92ce_phy_set_rf_sleep()
459 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl92ce_phy_set_rf_power_state() argument
462 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92ce_phy_set_rf_power_state()
463 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92ce_phy_set_rf_power_state()
464 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl92ce_phy_set_rf_power_state()
465 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92ce_phy_set_rf_power_state()
480 rtstatus = rtl_ps_enable_nic(hw); _rtl92ce_phy_set_rf_power_state()
491 rtl92ce_phy_set_rf_on(hw); _rtl92ce_phy_set_rf_power_state()
494 rtlpriv->cfg->ops->led_control(hw, _rtl92ce_phy_set_rf_power_state()
497 rtlpriv->cfg->ops->led_control(hw, _rtl92ce_phy_set_rf_power_state()
506 rtl_ps_disable_nic(hw); _rtl92ce_phy_set_rf_power_state()
510 rtlpriv->cfg->ops->led_control(hw, _rtl92ce_phy_set_rf_power_state()
513 rtlpriv->cfg->ops->led_control(hw, _rtl92ce_phy_set_rf_power_state()
552 _rtl92ce_phy_set_rf_sleep(hw); _rtl92ce_phy_set_rf_power_state()
566 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl92c_phy_set_rf_power_state() argument
569 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92c_phy_set_rf_power_state()
575 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state); rtl92c_phy_set_rf_power_state()
H A Dled.c35 static void _rtl92ce_init_led(struct ieee80211_hw *hw, _rtl92ce_init_led() argument
38 pled->hw = hw; _rtl92ce_init_led()
43 void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92ce_sw_led_on() argument
46 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ce_sw_led_on()
71 void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92ce_sw_led_off() argument
73 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ce_sw_led_off()
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl92ce_sw_led_off()
106 void rtl92ce_init_sw_leds(struct ieee80211_hw *hw) rtl92ce_init_sw_leds() argument
108 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl92ce_init_sw_leds()
109 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0); rtl92ce_init_sw_leds()
110 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1); rtl92ce_init_sw_leds()
113 static void _rtl92ce_sw_led_control(struct ieee80211_hw *hw, _rtl92ce_sw_led_control() argument
116 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92ce_sw_led_control()
122 rtl92ce_sw_led_on(hw, pLed0); _rtl92ce_sw_led_control()
125 rtl92ce_sw_led_off(hw, pLed0); _rtl92ce_sw_led_control()
132 void rtl92ce_led_control(struct ieee80211_hw *hw, rtl92ce_led_control() argument
135 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ce_led_control()
136 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92ce_led_control()
150 _rtl92ce_sw_led_control(hw, ledaction); rtl92ce_led_control()
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dsky2.c161 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) gm_phy_write() argument
165 gma_write16(hw, port, GM_SMI_DATA, val); gm_phy_write()
166 gma_write16(hw, port, GM_SMI_CTRL, gm_phy_write()
170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); gm_phy_write()
180 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); gm_phy_write()
184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); gm_phy_write()
188 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) __gm_phy_read() argument
192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) __gm_phy_read()
196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); __gm_phy_read()
201 *val = gma_read16(hw, port, GM_SMI_DATA); __gm_phy_read()
208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); __gm_phy_read()
211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); __gm_phy_read()
215 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) gm_phy_read() argument
218 __gm_phy_read(hw, port, reg, &v); gm_phy_read()
223 static void sky2_power_on(struct sky2_hw *hw) sky2_power_on() argument
226 sky2_write8(hw, B0_POWER_CTRL, sky2_power_on()
230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); sky2_power_on()
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) sky2_power_on()
234 sky2_write8(hw, B2_Y2_CLK_GATE, sky2_power_on()
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0); sky2_power_on()
241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { sky2_power_on()
244 sky2_pci_write32(hw, PCI_DEV_REG3, 0); sky2_power_on()
246 reg = sky2_pci_read32(hw, PCI_DEV_REG4); sky2_power_on()
249 sky2_pci_write32(hw, PCI_DEV_REG4, reg); sky2_power_on()
251 reg = sky2_pci_read32(hw, PCI_DEV_REG5); sky2_power_on()
254 sky2_pci_write32(hw, PCI_DEV_REG5, reg); sky2_power_on()
256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); sky2_power_on()
258 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); sky2_power_on()
261 reg = sky2_read32(hw, B2_GP_IO); sky2_power_on()
263 sky2_write32(hw, B2_GP_IO, reg); sky2_power_on()
265 sky2_read32(hw, B2_GP_IO); sky2_power_on()
269 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); sky2_power_on()
272 static void sky2_power_aux(struct sky2_hw *hw) sky2_power_aux() argument
274 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) sky2_power_aux()
275 sky2_write8(hw, B2_Y2_CLK_GATE, 0); sky2_power_aux()
278 sky2_write8(hw, B2_Y2_CLK_GATE, sky2_power_aux()
284 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && sky2_power_aux()
285 pci_pme_capable(hw->pdev, PCI_D3cold)) sky2_power_aux()
286 sky2_write8(hw, B0_POWER_CTRL, sky2_power_aux()
291 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); sky2_power_aux()
294 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) sky2_gmac_reset() argument
299 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); sky2_gmac_reset()
301 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ sky2_gmac_reset()
302 gma_write16(hw, port, GM_MC_ADDR_H2, 0); sky2_gmac_reset()
303 gma_write16(hw, port, GM_MC_ADDR_H3, 0); sky2_gmac_reset()
304 gma_write16(hw, port, GM_MC_ADDR_H4, 0); sky2_gmac_reset()
306 reg = gma_read16(hw, port, GM_RX_CTRL); sky2_gmac_reset()
308 gma_write16(hw, port, GM_RX_CTRL, reg); sky2_gmac_reset()
336 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) sky2_phy_init() argument
338 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); sky2_phy_init()
342 !(hw->flags & SKY2_HW_NEWER_PHY)) { sky2_phy_init()
343 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); sky2_phy_init()
350 if (hw->chip_id == CHIP_ID_YUKON_EC) sky2_phy_init()
357 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); sky2_phy_init()
360 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); sky2_phy_init()
361 if (sky2_is_copper(hw)) { sky2_phy_init()
362 if (!(hw->flags & SKY2_HW_GIGABIT)) { sky2_phy_init()
366 if (hw->chip_id == CHIP_ID_YUKON_FE_P && sky2_phy_init()
367 hw->chip_rev == CHIP_REV_YU_FE2_A0) { sky2_phy_init()
371 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); sky2_phy_init()
373 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); sky2_phy_init()
384 (hw->flags & SKY2_HW_NEWER_PHY)) { sky2_phy_init()
397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); sky2_phy_init()
400 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { sky2_phy_init()
401 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); sky2_phy_init()
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); sky2_phy_init()
405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); sky2_phy_init()
408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); sky2_phy_init()
410 if (hw->pmd_type == 'P') { sky2_phy_init()
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); sky2_phy_init()
415 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); sky2_phy_init()
417 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); sky2_phy_init()
420 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); sky2_phy_init()
429 if (sky2_is_copper(hw)) { sky2_phy_init()
478 if (sky2_is_copper(hw)) sky2_phy_init()
488 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); sky2_phy_init()
490 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); sky2_phy_init()
493 gma_write16(hw, port, GM_GP_CTRL, reg); sky2_phy_init()
495 if (hw->flags & SKY2_HW_GIGABIT) sky2_phy_init()
496 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); sky2_phy_init()
498 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); sky2_phy_init()
499 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); sky2_phy_init()
505 switch (hw->chip_id) { sky2_phy_init()
510 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); sky2_phy_init()
516 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); sky2_phy_init()
521 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); sky2_phy_init()
526 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); sky2_phy_init()
533 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); sky2_phy_init()
537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); sky2_phy_init()
540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); sky2_phy_init()
543 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, sky2_phy_init()
550 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, sky2_phy_init()
559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); sky2_phy_init()
565 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); sky2_phy_init()
568 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); sky2_phy_init()
571 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, sky2_phy_init()
578 gm_phy_write(hw, port, PHY_MARV_INT_MASK, sky2_phy_init()
581 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); sky2_phy_init()
592 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { sky2_phy_init()
594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); sky2_phy_init()
597 gm_phy_write(hw, port, 0x18, 0xaa99); sky2_phy_init()
598 gm_phy_write(hw, port, 0x17, 0x2011); sky2_phy_init()
600 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { sky2_phy_init()
602 gm_phy_write(hw, port, 0x18, 0xa204); sky2_phy_init()
603 gm_phy_write(hw, port, 0x17, 0x2002); sky2_phy_init()
607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); sky2_phy_init()
608 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && sky2_phy_init()
609 hw->chip_rev == CHIP_REV_YU_FE2_A0) { sky2_phy_init()
611 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); sky2_phy_init()
612 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); sky2_phy_init()
613 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { sky2_phy_init()
615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); sky2_phy_init()
618 gm_phy_write(hw, port, 24, 0x2800); sky2_phy_init()
619 gm_phy_write(hw, port, 23, 0x2001); sky2_phy_init()
622 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); sky2_phy_init()
623 } else if (hw->chip_id != CHIP_ID_YUKON_EX && sky2_phy_init()
624 hw->chip_id < CHIP_ID_YUKON_SUPR) { sky2_phy_init()
626 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); sky2_phy_init()
635 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); sky2_phy_init()
637 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && sky2_phy_init()
638 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { sky2_phy_init()
665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); sky2_phy_init()
667 gm_phy_write(hw, port, 1, 0x4099); sky2_phy_init()
668 gm_phy_write(hw, port, 3, 0x1120); sky2_phy_init()
669 gm_phy_write(hw, port, 11, 0x113c); sky2_phy_init()
670 gm_phy_write(hw, port, 14, 0x8100); sky2_phy_init()
671 gm_phy_write(hw, port, 15, 0x112a); sky2_phy_init()
672 gm_phy_write(hw, port, 17, 0x1008); sky2_phy_init()
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); sky2_phy_init()
675 gm_phy_write(hw, port, 1, 0x20b0); sky2_phy_init()
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); sky2_phy_init()
681 gm_phy_write(hw, port, 17, eee_afe[i].val); sky2_phy_init()
682 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); sky2_phy_init()
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); sky2_phy_init()
689 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { sky2_phy_init()
690 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); sky2_phy_init()
691 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, sky2_phy_init()
698 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); sky2_phy_init()
700 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); sky2_phy_init()
706 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) sky2_phy_power_up() argument
710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_phy_power_up()
711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); sky2_phy_power_up()
714 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) sky2_phy_power_up()
717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_phy_power_up()
718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_phy_power_up()
719 sky2_pci_read32(hw, PCI_DEV_REG1); sky2_phy_power_up()
721 if (hw->chip_id == CHIP_ID_YUKON_FE) sky2_phy_power_up()
722 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); sky2_phy_power_up()
723 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) sky2_phy_power_up()
724 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); sky2_phy_power_up()
727 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) sky2_phy_power_down() argument
733 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); sky2_phy_power_down()
736 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); sky2_phy_power_down()
738 if (hw->flags & SKY2_HW_NEWER_PHY) { sky2_phy_power_down()
740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); sky2_phy_power_down()
742 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); sky2_phy_power_down()
745 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); sky2_phy_power_down()
748 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); sky2_phy_power_down()
752 gma_write16(hw, port, GM_GP_CTRL, sky2_phy_power_down()
757 if (hw->chip_id != CHIP_ID_YUKON_EC) { sky2_phy_power_down()
758 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { sky2_phy_power_down()
760 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); sky2_phy_power_down()
762 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); sky2_phy_power_down()
765 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); sky2_phy_power_down()
768 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); sky2_phy_power_down()
772 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); sky2_phy_power_down()
775 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_phy_power_down()
776 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); sky2_phy_power_down()
778 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_phy_power_down()
779 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_phy_power_down()
787 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); sky2_set_ipg()
793 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); sky2_set_ipg()
799 struct sky2_hw *hw = sky2->hw; sky2_enable_rx_tx() local
803 reg = gma_read16(hw, port, GM_GP_CTRL); sky2_enable_rx_tx()
805 gma_write16(hw, port, GM_GP_CTRL, reg); sky2_enable_rx_tx()
812 sky2_phy_init(sky2->hw, sky2->port); sky2_phy_reinit()
820 struct sky2_hw *hw = sky2->hw; sky2_wol_init() local
826 sky2_write16(hw, B0_CTST, CS_RST_CLR); sky2_wol_init()
827 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); sky2_wol_init()
829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); sky2_wol_init()
830 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); sky2_wol_init()
842 sky2_phy_power_up(hw, port); sky2_wol_init()
843 sky2_phy_init(hw, port); sky2_wol_init()
850 gma_write16(hw, port, GM_GP_CTRL, sky2_wol_init()
855 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), sky2_wol_init()
859 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); sky2_wol_init()
872 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); sky2_wol_init()
875 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); sky2_wol_init()
879 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); sky2_wol_init()
881 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); sky2_wol_init()
885 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); sky2_wol_init()
886 sky2_read32(hw, B0_CTST); sky2_wol_init()
889 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) sky2_set_tx_stfwd() argument
891 struct net_device *dev = hw->dev[port]; sky2_set_tx_stfwd()
893 if ( (hw->chip_id == CHIP_ID_YUKON_EX && sky2_set_tx_stfwd()
894 hw->chip_rev != CHIP_REV_YU_EX_A0) || sky2_set_tx_stfwd()
895 hw->chip_id >= CHIP_ID_YUKON_FE_P) { sky2_set_tx_stfwd()
897 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); sky2_set_tx_stfwd()
900 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), sky2_set_tx_stfwd()
903 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); sky2_set_tx_stfwd()
905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); sky2_set_tx_stfwd()
908 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) sky2_mac_init() argument
910 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); sky2_mac_init()
914 const u8 *addr = hw->dev[port]->dev_addr; sky2_mac_init()
916 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); sky2_mac_init()
917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); sky2_mac_init()
919 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); sky2_mac_init()
921 if (hw->chip_id == CHIP_ID_YUKON_XL && sky2_mac_init()
922 hw->chip_rev == CHIP_REV_YU_XL_A0 && sky2_mac_init()
926 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); sky2_mac_init()
928 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); sky2_mac_init()
929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); sky2_mac_init()
930 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || sky2_mac_init()
931 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || sky2_mac_init()
932 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); sky2_mac_init()
935 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); sky2_mac_init()
938 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); sky2_mac_init()
941 sky2_phy_power_up(hw, port); sky2_mac_init()
942 sky2_phy_init(hw, port); sky2_mac_init()
946 reg = gma_read16(hw, port, GM_PHY_ADDR); sky2_mac_init()
947 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); sky2_mac_init()
950 gma_read16(hw, port, i); sky2_mac_init()
951 gma_write16(hw, port, GM_PHY_ADDR, reg); sky2_mac_init()
954 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); sky2_mac_init()
957 gma_write16(hw, port, GM_RX_CTRL, sky2_mac_init()
961 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); sky2_mac_init()
964 gma_write16(hw, port, GM_TX_PARAM, sky2_mac_init()
974 if (hw->dev[port]->mtu > ETH_DATA_LEN) sky2_mac_init()
977 if (hw->chip_id == CHIP_ID_YUKON_EC_U && sky2_mac_init()
978 hw->chip_rev == CHIP_REV_YU_EC_U_B1) sky2_mac_init()
981 gma_write16(hw, port, GM_SERIAL_MODE, reg); sky2_mac_init()
984 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); sky2_mac_init()
987 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); sky2_mac_init()
990 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); sky2_mac_init()
991 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); sky2_mac_init()
992 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); sky2_mac_init()
995 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); sky2_mac_init()
997 if (hw->chip_id == CHIP_ID_YUKON_EX || sky2_mac_init()
998 hw->chip_id == CHIP_ID_YUKON_FE_P) sky2_mac_init()
1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); sky2_mac_init()
1003 if (hw->chip_id == CHIP_ID_YUKON_XL) { sky2_mac_init()
1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); sky2_mac_init()
1008 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); sky2_mac_init()
1014 if (hw->chip_id == CHIP_ID_YUKON_FE_P && sky2_mac_init()
1015 hw->chip_rev == CHIP_REV_YU_FE2_A0) sky2_mac_init()
1017 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); sky2_mac_init()
1020 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); sky2_mac_init()
1021 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); sky2_mac_init()
1024 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { sky2_mac_init()
1026 if (hw->chip_id == CHIP_ID_YUKON_FE_P && sky2_mac_init()
1027 hw->chip_rev == CHIP_REV_YU_FE2_A0) sky2_mac_init()
1031 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); sky2_mac_init()
1032 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); sky2_mac_init()
1034 sky2_set_tx_stfwd(hw, port); sky2_mac_init()
1037 if (hw->chip_id == CHIP_ID_YUKON_FE_P && sky2_mac_init()
1038 hw->chip_rev == CHIP_REV_YU_FE2_A0) { sky2_mac_init()
1040 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); sky2_mac_init()
1042 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); sky2_mac_init()
1047 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) sky2_ramset() argument
1051 /* convert from K bytes to qwords used for hw register */ sky2_ramset()
1056 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); sky2_ramset()
1057 sky2_write32(hw, RB_ADDR(q, RB_START), start); sky2_ramset()
1058 sky2_write32(hw, RB_ADDR(q, RB_END), end); sky2_ramset()
1059 sky2_write32(hw, RB_ADDR(q, RB_WP), start); sky2_ramset()
1060 sky2_write32(hw, RB_ADDR(q, RB_RP), start); sky2_ramset()
1069 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); sky2_ramset()
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); sky2_ramset()
1073 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); sky2_ramset()
1074 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); sky2_ramset()
1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); sky2_ramset()
1082 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); sky2_ramset()
1083 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); sky2_ramset()
1087 static void sky2_qset(struct sky2_hw *hw, u16 q) sky2_qset() argument
1089 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); sky2_qset()
1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); sky2_qset()
1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); sky2_qset()
1092 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); sky2_qset()
1098 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, sky2_prefetch_init() argument
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); sky2_prefetch_init()
1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); sky2_prefetch_init()
1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); sky2_prefetch_init()
1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); sky2_prefetch_init()
1105 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); sky2_prefetch_init()
1106 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); sky2_prefetch_init()
1108 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); sky2_prefetch_init()
1136 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) sky2_put_idx() argument
1140 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); sky2_put_idx()
1287 sky2_write32(sky2->hw, rx_set_checksum()
1297 struct sky2_hw *hw = sky2->hw; rx_set_rss() local
1301 if (hw->flags & SKY2_HW_NEW_LE) { rx_set_rss()
1303 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); rx_set_rss()
1312 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), rx_set_rss()
1316 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), rx_set_rss()
1319 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), rx_set_rss()
1322 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), rx_set_rss()
1338 struct sky2_hw *hw = sky2->hw; sky2_rx_stop() local
1343 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); sky2_rx_stop()
1346 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) sky2_rx_stop()
1347 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) sky2_rx_stop()
1352 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); sky2_rx_stop()
1355 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); sky2_rx_stop()
1371 sky2_rx_unmap_skb(sky2->hw->pdev, re); sky2_rx_clean()
1383 struct sky2_hw *hw = sky2->hw; sky2_ioctl() local
1398 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); sky2_ioctl()
1407 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, sky2_ioctl()
1420 struct sky2_hw *hw = sky2->hw; sky2_vlan_mode() local
1424 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), sky2_vlan_mode()
1427 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), sky2_vlan_mode()
1431 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), sky2_vlan_mode()
1436 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), sky2_vlan_mode()
1439 /* Can't do transmit offload of vlan without hw vlan */ sky2_vlan_mode()
1445 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) sky2_rx_pad() argument
1447 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; sky2_rx_pad()
1460 sky2->rx_data_size + sky2_rx_pad(sky2->hw), sky2_rx_alloc()
1465 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { sky2_rx_alloc()
1495 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); sky2_rx_update()
1500 struct sky2_hw *hw = sky2->hw; sky2_alloc_rx_skbs() local
1513 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { sky2_alloc_rx_skbs()
1533 struct sky2_hw *hw = sky2->hw; sky2_rx_start() local
1539 sky2_qset(hw, rxq); sky2_rx_start()
1542 if (pci_is_pcie(hw->pdev)) sky2_rx_start()
1543 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); sky2_rx_start()
1547 if (hw->chip_id == CHIP_ID_YUKON_EC_U && sky2_rx_start()
1548 hw->chip_rev > CHIP_REV_YU_EC_U_A0) sky2_rx_start()
1549 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); sky2_rx_start()
1551 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); sky2_rx_start()
1553 if (!(hw->flags & SKY2_HW_NEW_LE)) sky2_rx_start()
1556 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) sky2_rx_start()
1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); sky2_rx_start()
1575 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); sky2_rx_start()
1576 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); sky2_rx_start()
1582 if (hw->chip_id == CHIP_ID_YUKON_EX || sky2_rx_start()
1583 hw->chip_id == CHIP_ID_YUKON_SUPR) { sky2_rx_start()
1591 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); sky2_rx_start()
1594 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { sky2_rx_start()
1596 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), sky2_rx_start()
1600 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), sky2_rx_start()
1607 struct sky2_hw *hw = sky2->hw; sky2_alloc_buffers() local
1610 sky2->tx_le = pci_alloc_consistent(hw->pdev, sky2_alloc_buffers()
1622 sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES, sky2_alloc_buffers()
1639 struct sky2_hw *hw = sky2->hw; sky2_free_buffers() local
1644 pci_free_consistent(hw->pdev, RX_LE_BYTES, sky2_free_buffers()
1649 pci_free_consistent(hw->pdev, sky2_free_buffers()
1663 struct sky2_hw *hw = sky2->hw; sky2_hw_up() local
1667 struct net_device *otherdev = hw->dev[sky2->port^1]; sky2_hw_up()
1676 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { sky2_hw_up()
1679 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); sky2_hw_up()
1681 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); sky2_hw_up()
1684 sky2_mac_init(hw, port); sky2_hw_up()
1687 ramsize = sky2_read8(hw, B2_E_0) * 4; sky2_hw_up()
1697 sky2_ramset(hw, rxqaddr[port], 0, rxspace); sky2_hw_up()
1698 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); sky2_hw_up()
1701 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), sky2_hw_up()
1705 sky2_qset(hw, txqaddr[port]); sky2_hw_up()
1708 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) sky2_hw_up()
1709 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); sky2_hw_up()
1712 if (hw->chip_id == CHIP_ID_YUKON_EC_U && sky2_hw_up()
1713 hw->chip_rev == CHIP_REV_YU_EC_U_A0) sky2_hw_up()
1714 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); sky2_hw_up()
1716 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, sky2_hw_up()
1726 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) sky2_setup_irq() argument
1728 struct pci_dev *pdev = hw->pdev; sky2_setup_irq()
1732 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, sky2_setup_irq()
1733 name, hw); sky2_setup_irq()
1737 hw->flags |= SKY2_HW_IRQ_SETUP; sky2_setup_irq()
1739 napi_enable(&hw->napi); sky2_setup_irq()
1740 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); sky2_setup_irq()
1741 sky2_read32(hw, B0_IMSK); sky2_setup_irq()
1752 struct sky2_hw *hw = sky2->hw; sky2_open() local
1764 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) sky2_open()
1770 imask = sky2_read32(hw, B0_IMSK); sky2_open()
1772 if (hw->chip_id == CHIP_ID_YUKON_OPT || sky2_open()
1773 hw->chip_id == CHIP_ID_YUKON_PRM || sky2_open()
1774 hw->chip_id == CHIP_ID_YUKON_OP_2) sky2_open()
1778 sky2_write32(hw, B0_IMSK, imask); sky2_open()
1779 sky2_read32(hw, B0_IMSK); sky2_open()
1844 struct sky2_hw *hw = sky2->hw; sky2_xmit_frame() local
1858 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); sky2_xmit_frame()
1860 if (pci_dma_mapping_error(hw->pdev, mapping)) sky2_xmit_frame()
1880 if (!(hw->flags & SKY2_HW_NEW_LE)) sky2_xmit_frame()
1887 if (hw->flags & SKY2_HW_NEW_LE) sky2_xmit_frame()
1912 if (hw->flags & SKY2_HW_AUTO_TX_SUM) sky2_xmit_frame()
1952 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, sky2_xmit_frame()
1955 if (dma_mapping_error(&hw->pdev->dev, mapping)) sky2_xmit_frame()
1987 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); sky2_xmit_frame()
1995 sky2_tx_unmap(hw->pdev, re); sky2_xmit_frame()
2000 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); sky2_xmit_frame()
2028 sky2_tx_unmap(sky2->hw->pdev, re); sky2_tx_complete()
2055 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) sky2_tx_reset() argument
2058 sky2_write8(hw, SK_REG(port, TXA_CTRL), sky2_tx_reset()
2062 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); sky2_tx_reset()
2063 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); sky2_tx_reset()
2066 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), sky2_tx_reset()
2070 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), sky2_tx_reset()
2073 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); sky2_tx_reset()
2074 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); sky2_tx_reset()
2076 sky2_read32(hw, B0_CTST); sky2_tx_reset()
2081 struct sky2_hw *hw = sky2->hw; sky2_hw_down() local
2086 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); sky2_hw_down()
2089 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); sky2_hw_down()
2090 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); sky2_hw_down()
2092 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), sky2_hw_down()
2095 ctrl = gma_read16(hw, port, GM_GP_CTRL); sky2_hw_down()
2097 gma_write16(hw, port, GM_GP_CTRL, ctrl); sky2_hw_down()
2099 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); sky2_hw_down()
2102 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && sky2_hw_down()
2103 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) sky2_hw_down()
2104 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); sky2_hw_down()
2106 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); sky2_hw_down()
2109 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); sky2_hw_down()
2110 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); sky2_hw_down()
2111 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); sky2_hw_down()
2112 sky2_read8(hw, STAT_ISR_TIMER_CTRL); sky2_hw_down()
2117 sky2_phy_power_down(hw, port); sky2_hw_down()
2120 sky2_tx_reset(hw, port); sky2_hw_down()
2130 struct sky2_hw *hw = sky2->hw; sky2_close() local
2138 if (hw->ports == 1) { sky2_close()
2139 sky2_write32(hw, B0_IMSK, 0); sky2_close()
2140 sky2_read32(hw, B0_IMSK); sky2_close()
2142 napi_disable(&hw->napi); sky2_close()
2143 free_irq(hw->pdev->irq, hw); sky2_close()
2144 hw->flags &= ~SKY2_HW_IRQ_SETUP; sky2_close()
2149 imask = sky2_read32(hw, B0_IMSK); sky2_close()
2151 sky2_write32(hw, B0_IMSK, imask); sky2_close()
2152 sky2_read32(hw, B0_IMSK); sky2_close()
2154 synchronize_irq(hw->pdev->irq); sky2_close()
2155 napi_synchronize(&hw->napi); sky2_close()
2165 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) sky2_phy_speed() argument
2167 if (hw->flags & SKY2_HW_FIBRE_PHY) sky2_phy_speed()
2170 if (!(hw->flags & SKY2_HW_GIGABIT)) { sky2_phy_speed()
2189 struct sky2_hw *hw = sky2->hw; sky2_link_up() local
2202 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); sky2_link_up()
2206 mod_timer(&hw->watchdog_timer, jiffies + 1); sky2_link_up()
2209 sky2_write8(hw, SK_REG(port, LNK_LED_REG), sky2_link_up()
2221 struct sky2_hw *hw = sky2->hw; sky2_link_down() local
2225 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); sky2_link_down()
2227 reg = gma_read16(hw, port, GM_GP_CTRL); sky2_link_down()
2229 gma_write16(hw, port, GM_GP_CTRL, reg); sky2_link_down()
2234 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); sky2_link_down()
2238 sky2_phy_init(hw, port); sky2_link_down()
2251 struct sky2_hw *hw = sky2->hw; sky2_autoneg_done() local
2255 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); sky2_autoneg_done()
2256 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); sky2_autoneg_done()
2267 sky2->speed = sky2_phy_speed(hw, aux); sky2_autoneg_done()
2273 if (hw->flags & SKY2_HW_FIBRE_PHY) { sky2_autoneg_done()
2300 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) sky2_autoneg_done()
2304 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); sky2_autoneg_done()
2306 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); sky2_autoneg_done()
2312 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) sky2_phy_intr() argument
2314 struct net_device *dev = hw->dev[port]; sky2_phy_intr()
2322 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); sky2_phy_intr()
2323 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); sky2_phy_intr()
2336 sky2->speed = sky2_phy_speed(hw, phystat); sky2_phy_intr()
2353 static void sky2_qlink_intr(struct sky2_hw *hw) sky2_qlink_intr() argument
2355 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); sky2_qlink_intr()
2360 imask = sky2_read32(hw, B0_IMSK); sky2_qlink_intr()
2362 sky2_write32(hw, B0_IMSK, imask); sky2_qlink_intr()
2365 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); sky2_qlink_intr()
2366 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_qlink_intr()
2367 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); sky2_qlink_intr()
2368 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_qlink_intr()
2379 struct sky2_hw *hw = sky2->hw; sky2_tx_timeout() local
2385 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), sky2_tx_timeout()
2386 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); sky2_tx_timeout()
2389 schedule_work(&hw->restart_work); sky2_tx_timeout()
2395 struct sky2_hw *hw = sky2->hw; sky2_change_mtu() local
2407 (hw->chip_id == CHIP_ID_YUKON_FE || sky2_change_mtu()
2408 hw->chip_id == CHIP_ID_YUKON_FE_P)) sky2_change_mtu()
2417 imask = sky2_read32(hw, B0_IMSK); sky2_change_mtu()
2418 sky2_write32(hw, B0_IMSK, 0); sky2_change_mtu()
2419 sky2_read32(hw, B0_IMSK); sky2_change_mtu()
2422 napi_disable(&hw->napi); sky2_change_mtu()
2425 synchronize_irq(hw->pdev->irq); sky2_change_mtu()
2427 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) sky2_change_mtu()
2428 sky2_set_tx_stfwd(hw, port); sky2_change_mtu()
2430 ctl = gma_read16(hw, port, GM_GP_CTRL); sky2_change_mtu()
2431 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); sky2_change_mtu()
2447 gma_write16(hw, port, GM_SERIAL_MODE, mode); sky2_change_mtu()
2449 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); sky2_change_mtu()
2456 sky2_write32(hw, B0_IMSK, imask); sky2_change_mtu()
2458 sky2_read32(hw, B0_Y2_SP_LISR); sky2_change_mtu()
2459 napi_enable(&hw->napi); sky2_change_mtu()
2464 gma_write16(hw, port, GM_GP_CTRL, ctl); sky2_change_mtu()
2492 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, receive_copy()
2501 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, receive_copy()
2558 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) receive_new()
2562 sky2_rx_unmap_skb(sky2->hw->pdev, re); receive_new()
2604 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && sky2_receive()
2605 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && sky2_receive()
2662 napi_gro_receive(&sky2->hw->napi, skb); sky2_skb_rx()
2665 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, sky2_rx_done() argument
2668 struct net_device *dev = hw->dev[port]; sky2_rx_done()
2686 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); sky2_rx_checksum()
2698 dev_notice(&sky2->hw->pdev->dev, sky2_rx_checksum()
2707 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), sky2_rx_checksum()
2729 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) sky2_status_intr() argument
2741 struct sky2_status_le *le = hw->st_le + hw->st_idx; sky2_status_intr()
2752 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); sky2_status_intr()
2755 dev = hw->dev[port]; sky2_status_intr()
2771 if (hw->flags & SKY2_HW_NEW_LE) { sky2_status_intr()
2806 sky2_tx_done(hw->dev[0], status & 0xfff); sky2_status_intr()
2807 if (hw->dev[1]) sky2_status_intr()
2808 sky2_tx_done(hw->dev[1], sky2_status_intr()
2817 } while (hw->st_idx != idx); sky2_status_intr()
2820 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); sky2_status_intr()
2823 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); sky2_status_intr()
2824 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); sky2_status_intr()
2829 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) sky2_hw_error() argument
2831 struct net_device *dev = hw->dev[port]; sky2_hw_error()
2834 netdev_info(dev, "hw error interrupt status 0x%x\n", status); sky2_hw_error()
2840 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); sky2_hw_error()
2847 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); sky2_hw_error()
2853 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); sky2_hw_error()
2859 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); sky2_hw_error()
2865 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); sky2_hw_error()
2869 static void sky2_hw_intr(struct sky2_hw *hw) sky2_hw_intr() argument
2871 struct pci_dev *pdev = hw->pdev; sky2_hw_intr()
2872 u32 status = sky2_read32(hw, B0_HWE_ISRC); sky2_hw_intr()
2873 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); sky2_hw_intr()
2878 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); sky2_hw_intr()
2883 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_hw_intr()
2884 pci_err = sky2_pci_read16(hw, PCI_STATUS); sky2_hw_intr()
2889 sky2_pci_write16(hw, PCI_STATUS, sky2_hw_intr()
2891 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_hw_intr()
2898 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_hw_intr()
2899 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); sky2_hw_intr()
2900 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, sky2_hw_intr()
2905 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); sky2_hw_intr()
2906 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_hw_intr()
2910 sky2_hw_error(hw, 0, status); sky2_hw_intr()
2913 sky2_hw_error(hw, 1, status); sky2_hw_intr()
2916 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) sky2_mac_intr() argument
2918 struct net_device *dev = hw->dev[port]; sky2_mac_intr()
2920 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); sky2_mac_intr()
2925 gma_read16(hw, port, GM_RX_IRQ_SRC); sky2_mac_intr()
2928 gma_read16(hw, port, GM_TX_IRQ_SRC); sky2_mac_intr()
2932 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); sky2_mac_intr()
2937 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); sky2_mac_intr()
2942 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) sky2_le_error() argument
2944 struct net_device *dev = hw->dev[port]; sky2_le_error()
2945 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); sky2_le_error()
2947 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", sky2_le_error()
2949 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); sky2_le_error()
2951 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); sky2_le_error()
2957 struct sky2_hw *hw = sky2->hw; sky2_rx_hung() local
2960 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); sky2_rx_hung()
2961 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); sky2_rx_hung()
2962 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); sky2_rx_hung()
2963 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); sky2_rx_hung()
2975 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); sky2_rx_hung()
2989 struct sky2_hw *hw = (struct sky2_hw *) arg; sky2_watchdog() local
2992 if (sky2_read32(hw, B0_ISRC)) { sky2_watchdog()
2993 napi_schedule(&hw->napi); sky2_watchdog()
2997 for (i = 0; i < hw->ports; i++) { sky2_watchdog()
2998 struct net_device *dev = hw->dev[i]; sky2_watchdog()
3004 if ((hw->flags & SKY2_HW_RAM_BUFFER) && sky2_watchdog()
3007 schedule_work(&hw->restart_work); sky2_watchdog()
3016 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); sky2_watchdog()
3020 static void sky2_err_intr(struct sky2_hw *hw, u32 status) sky2_err_intr() argument
3023 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); sky2_err_intr()
3026 sky2_hw_intr(hw); sky2_err_intr()
3029 sky2_mac_intr(hw, 0); sky2_err_intr()
3032 sky2_mac_intr(hw, 1); sky2_err_intr()
3035 sky2_le_error(hw, 0, Q_R1); sky2_err_intr()
3038 sky2_le_error(hw, 1, Q_R2); sky2_err_intr()
3041 sky2_le_error(hw, 0, Q_XA1); sky2_err_intr()
3044 sky2_le_error(hw, 1, Q_XA2); sky2_err_intr()
3049 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); sky2_poll() local
3050 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); sky2_poll()
3055 sky2_err_intr(hw, status); sky2_poll()
3058 sky2_phy_intr(hw, 0); sky2_poll()
3061 sky2_phy_intr(hw, 1); sky2_poll()
3064 sky2_qlink_intr(hw); sky2_poll()
3066 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { sky2_poll()
3067 work_done += sky2_status_intr(hw, work_limit - work_done, idx); sky2_poll()
3074 sky2_read32(hw, B0_Y2_SP_LISR); sky2_poll()
3082 struct sky2_hw *hw = dev_id; sky2_intr() local
3086 status = sky2_read32(hw, B0_Y2_SP_ISRC2); sky2_intr()
3088 sky2_write32(hw, B0_Y2_SP_ICR, 2); sky2_intr()
3092 prefetch(&hw->st_le[hw->st_idx]); sky2_intr()
3094 napi_schedule(&hw->napi); sky2_intr()
3104 napi_schedule(&sky2->hw->napi); sky2_netpoll()
3109 static u32 sky2_mhz(const struct sky2_hw *hw) sky2_mhz() argument
3111 switch (hw->chip_id) { sky2_mhz()
3136 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) sky2_us2clk() argument
3138 return sky2_mhz(hw) * us; sky2_us2clk()
3141 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) sky2_clk2us() argument
3143 return clk / sky2_mhz(hw); sky2_clk2us()
3147 static int sky2_init(struct sky2_hw *hw) sky2_init() argument
3152 sky2_pci_write32(hw, PCI_DEV_REG3, 0); sky2_init()
3154 sky2_write8(hw, B0_CTST, CS_RST_CLR); sky2_init()
3156 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); sky2_init()
3157 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; sky2_init()
3159 switch (hw->chip_id) { sky2_init()
3161 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; sky2_init()
3162 if (hw->chip_rev < CHIP_REV_YU_XL_A2) sky2_init()
3163 hw->flags |= SKY2_HW_RSS_BROKEN; sky2_init()
3167 hw->flags = SKY2_HW_GIGABIT sky2_init()
3173 hw->flags = SKY2_HW_GIGABIT sky2_init()
3180 if (hw->chip_rev != CHIP_REV_YU_EX_B0) sky2_init()
3181 hw->flags |= SKY2_HW_AUTO_TX_SUM; sky2_init()
3186 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { sky2_init()
3187 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); sky2_init()
3190 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; sky2_init()
3194 hw->flags = SKY2_HW_RSS_BROKEN; sky2_init()
3198 hw->flags = SKY2_HW_NEWER_PHY sky2_init()
3204 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) sky2_init()
3205 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; sky2_init()
3209 hw->flags = SKY2_HW_GIGABIT sky2_init()
3215 if (hw->chip_rev == CHIP_REV_YU_SU_A0) sky2_init()
3216 hw->flags |= SKY2_HW_RSS_CHKSUM; sky2_init()
3220 hw->flags = SKY2_HW_GIGABIT sky2_init()
3227 hw->flags = SKY2_HW_GIGABIT sky2_init()
3233 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", sky2_init()
3234 hw->chip_id); sky2_init()
3238 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); sky2_init()
3239 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') sky2_init()
3240 hw->flags |= SKY2_HW_FIBRE_PHY; sky2_init()
3242 hw->ports = 1; sky2_init()
3243 t8 = sky2_read8(hw, B2_Y2_HW_RES); sky2_init()
3245 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) sky2_init()
3246 ++hw->ports; sky2_init()
3249 if (sky2_read8(hw, B2_E_0)) sky2_init()
3250 hw->flags |= SKY2_HW_RAM_BUFFER; sky2_init()
3255 static void sky2_reset(struct sky2_hw *hw) sky2_reset() argument
3257 struct pci_dev *pdev = hw->pdev; sky2_reset()
3263 if (hw->chip_id == CHIP_ID_YUKON_EX sky2_reset()
3264 || hw->chip_id == CHIP_ID_YUKON_SUPR) { sky2_reset()
3265 sky2_write32(hw, CPU_WDOG, 0); sky2_reset()
3266 status = sky2_read16(hw, HCU_CCSR); sky2_reset()
3275 sky2_write16(hw, HCU_CCSR, status); sky2_reset()
3276 sky2_write32(hw, CPU_WDOG, 0); sky2_reset()
3278 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); sky2_reset()
3279 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); sky2_reset()
3282 sky2_write8(hw, B0_CTST, CS_RST_SET); sky2_reset()
3283 sky2_write8(hw, B0_CTST, CS_RST_CLR); sky2_reset()
3286 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_reset()
3289 status = sky2_pci_read16(hw, PCI_STATUS); sky2_reset()
3291 sky2_pci_write16(hw, PCI_STATUS, status); sky2_reset()
3293 sky2_write8(hw, B0_CTST, CS_MRST_CLR); sky2_reset()
3296 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, sky2_reset()
3300 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) sky2_reset()
3306 sky2_power_on(hw); sky2_reset()
3307 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_reset()
3309 for (i = 0; i < hw->ports; i++) { sky2_reset()
3310 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); sky2_reset()
3311 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); sky2_reset()
3313 if (hw->chip_id == CHIP_ID_YUKON_EX || sky2_reset()
3314 hw->chip_id == CHIP_ID_YUKON_SUPR) sky2_reset()
3315 sky2_write16(hw, SK_REG(i, GMAC_CTRL), sky2_reset()
3321 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { sky2_reset()
3323 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); sky2_reset()
3326 if (hw->chip_id == CHIP_ID_YUKON_OPT || sky2_reset()
3327 hw->chip_id == CHIP_ID_YUKON_PRM || sky2_reset()
3328 hw->chip_id == CHIP_ID_YUKON_OP_2) { sky2_reset()
3331 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { sky2_reset()
3333 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); sky2_reset()
3339 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); sky2_reset()
3349 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); sky2_reset()
3350 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); sky2_reset()
3353 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); sky2_reset()
3356 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, sky2_reset()
3359 if (hw->chip_id == CHIP_ID_YUKON_PRM && sky2_reset()
3360 hw->chip_rev == CHIP_REV_YU_PRM_A0) { sky2_reset()
3362 reg = sky2_read16(hw, GPHY_CTRL); sky2_reset()
3363 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); sky2_reset()
3366 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); sky2_reset()
3367 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); sky2_reset()
3370 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); sky2_reset()
3373 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); sky2_reset()
3377 sky2_write32(hw, B2_I2C_IRQ, 1); sky2_reset()
3380 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); sky2_reset()
3381 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); sky2_reset()
3384 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); sky2_reset()
3387 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); sky2_reset()
3388 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); sky2_reset()
3391 for (i = 0; i < hw->ports; i++) sky2_reset()
3392 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); sky2_reset()
3395 for (i = 0; i < hw->ports; i++) { sky2_reset()
3396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); sky2_reset()
3398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); sky2_reset()
3399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); sky2_reset()
3400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); sky2_reset()
3401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); sky2_reset()
3402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); sky2_reset()
3403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); sky2_reset()
3404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); sky2_reset()
3405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); sky2_reset()
3406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); sky2_reset()
3407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); sky2_reset()
3408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); sky2_reset()
3409 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); sky2_reset()
3412 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); sky2_reset()
3414 for (i = 0; i < hw->ports; i++) sky2_reset()
3415 sky2_gmac_reset(hw, i); sky2_reset()
3417 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); sky2_reset()
3418 hw->st_idx = 0; sky2_reset()
3420 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); sky2_reset()
3421 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); sky2_reset()
3423 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); sky2_reset()
3424 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); sky2_reset()
3427 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); sky2_reset()
3429 sky2_write16(hw, STAT_TX_IDX_TH, 10); sky2_reset()
3430 sky2_write8(hw, STAT_FIFO_WM, 16); sky2_reset()
3433 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) sky2_reset()
3434 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); sky2_reset()
3436 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); sky2_reset()
3438 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); sky2_reset()
3439 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); sky2_reset()
3440 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); sky2_reset()
3443 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); sky2_reset()
3445 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); sky2_reset()
3446 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); sky2_reset()
3447 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); sky2_reset()
3483 static void sky2_all_down(struct sky2_hw *hw) sky2_all_down() argument
3487 if (hw->flags & SKY2_HW_IRQ_SETUP) { sky2_all_down()
3488 sky2_write32(hw, B0_IMSK, 0); sky2_all_down()
3489 sky2_read32(hw, B0_IMSK); sky2_all_down()
3491 synchronize_irq(hw->pdev->irq); sky2_all_down()
3492 napi_disable(&hw->napi); sky2_all_down()
3495 for (i = 0; i < hw->ports; i++) { sky2_all_down()
3496 struct net_device *dev = hw->dev[i]; sky2_all_down()
3508 static void sky2_all_up(struct sky2_hw *hw) sky2_all_up() argument
3513 for (i = 0; i < hw->ports; i++) { sky2_all_up()
3514 struct net_device *dev = hw->dev[i]; sky2_all_up()
3526 if (hw->flags & SKY2_HW_IRQ_SETUP) { sky2_all_up()
3527 sky2_write32(hw, B0_IMSK, imask); sky2_all_up()
3528 sky2_read32(hw, B0_IMSK); sky2_all_up()
3529 sky2_read32(hw, B0_Y2_SP_LISR); sky2_all_up()
3530 napi_enable(&hw->napi); sky2_all_up()
3536 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); sky2_restart() local
3540 sky2_all_down(hw); sky2_restart()
3541 sky2_reset(hw); sky2_restart()
3542 sky2_all_up(hw); sky2_restart()
3547 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) sky2_wol_supported() argument
3549 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; sky2_wol_supported()
3556 wol->supported = sky2_wol_supported(sky2->hw); sky2_get_wol()
3563 struct sky2_hw *hw = sky2->hw; sky2_set_wol() local
3567 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || sky2_set_wol()
3568 !device_can_wakeup(&hw->pdev->dev)) sky2_set_wol()
3573 for (i = 0; i < hw->ports; i++) { sky2_set_wol()
3574 struct net_device *dev = hw->dev[i]; sky2_set_wol()
3580 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); sky2_set_wol()
3585 static u32 sky2_supported_modes(const struct sky2_hw *hw) sky2_supported_modes() argument
3587 if (sky2_is_copper(hw)) { sky2_supported_modes()
3593 if (hw->flags & SKY2_HW_GIGABIT) sky2_supported_modes()
3605 struct sky2_hw *hw = sky2->hw; sky2_get_settings() local
3608 ecmd->supported = sky2_supported_modes(hw); sky2_get_settings()
3610 if (sky2_is_copper(hw)) { sky2_get_settings()
3630 const struct sky2_hw *hw = sky2->hw; sky2_set_settings() local
3631 u32 supported = sky2_supported_modes(hw); sky2_set_settings()
3637 if (sky2_is_copper(hw)) sky2_set_settings()
3706 strlcpy(info->bus_info, pci_name(sky2->hw->pdev), sky2_get_drvinfo()
3775 struct sky2_hw *hw = sky2->hw; sky2_phy_stats() local
3779 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); sky2_phy_stats()
3780 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); sky2_phy_stats()
3783 data[i] = get_stats32(hw, port, sky2_stats[i].offset); sky2_phy_stats()
3826 struct sky2_hw *hw = sky2->hw; sky2_set_mac_address() local
3834 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, sky2_set_mac_address()
3836 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, sky2_set_mac_address()
3840 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); sky2_set_mac_address()
3843 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); sky2_set_mac_address()
3859 struct sky2_hw *hw = sky2->hw; sky2_set_multicast() local
3870 reg = gma_read16(hw, port, GM_RX_CTRL); sky2_set_multicast()
3889 gma_write16(hw, port, GM_MC_ADDR_H1, sky2_set_multicast()
3891 gma_write16(hw, port, GM_MC_ADDR_H2, sky2_set_multicast()
3893 gma_write16(hw, port, GM_MC_ADDR_H3, sky2_set_multicast()
3895 gma_write16(hw, port, GM_MC_ADDR_H4, sky2_set_multicast()
3898 gma_write16(hw, port, GM_RX_CTRL, reg); sky2_set_multicast()
3905 struct sky2_hw *hw = sky2->hw; sky2_get_stats() local
3928 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) sky2_get_stats()
3929 + get_stats32(hw, port, GM_RXF_BC_OK); sky2_get_stats()
3931 stats->collisions = get_stats32(hw, port, GM_TXF_COL); sky2_get_stats()
3933 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); sky2_get_stats()
3934 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); sky2_get_stats()
3935 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) sky2_get_stats()
3936 + get_stats32(hw, port, GM_RXE_FRAG); sky2_get_stats()
3937 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); sky2_get_stats()
3951 struct sky2_hw *hw = sky2->hw; sky2_led() local
3955 if (hw->chip_id == CHIP_ID_YUKON_EC_U || sky2_led()
3956 hw->chip_id == CHIP_ID_YUKON_EX || sky2_led()
3957 hw->chip_id == CHIP_ID_YUKON_SUPR) { sky2_led()
3959 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); sky2_led()
3960 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); sky2_led()
3964 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, sky2_led()
3971 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, sky2_led()
3978 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, sky2_led()
3985 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, sky2_led()
3992 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); sky2_led()
3994 gm_phy_write(hw, port, PHY_MARV_LED_OVER, sky2_led()
4073 struct sky2_hw *hw = sky2->hw; sky2_get_coalesce() local
4075 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) sky2_get_coalesce()
4078 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); sky2_get_coalesce()
4079 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); sky2_get_coalesce()
4081 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); sky2_get_coalesce()
4083 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) sky2_get_coalesce()
4086 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); sky2_get_coalesce()
4087 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); sky2_get_coalesce()
4089 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); sky2_get_coalesce()
4091 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) sky2_get_coalesce()
4094 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); sky2_get_coalesce()
4095 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); sky2_get_coalesce()
4098 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); sky2_get_coalesce()
4108 struct sky2_hw *hw = sky2->hw; sky2_set_coalesce() local
4109 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); sky2_set_coalesce()
4124 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); sky2_set_coalesce()
4126 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_set_coalesce()
4127 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); sky2_set_coalesce()
4128 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); sky2_set_coalesce()
4130 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); sky2_set_coalesce()
4133 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); sky2_set_coalesce()
4135 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_set_coalesce()
4136 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); sky2_set_coalesce()
4137 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); sky2_set_coalesce()
4139 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); sky2_set_coalesce()
4142 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); sky2_set_coalesce()
4144 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_set_coalesce()
4145 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); sky2_set_coalesce()
4146 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); sky2_set_coalesce()
4148 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); sky2_set_coalesce()
4199 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) sky2_reg_access_ok() argument
4218 return hw->ports > 1; sky2_reg_access_ok()
4251 const void __iomem *io = sky2->hw->regs; sky2_get_regs()
4260 else if (sky2_reg_access_ok(sky2->hw, b)) sky2_get_regs()
4273 struct sky2_hw *hw = sky2->hw; sky2_get_eeprom_len() local
4276 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); sky2_get_eeprom_len()
4280 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) sky2_vpd_wait() argument
4284 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { sky2_vpd_wait()
4287 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); sky2_vpd_wait()
4296 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, sky2_vpd_read() argument
4304 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); sky2_vpd_read()
4305 rc = sky2_vpd_wait(hw, cap, 0); sky2_vpd_read()
4309 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); sky2_vpd_read()
4320 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, sky2_vpd_write() argument
4329 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); sky2_vpd_write()
4330 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); sky2_vpd_write()
4332 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); sky2_vpd_write()
4343 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); sky2_get_eeprom()
4350 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); sky2_get_eeprom()
4357 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); sky2_set_eeprom()
4369 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); sky2_set_eeprom()
4376 const struct sky2_hw *hw = sky2->hw; sky2_fix_features() local
4381 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { sky2_fix_features()
4389 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { sky2_fix_features()
4403 !(sky2->hw->flags & SKY2_HW_NEW_LE)) { sky2_set_features()
4404 sky2_write32(sky2->hw, sky2_set_features()
4472 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) sky2_show_vpd() argument
4480 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); sky2_show_vpd()
4483 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); sky2_show_vpd()
4490 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { sky2_show_vpd()
4534 struct sky2_hw *hw = sky2->hw; sky2_debug_show() local
4539 sky2_show_vpd(seq, hw); sky2_debug_show()
4542 sky2_read32(hw, B0_ISRC), sky2_debug_show()
4543 sky2_read32(hw, B0_IMSK), sky2_debug_show()
4544 sky2_read32(hw, B0_Y2_SP_ICR)); sky2_debug_show()
4551 napi_disable(&hw->napi); sky2_debug_show()
4552 last = sky2_read16(hw, STAT_PUT_IDX); sky2_debug_show()
4554 seq_printf(seq, "Status ring %u\n", hw->st_size); sky2_debug_show()
4555 if (hw->st_idx == last) sky2_debug_show()
4559 for (idx = hw->st_idx; idx != last && idx < hw->st_size; sky2_debug_show()
4560 idx = RING_NEXT(idx, hw->st_size)) { sky2_debug_show()
4561 const struct sky2_status_le *le = hw->st_le + idx; sky2_debug_show()
4570 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), sky2_debug_show()
4571 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); sky2_debug_show()
4617 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", sky2_debug_show()
4618 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), sky2_debug_show()
4619 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), sky2_debug_show()
4620 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); sky2_debug_show()
4622 sky2_read32(hw, B0_Y2_SP_LISR); sky2_debug_show()
4623 napi_enable(&hw->napi); sky2_debug_show()
4748 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, sky2_init_netdev() argument
4758 SET_NETDEV_DEV(dev, &hw->pdev->dev); sky2_init_netdev()
4759 dev->irq = hw->pdev->irq; sky2_init_netdev()
4766 sky2->hw = hw; sky2_init_netdev()
4774 if (hw->chip_id != CHIP_ID_YUKON_XL) sky2_init_netdev()
4781 sky2->advertising = sky2_supported_modes(hw); sky2_init_netdev()
4790 hw->dev[port] = dev; sky2_init_netdev()
4800 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) sky2_init_netdev()
4803 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { sky2_init_netdev()
4815 iap = of_get_mac_address(hw->pdev->dev.of_node); sky2_init_netdev()
4819 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, sky2_init_netdev()
4847 struct sky2_hw *hw = dev_id; sky2_test_intr() local
4848 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); sky2_test_intr()
4854 hw->flags |= SKY2_HW_USE_MSI; sky2_test_intr()
4855 wake_up(&hw->msi_wait); sky2_test_intr()
4856 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); sky2_test_intr()
4858 sky2_write32(hw, B0_Y2_SP_ICR, 2); sky2_test_intr()
4864 static int sky2_test_msi(struct sky2_hw *hw) sky2_test_msi() argument
4866 struct pci_dev *pdev = hw->pdev; sky2_test_msi()
4869 init_waitqueue_head(&hw->msi_wait); sky2_test_msi()
4871 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); sky2_test_msi()
4877 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); sky2_test_msi()
4879 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); sky2_test_msi()
4880 sky2_read8(hw, B0_CTST); sky2_test_msi()
4882 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); sky2_test_msi()
4884 if (!(hw->flags & SKY2_HW_USE_MSI)) { sky2_test_msi()
4890 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); sky2_test_msi()
4893 sky2_write32(hw, B0_IMSK, 0); sky2_test_msi()
4894 sky2_read32(hw, B0_IMSK); sky2_test_msi()
4896 free_irq(pdev->irq, hw); sky2_test_msi()
4929 struct sky2_hw *hw; sky2_probe() local
4999 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") sky2_probe()
5001 if (!hw) sky2_probe()
5004 hw->pdev = pdev; sky2_probe()
5005 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); sky2_probe()
5007 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); sky2_probe()
5008 if (!hw->regs) { sky2_probe()
5013 err = sky2_init(hw); sky2_probe()
5018 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); sky2_probe()
5019 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), sky2_probe()
5020 &hw->st_dma); sky2_probe()
5021 if (!hw->st_le) { sky2_probe()
5027 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); sky2_probe()
5029 sky2_reset(hw); sky2_probe()
5031 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); sky2_probe()
5038 err = sky2_test_msi(hw); sky2_probe()
5046 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); sky2_probe()
5058 if (hw->ports > 1) { sky2_probe()
5059 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); sky2_probe()
5071 err = sky2_setup_irq(hw, hw->irq_name); sky2_probe()
5078 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); sky2_probe()
5079 INIT_WORK(&hw->restart_work, sky2_restart); sky2_probe()
5081 pci_set_drvdata(pdev, hw); sky2_probe()
5093 if (hw->flags & SKY2_HW_USE_MSI) sky2_probe()
5097 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), sky2_probe()
5098 hw->st_le, hw->st_dma); sky2_probe()
5100 sky2_write8(hw, B0_CTST, CS_RST_SET); sky2_probe()
5102 iounmap(hw->regs); sky2_probe()
5104 kfree(hw); sky2_probe()
5115 struct sky2_hw *hw = pci_get_drvdata(pdev); sky2_remove() local
5118 if (!hw) sky2_remove()
5121 del_timer_sync(&hw->watchdog_timer); sky2_remove()
5122 cancel_work_sync(&hw->restart_work); sky2_remove()
5124 for (i = hw->ports-1; i >= 0; --i) sky2_remove()
5125 unregister_netdev(hw->dev[i]); sky2_remove()
5127 sky2_write32(hw, B0_IMSK, 0); sky2_remove()
5128 sky2_read32(hw, B0_IMSK); sky2_remove()
5130 sky2_power_aux(hw); sky2_remove()
5132 sky2_write8(hw, B0_CTST, CS_RST_SET); sky2_remove()
5133 sky2_read8(hw, B0_CTST); sky2_remove()
5135 if (hw->ports > 1) { sky2_remove()
5136 napi_disable(&hw->napi); sky2_remove()
5137 free_irq(pdev->irq, hw); sky2_remove()
5140 if (hw->flags & SKY2_HW_USE_MSI) sky2_remove()
5142 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), sky2_remove()
5143 hw->st_le, hw->st_dma); sky2_remove()
5147 for (i = hw->ports-1; i >= 0; --i) sky2_remove()
5148 free_netdev(hw->dev[i]); sky2_remove()
5150 iounmap(hw->regs); sky2_remove()
5151 kfree(hw); sky2_remove()
5157 struct sky2_hw *hw = pci_get_drvdata(pdev); sky2_suspend() local
5160 if (!hw) sky2_suspend()
5163 del_timer_sync(&hw->watchdog_timer); sky2_suspend()
5164 cancel_work_sync(&hw->restart_work); sky2_suspend()
5168 sky2_all_down(hw); sky2_suspend()
5169 for (i = 0; i < hw->ports; i++) { sky2_suspend()
5170 struct net_device *dev = hw->dev[i]; sky2_suspend()
5177 sky2_power_aux(hw); sky2_suspend()
5187 struct sky2_hw *hw = pci_get_drvdata(pdev); sky2_resume() local
5190 if (!hw) sky2_resume()
5201 sky2_reset(hw); sky2_resume()
5202 sky2_all_up(hw); sky2_resume()
H A Dskge.c108 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
112 static void yukon_init(struct skge_hw *hw, int port);
113 static void genesis_mac_init(struct skge_hw *hw, int port);
126 static inline bool is_genesis(const struct skge_hw *hw) is_genesis() argument
129 return hw->chip_id == CHIP_ID_GENESIS; is_genesis()
149 const void __iomem *io = skge->hw->regs; skge_get_regs()
160 static u32 wol_supported(const struct skge_hw *hw) wol_supported() argument
162 if (is_genesis(hw)) wol_supported()
165 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) wol_supported()
173 struct skge_hw *hw = skge->hw; skge_wol_init() local
177 skge_write16(hw, B0_CTST, CS_RST_CLR); skge_wol_init()
178 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); skge_wol_init()
181 skge_write8(hw, B0_POWER_CTRL, skge_wol_init()
185 if (hw->chip_id == CHIP_ID_YUKON_LITE && skge_wol_init()
186 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { skge_wol_init()
187 u32 reg = skge_read32(hw, B2_GP_IO); skge_wol_init()
190 skge_write32(hw, B2_GP_IO, reg); skge_wol_init()
193 skge_write32(hw, SK_REG(port, GPHY_CTRL), skge_wol_init()
198 skge_write32(hw, SK_REG(port, GPHY_CTRL), skge_wol_init()
203 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); skge_wol_init()
206 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, skge_wol_init()
210 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); skge_wol_init()
211 gm_phy_write(hw, port, PHY_MARV_CTRL, skge_wol_init()
217 gma_write16(hw, port, GM_GP_CTRL, skge_wol_init()
222 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), skge_wol_init()
226 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); skge_wol_init()
239 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); skge_wol_init()
242 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); skge_wol_init()
249 wol->supported = wol_supported(skge->hw); skge_get_wol()
256 struct skge_hw *hw = skge->hw; skge_set_wol() local
258 if ((wol->wolopts & ~wol_supported(hw)) || skge_set_wol()
259 !device_can_wakeup(&hw->pdev->dev)) skge_set_wol()
264 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); skge_set_wol()
272 static u32 skge_supported_modes(const struct skge_hw *hw) skge_supported_modes() argument
276 if (hw->copper) { skge_supported_modes()
286 if (is_genesis(hw)) skge_supported_modes()
292 else if (hw->chip_id == CHIP_ID_YUKON) skge_supported_modes()
307 struct skge_hw *hw = skge->hw; skge_get_settings() local
310 ecmd->supported = skge_supported_modes(hw); skge_get_settings()
312 if (hw->copper) { skge_get_settings()
314 ecmd->phy_address = hw->phy_addr; skge_get_settings()
328 const struct skge_hw *hw = skge->hw; skge_set_settings() local
329 u32 supported = skge_supported_modes(hw); skge_set_settings()
399 strlcpy(info->bus_info, pci_name(skge->hw->pdev), skge_get_drvinfo()
449 if (is_genesis(skge->hw)) skge_get_ethtool_stats()
464 if (is_genesis(skge->hw)) skge_get_stats()
599 static inline u32 hwkhz(const struct skge_hw *hw) hwkhz() argument
601 return is_genesis(hw) ? 53125 : 78125; hwkhz()
605 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) skge_clk2usec() argument
607 return (ticks * 1000) / hwkhz(hw); skge_clk2usec()
611 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) skge_usecs2clk() argument
613 return hwkhz(hw) * usec / 1000; skge_usecs2clk()
620 struct skge_hw *hw = skge->hw; skge_get_coalesce() local
626 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { skge_get_coalesce()
627 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); skge_get_coalesce()
628 u32 msk = skge_read32(hw, B2_IRQM_MSK); skge_get_coalesce()
644 struct skge_hw *hw = skge->hw; skge_set_coalesce() local
646 u32 msk = skge_read32(hw, B2_IRQM_MSK); skge_set_coalesce()
669 skge_write32(hw, B2_IRQM_MSK, msk); skge_set_coalesce()
671 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); skge_set_coalesce()
673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); skge_set_coalesce()
674 skge_write32(hw, B2_IRQM_CTRL, TIM_START); skge_set_coalesce()
682 struct skge_hw *hw = skge->hw; skge_led() local
685 spin_lock_bh(&hw->phy_lock); skge_led()
686 if (is_genesis(hw)) { skge_led()
689 if (hw->phy_type == SK_PHY_BCOM) skge_led()
690 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); skge_led()
692 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); skge_led()
693 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); skge_led()
695 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); skge_led()
696 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); skge_led()
697 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); skge_led()
701 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); skge_led()
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); skge_led()
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); skge_led()
705 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); skge_led()
710 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); skge_led()
711 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); skge_led()
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); skge_led()
714 if (hw->phy_type == SK_PHY_BCOM) skge_led()
715 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); skge_led()
717 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); skge_led()
718 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); skge_led()
719 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); skge_led()
726 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); skge_led()
727 gm_phy_write(hw, port, PHY_MARV_LED_OVER, skge_led()
735 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, skge_led()
741 gm_phy_write(hw, port, PHY_MARV_LED_OVER, skge_led()
747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); skge_led()
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER, skge_led()
756 spin_unlock_bh(&hw->phy_lock); skge_led()
790 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2); skge_get_eeprom_len()
823 struct pci_dev *pdev = skge->hw->pdev; skge_get_eeprom()
849 struct pci_dev *pdev = skge->hw->pdev; skge_set_eeprom()
940 map = pci_map_single(skge->hw->pdev, skb->data, bufsize, skge_rx_setup()
943 if (pci_dma_mapping_error(skge->hw->pdev, map)) skge_rx_setup()
982 struct skge_hw *hw = skge->hw; skge_rx_clean() local
991 pci_unmap_single(hw->pdev, skge_rx_clean()
1050 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), skge_link_up()
1065 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); skge_link_down()
1072 static void xm_link_down(struct skge_hw *hw, int port) xm_link_down() argument
1074 struct net_device *dev = hw->dev[port]; xm_link_down()
1077 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); xm_link_down()
1083 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) __xm_phy_read() argument
1087 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); __xm_phy_read()
1088 *val = xm_read16(hw, port, XM_PHY_DATA); __xm_phy_read()
1090 if (hw->phy_type == SK_PHY_XMAC) __xm_phy_read()
1094 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) __xm_phy_read()
1101 *val = xm_read16(hw, port, XM_PHY_DATA); __xm_phy_read()
1106 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) xm_phy_read() argument
1109 if (__xm_phy_read(hw, port, reg, &v)) xm_phy_read()
1110 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); xm_phy_read()
1114 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) xm_phy_write() argument
1118 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); xm_phy_write()
1120 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) xm_phy_write()
1127 xm_write16(hw, port, XM_PHY_DATA, val); xm_phy_write()
1129 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) xm_phy_write()
1136 static void genesis_init(struct skge_hw *hw) genesis_init() argument
1139 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); genesis_init()
1140 skge_write8(hw, B2_BSC_CTRL, BSC_START); genesis_init()
1143 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); genesis_init()
1146 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); genesis_init()
1147 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); genesis_init()
1148 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); genesis_init()
1149 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); genesis_init()
1151 skge_write8(hw, B3_MA_RCINI_RX1, 0); genesis_init()
1152 skge_write8(hw, B3_MA_RCINI_RX2, 0); genesis_init()
1153 skge_write8(hw, B3_MA_RCINI_TX1, 0); genesis_init()
1154 skge_write8(hw, B3_MA_RCINI_TX2, 0); genesis_init()
1157 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); genesis_init()
1158 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); genesis_init()
1159 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); genesis_init()
1160 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); genesis_init()
1161 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); genesis_init()
1164 static void genesis_reset(struct skge_hw *hw, int port) genesis_reset() argument
1169 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); genesis_reset()
1172 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); genesis_reset()
1173 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); genesis_reset()
1174 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ genesis_reset()
1175 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ genesis_reset()
1176 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ genesis_reset()
1179 if (hw->phy_type == SK_PHY_BCOM) genesis_reset()
1180 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); genesis_reset()
1182 xm_outhash(hw, port, XM_HSM, zero); genesis_reset()
1185 reg = xm_read32(hw, port, XM_MODE); genesis_reset()
1186 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); genesis_reset()
1187 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); genesis_reset()
1208 static void bcom_check_link(struct skge_hw *hw, int port) bcom_check_link() argument
1210 struct net_device *dev = hw->dev[port]; bcom_check_link()
1215 xm_phy_read(hw, port, PHY_BCOM_STAT); bcom_check_link()
1216 status = xm_phy_read(hw, port, PHY_BCOM_STAT); bcom_check_link()
1219 xm_link_down(hw, port); bcom_check_link()
1229 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); bcom_check_link()
1235 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); bcom_check_link()
1276 struct skge_hw *hw = skge->hw; bcom_phy_init() local
1296 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); bcom_phy_init()
1299 r = xm_read16(hw, port, XM_MMU_CMD); bcom_phy_init()
1301 xm_write16(hw, port, XM_MMU_CMD, r); bcom_phy_init()
1310 xm_phy_write(hw, port, bcom_phy_init()
1320 xm_phy_write(hw, port, bcom_phy_init()
1329 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); bcom_phy_init()
1331 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); bcom_phy_init()
1334 xm_read16(hw, port, XM_ISRC); bcom_phy_init()
1350 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); bcom_phy_init()
1357 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); bcom_phy_init()
1361 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, bcom_phy_init()
1365 if (hw->dev[port]->mtu > ETH_DATA_LEN) { bcom_phy_init()
1366 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, bcom_phy_init()
1373 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); bcom_phy_init()
1374 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); bcom_phy_init()
1377 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); bcom_phy_init()
1382 struct skge_hw *hw = skge->hw; xm_phy_init() local
1394 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); xm_phy_init()
1408 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); xm_phy_init()
1417 struct skge_hw *hw = skge->hw; xm_check_link() local
1422 xm_phy_read(hw, port, PHY_XMAC_STAT); xm_check_link()
1423 status = xm_phy_read(hw, port, PHY_XMAC_STAT); xm_check_link()
1426 xm_link_down(hw, port); xm_check_link()
1436 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); xm_check_link()
1442 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); xm_check_link()
1491 struct skge_hw *hw = skge->hw; xm_link_timer() local
1499 spin_lock_irqsave(&hw->phy_lock, flags); xm_link_timer()
1506 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) xm_link_timer()
1512 u16 msk = xm_read16(hw, port, XM_IMSK); xm_link_timer()
1514 xm_write16(hw, port, XM_IMSK, msk); xm_link_timer()
1515 xm_read16(hw, port, XM_ISRC); xm_link_timer()
1521 spin_unlock_irqrestore(&hw->phy_lock, flags); xm_link_timer()
1524 static void genesis_mac_init(struct skge_hw *hw, int port) genesis_mac_init() argument
1526 struct net_device *dev = hw->dev[port]; genesis_mac_init()
1528 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; genesis_mac_init()
1534 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), genesis_mac_init()
1536 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) genesis_mac_init()
1545 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); genesis_mac_init()
1552 if (hw->phy_type != SK_PHY_XMAC) { genesis_mac_init()
1554 r = skge_read32(hw, B2_GP_IO); genesis_mac_init()
1560 skge_write32(hw, B2_GP_IO, r); genesis_mac_init()
1563 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); genesis_mac_init()
1567 switch (hw->phy_type) { genesis_mac_init()
1573 bcom_check_link(hw, port); genesis_mac_init()
1577 xm_outaddr(hw, port, XM_SA, dev->dev_addr); genesis_mac_init()
1581 xm_outaddr(hw, port, XM_EXM(i), zero); genesis_mac_init()
1584 xm_write16(hw, port, XM_STAT_CMD, genesis_mac_init()
1587 xm_write16(hw, port, XM_STAT_CMD, genesis_mac_init()
1591 xm_write16(hw, port, XM_RX_HI_WM, 1450); genesis_mac_init()
1606 xm_write16(hw, port, XM_RX_CMD, r); genesis_mac_init()
1609 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); genesis_mac_init()
1612 if (hw->ports > 1 && jumbo) genesis_mac_init()
1613 xm_write16(hw, port, XM_TX_THR, 1020); genesis_mac_init()
1615 xm_write16(hw, port, XM_TX_THR, 512); genesis_mac_init()
1631 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); genesis_mac_init()
1639 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); genesis_mac_init()
1646 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); genesis_mac_init()
1649 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); genesis_mac_init()
1652 skge_write8(hw, B3_MA_TOINI_RX1, 72); genesis_mac_init()
1653 skge_write8(hw, B3_MA_TOINI_RX2, 72); genesis_mac_init()
1654 skge_write8(hw, B3_MA_TOINI_TX1, 72); genesis_mac_init()
1655 skge_write8(hw, B3_MA_TOINI_TX2, 72); genesis_mac_init()
1657 skge_write8(hw, B3_MA_RCINI_RX1, 0); genesis_mac_init()
1658 skge_write8(hw, B3_MA_RCINI_RX2, 0); genesis_mac_init()
1659 skge_write8(hw, B3_MA_RCINI_TX1, 0); genesis_mac_init()
1660 skge_write8(hw, B3_MA_RCINI_TX2, 0); genesis_mac_init()
1663 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); genesis_mac_init()
1664 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); genesis_mac_init()
1665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); genesis_mac_init()
1668 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); genesis_mac_init()
1669 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); genesis_mac_init()
1670 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); genesis_mac_init()
1674 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); genesis_mac_init()
1677 skge_write16(hw, B3_PA_CTRL, genesis_mac_init()
1684 struct skge_hw *hw = skge->hw; genesis_stop() local
1690 cmd = xm_read16(hw, port, XM_MMU_CMD); genesis_stop()
1692 xm_write16(hw, port, XM_MMU_CMD, cmd); genesis_stop()
1694 genesis_reset(hw, port); genesis_stop()
1697 skge_write16(hw, B3_PA_CTRL, genesis_stop()
1701 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); genesis_stop()
1703 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); genesis_stop()
1704 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) genesis_stop()
1709 if (hw->phy_type != SK_PHY_XMAC) { genesis_stop()
1710 u32 reg = skge_read32(hw, B2_GP_IO); genesis_stop()
1718 skge_write32(hw, B2_GP_IO, reg); genesis_stop()
1719 skge_read32(hw, B2_GP_IO); genesis_stop()
1722 xm_write16(hw, port, XM_MMU_CMD, genesis_stop()
1723 xm_read16(hw, port, XM_MMU_CMD) genesis_stop()
1726 xm_read16(hw, port, XM_MMU_CMD); genesis_stop()
1732 struct skge_hw *hw = skge->hw; genesis_get_stats() local
1737 xm_write16(hw, port, genesis_get_stats()
1741 while (xm_read16(hw, port, XM_STAT_CMD) genesis_get_stats()
1749 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 genesis_get_stats()
1750 | xm_read32(hw, port, XM_TXO_OK_LO); genesis_get_stats()
1751 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 genesis_get_stats()
1752 | xm_read32(hw, port, XM_RXO_OK_LO); genesis_get_stats()
1755 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); genesis_get_stats()
1758 static void genesis_mac_intr(struct skge_hw *hw, int port) genesis_mac_intr() argument
1760 struct net_device *dev = hw->dev[port]; genesis_mac_intr()
1762 u16 status = xm_read16(hw, port, XM_ISRC); genesis_mac_intr()
1767 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { genesis_mac_intr()
1768 xm_link_down(hw, port); genesis_mac_intr()
1773 xm_write32(hw, port, XM_MODE, XM_MD_FTF); genesis_mac_intr()
1780 struct skge_hw *hw = skge->hw; genesis_link_up() local
1785 cmd = xm_read16(hw, port, XM_MMU_CMD); genesis_link_up()
1799 xm_write16(hw, port, XM_MMU_CMD, cmd); genesis_link_up()
1801 mode = xm_read32(hw, port, XM_MODE); genesis_link_up()
1815 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); genesis_link_up()
1818 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); genesis_link_up()
1827 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); genesis_link_up()
1830 xm_write32(hw, port, XM_MODE, mode); genesis_link_up()
1833 msk = xm_read16(hw, port, XM_IMSK); genesis_link_up()
1835 xm_write16(hw, port, XM_IMSK, msk); genesis_link_up()
1837 xm_read16(hw, port, XM_ISRC); genesis_link_up()
1840 cmd = xm_read16(hw, port, XM_MMU_CMD); genesis_link_up()
1841 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) genesis_link_up()
1848 if (hw->phy_type == SK_PHY_BCOM) { genesis_link_up()
1849 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, genesis_link_up()
1850 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) genesis_link_up()
1852 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); genesis_link_up()
1856 xm_write16(hw, port, XM_MMU_CMD, genesis_link_up()
1864 struct skge_hw *hw = skge->hw; bcom_phy_intr() local
1868 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); bcom_phy_intr()
1874 hw->dev[port]->name); bcom_phy_intr()
1880 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); bcom_phy_intr()
1881 xm_phy_write(hw, port, PHY_BCOM_CTRL, bcom_phy_intr()
1883 xm_phy_write(hw, port, PHY_BCOM_CTRL, bcom_phy_intr()
1888 bcom_check_link(hw, port); bcom_phy_intr()
1892 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) gm_phy_write() argument
1896 gma_write16(hw, port, GM_SMI_DATA, val); gm_phy_write()
1897 gma_write16(hw, port, GM_SMI_CTRL, gm_phy_write()
1898 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); gm_phy_write()
1902 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) gm_phy_write()
1906 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); gm_phy_write()
1910 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) __gm_phy_read() argument
1914 gma_write16(hw, port, GM_SMI_CTRL, __gm_phy_read()
1915 GM_SMI_CT_PHY_AD(hw->phy_addr) __gm_phy_read()
1920 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) __gm_phy_read()
1926 *val = gma_read16(hw, port, GM_SMI_DATA); __gm_phy_read()
1930 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) gm_phy_read() argument
1933 if (__gm_phy_read(hw, port, reg, &v)) gm_phy_read()
1934 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); gm_phy_read()
1939 static void yukon_init(struct skge_hw *hw, int port) yukon_init() argument
1941 struct skge_port *skge = netdev_priv(hw->dev[port]); yukon_init()
1945 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); yukon_init()
1953 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); yukon_init()
1956 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); yukon_init()
1961 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); yukon_init()
1968 if (hw->copper) { yukon_init()
2014 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); yukon_init()
2016 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); yukon_init()
2017 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); yukon_init()
2021 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); yukon_init()
2023 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); yukon_init()
2026 static void yukon_reset(struct skge_hw *hw, int port) yukon_reset() argument
2028 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ yukon_reset()
2029 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ yukon_reset()
2030 gma_write16(hw, port, GM_MC_ADDR_H2, 0); yukon_reset()
2031 gma_write16(hw, port, GM_MC_ADDR_H3, 0); yukon_reset()
2032 gma_write16(hw, port, GM_MC_ADDR_H4, 0); yukon_reset()
2034 gma_write16(hw, port, GM_RX_CTRL, yukon_reset()
2035 gma_read16(hw, port, GM_RX_CTRL) yukon_reset()
2040 static int is_yukon_lite_a0(struct skge_hw *hw) is_yukon_lite_a0() argument
2045 if (hw->chip_id != CHIP_ID_YUKON) is_yukon_lite_a0()
2048 reg = skge_read32(hw, B2_FAR); is_yukon_lite_a0()
2049 skge_write8(hw, B2_FAR + 3, 0xff); is_yukon_lite_a0()
2050 ret = (skge_read8(hw, B2_FAR + 3) != 0); is_yukon_lite_a0()
2051 skge_write32(hw, B2_FAR, reg); is_yukon_lite_a0()
2055 static void yukon_mac_init(struct skge_hw *hw, int port) yukon_mac_init() argument
2057 struct skge_port *skge = netdev_priv(hw->dev[port]); yukon_mac_init()
2060 const u8 *addr = hw->dev[port]->dev_addr; yukon_mac_init()
2063 if (hw->chip_id == CHIP_ID_YUKON_LITE && yukon_mac_init()
2064 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { yukon_mac_init()
2065 reg = skge_read32(hw, B2_GP_IO); yukon_mac_init()
2067 skge_write32(hw, B2_GP_IO, reg); yukon_mac_init()
2071 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); yukon_mac_init()
2072 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); yukon_mac_init()
2075 if (hw->chip_id == CHIP_ID_YUKON_LITE && yukon_mac_init()
2076 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { yukon_mac_init()
2077 reg = skge_read32(hw, B2_GP_IO); yukon_mac_init()
2080 skge_write32(hw, B2_GP_IO, reg); yukon_mac_init()
2086 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; yukon_mac_init()
2089 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); yukon_mac_init()
2090 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); yukon_mac_init()
2091 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); yukon_mac_init()
2095 gma_write16(hw, port, GM_GP_CTRL, yukon_mac_init()
2096 gma_read16(hw, port, GM_GP_CTRL) | reg); yukon_mac_init()
2119 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); yukon_mac_init()
2132 gma_write16(hw, port, GM_GP_CTRL, reg); yukon_mac_init()
2133 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); yukon_mac_init()
2135 yukon_init(hw, port); yukon_mac_init()
2138 reg = gma_read16(hw, port, GM_PHY_ADDR); yukon_mac_init()
2139 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); yukon_mac_init()
2142 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); yukon_mac_init()
2143 gma_write16(hw, port, GM_PHY_ADDR, reg); yukon_mac_init()
2146 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); yukon_mac_init()
2149 gma_write16(hw, port, GM_RX_CTRL, yukon_mac_init()
2153 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); yukon_mac_init()
2156 gma_write16(hw, port, GM_TX_PARAM, yukon_mac_init()
2166 if (hw->dev[port]->mtu > ETH_DATA_LEN) yukon_mac_init()
2169 gma_write16(hw, port, GM_SERIAL_MODE, reg); yukon_mac_init()
2172 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); yukon_mac_init()
2174 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); yukon_mac_init()
2177 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); yukon_mac_init()
2178 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); yukon_mac_init()
2179 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); yukon_mac_init()
2184 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); yukon_mac_init()
2188 if (is_yukon_lite_a0(hw)) yukon_mac_init()
2191 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); yukon_mac_init()
2192 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); yukon_mac_init()
2198 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); yukon_mac_init()
2201 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); yukon_mac_init()
2202 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); yukon_mac_init()
2206 static void yukon_suspend(struct skge_hw *hw, int port) yukon_suspend() argument
2210 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); yukon_suspend()
2212 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); yukon_suspend()
2214 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); yukon_suspend()
2216 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); yukon_suspend()
2219 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); yukon_suspend()
2221 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); yukon_suspend()
2226 struct skge_hw *hw = skge->hw; yukon_stop() local
2229 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); yukon_stop()
2230 yukon_reset(hw, port); yukon_stop()
2232 gma_write16(hw, port, GM_GP_CTRL, yukon_stop()
2233 gma_read16(hw, port, GM_GP_CTRL) yukon_stop()
2235 gma_read16(hw, port, GM_GP_CTRL); yukon_stop()
2237 yukon_suspend(hw, port); yukon_stop()
2240 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); yukon_stop()
2241 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); yukon_stop()
2246 struct skge_hw *hw = skge->hw; yukon_get_stats() local
2250 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 yukon_get_stats()
2251 | gma_read32(hw, port, GM_TXO_OK_LO); yukon_get_stats()
2252 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 yukon_get_stats()
2253 | gma_read32(hw, port, GM_RXO_OK_LO); yukon_get_stats()
2256 data[i] = gma_read32(hw, port, yukon_get_stats()
2260 static void yukon_mac_intr(struct skge_hw *hw, int port) yukon_mac_intr() argument
2262 struct net_device *dev = hw->dev[port]; yukon_mac_intr()
2264 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); yukon_mac_intr()
2271 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); yukon_mac_intr()
2276 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); yukon_mac_intr()
2281 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) yukon_speed() argument
2295 struct skge_hw *hw = skge->hw; yukon_link_up() local
2300 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); yukon_link_up()
2302 reg = gma_read16(hw, port, GM_GP_CTRL); yukon_link_up()
2308 gma_write16(hw, port, GM_GP_CTRL, reg); yukon_link_up()
2310 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); yukon_link_up()
2316 struct skge_hw *hw = skge->hw; yukon_link_down() local
2320 ctrl = gma_read16(hw, port, GM_GP_CTRL); yukon_link_down()
2322 gma_write16(hw, port, GM_GP_CTRL, ctrl); yukon_link_down()
2325 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); yukon_link_down()
2328 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); yukon_link_down()
2333 yukon_init(hw, port); yukon_link_down()
2338 struct skge_hw *hw = skge->hw; yukon_phy_intr() local
2343 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); yukon_phy_intr()
2344 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); yukon_phy_intr()
2350 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) yukon_phy_intr()
2356 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { yukon_phy_intr()
2368 skge->speed = yukon_speed(hw, phystat); yukon_phy_intr()
2387 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); yukon_phy_intr()
2389 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); yukon_phy_intr()
2395 skge->speed = yukon_speed(hw, phystat); yukon_phy_intr()
2414 struct skge_hw *hw = skge->hw; skge_phy_reset() local
2416 struct net_device *dev = hw->dev[port]; skge_phy_reset()
2421 spin_lock_bh(&hw->phy_lock); skge_phy_reset()
2422 if (is_genesis(hw)) { skge_phy_reset()
2423 genesis_reset(hw, port); skge_phy_reset()
2424 genesis_mac_init(hw, port); skge_phy_reset()
2426 yukon_reset(hw, port); skge_phy_reset()
2427 yukon_init(hw, port); skge_phy_reset()
2429 spin_unlock_bh(&hw->phy_lock); skge_phy_reset()
2439 struct skge_hw *hw = skge->hw; skge_ioctl() local
2447 data->phy_id = hw->phy_addr; skge_ioctl()
2452 spin_lock_bh(&hw->phy_lock); skge_ioctl()
2454 if (is_genesis(hw)) skge_ioctl()
2455 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); skge_ioctl()
2457 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); skge_ioctl()
2458 spin_unlock_bh(&hw->phy_lock); skge_ioctl()
2464 spin_lock_bh(&hw->phy_lock); skge_ioctl()
2465 if (is_genesis(hw)) skge_ioctl()
2466 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, skge_ioctl()
2469 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, skge_ioctl()
2471 spin_unlock_bh(&hw->phy_lock); skge_ioctl()
2477 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) skge_ramset() argument
2485 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); skge_ramset()
2486 skge_write32(hw, RB_ADDR(q, RB_START), start); skge_ramset()
2487 skge_write32(hw, RB_ADDR(q, RB_WP), start); skge_ramset()
2488 skge_write32(hw, RB_ADDR(q, RB_RP), start); skge_ramset()
2489 skge_write32(hw, RB_ADDR(q, RB_END), end); skge_ramset()
2493 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), skge_ramset()
2495 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), skge_ramset()
2501 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); skge_ramset()
2504 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); skge_ramset()
2511 struct skge_hw *hw = skge->hw; skge_qset() local
2516 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) skge_qset()
2519 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); skge_qset()
2520 skge_write32(hw, Q_ADDR(q, Q_F), watermark); skge_qset()
2521 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); skge_qset()
2522 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); skge_qset()
2528 struct skge_hw *hw = skge->hw; skge_up() local
2548 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); skge_up()
2555 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n"); skge_up()
2575 if (hw->ports == 1) { skge_up()
2576 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, skge_up()
2577 dev->name, hw); skge_up()
2580 hw->pdev->irq, err); skge_up()
2587 spin_lock_bh(&hw->phy_lock); skge_up()
2588 if (is_genesis(hw)) skge_up()
2589 genesis_mac_init(hw, port); skge_up()
2591 yukon_mac_init(hw, port); skge_up()
2592 spin_unlock_bh(&hw->phy_lock); skge_up()
2595 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); skge_up()
2596 ram_addr = hw->ram_offset + 2 * chunk * port; skge_up()
2598 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); skge_up()
2602 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); skge_up()
2607 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); skge_up()
2610 spin_lock_irq(&hw->hw_lock); skge_up()
2611 hw->intr_mask |= portmask[port]; skge_up()
2612 skge_write32(hw, B0_IMSK, hw->intr_mask); skge_up()
2613 skge_read32(hw, B0_IMSK); skge_up()
2614 spin_unlock_irq(&hw->hw_lock); skge_up()
2628 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); skge_up()
2635 static void skge_rx_stop(struct skge_hw *hw, int port) skge_rx_stop() argument
2637 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); skge_rx_stop()
2638 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), skge_rx_stop()
2640 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); skge_rx_stop()
2646 struct skge_hw *hw = skge->hw; skge_down() local
2656 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) skge_down()
2662 spin_lock_irq(&hw->hw_lock); skge_down()
2663 hw->intr_mask &= ~portmask[port]; skge_down()
2664 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); skge_down()
2665 skge_read32(hw, B0_IMSK); skge_down()
2666 spin_unlock_irq(&hw->hw_lock); skge_down()
2668 if (hw->ports == 1) skge_down()
2669 free_irq(hw->pdev->irq, hw); skge_down()
2671 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); skge_down()
2672 if (is_genesis(hw)) skge_down()
2678 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); skge_down()
2679 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), skge_down()
2684 skge_write8(hw, SK_REG(port, TXA_CTRL), skge_down()
2688 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); skge_down()
2689 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); skge_down()
2692 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); skge_down()
2693 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); skge_down()
2696 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); skge_down()
2698 skge_rx_stop(hw, port); skge_down()
2700 if (is_genesis(hw)) { skge_down()
2701 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); skge_down()
2702 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); skge_down()
2704 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); skge_down()
2705 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); skge_down()
2718 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); skge_down()
2734 struct skge_hw *hw = skge->hw; skge_xmit_frame() local
2752 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); skge_xmit_frame()
2753 if (pci_dma_mapping_error(hw->pdev, map)) skge_xmit_frame()
2769 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) skge_xmit_frame()
2789 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, skge_xmit_frame()
2791 if (dma_mapping_error(&hw->pdev->dev, map)) skge_xmit_frame()
2815 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); skge_xmit_frame()
2833 pci_unmap_single(hw->pdev, skge_xmit_frame()
2839 pci_unmap_page(hw->pdev, skge_xmit_frame()
2847 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); skge_xmit_frame()
2877 skge_tx_unmap(skge->hw->pdev, e, td->control); skge_tx_clean()
2894 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); skge_tx_timeout()
2936 struct skge_hw *hw = skge->hw; genesis_set_multicast() local
2942 mode = xm_read32(hw, port, XM_MODE); genesis_set_multicast()
2962 xm_write32(hw, port, XM_MODE, mode); genesis_set_multicast()
2963 xm_outhash(hw, port, XM_HSM, filter); genesis_set_multicast()
2975 struct skge_hw *hw = skge->hw; yukon_set_multicast() local
2985 reg = gma_read16(hw, port, GM_RX_CTRL); yukon_set_multicast()
3005 gma_write16(hw, port, GM_MC_ADDR_H1, yukon_set_multicast()
3007 gma_write16(hw, port, GM_MC_ADDR_H2, yukon_set_multicast()
3009 gma_write16(hw, port, GM_MC_ADDR_H3, yukon_set_multicast()
3011 gma_write16(hw, port, GM_MC_ADDR_H4, yukon_set_multicast()
3014 gma_write16(hw, port, GM_RX_CTRL, reg); yukon_set_multicast()
3017 static inline u16 phy_length(const struct skge_hw *hw, u32 status) phy_length() argument
3019 if (is_genesis(hw)) phy_length()
3025 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) bad_phy_status() argument
3027 if (is_genesis(hw)) bad_phy_status()
3038 if (is_genesis(skge->hw)) skge_set_multicast()
3067 if (bad_phy_status(skge->hw, status)) skge_rx_get()
3070 if (phy_length(skge->hw, status) != len) skge_rx_get()
3078 pci_dma_sync_single_for_cpu(skge->hw->pdev, skge_rx_get()
3083 pci_dma_sync_single_for_device(skge->hw->pdev, skge_rx_get()
3106 pci_unmap_single(skge->hw->pdev, skge_rx_get()
3128 if (is_genesis(skge->hw)) { skge_rx_get()
3157 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); skge_tx_done()
3165 skge_tx_unmap(skge->hw->pdev, e, control); skge_tx_done()
3200 struct skge_hw *hw = skge->hw; skge_poll() local
3207 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); skge_poll()
3229 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); skge_poll()
3235 spin_lock_irqsave(&hw->hw_lock, flags); skge_poll()
3237 hw->intr_mask |= napimask[skge->port]; skge_poll()
3238 skge_write32(hw, B0_IMSK, hw->intr_mask); skge_poll()
3239 skge_read32(hw, B0_IMSK); skge_poll()
3240 spin_unlock_irqrestore(&hw->hw_lock, flags); skge_poll()
3249 static void skge_mac_parity(struct skge_hw *hw, int port) skge_mac_parity() argument
3251 struct net_device *dev = hw->dev[port]; skge_mac_parity()
3255 if (is_genesis(hw)) skge_mac_parity()
3256 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), skge_mac_parity()
3260 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), skge_mac_parity()
3261 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) skge_mac_parity()
3265 static void skge_mac_intr(struct skge_hw *hw, int port) skge_mac_intr() argument
3267 if (is_genesis(hw)) skge_mac_intr()
3268 genesis_mac_intr(hw, port); skge_mac_intr()
3270 yukon_mac_intr(hw, port); skge_mac_intr()
3274 static void skge_error_irq(struct skge_hw *hw) skge_error_irq() argument
3276 struct pci_dev *pdev = hw->pdev; skge_error_irq()
3277 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); skge_error_irq()
3279 if (is_genesis(hw)) { skge_error_irq()
3282 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); skge_error_irq()
3284 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); skge_error_irq()
3288 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); skge_error_irq()
3293 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); skge_error_irq()
3298 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); skge_error_irq()
3302 skge_mac_parity(hw, 0); skge_error_irq()
3305 skge_mac_parity(hw, 1); skge_error_irq()
3309 hw->dev[0]->name); skge_error_irq()
3310 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); skge_error_irq()
3315 hw->dev[1]->name); skge_error_irq()
3316 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); skge_error_irq()
3330 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); skge_error_irq()
3334 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); skge_error_irq()
3337 hwstatus = skge_read32(hw, B0_HWE_ISRC); skge_error_irq()
3339 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); skge_error_irq()
3340 hw->intr_mask &= ~IS_HW_ERR; skge_error_irq()
3352 struct skge_hw *hw = (struct skge_hw *) arg; skge_extirq() local
3355 for (port = 0; port < hw->ports; port++) { skge_extirq()
3356 struct net_device *dev = hw->dev[port]; skge_extirq()
3361 spin_lock(&hw->phy_lock); skge_extirq()
3362 if (!is_genesis(hw)) skge_extirq()
3364 else if (hw->phy_type == SK_PHY_BCOM) skge_extirq()
3366 spin_unlock(&hw->phy_lock); skge_extirq()
3370 spin_lock_irq(&hw->hw_lock); skge_extirq()
3371 hw->intr_mask |= IS_EXT_REG; skge_extirq()
3372 skge_write32(hw, B0_IMSK, hw->intr_mask); skge_extirq()
3373 skge_read32(hw, B0_IMSK); skge_extirq()
3374 spin_unlock_irq(&hw->hw_lock); skge_extirq()
3379 struct skge_hw *hw = dev_id; skge_intr() local
3383 spin_lock(&hw->hw_lock); skge_intr()
3385 status = skge_read32(hw, B0_SP_ISRC); skge_intr()
3390 status &= hw->intr_mask; skge_intr()
3392 hw->intr_mask &= ~IS_EXT_REG; skge_intr()
3393 tasklet_schedule(&hw->phy_task); skge_intr()
3397 struct skge_port *skge = netdev_priv(hw->dev[0]); skge_intr()
3398 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); skge_intr()
3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); skge_intr()
3406 ++hw->dev[0]->stats.rx_over_errors; skge_intr()
3407 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); skge_intr()
3412 skge_mac_intr(hw, 0); skge_intr()
3414 if (hw->dev[1]) { skge_intr()
3415 struct skge_port *skge = netdev_priv(hw->dev[1]); skge_intr()
3418 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); skge_intr()
3423 ++hw->dev[1]->stats.rx_over_errors; skge_intr()
3424 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); skge_intr()
3428 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); skge_intr()
3431 skge_mac_intr(hw, 1); skge_intr()
3435 skge_error_irq(hw); skge_intr()
3437 skge_write32(hw, B0_IMSK, hw->intr_mask); skge_intr()
3438 skge_read32(hw, B0_IMSK); skge_intr()
3439 spin_unlock(&hw->hw_lock); skge_intr()
3450 skge_intr(dev->irq, skge->hw); skge_netpoll()
3458 struct skge_hw *hw = skge->hw; skge_set_mac_address() local
3469 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); skge_set_mac_address()
3470 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); skge_set_mac_address()
3473 spin_lock_bh(&hw->phy_lock); skge_set_mac_address()
3474 ctrl = gma_read16(hw, port, GM_GP_CTRL); skge_set_mac_address()
3475 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); skge_set_mac_address()
3477 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); skge_set_mac_address()
3478 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); skge_set_mac_address()
3480 if (is_genesis(hw)) skge_set_mac_address()
3481 xm_outaddr(hw, port, XM_SA, dev->dev_addr); skge_set_mac_address()
3483 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); skge_set_mac_address()
3484 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); skge_set_mac_address()
3487 gma_write16(hw, port, GM_GP_CTRL, ctrl); skge_set_mac_address()
3488 spin_unlock_bh(&hw->phy_lock); skge_set_mac_address()
3504 static const char *skge_board_name(const struct skge_hw *hw) skge_board_name() argument
3510 if (skge_chips[i].id == hw->chip_id) skge_board_name()
3513 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); skge_board_name()
3522 static int skge_reset(struct skge_hw *hw) skge_reset() argument
3529 ctst = skge_read16(hw, B0_CTST); skge_reset()
3532 skge_write8(hw, B0_CTST, CS_RST_SET); skge_reset()
3533 skge_write8(hw, B0_CTST, CS_RST_CLR); skge_reset()
3536 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); skge_reset()
3537 skge_write8(hw, B2_TST_CTRL2, 0); skge_reset()
3539 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); skge_reset()
3540 pci_write_config_word(hw->pdev, PCI_STATUS, skge_reset()
3542 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); skge_reset()
3543 skge_write8(hw, B0_CTST, CS_MRST_CLR); skge_reset()
3546 skge_write16(hw, B0_CTST, skge_reset()
3549 hw->chip_id = skge_read8(hw, B2_CHIP_ID); skge_reset()
3550 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; skge_reset()
3551 pmd_type = skge_read8(hw, B2_PMD_TYP); skge_reset()
3552 hw->copper = (pmd_type == 'T' || pmd_type == '1'); skge_reset()
3554 switch (hw->chip_id) { skge_reset()
3557 switch (hw->phy_type) { skge_reset()
3559 hw->phy_addr = PHY_ADDR_XMAC; skge_reset()
3562 hw->phy_addr = PHY_ADDR_BCOM; skge_reset()
3565 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", skge_reset()
3566 hw->phy_type); skge_reset()
3571 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); skge_reset()
3578 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') skge_reset()
3579 hw->copper = 1; skge_reset()
3581 hw->phy_addr = PHY_ADDR_MARV; skge_reset()
3585 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", skge_reset()
3586 hw->chip_id); skge_reset()
3590 mac_cfg = skge_read8(hw, B2_MAC_CFG); skge_reset()
3591 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; skge_reset()
3592 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; skge_reset()
3595 t8 = skge_read8(hw, B2_E_0); skge_reset()
3596 if (is_genesis(hw)) { skge_reset()
3599 hw->ram_size = 0x100000; skge_reset()
3600 hw->ram_offset = 0x80000; skge_reset()
3602 hw->ram_size = t8 * 512; skge_reset()
3604 hw->ram_size = 0x20000; skge_reset()
3606 hw->ram_size = t8 * 4096; skge_reset()
3608 hw->intr_mask = IS_HW_ERR; skge_reset()
3611 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) skge_reset()
3612 hw->intr_mask |= IS_EXT_REG; skge_reset()
3614 if (is_genesis(hw)) skge_reset()
3615 genesis_init(hw); skge_reset()
3618 skge_write8(hw, B0_POWER_CTRL, skge_reset()
3622 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && skge_reset()
3623 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { skge_reset()
3624 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); skge_reset()
3625 hw->intr_mask &= ~IS_HW_ERR; skge_reset()
3629 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); skge_reset()
3630 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg); skge_reset()
3632 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); skge_reset()
3633 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); skge_reset()
3636 for (i = 0; i < hw->ports; i++) { skge_reset()
3637 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); skge_reset()
3638 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); skge_reset()
3643 skge_write8(hw, B2_TI_CTRL, TIM_STOP); skge_reset()
3644 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); skge_reset()
3645 skge_write8(hw, B0_LED, LED_STAT_ON); skge_reset()
3648 for (i = 0; i < hw->ports; i++) skge_reset()
3649 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); skge_reset()
3652 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); skge_reset()
3654 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); skge_reset()
3655 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); skge_reset()
3656 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); skge_reset()
3657 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); skge_reset()
3658 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); skge_reset()
3659 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); skge_reset()
3660 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); skge_reset()
3661 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); skge_reset()
3662 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); skge_reset()
3663 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); skge_reset()
3664 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); skge_reset()
3665 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); skge_reset()
3667 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); skge_reset()
3672 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); skge_reset()
3673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); skge_reset()
3674 skge_write32(hw, B2_IRQM_CTRL, TIM_START); skge_reset()
3677 skge_write32(hw, B0_IMSK, 0); skge_reset()
3679 for (i = 0; i < hw->ports; i++) { skge_reset()
3680 if (is_genesis(hw)) skge_reset()
3681 genesis_reset(hw, i); skge_reset()
3683 yukon_reset(hw, i); skge_reset()
3698 const struct skge_hw *hw = skge->hw; skge_debug_show() local
3704 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), skge_debug_show()
3705 skge_read32(hw, B0_IMSK)); skge_debug_show()
3845 static struct net_device *skge_devinit(struct skge_hw *hw, int port, skge_devinit() argument
3854 SET_NETDEV_DEV(dev, &hw->pdev->dev); skge_devinit()
3858 dev->irq = hw->pdev->irq; skge_devinit()
3866 skge->hw = hw; skge_devinit()
3877 skge->advertising = skge_supported_modes(hw); skge_devinit()
3879 if (device_can_wakeup(&hw->pdev->dev)) { skge_devinit()
3880 skge->wol = wol_supported(hw) & WAKE_MAGIC; skge_devinit()
3881 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); skge_devinit()
3884 hw->dev[port] = dev; skge_devinit()
3889 if (is_genesis(hw)) skge_devinit()
3898 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); skge_devinit()
3915 struct skge_hw *hw; skge_probe() local
3958 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") skge_probe()
3960 if (!hw) skge_probe()
3963 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); skge_probe()
3965 hw->pdev = pdev; skge_probe()
3966 spin_lock_init(&hw->hw_lock); skge_probe()
3967 spin_lock_init(&hw->phy_lock); skge_probe()
3968 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw); skge_probe()
3970 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); skge_probe()
3971 if (!hw->regs) { skge_probe()
3976 err = skge_reset(hw); skge_probe()
3983 skge_board_name(hw), hw->chip_rev); skge_probe()
3985 dev = skge_devinit(hw, 0, using_dac); skge_probe()
4003 if (hw->ports > 1) { skge_probe()
4004 dev1 = skge_devinit(hw, 1, using_dac); skge_probe()
4017 hw->irq_name, hw); skge_probe()
4026 pci_set_drvdata(pdev, hw); skge_probe()
4039 skge_write16(hw, B0_LED, LED_STAT_OFF); skge_probe()
4041 iounmap(hw->regs); skge_probe()
4043 kfree(hw); skge_probe()
4054 struct skge_hw *hw = pci_get_drvdata(pdev); skge_remove() local
4057 if (!hw) skge_remove()
4060 dev1 = hw->dev[1]; skge_remove()
4063 dev0 = hw->dev[0]; skge_remove()
4066 tasklet_kill(&hw->phy_task); skge_remove()
4068 spin_lock_irq(&hw->hw_lock); skge_remove()
4069 hw->intr_mask = 0; skge_remove()
4071 if (hw->ports > 1) { skge_remove()
4072 skge_write32(hw, B0_IMSK, 0); skge_remove()
4073 skge_read32(hw, B0_IMSK); skge_remove()
4074 free_irq(pdev->irq, hw); skge_remove()
4076 spin_unlock_irq(&hw->hw_lock); skge_remove()
4078 skge_write16(hw, B0_LED, LED_STAT_OFF); skge_remove()
4079 skge_write8(hw, B0_CTST, CS_RST_SET); skge_remove()
4081 if (hw->ports > 1) skge_remove()
4082 free_irq(pdev->irq, hw); skge_remove()
4089 iounmap(hw->regs); skge_remove()
4090 kfree(hw); skge_remove()
4097 struct skge_hw *hw = pci_get_drvdata(pdev); skge_suspend() local
4100 if (!hw) skge_suspend()
4103 for (i = 0; i < hw->ports; i++) { skge_suspend()
4104 struct net_device *dev = hw->dev[i]; skge_suspend()
4114 skge_write32(hw, B0_IMSK, 0); skge_suspend()
4122 struct skge_hw *hw = pci_get_drvdata(pdev); skge_resume() local
4125 if (!hw) skge_resume()
4128 err = skge_reset(hw); skge_resume()
4132 for (i = 0; i < hw->ports; i++) { skge_resume()
4133 struct net_device *dev = hw->dev[i]; skge_resume()
4159 struct skge_hw *hw = pci_get_drvdata(pdev); skge_shutdown() local
4162 if (!hw) skge_shutdown()
4165 for (i = 0; i < hw->ports; i++) { skge_shutdown()
4166 struct net_device *dev = hw->dev[i]; skge_shutdown()
/linux-4.4.14/drivers/net/ethernet/intel/ixgb/
H A Dixgb_hw.c43 static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
45 static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
47 static void ixgb_get_bus_info(struct ixgb_hw *hw);
49 static bool ixgb_link_reset(struct ixgb_hw *hw);
51 static void ixgb_optics_reset(struct ixgb_hw *hw);
53 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
55 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
57 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
59 static void ixgb_clear_vfta(struct ixgb_hw *hw);
61 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
63 static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
68 static bool ixgb_setup_fc(struct ixgb_hw *hw);
72 static u32 ixgb_mac_reset(struct ixgb_hw *hw) ixgb_mac_reset() argument
87 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); ixgb_mac_reset()
89 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); ixgb_mac_reset()
94 ctrl_reg = IXGB_READ_REG(hw, CTRL0); ixgb_mac_reset()
100 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) { ixgb_mac_reset()
107 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); ixgb_mac_reset()
108 ixgb_optics_reset_bcm(hw); ixgb_mac_reset()
111 if (hw->phy_type == ixgb_phy_type_txn17401) ixgb_mac_reset()
112 ixgb_optics_reset(hw); ixgb_mac_reset()
120 * hw - Struct containing variables accessed by shared code
123 ixgb_adapter_stop(struct ixgb_hw *hw) ixgb_adapter_stop() argument
133 if (hw->adapter_stopped) { ixgb_adapter_stop()
141 hw->adapter_stopped = true; ixgb_adapter_stop()
145 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); ixgb_adapter_stop()
151 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); ixgb_adapter_stop()
152 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); ixgb_adapter_stop()
153 IXGB_WRITE_FLUSH(hw); ixgb_adapter_stop()
163 ctrl_reg = ixgb_mac_reset(hw); ixgb_adapter_stop()
167 IXGB_WRITE_REG(hw, IMC, 0xffffffff); ixgb_adapter_stop()
170 icr_reg = IXGB_READ_REG(hw, ICR); ixgb_adapter_stop()
181 * hw - Struct containing variables accessed by shared code.
186 ixgb_identify_xpak_vendor(struct ixgb_hw *hw) ixgb_identify_xpak_vendor() argument
198 vendor_name[i] = ixgb_read_phy_reg(hw, ixgb_identify_xpak_vendor()
220 * hw - Struct containing variables accessed by shared code. The device_id
226 ixgb_identify_phy(struct ixgb_hw *hw) ixgb_identify_phy() argument
234 switch (hw->device_id) { ixgb_identify_phy()
244 xpak_vendor = ixgb_identify_xpak_vendor(hw); ixgb_identify_phy()
259 xpak_vendor = ixgb_identify_xpak_vendor(hw); ixgb_identify_phy()
275 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) ixgb_identify_phy()
284 * hw - Struct containing variables accessed by shared code
299 ixgb_init_hw(struct ixgb_hw *hw) ixgb_init_hw() argument
314 ctrl_reg = ixgb_mac_reset(hw); ixgb_init_hw()
319 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); ixgb_init_hw()
321 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); ixgb_init_hw()
327 if (!ixgb_get_eeprom_data(hw)) ixgb_init_hw()
331 hw->device_id = ixgb_get_ee_device_id(hw); ixgb_init_hw()
332 hw->phy_type = ixgb_identify_phy(hw); ixgb_init_hw()
337 ixgb_init_rx_addrs(hw); ixgb_init_hw()
343 if (!mac_addr_valid(hw->curr_mac_addr)) { ixgb_init_hw()
349 hw->adapter_stopped = false; ixgb_init_hw()
352 ixgb_get_bus_info(hw); ixgb_init_hw()
357 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); ixgb_init_hw()
360 ixgb_clear_vfta(hw); ixgb_init_hw()
363 ixgb_clear_hw_cntrs(hw); ixgb_init_hw()
366 status = ixgb_setup_fc(hw); ixgb_init_hw()
369 ixgb_check_for_link(hw); ixgb_init_hw()
377 * hw - Struct containing variables accessed by shared code
384 ixgb_init_rx_addrs(struct ixgb_hw *hw) ixgb_init_rx_addrs() argument
395 if (!mac_addr_valid(hw->curr_mac_addr)) { ixgb_init_rx_addrs()
398 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); ixgb_init_rx_addrs()
401 hw->curr_mac_addr); ixgb_init_rx_addrs()
406 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr); ixgb_init_rx_addrs()
408 ixgb_rar_set(hw, hw->curr_mac_addr, 0); ixgb_init_rx_addrs()
415 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); ixgb_init_rx_addrs()
416 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); ixgb_init_rx_addrs()
423 * hw - Struct containing variables accessed by shared code
434 ixgb_mc_addr_list_update(struct ixgb_hw *hw, ixgb_mc_addr_list_update() argument
447 hw->num_mc_addrs = mc_addr_count; ixgb_mc_addr_list_update()
452 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); ixgb_mc_addr_list_update()
453 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); ixgb_mc_addr_list_update()
459 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); ixgb_mc_addr_list_update()
471 ixgb_rar_set(hw, mca, rar_used_count); ixgb_mc_addr_list_update()
475 hash_value = ixgb_hash_mc_addr(hw, mca); ixgb_mc_addr_list_update()
479 ixgb_mta_set(hw, hash_value); ixgb_mc_addr_list_update()
491 * hw - Struct containing variables accessed by shared code
498 ixgb_hash_mc_addr(struct ixgb_hw *hw, ixgb_hash_mc_addr() argument
508 switch (hw->mc_filter_type) { ixgb_hash_mc_addr()
542 * hw - Struct containing variables accessed by shared code
546 ixgb_mta_set(struct ixgb_hw *hw, ixgb_mta_set() argument
563 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); ixgb_mta_set()
567 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); ixgb_mta_set()
573 * hw - Struct containing variables accessed by shared code
578 ixgb_rar_set(struct ixgb_hw *hw, ixgb_rar_set() argument
598 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); ixgb_rar_set()
599 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); ixgb_rar_set()
605 * hw - Struct containing variables accessed by shared code
610 ixgb_write_vfta(struct ixgb_hw *hw, ixgb_write_vfta() argument
614 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); ixgb_write_vfta()
620 * hw - Struct containing variables accessed by shared code
623 ixgb_clear_vfta(struct ixgb_hw *hw) ixgb_clear_vfta() argument
628 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); ixgb_clear_vfta()
634 * hw - Struct containing variables accessed by shared code
638 ixgb_setup_fc(struct ixgb_hw *hw) ixgb_setup_fc() argument
647 ctrl_reg = IXGB_READ_REG(hw, CTRL0); ixgb_setup_fc()
661 switch (hw->fc.type) { ixgb_setup_fc()
677 pap_reg = hw->fc.pause_time; ixgb_setup_fc()
684 pap_reg = hw->fc.pause_time; ixgb_setup_fc()
694 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); ixgb_setup_fc()
697 IXGB_WRITE_REG(hw, PAP, pap_reg); ixgb_setup_fc()
705 if (!(hw->fc.type & ixgb_fc_tx_pause)) { ixgb_setup_fc()
706 IXGB_WRITE_REG(hw, FCRTL, 0); ixgb_setup_fc()
707 IXGB_WRITE_REG(hw, FCRTH, 0); ixgb_setup_fc()
712 if (hw->fc.send_xon) { ixgb_setup_fc()
713 IXGB_WRITE_REG(hw, FCRTL, ixgb_setup_fc()
714 (hw->fc.low_water | IXGB_FCRTL_XONE)); ixgb_setup_fc()
716 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); ixgb_setup_fc()
718 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); ixgb_setup_fc()
727 * hw - Struct containing variables accessed by hw code
739 ixgb_read_phy_reg(struct ixgb_hw *hw, ixgb_read_phy_reg() argument
758 IXGB_WRITE_REG(hw, MSCA, command); ixgb_read_phy_reg()
771 command = IXGB_READ_REG(hw, MSCA); ixgb_read_phy_reg()
785 IXGB_WRITE_REG(hw, MSCA, command); ixgb_read_phy_reg()
798 command = IXGB_READ_REG(hw, MSCA); ixgb_read_phy_reg()
809 data = IXGB_READ_REG(hw, MSRWD); ixgb_read_phy_reg()
818 * hw - Struct containing variables accessed by hw code
832 ixgb_write_phy_reg(struct ixgb_hw *hw, ixgb_write_phy_reg() argument
846 IXGB_WRITE_REG(hw, MSRWD, (u32)data); ixgb_write_phy_reg()
854 IXGB_WRITE_REG(hw, MSCA, command); ixgb_write_phy_reg()
867 command = IXGB_READ_REG(hw, MSCA); ixgb_write_phy_reg()
881 IXGB_WRITE_REG(hw, MSCA, command); ixgb_write_phy_reg()
894 command = IXGB_READ_REG(hw, MSCA); ixgb_write_phy_reg()
908 * hw - Struct containing variables accessed by hw code
913 ixgb_check_for_link(struct ixgb_hw *hw) ixgb_check_for_link() argument
920 xpcss_reg = IXGB_READ_REG(hw, XPCSS); ixgb_check_for_link()
921 status_reg = IXGB_READ_REG(hw, STATUS); ixgb_check_for_link()
925 hw->link_up = true; ixgb_check_for_link()
929 hw->link_up = ixgb_link_reset(hw); ixgb_check_for_link()
935 hw->link_up = ixgb_link_reset(hw); ixgb_check_for_link()
945 * hw - Struct containing variables accessed by hw code
949 bool ixgb_check_for_bad_link(struct ixgb_hw *hw) ixgb_check_for_bad_link() argument
954 if (hw->phy_type == ixgb_phy_type_txn17401) { ixgb_check_for_bad_link()
955 newLFC = IXGB_READ_REG(hw, LFC); ixgb_check_for_bad_link()
956 newRFC = IXGB_READ_REG(hw, RFC); ixgb_check_for_bad_link()
957 if ((hw->lastLFC + 250 < newLFC) ixgb_check_for_bad_link()
958 || (hw->lastRFC + 250 < newRFC)) { ixgb_check_for_bad_link()
962 hw->lastLFC = newLFC; ixgb_check_for_bad_link()
963 hw->lastRFC = newRFC; ixgb_check_for_bad_link()
972 * hw - Struct containing variables accessed by shared code
975 ixgb_clear_hw_cntrs(struct ixgb_hw *hw) ixgb_clear_hw_cntrs() argument
982 if (hw->adapter_stopped) { ixgb_clear_hw_cntrs()
987 temp_reg = IXGB_READ_REG(hw, TPRL); ixgb_clear_hw_cntrs()
988 temp_reg = IXGB_READ_REG(hw, TPRH); ixgb_clear_hw_cntrs()
989 temp_reg = IXGB_READ_REG(hw, GPRCL); ixgb_clear_hw_cntrs()
990 temp_reg = IXGB_READ_REG(hw, GPRCH); ixgb_clear_hw_cntrs()
991 temp_reg = IXGB_READ_REG(hw, BPRCL); ixgb_clear_hw_cntrs()
992 temp_reg = IXGB_READ_REG(hw, BPRCH); ixgb_clear_hw_cntrs()
993 temp_reg = IXGB_READ_REG(hw, MPRCL); ixgb_clear_hw_cntrs()
994 temp_reg = IXGB_READ_REG(hw, MPRCH); ixgb_clear_hw_cntrs()
995 temp_reg = IXGB_READ_REG(hw, UPRCL); ixgb_clear_hw_cntrs()
996 temp_reg = IXGB_READ_REG(hw, UPRCH); ixgb_clear_hw_cntrs()
997 temp_reg = IXGB_READ_REG(hw, VPRCL); ixgb_clear_hw_cntrs()
998 temp_reg = IXGB_READ_REG(hw, VPRCH); ixgb_clear_hw_cntrs()
999 temp_reg = IXGB_READ_REG(hw, JPRCL); ixgb_clear_hw_cntrs()
1000 temp_reg = IXGB_READ_REG(hw, JPRCH); ixgb_clear_hw_cntrs()
1001 temp_reg = IXGB_READ_REG(hw, GORCL); ixgb_clear_hw_cntrs()
1002 temp_reg = IXGB_READ_REG(hw, GORCH); ixgb_clear_hw_cntrs()
1003 temp_reg = IXGB_READ_REG(hw, TORL); ixgb_clear_hw_cntrs()
1004 temp_reg = IXGB_READ_REG(hw, TORH); ixgb_clear_hw_cntrs()
1005 temp_reg = IXGB_READ_REG(hw, RNBC); ixgb_clear_hw_cntrs()
1006 temp_reg = IXGB_READ_REG(hw, RUC); ixgb_clear_hw_cntrs()
1007 temp_reg = IXGB_READ_REG(hw, ROC); ixgb_clear_hw_cntrs()
1008 temp_reg = IXGB_READ_REG(hw, RLEC); ixgb_clear_hw_cntrs()
1009 temp_reg = IXGB_READ_REG(hw, CRCERRS); ixgb_clear_hw_cntrs()
1010 temp_reg = IXGB_READ_REG(hw, ICBC); ixgb_clear_hw_cntrs()
1011 temp_reg = IXGB_READ_REG(hw, ECBC); ixgb_clear_hw_cntrs()
1012 temp_reg = IXGB_READ_REG(hw, MPC); ixgb_clear_hw_cntrs()
1013 temp_reg = IXGB_READ_REG(hw, TPTL); ixgb_clear_hw_cntrs()
1014 temp_reg = IXGB_READ_REG(hw, TPTH); ixgb_clear_hw_cntrs()
1015 temp_reg = IXGB_READ_REG(hw, GPTCL); ixgb_clear_hw_cntrs()
1016 temp_reg = IXGB_READ_REG(hw, GPTCH); ixgb_clear_hw_cntrs()
1017 temp_reg = IXGB_READ_REG(hw, BPTCL); ixgb_clear_hw_cntrs()
1018 temp_reg = IXGB_READ_REG(hw, BPTCH); ixgb_clear_hw_cntrs()
1019 temp_reg = IXGB_READ_REG(hw, MPTCL); ixgb_clear_hw_cntrs()
1020 temp_reg = IXGB_READ_REG(hw, MPTCH); ixgb_clear_hw_cntrs()
1021 temp_reg = IXGB_READ_REG(hw, UPTCL); ixgb_clear_hw_cntrs()
1022 temp_reg = IXGB_READ_REG(hw, UPTCH); ixgb_clear_hw_cntrs()
1023 temp_reg = IXGB_READ_REG(hw, VPTCL); ixgb_clear_hw_cntrs()
1024 temp_reg = IXGB_READ_REG(hw, VPTCH); ixgb_clear_hw_cntrs()
1025 temp_reg = IXGB_READ_REG(hw, JPTCL); ixgb_clear_hw_cntrs()
1026 temp_reg = IXGB_READ_REG(hw, JPTCH); ixgb_clear_hw_cntrs()
1027 temp_reg = IXGB_READ_REG(hw, GOTCL); ixgb_clear_hw_cntrs()
1028 temp_reg = IXGB_READ_REG(hw, GOTCH); ixgb_clear_hw_cntrs()
1029 temp_reg = IXGB_READ_REG(hw, TOTL); ixgb_clear_hw_cntrs()
1030 temp_reg = IXGB_READ_REG(hw, TOTH); ixgb_clear_hw_cntrs()
1031 temp_reg = IXGB_READ_REG(hw, DC); ixgb_clear_hw_cntrs()
1032 temp_reg = IXGB_READ_REG(hw, PLT64C); ixgb_clear_hw_cntrs()
1033 temp_reg = IXGB_READ_REG(hw, TSCTC); ixgb_clear_hw_cntrs()
1034 temp_reg = IXGB_READ_REG(hw, TSCTFC); ixgb_clear_hw_cntrs()
1035 temp_reg = IXGB_READ_REG(hw, IBIC); ixgb_clear_hw_cntrs()
1036 temp_reg = IXGB_READ_REG(hw, RFC); ixgb_clear_hw_cntrs()
1037 temp_reg = IXGB_READ_REG(hw, LFC); ixgb_clear_hw_cntrs()
1038 temp_reg = IXGB_READ_REG(hw, PFRC); ixgb_clear_hw_cntrs()
1039 temp_reg = IXGB_READ_REG(hw, PFTC); ixgb_clear_hw_cntrs()
1040 temp_reg = IXGB_READ_REG(hw, MCFRC); ixgb_clear_hw_cntrs()
1041 temp_reg = IXGB_READ_REG(hw, MCFTC); ixgb_clear_hw_cntrs()
1042 temp_reg = IXGB_READ_REG(hw, XONRXC); ixgb_clear_hw_cntrs()
1043 temp_reg = IXGB_READ_REG(hw, XONTXC); ixgb_clear_hw_cntrs()
1044 temp_reg = IXGB_READ_REG(hw, XOFFRXC); ixgb_clear_hw_cntrs()
1045 temp_reg = IXGB_READ_REG(hw, XOFFTXC); ixgb_clear_hw_cntrs()
1046 temp_reg = IXGB_READ_REG(hw, RJC); ixgb_clear_hw_cntrs()
1052 * hw - Struct containing variables accessed by shared code
1055 ixgb_led_on(struct ixgb_hw *hw) ixgb_led_on() argument
1057 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0); ixgb_led_on()
1061 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); ixgb_led_on()
1067 * hw - Struct containing variables accessed by shared code
1070 ixgb_led_off(struct ixgb_hw *hw) ixgb_led_off() argument
1072 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0); ixgb_led_off()
1076 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); ixgb_led_off()
1082 * hw - Struct containing variables accessed by shared code
1085 ixgb_get_bus_info(struct ixgb_hw *hw) ixgb_get_bus_info() argument
1089 status_reg = IXGB_READ_REG(hw, STATUS); ixgb_get_bus_info()
1091 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_get_bus_info()
1094 if (hw->bus.type == ixgb_bus_type_pci) { ixgb_get_bus_info()
1095 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_get_bus_info()
1100 hw->bus.speed = ixgb_bus_speed_66; ixgb_get_bus_info()
1103 hw->bus.speed = ixgb_bus_speed_100; ixgb_get_bus_info()
1106 hw->bus.speed = ixgb_bus_speed_133; ixgb_get_bus_info()
1109 hw->bus.speed = ixgb_bus_speed_reserved; ixgb_get_bus_info()
1114 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? ixgb_get_bus_info()
1152 * hw - Struct containing variables accessed by shared code
1155 ixgb_link_reset(struct ixgb_hw *hw) ixgb_link_reset() argument
1163 IXGB_WRITE_REG(hw, CTRL0, ixgb_link_reset()
1164 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); ixgb_link_reset()
1170 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) ixgb_link_reset()
1171 && (IXGB_READ_REG(hw, XPCSS) & ixgb_link_reset()
1183 * hw - Struct containing variables accessed by shared code
1186 ixgb_optics_reset(struct ixgb_hw *hw) ixgb_optics_reset() argument
1188 if (hw->phy_type == ixgb_phy_type_txn17401) { ixgb_optics_reset()
1191 ixgb_write_phy_reg(hw, ixgb_optics_reset()
1197 mdio_reg = ixgb_read_phy_reg(hw, ixgb_optics_reset()
1207 * hw - Struct containing variables accessed by shared code
1219 ixgb_optics_reset_bcm(struct ixgb_hw *hw) ixgb_optics_reset_bcm() argument
1221 u32 ctrl = IXGB_READ_REG(hw, CTRL0); ixgb_optics_reset_bcm()
1224 IXGB_WRITE_REG(hw, CTRL0, ctrl); ixgb_optics_reset_bcm()
1225 IXGB_WRITE_FLUSH(hw); ixgb_optics_reset_bcm()
1232 ixgb_write_phy_reg(hw, ixgb_optics_reset_bcm()
1238 ixgb_read_phy_reg(hw, ixgb_optics_reset_bcm()
1242 ixgb_read_phy_reg(hw, ixgb_optics_reset_bcm()
1247 ixgb_write_phy_reg(hw, ixgb_optics_reset_bcm()
1252 ixgb_read_phy_reg(hw, ixgb_optics_reset_bcm()
1256 ixgb_read_phy_reg(hw, ixgb_optics_reset_bcm()
H A Dixgb_ee.c34 static u16 ixgb_shift_in_bits(struct ixgb_hw *hw);
36 static void ixgb_shift_out_bits(struct ixgb_hw *hw,
39 static void ixgb_standby_eeprom(struct ixgb_hw *hw);
41 static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw);
43 static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
48 * hw - Struct containing variables accessed by shared code
52 ixgb_raise_clock(struct ixgb_hw *hw, ixgb_raise_clock() argument
59 IXGB_WRITE_REG(hw, EECD, *eecd_reg); ixgb_raise_clock()
60 IXGB_WRITE_FLUSH(hw); ixgb_raise_clock()
67 * hw - Struct containing variables accessed by shared code
71 ixgb_lower_clock(struct ixgb_hw *hw, ixgb_lower_clock() argument
78 IXGB_WRITE_REG(hw, EECD, *eecd_reg); ixgb_lower_clock()
79 IXGB_WRITE_FLUSH(hw); ixgb_lower_clock()
86 * hw - Struct containing variables accessed by shared code
91 ixgb_shift_out_bits(struct ixgb_hw *hw, ixgb_shift_out_bits() argument
103 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_shift_out_bits()
116 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_shift_out_bits()
117 IXGB_WRITE_FLUSH(hw); ixgb_shift_out_bits()
121 ixgb_raise_clock(hw, &eecd_reg); ixgb_shift_out_bits()
122 ixgb_lower_clock(hw, &eecd_reg); ixgb_shift_out_bits()
130 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_shift_out_bits()
136 * hw - Struct containing variables accessed by shared code
139 ixgb_shift_in_bits(struct ixgb_hw *hw) ixgb_shift_in_bits() argument
152 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_shift_in_bits()
159 ixgb_raise_clock(hw, &eecd_reg); ixgb_shift_in_bits()
161 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_shift_in_bits()
167 ixgb_lower_clock(hw, &eecd_reg); ixgb_shift_in_bits()
176 * hw - Struct containing variables accessed by shared code
182 ixgb_setup_eeprom(struct ixgb_hw *hw) ixgb_setup_eeprom() argument
186 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_setup_eeprom()
190 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_setup_eeprom()
194 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_setup_eeprom()
200 * hw - Struct containing variables accessed by shared code
203 ixgb_standby_eeprom(struct ixgb_hw *hw) ixgb_standby_eeprom() argument
207 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_standby_eeprom()
211 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_standby_eeprom()
212 IXGB_WRITE_FLUSH(hw); ixgb_standby_eeprom()
217 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_standby_eeprom()
218 IXGB_WRITE_FLUSH(hw); ixgb_standby_eeprom()
223 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_standby_eeprom()
224 IXGB_WRITE_FLUSH(hw); ixgb_standby_eeprom()
229 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_standby_eeprom()
230 IXGB_WRITE_FLUSH(hw); ixgb_standby_eeprom()
237 * hw - Struct containing variables accessed by shared code
240 ixgb_clock_eeprom(struct ixgb_hw *hw) ixgb_clock_eeprom() argument
244 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_clock_eeprom()
248 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_clock_eeprom()
249 IXGB_WRITE_FLUSH(hw); ixgb_clock_eeprom()
254 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_clock_eeprom()
255 IXGB_WRITE_FLUSH(hw); ixgb_clock_eeprom()
262 * hw - Struct containing variables accessed by shared code
265 ixgb_cleanup_eeprom(struct ixgb_hw *hw) ixgb_cleanup_eeprom() argument
269 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_cleanup_eeprom()
273 IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_cleanup_eeprom()
275 ixgb_clock_eeprom(hw); ixgb_cleanup_eeprom()
281 * hw - Struct containing variables accessed by shared code
290 ixgb_wait_eeprom_command(struct ixgb_hw *hw) ixgb_wait_eeprom_command() argument
298 ixgb_standby_eeprom(hw); ixgb_wait_eeprom_command()
305 eecd_reg = IXGB_READ_REG(hw, EECD); ixgb_wait_eeprom_command()
319 * hw - Struct containing variables accessed by shared code
330 ixgb_validate_eeprom_checksum(struct ixgb_hw *hw) ixgb_validate_eeprom_checksum() argument
336 checksum += ixgb_read_eeprom(hw, i); ixgb_validate_eeprom_checksum()
347 * hw - Struct containing variables accessed by shared code
353 ixgb_update_eeprom_checksum(struct ixgb_hw *hw) ixgb_update_eeprom_checksum() argument
359 checksum += ixgb_read_eeprom(hw, i); ixgb_update_eeprom_checksum()
363 ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum); ixgb_update_eeprom_checksum()
369 * hw - Struct containing variables accessed by shared code
378 ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data) ixgb_write_eeprom() argument
380 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; ixgb_write_eeprom()
383 ixgb_setup_eeprom(hw); ixgb_write_eeprom()
388 ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5); ixgb_write_eeprom()
389 ixgb_shift_out_bits(hw, 0, 4); ixgb_write_eeprom()
392 ixgb_standby_eeprom(hw); ixgb_write_eeprom()
395 ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3); ixgb_write_eeprom()
396 ixgb_shift_out_bits(hw, offset, 6); ixgb_write_eeprom()
399 ixgb_shift_out_bits(hw, data, 16); ixgb_write_eeprom()
401 ixgb_wait_eeprom_command(hw); ixgb_write_eeprom()
404 ixgb_standby_eeprom(hw); ixgb_write_eeprom()
410 ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5); ixgb_write_eeprom()
411 ixgb_shift_out_bits(hw, 0, 4); ixgb_write_eeprom()
414 ixgb_cleanup_eeprom(hw); ixgb_write_eeprom()
423 * hw - Struct containing variables accessed by shared code
430 ixgb_read_eeprom(struct ixgb_hw *hw, ixgb_read_eeprom() argument
436 ixgb_setup_eeprom(hw); ixgb_read_eeprom()
439 ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3); ixgb_read_eeprom()
443 ixgb_shift_out_bits(hw, offset, 6); ixgb_read_eeprom()
446 data = ixgb_shift_in_bits(hw); ixgb_read_eeprom()
449 ixgb_standby_eeprom(hw); ixgb_read_eeprom()
458 * hw - Struct containing variables accessed by shared code
465 ixgb_get_eeprom_data(struct ixgb_hw *hw) ixgb_get_eeprom_data() argument
473 ee_map = (struct ixgb_ee_map_type *)hw->eeprom; ixgb_get_eeprom_data()
478 ee_data = ixgb_read_eeprom(hw, i); ixgb_get_eeprom_data()
480 hw->eeprom[i] = cpu_to_le16(ee_data); ixgb_get_eeprom_data()
504 * hw - Struct containing variables accessed by shared code
511 ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw) ixgb_check_and_get_eeprom_data() argument
513 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; ixgb_check_and_get_eeprom_data()
519 return ixgb_get_eeprom_data(hw); ixgb_check_and_get_eeprom_data()
526 * hw - Struct containing variables accessed by shared code
533 ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index) ixgb_get_eeprom_word() argument
536 if (index < IXGB_EEPROM_SIZE && ixgb_check_and_get_eeprom_data(hw)) ixgb_get_eeprom_word()
537 return hw->eeprom[index]; ixgb_get_eeprom_word()
545 * hw - Struct containing variables accessed by shared code
551 ixgb_get_ee_mac_addr(struct ixgb_hw *hw, ixgb_get_ee_mac_addr() argument
555 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; ixgb_get_ee_mac_addr()
559 if (ixgb_check_and_get_eeprom_data(hw)) { ixgb_get_ee_mac_addr()
571 * hw - Struct containing variables accessed by shared code
577 ixgb_get_ee_pba_number(struct ixgb_hw *hw) ixgb_get_ee_pba_number() argument
579 if (ixgb_check_and_get_eeprom_data(hw)) ixgb_get_ee_pba_number()
580 return le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG]) ixgb_get_ee_pba_number()
581 | (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16); ixgb_get_ee_pba_number()
590 * hw - Struct containing variables accessed by shared code
596 ixgb_get_ee_device_id(struct ixgb_hw *hw) ixgb_get_ee_device_id() argument
598 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; ixgb_get_ee_device_id()
600 if (ixgb_check_and_get_eeprom_data(hw)) ixgb_get_ee_device_id()
/linux-4.4.14/drivers/net/ieee802154/
H A Dfakelb.c39 struct ieee802154_hw *hw; member in struct:fakelb_phy
50 static int fakelb_hw_ed(struct ieee802154_hw *hw, u8 *level) fakelb_hw_ed() argument
58 static int fakelb_hw_channel(struct ieee802154_hw *hw, u8 page, u8 channel) fakelb_hw_channel() argument
60 struct fakelb_phy *phy = hw->priv; fakelb_hw_channel()
69 static int fakelb_hw_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) fakelb_hw_xmit() argument
71 struct fakelb_phy *current_phy = hw->priv, *phy; fakelb_hw_xmit()
84 ieee802154_rx_irqsafe(phy->hw, newskb, 0xcc); fakelb_hw_xmit()
89 ieee802154_xmit_complete(hw, skb, false); fakelb_hw_xmit()
93 static int fakelb_hw_start(struct ieee802154_hw *hw) fakelb_hw_start() argument
95 struct fakelb_phy *phy = hw->priv; fakelb_hw_start()
105 static void fakelb_hw_stop(struct ieee802154_hw *hw) fakelb_hw_stop() argument
107 struct fakelb_phy *phy = hw->priv; fakelb_hw_stop()
130 struct ieee802154_hw *hw; fakelb_add_one() local
134 hw = ieee802154_alloc_hw(sizeof(*phy), &fakelb_ops); fakelb_add_one()
135 if (!hw) fakelb_add_one()
138 phy = hw->priv; fakelb_add_one()
139 phy->hw = hw; fakelb_add_one()
142 hw->phy->supported.channels[0] |= 1; fakelb_add_one()
144 hw->phy->supported.channels[0] |= 0x7fe; fakelb_add_one()
146 hw->phy->supported.channels[0] |= 0x7FFF800; fakelb_add_one()
148 hw->phy->supported.channels[1] |= 1; fakelb_add_one()
150 hw->phy->supported.channels[1] |= 0x7fe; fakelb_add_one()
152 hw->phy->supported.channels[2] |= 1; fakelb_add_one()
154 hw->phy->supported.channels[2] |= 0x7fe; fakelb_add_one()
156 hw->phy->supported.channels[3] |= 0x3fff; fakelb_add_one()
158 hw->phy->supported.channels[4] |= 1; fakelb_add_one()
160 hw->phy->supported.channels[4] |= 0x1e; fakelb_add_one()
162 hw->phy->supported.channels[4] |= 0xffe0; fakelb_add_one()
164 hw->phy->supported.channels[5] |= 0xf; fakelb_add_one()
166 hw->phy->supported.channels[5] |= 0xf0; fakelb_add_one()
168 hw->phy->supported.channels[6] |= 0x3ff; fakelb_add_one()
170 hw->phy->supported.channels[6] |= 0x3ffc00; fakelb_add_one()
172 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); fakelb_add_one()
174 hw->phy->current_channel = 13; fakelb_add_one()
175 phy->channel = hw->phy->current_channel; fakelb_add_one()
177 hw->parent = dev; fakelb_add_one()
179 err = ieee802154_register_hw(hw); fakelb_add_one()
190 ieee802154_free_hw(phy->hw); fakelb_add_one()
198 ieee802154_unregister_hw(phy->hw); fakelb_del()
199 ieee802154_free_hw(phy->hw); fakelb_del()
/linux-4.4.14/drivers/media/platform/sti/bdisp/
H A DMakefile3 bdisp-objs := bdisp-v4l2.o bdisp-hw.o bdisp-debug.o
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A DMakefile3 hw.o \
H A Dhw.h88 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw);
89 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw);
90 int rtl92cu_hw_init(struct ieee80211_hw *hw);
91 void rtl92cu_card_disable(struct ieee80211_hw *hw);
92 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
93 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw);
94 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw);
95 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
97 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
98 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
100 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
101 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
102 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
103 int rtl92c_download_fw(struct ieee80211_hw *hw);
104 void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
105 void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
106 void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
108 bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw);
109 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
H A Dled.c33 static void _rtl92cu_init_led(struct ieee80211_hw *hw, _rtl92cu_init_led() argument
36 pled->hw = hw; _rtl92cu_init_led()
45 void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92cu_sw_led_on() argument
48 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_sw_led_on()
71 void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) rtl92cu_sw_led_off() argument
73 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_sw_led_off()
74 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw); rtl92cu_sw_led_off()
104 void rtl92cu_init_sw_leds(struct ieee80211_hw *hw) rtl92cu_init_sw_leds() argument
106 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw); rtl92cu_init_sw_leds()
107 _rtl92cu_init_led(hw, &(usbpriv->ledctl.sw_led0), LED_PIN_LED0); rtl92cu_init_sw_leds()
108 _rtl92cu_init_led(hw, &(usbpriv->ledctl.sw_led1), LED_PIN_LED1); rtl92cu_init_sw_leds()
111 void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw) rtl92cu_deinit_sw_leds() argument
113 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw); rtl92cu_deinit_sw_leds()
118 static void _rtl92cu_sw_led_control(struct ieee80211_hw *hw, _rtl92cu_sw_led_control() argument
123 void rtl92cu_led_control(struct ieee80211_hw *hw, rtl92cu_led_control() argument
126 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_led_control()
127 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92cu_led_control()
140 _rtl92cu_sw_led_control(hw, ledaction); rtl92cu_led_control()
H A Dphy.c44 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw, rtl92cu_phy_query_rf_reg() argument
47 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_phy_query_rf_reg()
55 original_value = _rtl92c_phy_rf_serial_read(hw, rtl92cu_phy_query_rf_reg()
58 original_value = _rtl92c_phy_fw_rf_serial_read(hw, rtl92cu_phy_query_rf_reg()
69 void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw, rtl92cu_phy_set_rf_reg() argument
73 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_phy_set_rf_reg()
82 original_value = _rtl92c_phy_rf_serial_read(hw, rtl92cu_phy_set_rf_reg()
90 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data); rtl92cu_phy_set_rf_reg()
93 original_value = _rtl92c_phy_fw_rf_serial_read(hw, rtl92cu_phy_set_rf_reg()
101 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data); rtl92cu_phy_set_rf_reg()
108 bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw) rtl92cu_phy_mac_config() argument
112 rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw); rtl92cu_phy_mac_config()
116 bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw) rtl92cu_phy_bb_config() argument
119 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_phy_bb_config()
124 _rtl92c_phy_init_bb_rf_register_definition(hw); rtl92cu_phy_bb_config()
138 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw); rtl92cu_phy_bb_config()
142 bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) _rtl92cu_phy_config_mac_with_headerfile() argument
144 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92cu_phy_config_mac_with_headerfile()
159 bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, _rtl92cu_phy_config_bb_with_headerfile() argument
166 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92cu_phy_config_bb_with_headerfile()
167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92cu_phy_config_bb_with_headerfile()
184 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl92cu_phy_config_bb_with_headerfile()
194 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, _rtl92cu_phy_config_bb_with_headerfile()
206 bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, _rtl92cu_phy_config_bb_with_pgheaderfile() argument
209 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92cu_phy_config_bb_with_pgheaderfile()
221 _rtl92c_store_pwrIndex_diffrate_offset(hw, _rtl92cu_phy_config_bb_with_pgheaderfile()
233 bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, rtl92cu_phy_config_rf_with_headerfile() argument
240 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_phy_config_rf_with_headerfile()
241 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92cu_phy_config_rf_with_headerfile()
267 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], rtl92cu_phy_config_rf_with_headerfile()
274 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], rtl92cu_phy_config_rf_with_headerfile()
293 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw) rtl92cu_phy_set_bw_mode_callback() argument
295 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_phy_set_bw_mode_callback()
296 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92cu_phy_set_bw_mode_callback()
298 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92cu_phy_set_bw_mode_callback()
330 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); rtl92cu_phy_set_bw_mode_callback()
331 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); rtl92cu_phy_set_bw_mode_callback()
332 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); rtl92cu_phy_set_bw_mode_callback()
335 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); rtl92cu_phy_set_bw_mode_callback()
336 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); rtl92cu_phy_set_bw_mode_callback()
337 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, rtl92cu_phy_set_bw_mode_callback()
339 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); rtl92cu_phy_set_bw_mode_callback()
340 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); rtl92cu_phy_set_bw_mode_callback()
341 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), rtl92cu_phy_set_bw_mode_callback()
350 rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); rtl92cu_phy_set_bw_mode_callback()
355 void rtl92cu_bb_block_on(struct ieee80211_hw *hw) rtl92cu_bb_block_on() argument
357 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92cu_bb_block_on()
360 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); rtl92cu_bb_block_on()
361 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); rtl92cu_bb_block_on()
365 void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) _rtl92cu_phy_lc_calibrate() argument
369 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92cu_phy_lc_calibrate()
379 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); _rtl92cu_phy_lc_calibrate()
381 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, _rtl92cu_phy_lc_calibrate()
383 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, _rtl92cu_phy_lc_calibrate()
386 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl92cu_phy_lc_calibrate()
389 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); _rtl92cu_phy_lc_calibrate()
390 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); _rtl92cu_phy_lc_calibrate()
394 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); _rtl92cu_phy_lc_calibrate()
396 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, _rtl92cu_phy_lc_calibrate()
403 static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw, _rtl92cu_phy_set_rf_power_state() argument
406 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92cu_phy_set_rf_power_state()
407 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl92cu_phy_set_rf_power_state()
408 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl92cu_phy_set_rf_power_state()
409 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl92cu_phy_set_rf_power_state()
425 rtstatus = rtl_ps_enable_nic(hw); _rtl92cu_phy_set_rf_power_state()
435 rtl92ce_phy_set_rf_on(hw); _rtl92cu_phy_set_rf_power_state()
438 rtlpriv->cfg->ops->led_control(hw, _rtl92cu_phy_set_rf_power_state()
441 rtlpriv->cfg->ops->led_control(hw, _rtl92cu_phy_set_rf_power_state()
474 rtl_ps_disable_nic(hw); _rtl92cu_phy_set_rf_power_state()
478 rtlpriv->cfg->ops->led_control(hw, _rtl92cu_phy_set_rf_power_state()
481 rtlpriv->cfg->ops->led_control(hw, _rtl92cu_phy_set_rf_power_state()
516 _rtl92c_phy_set_rf_sleep(hw); _rtl92cu_phy_set_rf_power_state()
529 bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw, rtl92cu_phy_set_rf_power_state() argument
532 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92cu_phy_set_rf_power_state()
537 bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state); rtl92cu_phy_set_rf_power_state()
/linux-4.4.14/drivers/net/ethernet/intel/igb/
H A De1000_mac.h37 s32 igb_blink_led(struct e1000_hw *hw);
38 s32 igb_check_for_copper_link(struct e1000_hw *hw);
39 s32 igb_cleanup_led(struct e1000_hw *hw);
40 s32 igb_config_fc_after_link_up(struct e1000_hw *hw);
41 s32 igb_disable_pcie_master(struct e1000_hw *hw);
42 s32 igb_force_mac_fc(struct e1000_hw *hw);
43 s32 igb_get_auto_rd_done(struct e1000_hw *hw);
44 s32 igb_get_bus_info_pcie(struct e1000_hw *hw);
45 s32 igb_get_hw_semaphore(struct e1000_hw *hw);
46 s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
48 s32 igb_id_led_init(struct e1000_hw *hw);
49 s32 igb_led_off(struct e1000_hw *hw);
50 void igb_update_mc_addr_list(struct e1000_hw *hw,
52 s32 igb_setup_link(struct e1000_hw *hw);
53 s32 igb_validate_mdi_setting(struct e1000_hw *hw);
54 s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
57 void igb_clear_hw_cntrs_base(struct e1000_hw *hw);
58 void igb_clear_vfta(struct e1000_hw *hw);
59 void igb_clear_vfta_i350(struct e1000_hw *hw);
60 s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add);
61 void igb_config_collision_dist(struct e1000_hw *hw);
62 void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
63 void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
64 void igb_put_hw_semaphore(struct e1000_hw *hw);
65 void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
66 s32 igb_check_alt_mac_addr(struct e1000_hw *hw);
68 bool igb_enable_mng_pass_thru(struct e1000_hw *hw);
85 void e1000_init_function_pointers_82575(struct e1000_hw *hw);
H A De1000_phy.h40 s32 igb_check_downshift(struct e1000_hw *hw);
41 s32 igb_check_reset_block(struct e1000_hw *hw);
42 s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
43 s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
44 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
45 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
46 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
47 s32 igb_get_cable_length_m88(struct e1000_hw *hw);
48 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
49 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
50 s32 igb_get_phy_id(struct e1000_hw *hw);
51 s32 igb_get_phy_info_igp(struct e1000_hw *hw);
52 s32 igb_get_phy_info_m88(struct e1000_hw *hw);
53 s32 igb_phy_sw_reset(struct e1000_hw *hw);
54 s32 igb_phy_hw_reset(struct e1000_hw *hw);
55 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
56 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
57 s32 igb_setup_copper_link(struct e1000_hw *hw);
58 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
59 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
61 void igb_power_up_phy_copper(struct e1000_hw *hw);
62 void igb_power_down_phy_copper(struct e1000_hw *hw);
63 s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
64 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
65 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
66 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
67 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
68 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
69 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
70 s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
71 s32 igb_get_phy_info_82580(struct e1000_hw *hw);
72 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
73 s32 igb_get_cable_length_82580(struct e1000_hw *hw);
74 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
75 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
76 s32 igb_check_polarity_m88(struct e1000_hw *hw);
H A De1000_i210.c34 static s32 igb_update_flash_i210(struct e1000_hw *hw);
38 * @hw: pointer to the HW structure
42 static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw) igb_get_hw_semaphore_i210() argument
45 s32 timeout = hw->nvm.word_size + 1; igb_get_hw_semaphore_i210()
62 if (hw->dev_spec._82575.clear_semaphore_once) { igb_get_hw_semaphore_i210()
63 hw->dev_spec._82575.clear_semaphore_once = false; igb_get_hw_semaphore_i210()
64 igb_put_hw_semaphore(hw); igb_get_hw_semaphore_i210()
95 igb_put_hw_semaphore(hw); igb_get_hw_semaphore_i210()
105 * @hw: pointer to the HW structure
112 static s32 igb_acquire_nvm_i210(struct e1000_hw *hw) igb_acquire_nvm_i210() argument
114 return igb_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM); igb_acquire_nvm_i210()
119 * @hw: pointer to the HW structure
124 static void igb_release_nvm_i210(struct e1000_hw *hw) igb_release_nvm_i210() argument
126 igb_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM); igb_release_nvm_i210()
131 * @hw: pointer to the HW structure
137 s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) igb_acquire_swfw_sync_i210() argument
146 if (igb_get_hw_semaphore_i210(hw)) { igb_acquire_swfw_sync_i210()
156 igb_put_hw_semaphore(hw); igb_acquire_swfw_sync_i210()
170 igb_put_hw_semaphore(hw); igb_acquire_swfw_sync_i210()
177 * @hw: pointer to the HW structure
183 void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) igb_release_swfw_sync_i210() argument
187 while (igb_get_hw_semaphore_i210(hw)) igb_release_swfw_sync_i210()
194 igb_put_hw_semaphore(hw); igb_release_swfw_sync_i210()
199 * @hw: pointer to the HW structure
207 static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, igb_read_nvm_srrd_i210() argument
220 if (!(hw->nvm.ops.acquire(hw))) { igb_read_nvm_srrd_i210()
221 status = igb_read_nvm_eerd(hw, offset, count, igb_read_nvm_srrd_i210()
223 hw->nvm.ops.release(hw); igb_read_nvm_srrd_i210()
237 * @hw: pointer to the HW structure
247 static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, igb_write_nvm_srwr() argument
250 struct e1000_nvm_info *nvm = &hw->nvm; igb_write_nvm_srwr()
293 * @hw: pointer to the HW structure
307 static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, igb_write_nvm_srwr_i210() argument
320 if (!(hw->nvm.ops.acquire(hw))) { igb_write_nvm_srwr_i210()
321 status = igb_write_nvm_srwr(hw, offset, count, igb_write_nvm_srwr_i210()
323 hw->nvm.ops.release(hw); igb_write_nvm_srwr_i210()
337 * @hw: pointer to the HW structure
344 static s32 igb_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data) igb_read_invm_word_i210() argument
379 * @hw: pointer to the HW structure
385 static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset, igb_read_invm_i210() argument
393 ret_val = igb_read_invm_word_i210(hw, (u8)offset, &data[0]); igb_read_invm_i210()
394 ret_val |= igb_read_invm_word_i210(hw, (u8)offset+1, igb_read_invm_i210()
396 ret_val |= igb_read_invm_word_i210(hw, (u8)offset+2, igb_read_invm_i210()
402 ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); igb_read_invm_i210()
409 ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); igb_read_invm_i210()
416 ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); igb_read_invm_i210()
423 ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); igb_read_invm_i210()
430 ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); igb_read_invm_i210()
437 *data = hw->subsystem_device_id; igb_read_invm_i210()
440 *data = hw->subsystem_vendor_id; igb_read_invm_i210()
443 *data = hw->device_id; igb_read_invm_i210()
446 *data = hw->vendor_id; igb_read_invm_i210()
458 * @hw: pointer to the HW structure
463 s32 igb_read_invm_version(struct e1000_hw *hw, igb_read_invm_version() argument
552 * @hw: pointer to the HW structure
557 static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw) igb_validate_nvm_checksum_i210() argument
562 if (!(hw->nvm.ops.acquire(hw))) { igb_validate_nvm_checksum_i210()
568 read_op_ptr = hw->nvm.ops.read; igb_validate_nvm_checksum_i210()
569 hw->nvm.ops.read = igb_read_nvm_eerd; igb_validate_nvm_checksum_i210()
571 status = igb_validate_nvm_checksum(hw); igb_validate_nvm_checksum_i210()
574 hw->nvm.ops.read = read_op_ptr; igb_validate_nvm_checksum_i210()
576 hw->nvm.ops.release(hw); igb_validate_nvm_checksum_i210()
586 * @hw: pointer to the HW structure
592 static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw) igb_update_nvm_checksum_i210() argument
602 ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data); igb_update_nvm_checksum_i210()
608 if (!(hw->nvm.ops.acquire(hw))) { igb_update_nvm_checksum_i210()
609 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read igb_update_nvm_checksum_i210()
615 ret_val = igb_read_nvm_eerd(hw, i, 1, &nvm_data); igb_update_nvm_checksum_i210()
617 hw->nvm.ops.release(hw); igb_update_nvm_checksum_i210()
624 ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, igb_update_nvm_checksum_i210()
627 hw->nvm.ops.release(hw); igb_update_nvm_checksum_i210()
632 hw->nvm.ops.release(hw); igb_update_nvm_checksum_i210()
634 ret_val = igb_update_flash_i210(hw); igb_update_nvm_checksum_i210()
644 * @hw: pointer to the HW structure
647 static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw) igb_pool_flash_update_done_i210() argument
666 * @hw: pointer to the HW structure
669 bool igb_get_flash_presence_i210(struct e1000_hw *hw) igb_get_flash_presence_i210() argument
683 * @hw: pointer to the HW structure
686 static s32 igb_update_flash_i210(struct e1000_hw *hw) igb_update_flash_i210() argument
691 ret_val = igb_pool_flash_update_done_i210(hw); igb_update_flash_i210()
700 ret_val = igb_pool_flash_update_done_i210(hw); igb_update_flash_i210()
712 * @hw: pointer to the HW structure
718 s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data) igb_valid_led_default_i210() argument
722 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); igb_valid_led_default_i210()
729 switch (hw->phy.media_type) { igb_valid_led_default_i210()
745 * @hw: pointer to the HW structure
751 static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address, __igb_access_xmdio_reg() argument
756 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); __igb_access_xmdio_reg()
760 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); __igb_access_xmdio_reg()
764 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | __igb_access_xmdio_reg()
770 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data); __igb_access_xmdio_reg()
772 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); __igb_access_xmdio_reg()
777 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0); __igb_access_xmdio_reg()
786 * @hw: pointer to the HW structure
791 s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data) igb_read_xmdio_reg() argument
793 return __igb_access_xmdio_reg(hw, addr, dev_addr, data, true); igb_read_xmdio_reg()
798 * @hw: pointer to the HW structure
803 s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data) igb_write_xmdio_reg() argument
805 return __igb_access_xmdio_reg(hw, addr, dev_addr, &data, false); igb_write_xmdio_reg()
810 * @hw: pointer to the HW structure
812 s32 igb_init_nvm_params_i210(struct e1000_hw *hw) igb_init_nvm_params_i210() argument
815 struct e1000_nvm_info *nvm = &hw->nvm; igb_init_nvm_params_i210()
822 if (igb_get_flash_presence_i210(hw)) { igb_init_nvm_params_i210()
823 hw->nvm.type = e1000_nvm_flash_hw; igb_init_nvm_params_i210()
829 hw->nvm.type = e1000_nvm_invm; igb_init_nvm_params_i210()
840 * @hw: pointer to the HW structure
845 s32 igb_pll_workaround_i210(struct e1000_hw *hw) igb_pll_workaround_i210() argument
859 ret_val = igb_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD, igb_pll_workaround_i210()
866 igb_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE | igb_pll_workaround_i210()
887 igb_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); igb_pll_workaround_i210()
889 igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); igb_pll_workaround_i210()
892 igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word); igb_pll_workaround_i210()
H A De1000_nvm.h27 s32 igb_acquire_nvm(struct e1000_hw *hw);
28 void igb_release_nvm(struct e1000_hw *hw);
29 s32 igb_read_mac_addr(struct e1000_hw *hw);
30 s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
31 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num,
33 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
34 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
35 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
36 s32 igb_validate_nvm_checksum(struct e1000_hw *hw);
37 s32 igb_update_nvm_checksum(struct e1000_hw *hw);
54 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers);
H A De1000_nvm.c31 * @hw: pointer to the HW structure
36 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) igb_raise_eec_clk() argument
41 udelay(hw->nvm.delay_usec); igb_raise_eec_clk()
46 * @hw: pointer to the HW structure
51 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) igb_lower_eec_clk() argument
56 udelay(hw->nvm.delay_usec); igb_lower_eec_clk()
61 * @hw: pointer to the HW structure
69 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) igb_shift_out_eec_bits() argument
71 struct e1000_nvm_info *nvm = &hw->nvm; igb_shift_out_eec_bits()
90 igb_raise_eec_clk(hw, &eecd); igb_shift_out_eec_bits()
91 igb_lower_eec_clk(hw, &eecd); igb_shift_out_eec_bits()
102 * @hw: pointer to the HW structure
111 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) igb_shift_in_eec_bits() argument
124 igb_raise_eec_clk(hw, &eecd); igb_shift_in_eec_bits()
132 igb_lower_eec_clk(hw, &eecd); igb_shift_in_eec_bits()
140 * @hw: pointer to the HW structure
146 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) igb_poll_eerd_eewr_done() argument
171 * @hw: pointer to the HW structure
177 s32 igb_acquire_nvm(struct e1000_hw *hw) igb_acquire_nvm() argument
207 * @hw: pointer to the HW structure
211 static void igb_standby_nvm(struct e1000_hw *hw) igb_standby_nvm() argument
213 struct e1000_nvm_info *nvm = &hw->nvm; igb_standby_nvm()
231 * @hw: pointer to the HW structure
235 static void e1000_stop_nvm(struct e1000_hw *hw) e1000_stop_nvm() argument
240 if (hw->nvm.type == e1000_nvm_eeprom_spi) { e1000_stop_nvm()
243 igb_lower_eec_clk(hw, &eecd); e1000_stop_nvm()
249 * @hw: pointer to the HW structure
253 void igb_release_nvm(struct e1000_hw *hw) igb_release_nvm() argument
257 e1000_stop_nvm(hw); igb_release_nvm()
266 * @hw: pointer to the HW structure
270 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) igb_ready_nvm_eeprom() argument
272 struct e1000_nvm_info *nvm = &hw->nvm; igb_ready_nvm_eeprom()
293 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, igb_ready_nvm_eeprom()
294 hw->nvm.opcode_bits); igb_ready_nvm_eeprom()
295 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); igb_ready_nvm_eeprom()
300 igb_standby_nvm(hw); igb_ready_nvm_eeprom()
317 * @hw: pointer to the HW structure
324 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) igb_read_nvm_spi() argument
326 struct e1000_nvm_info *nvm = &hw->nvm; igb_read_nvm_spi()
342 ret_val = nvm->ops.acquire(hw); igb_read_nvm_spi()
346 ret_val = igb_ready_nvm_eeprom(hw); igb_read_nvm_spi()
350 igb_standby_nvm(hw); igb_read_nvm_spi()
356 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); igb_read_nvm_spi()
357 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); igb_read_nvm_spi()
364 word_in = igb_shift_in_eec_bits(hw, 16); igb_read_nvm_spi()
369 nvm->ops.release(hw); igb_read_nvm_spi()
377 * @hw: pointer to the HW structure
384 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) igb_read_nvm_eerd() argument
386 struct e1000_nvm_info *nvm = &hw->nvm; igb_read_nvm_eerd()
405 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); igb_read_nvm_eerd()
419 * @hw: pointer to the HW structure
429 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) igb_write_nvm_spi() argument
431 struct e1000_nvm_info *nvm = &hw->nvm; igb_write_nvm_spi()
447 ret_val = nvm->ops.acquire(hw); igb_write_nvm_spi()
451 ret_val = igb_ready_nvm_eeprom(hw); igb_write_nvm_spi()
453 nvm->ops.release(hw); igb_write_nvm_spi()
457 igb_standby_nvm(hw); igb_write_nvm_spi()
460 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, igb_write_nvm_spi()
463 igb_standby_nvm(hw); igb_write_nvm_spi()
472 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); igb_write_nvm_spi()
473 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), igb_write_nvm_spi()
481 igb_shift_out_eec_bits(hw, word_out, 16); igb_write_nvm_spi()
485 igb_standby_nvm(hw); igb_write_nvm_spi()
490 nvm->ops.release(hw); igb_write_nvm_spi()
498 * @hw: pointer to the HW structure
505 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size) igb_read_part_string() argument
519 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); igb_read_part_string()
525 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer); igb_read_part_string()
570 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length); igb_read_part_string()
593 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data); igb_read_part_string()
609 * @hw: pointer to the HW structure
615 s32 igb_read_mac_addr(struct e1000_hw *hw) igb_read_mac_addr() argument
625 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); igb_read_mac_addr()
628 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); igb_read_mac_addr()
631 hw->mac.addr[i] = hw->mac.perm_addr[i]; igb_read_mac_addr()
638 * @hw: pointer to the HW structure
643 s32 igb_validate_nvm_checksum(struct e1000_hw *hw) igb_validate_nvm_checksum() argument
650 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); igb_validate_nvm_checksum()
670 * @hw: pointer to the HW structure
676 s32 igb_update_nvm_checksum(struct e1000_hw *hw) igb_update_nvm_checksum() argument
683 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); igb_update_nvm_checksum()
691 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); igb_update_nvm_checksum()
701 * @hw: pointer to the HW structure
706 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) igb_get_fw_version() argument
717 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); igb_get_fw_version()
718 switch (hw->mac.type) { igb_get_fw_version()
720 igb_read_invm_version(hw, fw_vers); igb_get_fw_version()
729 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); igb_get_fw_version()
739 if (!(igb_get_flash_presence_i210(hw))) { igb_get_fw_version()
740 igb_read_invm_version(hw, fw_vers); igb_get_fw_version()
746 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); igb_get_fw_version()
750 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset igb_get_fw_version()
752 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), igb_get_fw_version()
774 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); igb_get_fw_version()
796 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); igb_get_fw_version()
797 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); igb_get_fw_version()
H A De1000_82575.c67 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
68 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
69 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
70 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
71 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
72 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
78 * @hw: pointer to the HW structure
83 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) igb_sgmii_uses_mdio_82575() argument
88 switch (hw->mac.type) { igb_sgmii_uses_mdio_82575()
110 * @hw: pointer to the HW structure
114 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) igb_check_for_link_media_swap() argument
116 struct e1000_phy_info *phy = &hw->phy; igb_check_for_link_media_swap()
122 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); igb_check_for_link_media_swap()
126 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); igb_check_for_link_media_swap()
134 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); igb_check_for_link_media_swap()
138 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); igb_check_for_link_media_swap()
147 if (port && (hw->dev_spec._82575.media_port != port)) { igb_check_for_link_media_swap()
148 hw->dev_spec._82575.media_port = port; igb_check_for_link_media_swap()
149 hw->dev_spec._82575.media_changed = true; igb_check_for_link_media_swap()
154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); igb_check_for_link_media_swap()
157 igb_check_for_link_82575(hw); igb_check_for_link_media_swap()
159 igb_check_for_link_82575(hw); igb_check_for_link_media_swap()
161 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); igb_check_for_link_media_swap()
171 * @hw: pointer to the HW structure
173 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) igb_init_phy_params_82575() argument
175 struct e1000_phy_info *phy = &hw->phy; igb_init_phy_params_82575()
179 if (hw->phy.media_type != e1000_media_type_copper) { igb_init_phy_params_82575()
189 if (igb_sgmii_active_82575(hw)) { igb_init_phy_params_82575()
198 igb_reset_mdicnfg_82580(hw); igb_init_phy_params_82575()
200 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { igb_init_phy_params_82575()
204 switch (hw->mac.type) { igb_init_phy_params_82575()
223 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> igb_init_phy_params_82575()
227 ret_val = igb_get_phy_id_82575(hw); igb_init_phy_params_82575()
251 ret_val = phy->ops.write_reg(hw, igb_init_phy_params_82575()
257 ret_val = phy->ops.read_reg(hw, igb_init_phy_params_82575()
267 hw->mac.ops.check_for_link = igb_init_phy_params_82575()
271 ret_val = igb_initialize_M88E1512_phy(hw); igb_init_phy_params_82575()
314 * @hw: pointer to the HW structure
316 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) igb_init_nvm_params_82575() argument
318 struct e1000_nvm_info *nvm = &hw->nvm; igb_init_nvm_params_82575()
372 switch (hw->mac.type) { igb_init_nvm_params_82575()
391 * @hw: pointer to the HW structure
393 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) igb_init_mac_params_82575() argument
395 struct e1000_mac_info *mac = &hw->mac; igb_init_mac_params_82575()
396 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; igb_init_mac_params_82575()
447 (hw->phy.media_type == e1000_media_type_copper) igb_init_mac_params_82575()
452 switch (hw->device_id) { igb_init_mac_params_82575()
460 hw->dev_spec._82575.mas_capable = true; igb_init_mac_params_82575()
469 * @hw: pointer to the HW structure
474 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) igb_set_sfp_media_type_82575() argument
478 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; igb_set_sfp_media_type_82575()
492 ret_val = igb_read_sfp_data_byte(hw, igb_set_sfp_media_type_82575()
503 ret_val = igb_read_sfp_data_byte(hw, igb_set_sfp_media_type_82575()
514 hw->phy.media_type = e1000_media_type_internal_serdes; igb_set_sfp_media_type_82575()
517 hw->phy.media_type = e1000_media_type_internal_serdes; igb_set_sfp_media_type_82575()
520 hw->phy.media_type = e1000_media_type_copper; igb_set_sfp_media_type_82575()
522 hw->phy.media_type = e1000_media_type_unknown; igb_set_sfp_media_type_82575()
527 hw->phy.media_type = e1000_media_type_unknown; igb_set_sfp_media_type_82575()
536 static s32 igb_get_invariants_82575(struct e1000_hw *hw) igb_get_invariants_82575() argument
538 struct e1000_mac_info *mac = &hw->mac; igb_get_invariants_82575()
539 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; igb_get_invariants_82575()
544 switch (hw->device_id) { igb_get_invariants_82575()
605 hw->phy.media_type = e1000_media_type_copper; igb_get_invariants_82575()
614 hw->phy.media_type = e1000_media_type_internal_serdes; igb_get_invariants_82575()
618 if (igb_sgmii_uses_mdio_82575(hw)) { igb_get_invariants_82575()
619 hw->phy.media_type = e1000_media_type_copper; igb_get_invariants_82575()
626 ret_val = igb_set_sfp_media_type_82575(hw); igb_get_invariants_82575()
628 (hw->phy.media_type == e1000_media_type_unknown)) { igb_get_invariants_82575()
632 hw->phy.media_type = e1000_media_type_internal_serdes; igb_get_invariants_82575()
635 hw->phy.media_type = e1000_media_type_copper; igb_get_invariants_82575()
649 if (hw->phy.media_type == e1000_media_type_copper) igb_get_invariants_82575()
662 ret_val = igb_init_mac_params_82575(hw); igb_get_invariants_82575()
667 ret_val = igb_init_nvm_params_82575(hw); igb_get_invariants_82575()
668 switch (hw->mac.type) { igb_get_invariants_82575()
671 ret_val = igb_init_nvm_params_i210(hw); igb_get_invariants_82575()
684 igb_init_mbx_params_pf(hw); igb_get_invariants_82575()
691 ret_val = igb_init_phy_params_82575(hw); igb_get_invariants_82575()
699 * @hw: pointer to the HW structure
704 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) igb_acquire_phy_82575() argument
708 if (hw->bus.func == E1000_FUNC_1) igb_acquire_phy_82575()
710 else if (hw->bus.func == E1000_FUNC_2) igb_acquire_phy_82575()
712 else if (hw->bus.func == E1000_FUNC_3) igb_acquire_phy_82575()
715 return hw->mac.ops.acquire_swfw_sync(hw, mask); igb_acquire_phy_82575()
720 * @hw: pointer to the HW structure
725 static void igb_release_phy_82575(struct e1000_hw *hw) igb_release_phy_82575() argument
729 if (hw->bus.func == E1000_FUNC_1) igb_release_phy_82575()
731 else if (hw->bus.func == E1000_FUNC_2) igb_release_phy_82575()
733 else if (hw->bus.func == E1000_FUNC_3) igb_release_phy_82575()
736 hw->mac.ops.release_swfw_sync(hw, mask); igb_release_phy_82575()
741 * @hw: pointer to the HW structure
748 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, igb_read_phy_reg_sgmii_82575() argument
758 ret_val = hw->phy.ops.acquire(hw); igb_read_phy_reg_sgmii_82575()
762 ret_val = igb_read_phy_reg_i2c(hw, offset, data); igb_read_phy_reg_sgmii_82575()
764 hw->phy.ops.release(hw); igb_read_phy_reg_sgmii_82575()
772 * @hw: pointer to the HW structure
779 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, igb_write_phy_reg_sgmii_82575() argument
790 ret_val = hw->phy.ops.acquire(hw); igb_write_phy_reg_sgmii_82575()
794 ret_val = igb_write_phy_reg_i2c(hw, offset, data); igb_write_phy_reg_sgmii_82575()
796 hw->phy.ops.release(hw); igb_write_phy_reg_sgmii_82575()
804 * @hw: pointer to the HW structure
809 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) igb_get_phy_id_82575() argument
811 struct e1000_phy_info *phy = &hw->phy; igb_get_phy_id_82575()
818 if (hw->mac.type == e1000_i354) igb_get_phy_id_82575()
819 igb_get_phy_id(hw); igb_get_phy_id_82575()
827 if (!(igb_sgmii_active_82575(hw))) { igb_get_phy_id_82575()
829 ret_val = igb_get_phy_id(hw); igb_get_phy_id_82575()
833 if (igb_sgmii_uses_mdio_82575(hw)) { igb_get_phy_id_82575()
834 switch (hw->mac.type) { igb_get_phy_id_82575()
854 ret_val = igb_get_phy_id(hw); igb_get_phy_id_82575()
868 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); igb_get_phy_id_82575()
888 ret_val = igb_get_phy_id(hw); igb_get_phy_id_82575()
900 * @hw: pointer to the HW structure
904 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) igb_phy_hw_reset_sgmii_82575() argument
906 struct e1000_phy_info *phy = &hw->phy; igb_phy_hw_reset_sgmii_82575()
918 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); igb_phy_hw_reset_sgmii_82575()
922 ret_val = igb_phy_sw_reset(hw); igb_phy_hw_reset_sgmii_82575()
927 ret_val = igb_initialize_M88E1512_phy(hw); igb_phy_hw_reset_sgmii_82575()
934 * @hw: pointer to the HW structure
945 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) igb_set_d0_lplu_state_82575() argument
947 struct e1000_phy_info *phy = &hw->phy; igb_set_d0_lplu_state_82575()
951 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); igb_set_d0_lplu_state_82575()
957 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d0_lplu_state_82575()
963 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, igb_set_d0_lplu_state_82575()
966 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, igb_set_d0_lplu_state_82575()
972 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d0_lplu_state_82575()
980 ret_val = phy->ops.read_reg(hw, igb_set_d0_lplu_state_82575()
986 ret_val = phy->ops.write_reg(hw, igb_set_d0_lplu_state_82575()
991 ret_val = phy->ops.read_reg(hw, igb_set_d0_lplu_state_82575()
997 ret_val = phy->ops.write_reg(hw, igb_set_d0_lplu_state_82575()
1010 * @hw: pointer to the HW structure
1021 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) igb_set_d0_lplu_state_82580() argument
1023 struct e1000_phy_info *phy = &hw->phy; igb_set_d0_lplu_state_82580()
1052 * @hw: pointer to the HW structure
1064 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) igb_set_d3_lplu_state_82580() argument
1066 struct e1000_phy_info *phy = &hw->phy; igb_set_d3_lplu_state_82580()
1096 * @hw: pointer to the HW structure
1103 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) igb_acquire_nvm_82575() argument
1107 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); igb_acquire_nvm_82575()
1111 ret_val = igb_acquire_nvm(hw); igb_acquire_nvm_82575()
1114 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); igb_acquire_nvm_82575()
1122 * @hw: pointer to the HW structure
1127 static void igb_release_nvm_82575(struct e1000_hw *hw) igb_release_nvm_82575() argument
1129 igb_release_nvm(hw); igb_release_nvm_82575()
1130 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); igb_release_nvm_82575()
1135 * @hw: pointer to the HW structure
1141 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) igb_acquire_swfw_sync_82575() argument
1150 if (igb_get_hw_semaphore(hw)) { igb_acquire_swfw_sync_82575()
1162 igb_put_hw_semaphore(hw); igb_acquire_swfw_sync_82575()
1176 igb_put_hw_semaphore(hw); igb_acquire_swfw_sync_82575()
1184 * @hw: pointer to the HW structure
1190 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) igb_release_swfw_sync_82575() argument
1194 while (igb_get_hw_semaphore(hw) != 0) igb_release_swfw_sync_82575()
1201 igb_put_hw_semaphore(hw); igb_release_swfw_sync_82575()
1206 * @hw: pointer to the HW structure
1214 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) igb_get_cfg_done_82575() argument
1219 if (hw->bus.func == 1) igb_get_cfg_done_82575()
1221 else if (hw->bus.func == E1000_FUNC_2) igb_get_cfg_done_82575()
1223 else if (hw->bus.func == E1000_FUNC_3) igb_get_cfg_done_82575()
1237 (hw->phy.type == e1000_phy_igp_3)) igb_get_cfg_done_82575()
1238 igb_phy_init_script_igp3(hw); igb_get_cfg_done_82575()
1245 * @hw: pointer to the HW structure
1253 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, igb_get_link_up_info_82575() argument
1258 if (hw->phy.media_type != e1000_media_type_copper) igb_get_link_up_info_82575()
1259 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, igb_get_link_up_info_82575()
1262 ret_val = igb_get_speed_and_duplex_copper(hw, speed, igb_get_link_up_info_82575()
1270 * @hw: pointer to the HW structure
1275 static s32 igb_check_for_link_82575(struct e1000_hw *hw) igb_check_for_link_82575() argument
1280 if (hw->phy.media_type != e1000_media_type_copper) { igb_check_for_link_82575()
1281 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, igb_check_for_link_82575()
1287 hw->mac.get_link_status = !hw->mac.serdes_has_link; igb_check_for_link_82575()
1294 ret_val = igb_config_fc_after_link_up(hw); igb_check_for_link_82575()
1298 ret_val = igb_check_for_copper_link(hw); igb_check_for_link_82575()
1306 * @hw: pointer to the HW structure
1308 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) igb_power_up_serdes_link_82575() argument
1313 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && igb_power_up_serdes_link_82575()
1314 !igb_sgmii_active_82575(hw)) igb_power_up_serdes_link_82575()
1334 * @hw: pointer to the HW structure
1341 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, igb_get_pcs_speed_and_duplex_82575() argument
1344 struct e1000_mac_info *mac = &hw->mac; igb_get_pcs_speed_and_duplex_82575()
1398 * @hw: pointer to the HW structure
1403 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) igb_shutdown_serdes_link_82575() argument
1407 if (hw->phy.media_type != e1000_media_type_internal_serdes && igb_shutdown_serdes_link_82575()
1408 igb_sgmii_active_82575(hw)) igb_shutdown_serdes_link_82575()
1411 if (!igb_enable_mng_pass_thru(hw)) { igb_shutdown_serdes_link_82575()
1430 * @hw: pointer to the HW structure
1435 static s32 igb_reset_hw_82575(struct e1000_hw *hw) igb_reset_hw_82575() argument
1443 ret_val = igb_disable_pcie_master(hw); igb_reset_hw_82575()
1448 ret_val = igb_set_pcie_completion_timeout(hw); igb_reset_hw_82575()
1466 ret_val = igb_get_auto_rd_done(hw); igb_reset_hw_82575()
1477 igb_reset_init_script_82575(hw); igb_reset_hw_82575()
1484 ret_val = igb_check_alt_mac_addr(hw); igb_reset_hw_82575()
1491 * @hw: pointer to the HW structure
1495 static s32 igb_init_hw_82575(struct e1000_hw *hw) igb_init_hw_82575() argument
1497 struct e1000_mac_info *mac = &hw->mac; igb_init_hw_82575()
1501 if ((hw->mac.type >= e1000_i210) && igb_init_hw_82575()
1502 !(igb_get_flash_presence_i210(hw))) { igb_init_hw_82575()
1503 ret_val = igb_pll_workaround_i210(hw); igb_init_hw_82575()
1509 ret_val = igb_id_led_init(hw); igb_init_hw_82575()
1517 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) igb_init_hw_82575()
1518 igb_clear_vfta_i350(hw); igb_init_hw_82575()
1520 igb_clear_vfta(hw); igb_init_hw_82575()
1523 igb_init_rx_addrs(hw, rar_count); igb_init_hw_82575()
1536 ret_val = igb_setup_link(hw); igb_init_hw_82575()
1543 igb_clear_hw_cntrs_82575(hw); igb_init_hw_82575()
1549 * @hw: pointer to the HW structure
1555 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) igb_setup_copper_link_82575() argument
1567 switch (hw->mac.type) { igb_setup_copper_link_82575()
1580 ret_val = igb_setup_serdes_link_82575(hw); igb_setup_copper_link_82575()
1584 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { igb_setup_copper_link_82575()
1588 ret_val = hw->phy.ops.reset(hw); igb_setup_copper_link_82575()
1594 switch (hw->phy.type) { igb_setup_copper_link_82575()
1597 switch (hw->phy.id) { igb_setup_copper_link_82575()
1603 ret_val = igb_copper_link_setup_m88_gen2(hw); igb_setup_copper_link_82575()
1606 ret_val = igb_copper_link_setup_m88(hw); igb_setup_copper_link_82575()
1611 ret_val = igb_copper_link_setup_igp(hw); igb_setup_copper_link_82575()
1614 ret_val = igb_copper_link_setup_82580(hw); igb_setup_copper_link_82575()
1624 ret_val = igb_setup_copper_link(hw); igb_setup_copper_link_82575()
1631 * @hw: pointer to the HW structure
1638 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) igb_setup_serdes_link_82575() argument
1645 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && igb_setup_serdes_link_82575()
1646 !igb_sgmii_active_82575(hw)) igb_setup_serdes_link_82575()
1666 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { igb_setup_serdes_link_82575()
1679 pcs_autoneg = hw->mac.autoneg; igb_setup_serdes_link_82575()
1692 if (hw->mac.type == e1000_82575 || igb_setup_serdes_link_82575()
1693 hw->mac.type == e1000_82576) { igb_setup_serdes_link_82575()
1694 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); igb_setup_serdes_link_82575()
1737 switch (hw->fc.requested_mode) { igb_setup_serdes_link_82575()
1764 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) igb_setup_serdes_link_82575()
1765 igb_force_mac_fc(hw); igb_setup_serdes_link_82575()
1772 * @hw: pointer to the HW structure
1778 static bool igb_sgmii_active_82575(struct e1000_hw *hw) igb_sgmii_active_82575() argument
1780 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; igb_sgmii_active_82575()
1786 * @hw: pointer to the HW structure
1791 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) igb_reset_init_script_82575() argument
1793 if (hw->mac.type == e1000_82575) { igb_reset_init_script_82575()
1796 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); igb_reset_init_script_82575()
1797 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); igb_reset_init_script_82575()
1798 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); igb_reset_init_script_82575()
1799 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); igb_reset_init_script_82575()
1802 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); igb_reset_init_script_82575()
1803 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); igb_reset_init_script_82575()
1806 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); igb_reset_init_script_82575()
1807 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); igb_reset_init_script_82575()
1808 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); igb_reset_init_script_82575()
1809 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); igb_reset_init_script_82575()
1812 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); igb_reset_init_script_82575()
1813 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); igb_reset_init_script_82575()
1814 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); igb_reset_init_script_82575()
1822 * @hw: pointer to the HW structure
1824 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) igb_read_mac_addr_82575() argument
1832 ret_val = igb_check_alt_mac_addr(hw); igb_read_mac_addr_82575()
1836 ret_val = igb_read_mac_addr(hw); igb_read_mac_addr_82575()
1844 * @hw: pointer to the HW structure
1849 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) igb_power_down_phy_copper_82575() argument
1852 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) igb_power_down_phy_copper_82575()
1853 igb_power_down_phy_copper(hw); igb_power_down_phy_copper_82575()
1858 * @hw: pointer to the HW structure
1862 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) igb_clear_hw_cntrs_82575() argument
1864 igb_clear_hw_cntrs_base(hw); igb_clear_hw_cntrs_82575()
1914 if (hw->phy.media_type == e1000_media_type_internal_serdes || igb_clear_hw_cntrs_82575()
1915 igb_sgmii_active_82575(hw)) igb_clear_hw_cntrs_82575()
1921 * @hw: pointer to the HW structure
1928 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) igb_rx_fifo_flush_82575() argument
1938 if (hw->mac.type != e1000_82575 || igb_rx_fifo_flush_82575()
1998 * @hw: pointer to the HW structure
2006 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) igb_set_pcie_completion_timeout() argument
2028 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, igb_set_pcie_completion_timeout()
2035 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, igb_set_pcie_completion_timeout()
2047 * @hw: pointer to the hardware struct
2053 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) igb_vmdq_set_anti_spoofing_pf() argument
2057 switch (hw->mac.type) { igb_vmdq_set_anti_spoofing_pf()
2086 * @hw: pointer to the hardware struct
2091 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) igb_vmdq_set_loopback_pf() argument
2095 switch (hw->mac.type) { igb_vmdq_set_loopback_pf()
2122 * @hw: pointer to the hardware struct
2127 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) igb_vmdq_set_replication_pf() argument
2141 * @hw: pointer to the HW structure
2148 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) igb_read_phy_reg_82580() argument
2152 ret_val = hw->phy.ops.acquire(hw); igb_read_phy_reg_82580()
2156 ret_val = igb_read_phy_reg_mdic(hw, offset, data); igb_read_phy_reg_82580()
2158 hw->phy.ops.release(hw); igb_read_phy_reg_82580()
2166 * @hw: pointer to the HW structure
2172 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) igb_write_phy_reg_82580() argument
2177 ret_val = hw->phy.ops.acquire(hw); igb_write_phy_reg_82580()
2181 ret_val = igb_write_phy_reg_mdic(hw, offset, data); igb_write_phy_reg_82580()
2183 hw->phy.ops.release(hw); igb_write_phy_reg_82580()
2191 * @hw: pointer to the HW structure
2197 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) igb_reset_mdicnfg_82580() argument
2203 if (hw->mac.type != e1000_82580) igb_reset_mdicnfg_82580()
2205 if (!igb_sgmii_active_82575(hw)) igb_reset_mdicnfg_82580()
2208 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + igb_reset_mdicnfg_82580()
2209 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, igb_reset_mdicnfg_82580()
2228 * @hw: pointer to the HW structure
2233 static s32 igb_reset_hw_82580(struct e1000_hw *hw) igb_reset_hw_82580() argument
2239 bool global_device_reset = hw->dev_spec._82575.global_device_reset; igb_reset_hw_82580()
2241 hw->dev_spec._82575.global_device_reset = false; igb_reset_hw_82580()
2243 /* due to hw errata, global device reset doesn't always igb_reset_hw_82580()
2246 if (hw->mac.type == e1000_82580) igb_reset_hw_82580()
2255 ret_val = igb_disable_pcie_master(hw); igb_reset_hw_82580()
2269 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) igb_reset_hw_82580()
2285 ret_val = igb_get_auto_rd_done(hw); igb_reset_hw_82580()
2301 ret_val = igb_reset_mdicnfg_82580(hw); igb_reset_hw_82580()
2306 ret_val = igb_check_alt_mac_addr(hw); igb_reset_hw_82580()
2310 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); igb_reset_hw_82580()
2338 * @hw: pointer to the HW structure
2344 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, igb_validate_nvm_checksum_with_offset() argument
2352 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); igb_validate_nvm_checksum_with_offset()
2373 * @hw: pointer to the HW structure
2380 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) igb_update_nvm_checksum_with_offset() argument
2387 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); igb_update_nvm_checksum_with_offset()
2395 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, igb_update_nvm_checksum_with_offset()
2406 * @hw: pointer to the HW structure
2412 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) igb_validate_nvm_checksum_82580() argument
2419 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); igb_validate_nvm_checksum_82580()
2434 ret_val = igb_validate_nvm_checksum_with_offset(hw, igb_validate_nvm_checksum_82580()
2446 * @hw: pointer to the HW structure
2452 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) igb_update_nvm_checksum_82580() argument
2458 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); igb_update_nvm_checksum_82580()
2467 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, igb_update_nvm_checksum_82580()
2477 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); igb_update_nvm_checksum_82580()
2488 * @hw: pointer to the HW structure
2494 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) igb_validate_nvm_checksum_i350() argument
2502 ret_val = igb_validate_nvm_checksum_with_offset(hw, igb_validate_nvm_checksum_i350()
2514 * @hw: pointer to the HW structure
2520 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) igb_update_nvm_checksum_i350() argument
2528 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); igb_update_nvm_checksum_i350()
2539 * @hw: pointer to the HW structure
2544 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, __igb_access_emi_reg() argument
2549 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); __igb_access_emi_reg()
2554 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); __igb_access_emi_reg()
2556 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); __igb_access_emi_reg()
2563 * @hw: pointer to the HW structure
2567 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) igb_read_emi_reg() argument
2569 return __igb_access_emi_reg(hw, addr, data, true); igb_read_emi_reg()
2574 * @hw: pointer to the HW structure
2581 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) igb_set_eee_i350() argument
2585 if ((hw->mac.type < e1000_i350) || igb_set_eee_i350()
2586 (hw->phy.media_type != e1000_media_type_copper)) igb_set_eee_i350()
2592 if (!(hw->dev_spec._82575.eee_disable)) { igb_set_eee_i350()
2630 * @hw: pointer to the HW structure
2637 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) igb_set_eee_i354() argument
2639 struct e1000_phy_info *phy = &hw->phy; igb_set_eee_i354()
2643 if ((hw->phy.media_type != e1000_media_type_copper) || igb_set_eee_i354()
2648 if (!hw->dev_spec._82575.eee_disable) { igb_set_eee_i354()
2650 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); igb_set_eee_i354()
2654 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, igb_set_eee_i354()
2660 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, igb_set_eee_i354()
2666 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); igb_set_eee_i354()
2671 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, igb_set_eee_i354()
2687 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, igb_set_eee_i354()
2692 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, igb_set_eee_i354()
2700 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, igb_set_eee_i354()
2711 * @hw: pointer to the HW structure
2717 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) igb_get_eee_status_i354() argument
2719 struct e1000_phy_info *phy = &hw->phy; igb_get_eee_status_i354()
2724 if ((hw->phy.media_type != e1000_media_type_copper) || igb_get_eee_status_i354()
2729 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, igb_get_eee_status_i354()
2758 * @hw: pointer to hardware structure
2762 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) igb_get_thermal_sensor_data_generic() argument
2771 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; igb_get_thermal_sensor_data_generic()
2773 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) igb_get_thermal_sensor_data_generic()
2779 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); igb_get_thermal_sensor_data_generic()
2783 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); igb_get_thermal_sensor_data_generic()
2793 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); igb_get_thermal_sensor_data_generic()
2800 hw->phy.ops.read_i2c_byte(hw, igb_get_thermal_sensor_data_generic()
2810 * @hw: pointer to hardware structure
2815 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) igb_init_thermal_sensor_thresh_generic() argument
2826 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; igb_init_thermal_sensor_thresh_generic()
2828 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) igb_init_thermal_sensor_thresh_generic()
2840 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); igb_init_thermal_sensor_thresh_generic()
2844 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); igb_init_thermal_sensor_thresh_generic()
2854 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); igb_init_thermal_sensor_thresh_generic()
2861 hw->phy.ops.write_i2c_byte(hw, igb_init_thermal_sensor_thresh_generic()
H A De1000_phy.c30 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
31 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
33 static s32 igb_wait_autoneg(struct e1000_hw *hw);
34 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
52 * @hw: pointer to the HW structure
58 s32 igb_check_reset_block(struct e1000_hw *hw) igb_check_reset_block() argument
69 * @hw: pointer to the HW structure
74 s32 igb_get_phy_id(struct e1000_hw *hw) igb_get_phy_id() argument
76 struct e1000_phy_info *phy = &hw->phy; igb_get_phy_id()
80 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); igb_get_phy_id()
86 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); igb_get_phy_id()
99 * @hw: pointer to the HW structure
103 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) igb_phy_reset_dsp() argument
107 if (!(hw->phy.ops.write_reg)) igb_phy_reset_dsp()
110 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); igb_phy_reset_dsp()
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); igb_phy_reset_dsp()
122 * @hw: pointer to the HW structure
129 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) igb_read_phy_reg_mdic() argument
131 struct e1000_phy_info *phy = &hw->phy; igb_read_phy_reg_mdic()
179 * @hw: pointer to the HW structure
185 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) igb_write_phy_reg_mdic() argument
187 struct e1000_phy_info *phy = &hw->phy; igb_write_phy_reg_mdic()
235 * @hw: pointer to the HW structure
242 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) igb_read_phy_reg_i2c() argument
244 struct e1000_phy_info *phy = &hw->phy; igb_read_phy_reg_i2c()
281 * @hw: pointer to the HW structure
287 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) igb_write_phy_reg_i2c() argument
289 struct e1000_phy_info *phy = &hw->phy; igb_write_phy_reg_i2c()
294 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { igb_write_phy_reg_i2c()
296 hw->phy.addr); igb_write_phy_reg_i2c()
335 * @hw: pointer to the HW structure
346 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) igb_read_sfp_data_byte() argument
388 * @hw: pointer to the HW structure
396 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) igb_read_phy_reg_igp() argument
400 if (!(hw->phy.ops.acquire)) igb_read_phy_reg_igp()
403 ret_val = hw->phy.ops.acquire(hw); igb_read_phy_reg_igp()
408 ret_val = igb_write_phy_reg_mdic(hw, igb_read_phy_reg_igp()
412 hw->phy.ops.release(hw); igb_read_phy_reg_igp()
417 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, igb_read_phy_reg_igp()
420 hw->phy.ops.release(hw); igb_read_phy_reg_igp()
428 * @hw: pointer to the HW structure
435 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) igb_write_phy_reg_igp() argument
439 if (!(hw->phy.ops.acquire)) igb_write_phy_reg_igp()
442 ret_val = hw->phy.ops.acquire(hw); igb_write_phy_reg_igp()
447 ret_val = igb_write_phy_reg_mdic(hw, igb_write_phy_reg_igp()
451 hw->phy.ops.release(hw); igb_write_phy_reg_igp()
456 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, igb_write_phy_reg_igp()
459 hw->phy.ops.release(hw); igb_write_phy_reg_igp()
467 * @hw: pointer to the HW structure
471 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) igb_copper_link_setup_82580() argument
473 struct e1000_phy_info *phy = &hw->phy; igb_copper_link_setup_82580()
483 ret_val = hw->phy.ops.reset(hw); igb_copper_link_setup_82580()
491 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); igb_copper_link_setup_82580()
500 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); igb_copper_link_setup_82580()
505 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); igb_copper_link_setup_82580()
514 switch (hw->phy.mdix) { igb_copper_link_setup_82580()
525 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); igb_copper_link_setup_82580()
533 * @hw: pointer to the HW structure
538 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) igb_copper_link_setup_m88() argument
540 struct e1000_phy_info *phy = &hw->phy; igb_copper_link_setup_m88()
550 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); igb_copper_link_setup_m88()
591 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_copper_link_setup_m88()
599 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, igb_copper_link_setup_m88()
618 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, igb_copper_link_setup_m88()
625 ret_val = igb_phy_sw_reset(hw); igb_copper_link_setup_m88()
637 * @hw: pointer to the HW structure
642 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) igb_copper_link_setup_m88_gen2() argument
644 struct e1000_phy_info *phy = &hw->phy; igb_copper_link_setup_m88_gen2()
652 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); igb_copper_link_setup_m88_gen2()
698 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_copper_link_setup_m88_gen2()
702 ret_val = igb_phy_sw_reset(hw); igb_copper_link_setup_m88_gen2()
713 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_copper_link_setup_m88_gen2()
718 ret_val = igb_phy_sw_reset(hw); igb_copper_link_setup_m88_gen2()
723 ret_val = igb_set_master_slave_mode(hw); igb_copper_link_setup_m88_gen2()
732 * @hw: pointer to the HW structure
737 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) igb_copper_link_setup_igp() argument
739 struct e1000_phy_info *phy = &hw->phy; igb_copper_link_setup_igp()
748 ret_val = phy->ops.reset(hw); igb_copper_link_setup_igp()
765 ret_val = phy->ops.set_d3_lplu_state(hw, false); igb_copper_link_setup_igp()
773 ret_val = phy->ops.set_d0_lplu_state(hw, false); igb_copper_link_setup_igp()
779 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); igb_copper_link_setup_igp()
797 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); igb_copper_link_setup_igp()
802 if (hw->mac.autoneg) { igb_copper_link_setup_igp()
809 ret_val = phy->ops.read_reg(hw, igb_copper_link_setup_igp()
816 ret_val = phy->ops.write_reg(hw, igb_copper_link_setup_igp()
823 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); igb_copper_link_setup_igp()
828 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); igb_copper_link_setup_igp()
833 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); igb_copper_link_setup_igp()
857 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); igb_copper_link_setup_igp()
868 * @hw: pointer to the HW structure
875 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) igb_copper_link_autoneg() argument
877 struct e1000_phy_info *phy = &hw->phy; igb_copper_link_autoneg()
893 ret_val = igb_phy_setup_autoneg(hw); igb_copper_link_autoneg()
903 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); igb_copper_link_autoneg()
908 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); igb_copper_link_autoneg()
916 ret_val = igb_wait_autoneg(hw); igb_copper_link_autoneg()
923 hw->mac.get_link_status = true; igb_copper_link_autoneg()
931 * @hw: pointer to the HW structure
938 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) igb_phy_setup_autoneg() argument
940 struct e1000_phy_info *phy = &hw->phy; igb_phy_setup_autoneg()
948 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); igb_phy_setup_autoneg()
954 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, igb_phy_setup_autoneg()
1030 switch (hw->fc.current_mode) { igb_phy_setup_autoneg()
1045 * hw's ability to send PAUSE frames. igb_phy_setup_autoneg()
1068 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); igb_phy_setup_autoneg()
1075 ret_val = phy->ops.write_reg(hw, igb_phy_setup_autoneg()
1088 * @hw: pointer to the HW structure
1095 s32 igb_setup_copper_link(struct e1000_hw *hw) igb_setup_copper_link() argument
1100 if (hw->mac.autoneg) { igb_setup_copper_link()
1104 ret_val = igb_copper_link_autoneg(hw); igb_setup_copper_link()
1112 ret_val = hw->phy.ops.force_speed_duplex(hw); igb_setup_copper_link()
1122 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); igb_setup_copper_link()
1128 igb_config_collision_dist(hw); igb_setup_copper_link()
1129 ret_val = igb_config_fc_after_link_up(hw); igb_setup_copper_link()
1140 * @hw: pointer to the HW structure
1146 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) igb_phy_force_speed_duplex_igp() argument
1148 struct e1000_phy_info *phy = &hw->phy; igb_phy_force_speed_duplex_igp()
1153 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); igb_phy_force_speed_duplex_igp()
1157 igb_phy_force_speed_duplex_setup(hw, &phy_data); igb_phy_force_speed_duplex_igp()
1159 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); igb_phy_force_speed_duplex_igp()
1166 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); igb_phy_force_speed_duplex_igp()
1173 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); igb_phy_force_speed_duplex_igp()
1184 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); igb_phy_force_speed_duplex_igp()
1192 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); igb_phy_force_speed_duplex_igp()
1203 * @hw: pointer to the HW structure
1211 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) igb_phy_force_speed_duplex_m88() argument
1213 struct e1000_phy_info *phy = &hw->phy; igb_phy_force_speed_duplex_m88()
1223 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, igb_phy_force_speed_duplex_m88()
1229 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, igb_phy_force_speed_duplex_m88()
1237 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); igb_phy_force_speed_duplex_m88()
1241 igb_phy_force_speed_duplex_setup(hw, &phy_data); igb_phy_force_speed_duplex_m88()
1243 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); igb_phy_force_speed_duplex_m88()
1248 ret_val = igb_phy_sw_reset(hw); igb_phy_force_speed_duplex_m88()
1255 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); igb_phy_force_speed_duplex_m88()
1262 switch (hw->phy.id) { igb_phy_force_speed_duplex_m88()
1271 if (hw->phy.type != e1000_phy_m88) igb_phy_force_speed_duplex_m88()
1281 ret_val = phy->ops.write_reg(hw, igb_phy_force_speed_duplex_m88()
1286 ret_val = igb_phy_reset_dsp(hw); igb_phy_force_speed_duplex_m88()
1293 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, igb_phy_force_speed_duplex_m88()
1299 if (hw->phy.type != e1000_phy_m88 || igb_phy_force_speed_duplex_m88()
1300 hw->phy.id == I347AT4_E_PHY_ID || igb_phy_force_speed_duplex_m88()
1301 hw->phy.id == M88E1112_E_PHY_ID || igb_phy_force_speed_duplex_m88()
1302 hw->phy.id == M88E1543_E_PHY_ID || igb_phy_force_speed_duplex_m88()
1303 hw->phy.id == M88E1512_E_PHY_ID || igb_phy_force_speed_duplex_m88()
1304 hw->phy.id == I210_I_PHY_ID) igb_phy_force_speed_duplex_m88()
1307 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); igb_phy_force_speed_duplex_m88()
1316 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); igb_phy_force_speed_duplex_m88()
1323 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); igb_phy_force_speed_duplex_m88()
1328 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_phy_force_speed_duplex_m88()
1336 * @hw: pointer to the HW structure
1346 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, igb_phy_force_speed_duplex_setup() argument
1349 struct e1000_mac_info *mac = &hw->mac; igb_phy_force_speed_duplex_setup()
1353 hw->fc.current_mode = e1000_fc_none; igb_phy_force_speed_duplex_setup()
1390 igb_config_collision_dist(hw); igb_phy_force_speed_duplex_setup()
1397 * @hw: pointer to the HW structure
1409 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) igb_set_d3_lplu_state() argument
1411 struct e1000_phy_info *phy = &hw->phy; igb_set_d3_lplu_state()
1415 if (!(hw->phy.ops.read_reg)) igb_set_d3_lplu_state()
1418 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); igb_set_d3_lplu_state()
1424 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d3_lplu_state()
1434 ret_val = phy->ops.read_reg(hw, igb_set_d3_lplu_state()
1441 ret_val = phy->ops.write_reg(hw, igb_set_d3_lplu_state()
1447 ret_val = phy->ops.read_reg(hw, igb_set_d3_lplu_state()
1454 ret_val = phy->ops.write_reg(hw, igb_set_d3_lplu_state()
1464 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d3_lplu_state()
1470 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, igb_set_d3_lplu_state()
1476 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, igb_set_d3_lplu_state()
1486 * @hw: pointer to the HW structure
1492 s32 igb_check_downshift(struct e1000_hw *hw) igb_check_downshift() argument
1494 struct e1000_phy_info *phy = &hw->phy; igb_check_downshift()
1518 ret_val = phy->ops.read_reg(hw, offset, &phy_data); igb_check_downshift()
1529 * @hw: pointer to the HW structure
1535 s32 igb_check_polarity_m88(struct e1000_hw *hw) igb_check_polarity_m88() argument
1537 struct e1000_phy_info *phy = &hw->phy; igb_check_polarity_m88()
1541 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); igb_check_polarity_m88()
1553 * @hw: pointer to the HW structure
1560 static s32 igb_check_polarity_igp(struct e1000_hw *hw) igb_check_polarity_igp() argument
1562 struct e1000_phy_info *phy = &hw->phy; igb_check_polarity_igp()
1569 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); igb_check_polarity_igp()
1585 ret_val = phy->ops.read_reg(hw, offset, &data); igb_check_polarity_igp()
1598 * @hw: pointer to the HW structure
1603 static s32 igb_wait_autoneg(struct e1000_hw *hw) igb_wait_autoneg() argument
1610 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); igb_wait_autoneg()
1613 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); igb_wait_autoneg()
1629 * @hw: pointer to the HW structure
1636 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, igb_phy_has_link() argument
1647 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); igb_phy_has_link()
1658 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); igb_phy_has_link()
1676 * @hw: pointer to the HW structure
1689 s32 igb_get_cable_length_m88(struct e1000_hw *hw) igb_get_cable_length_m88() argument
1691 struct e1000_phy_info *phy = &hw->phy; igb_get_cable_length_m88()
1695 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); igb_get_cable_length_m88()
1715 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) igb_get_cable_length_m88_gen2() argument
1717 struct e1000_phy_info *phy = &hw->phy; igb_get_cable_length_m88_gen2()
1721 switch (hw->phy.id) { igb_get_cable_length_m88_gen2()
1724 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + igb_get_cable_length_m88_gen2()
1731 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + igb_get_cable_length_m88_gen2()
1747 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, igb_get_cable_length_m88_gen2()
1752 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); igb_get_cable_length_m88_gen2()
1757 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), igb_get_cable_length_m88_gen2()
1763 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); igb_get_cable_length_m88_gen2()
1775 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, igb_get_cable_length_m88_gen2()
1782 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, igb_get_cable_length_m88_gen2()
1787 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); igb_get_cable_length_m88_gen2()
1791 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, igb_get_cable_length_m88_gen2()
1810 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, igb_get_cable_length_m88_gen2()
1827 * @hw: pointer to the HW structure
1836 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) igb_get_cable_length_igp_2() argument
1838 struct e1000_phy_info *phy = &hw->phy; igb_get_cable_length_igp_2()
1852 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); igb_get_cable_length_igp_2()
1899 * @hw: pointer to the HW structure
1907 s32 igb_get_phy_info_m88(struct e1000_hw *hw) igb_get_phy_info_m88() argument
1909 struct e1000_phy_info *phy = &hw->phy; igb_get_phy_info_m88()
1920 ret_val = igb_phy_has_link(hw, 1, 0, &link); igb_get_phy_info_m88()
1930 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); igb_get_phy_info_m88()
1937 ret_val = igb_check_polarity_m88(hw); igb_get_phy_info_m88()
1941 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); igb_get_phy_info_m88()
1948 ret_val = phy->ops.get_cable_length(hw); igb_get_phy_info_m88()
1952 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); igb_get_phy_info_m88()
1976 * @hw: pointer to the HW structure
1983 s32 igb_get_phy_info_igp(struct e1000_hw *hw) igb_get_phy_info_igp() argument
1985 struct e1000_phy_info *phy = &hw->phy; igb_get_phy_info_igp()
1990 ret_val = igb_phy_has_link(hw, 1, 0, &link); igb_get_phy_info_igp()
2002 ret_val = igb_check_polarity_igp(hw); igb_get_phy_info_igp()
2006 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); igb_get_phy_info_igp()
2014 ret_val = phy->ops.get_cable_length(hw); igb_get_phy_info_igp()
2018 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); igb_get_phy_info_igp()
2041 * @hw: pointer to the HW structure
2046 s32 igb_phy_sw_reset(struct e1000_hw *hw) igb_phy_sw_reset() argument
2051 if (!(hw->phy.ops.read_reg)) igb_phy_sw_reset()
2054 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); igb_phy_sw_reset()
2059 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); igb_phy_sw_reset()
2071 * @hw: pointer to the HW structure
2078 s32 igb_phy_hw_reset(struct e1000_hw *hw) igb_phy_hw_reset() argument
2080 struct e1000_phy_info *phy = &hw->phy; igb_phy_hw_reset()
2084 ret_val = igb_check_reset_block(hw); igb_phy_hw_reset()
2090 ret_val = phy->ops.acquire(hw); igb_phy_hw_reset()
2105 phy->ops.release(hw); igb_phy_hw_reset()
2107 ret_val = phy->ops.get_cfg_done(hw); igb_phy_hw_reset()
2115 * @hw: pointer to the HW structure
2119 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) igb_phy_init_script_igp3() argument
2125 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); igb_phy_init_script_igp3()
2127 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); igb_phy_init_script_igp3()
2129 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); igb_phy_init_script_igp3()
2131 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); igb_phy_init_script_igp3()
2133 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); igb_phy_init_script_igp3()
2135 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); igb_phy_init_script_igp3()
2137 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); igb_phy_init_script_igp3()
2139 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); igb_phy_init_script_igp3()
2141 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); igb_phy_init_script_igp3()
2143 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); igb_phy_init_script_igp3()
2145 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); igb_phy_init_script_igp3()
2147 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); igb_phy_init_script_igp3()
2149 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); igb_phy_init_script_igp3()
2151 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); igb_phy_init_script_igp3()
2153 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); igb_phy_init_script_igp3()
2155 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); igb_phy_init_script_igp3()
2157 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); igb_phy_init_script_igp3()
2159 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); igb_phy_init_script_igp3()
2161 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); igb_phy_init_script_igp3()
2163 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); igb_phy_init_script_igp3()
2165 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); igb_phy_init_script_igp3()
2167 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); igb_phy_init_script_igp3()
2169 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); igb_phy_init_script_igp3()
2171 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); igb_phy_init_script_igp3()
2173 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); igb_phy_init_script_igp3()
2175 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); igb_phy_init_script_igp3()
2179 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); igb_phy_init_script_igp3()
2181 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); igb_phy_init_script_igp3()
2185 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); igb_phy_init_script_igp3()
2187 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); igb_phy_init_script_igp3()
2189 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); igb_phy_init_script_igp3()
2191 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); igb_phy_init_script_igp3()
2198 * @hw: pointer to the HW structure
2202 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw) igb_initialize_M88E1512_phy() argument
2204 struct e1000_phy_info *phy = &hw->phy; igb_initialize_M88E1512_phy()
2208 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); igb_initialize_M88E1512_phy()
2212 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); igb_initialize_M88E1512_phy()
2216 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); igb_initialize_M88E1512_phy()
2220 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); igb_initialize_M88E1512_phy()
2224 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); igb_initialize_M88E1512_phy()
2228 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); igb_initialize_M88E1512_phy()
2232 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); igb_initialize_M88E1512_phy()
2236 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); igb_initialize_M88E1512_phy()
2240 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); igb_initialize_M88E1512_phy()
2245 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); igb_initialize_M88E1512_phy()
2249 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); igb_initialize_M88E1512_phy()
2254 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); igb_initialize_M88E1512_phy()
2259 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); igb_initialize_M88E1512_phy()
2264 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); igb_initialize_M88E1512_phy()
2268 ret_val = igb_phy_sw_reset(hw); igb_initialize_M88E1512_phy()
2282 * @hw: pointer to the HW structure
2287 void igb_power_up_phy_copper(struct e1000_hw *hw) igb_power_up_phy_copper() argument
2292 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); igb_power_up_phy_copper()
2294 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); igb_power_up_phy_copper()
2299 * @hw: pointer to the HW structure
2304 void igb_power_down_phy_copper(struct e1000_hw *hw) igb_power_down_phy_copper() argument
2309 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); igb_power_down_phy_copper()
2311 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); igb_power_down_phy_copper()
2317 * @hw: pointer to the HW structure
2323 static s32 igb_check_polarity_82580(struct e1000_hw *hw) igb_check_polarity_82580() argument
2325 struct e1000_phy_info *phy = &hw->phy; igb_check_polarity_82580()
2330 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); igb_check_polarity_82580()
2342 * @hw: pointer to the HW structure
2348 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) igb_phy_force_speed_duplex_82580() argument
2350 struct e1000_phy_info *phy = &hw->phy; igb_phy_force_speed_duplex_82580()
2355 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); igb_phy_force_speed_duplex_82580()
2359 igb_phy_force_speed_duplex_setup(hw, &phy_data); igb_phy_force_speed_duplex_82580()
2361 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); igb_phy_force_speed_duplex_82580()
2368 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); igb_phy_force_speed_duplex_82580()
2374 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); igb_phy_force_speed_duplex_82580()
2385 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); igb_phy_force_speed_duplex_82580()
2393 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); igb_phy_force_speed_duplex_82580()
2404 * @hw: pointer to the HW structure
2411 s32 igb_get_phy_info_82580(struct e1000_hw *hw) igb_get_phy_info_82580() argument
2413 struct e1000_phy_info *phy = &hw->phy; igb_get_phy_info_82580()
2418 ret_val = igb_phy_has_link(hw, 1, 0, &link); igb_get_phy_info_82580()
2430 ret_val = igb_check_polarity_82580(hw); igb_get_phy_info_82580()
2434 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); igb_get_phy_info_82580()
2442 ret_val = hw->phy.ops.get_cable_length(hw); igb_get_phy_info_82580()
2446 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); igb_get_phy_info_82580()
2469 * @hw: pointer to the HW structure
2474 s32 igb_get_cable_length_82580(struct e1000_hw *hw) igb_get_cable_length_82580() argument
2476 struct e1000_phy_info *phy = &hw->phy; igb_get_cable_length_82580()
2480 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); igb_get_cable_length_82580()
2498 * @hw: pointer to the HW structure
2506 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) igb_write_phy_reg_gs40g() argument
2512 ret_val = hw->phy.ops.acquire(hw); igb_write_phy_reg_gs40g()
2516 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); igb_write_phy_reg_gs40g()
2519 ret_val = igb_write_phy_reg_mdic(hw, offset, data); igb_write_phy_reg_gs40g()
2522 hw->phy.ops.release(hw); igb_write_phy_reg_gs40g()
2528 * @hw: pointer to the HW structure
2536 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) igb_read_phy_reg_gs40g() argument
2542 ret_val = hw->phy.ops.acquire(hw); igb_read_phy_reg_gs40g()
2546 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); igb_read_phy_reg_gs40g()
2549 ret_val = igb_read_phy_reg_mdic(hw, offset, data); igb_read_phy_reg_gs40g()
2552 hw->phy.ops.release(hw); igb_read_phy_reg_gs40g()
2558 * @hw: pointer to the HW structure
2562 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) igb_set_master_slave_mode() argument
2568 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); igb_set_master_slave_mode()
2573 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? igb_set_master_slave_mode()
2578 switch (hw->phy.ms_type) { igb_set_master_slave_mode()
2593 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); igb_set_master_slave_mode()
H A De1000_mbx.c28 * @hw: pointer to the HW structure
35 s32 igb_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) igb_read_mbx() argument
37 struct e1000_mbx_info *mbx = &hw->mbx; igb_read_mbx()
45 ret_val = mbx->ops.read(hw, msg, size, mbx_id); igb_read_mbx()
52 * @hw: pointer to the HW structure
59 s32 igb_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) igb_write_mbx() argument
61 struct e1000_mbx_info *mbx = &hw->mbx; igb_write_mbx()
68 ret_val = mbx->ops.write(hw, msg, size, mbx_id); igb_write_mbx()
75 * @hw: pointer to the HW structure
80 s32 igb_check_for_msg(struct e1000_hw *hw, u16 mbx_id) igb_check_for_msg() argument
82 struct e1000_mbx_info *mbx = &hw->mbx; igb_check_for_msg()
86 ret_val = mbx->ops.check_for_msg(hw, mbx_id); igb_check_for_msg()
93 * @hw: pointer to the HW structure
98 s32 igb_check_for_ack(struct e1000_hw *hw, u16 mbx_id) igb_check_for_ack() argument
100 struct e1000_mbx_info *mbx = &hw->mbx; igb_check_for_ack()
104 ret_val = mbx->ops.check_for_ack(hw, mbx_id); igb_check_for_ack()
111 * @hw: pointer to the HW structure
116 s32 igb_check_for_rst(struct e1000_hw *hw, u16 mbx_id) igb_check_for_rst() argument
118 struct e1000_mbx_info *mbx = &hw->mbx; igb_check_for_rst()
122 ret_val = mbx->ops.check_for_rst(hw, mbx_id); igb_check_for_rst()
129 * @hw: pointer to the HW structure
134 static s32 igb_poll_for_msg(struct e1000_hw *hw, u16 mbx_id) igb_poll_for_msg() argument
136 struct e1000_mbx_info *mbx = &hw->mbx; igb_poll_for_msg()
142 while (countdown && mbx->ops.check_for_msg(hw, mbx_id)) { igb_poll_for_msg()
158 * @hw: pointer to the HW structure
163 static s32 igb_poll_for_ack(struct e1000_hw *hw, u16 mbx_id) igb_poll_for_ack() argument
165 struct e1000_mbx_info *mbx = &hw->mbx; igb_poll_for_ack()
171 while (countdown && mbx->ops.check_for_ack(hw, mbx_id)) { igb_poll_for_ack()
187 * @hw: pointer to the HW structure
195 static s32 igb_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, igb_read_posted_mbx() argument
198 struct e1000_mbx_info *mbx = &hw->mbx; igb_read_posted_mbx()
204 ret_val = igb_poll_for_msg(hw, mbx_id); igb_read_posted_mbx()
207 ret_val = mbx->ops.read(hw, msg, size, mbx_id); igb_read_posted_mbx()
214 * @hw: pointer to the HW structure
222 static s32 igb_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, igb_write_posted_mbx() argument
225 struct e1000_mbx_info *mbx = &hw->mbx; igb_write_posted_mbx()
233 ret_val = mbx->ops.write(hw, msg, size, mbx_id); igb_write_posted_mbx()
237 ret_val = igb_poll_for_ack(hw, mbx_id); igb_write_posted_mbx()
242 static s32 igb_check_for_bit_pf(struct e1000_hw *hw, u32 mask) igb_check_for_bit_pf() argument
257 * @hw: pointer to the HW structure
262 static s32 igb_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number) igb_check_for_msg_pf() argument
266 if (!igb_check_for_bit_pf(hw, E1000_MBVFICR_VFREQ_VF1 << vf_number)) { igb_check_for_msg_pf()
268 hw->mbx.stats.reqs++; igb_check_for_msg_pf()
276 * @hw: pointer to the HW structure
281 static s32 igb_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number) igb_check_for_ack_pf() argument
285 if (!igb_check_for_bit_pf(hw, E1000_MBVFICR_VFACK_VF1 << vf_number)) { igb_check_for_ack_pf()
287 hw->mbx.stats.acks++; igb_check_for_ack_pf()
295 * @hw: pointer to the HW structure
300 static s32 igb_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number) igb_check_for_rst_pf() argument
308 hw->mbx.stats.rsts++; igb_check_for_rst_pf()
316 * @hw: pointer to the HW structure
321 static s32 igb_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number) igb_obtain_mbx_lock_pf() argument
339 * @hw: pointer to the HW structure
346 static s32 igb_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size, igb_write_mbx_pf() argument
353 ret_val = igb_obtain_mbx_lock_pf(hw, vf_number); igb_write_mbx_pf()
358 igb_check_for_msg_pf(hw, vf_number); igb_write_mbx_pf()
359 igb_check_for_ack_pf(hw, vf_number); igb_write_mbx_pf()
369 hw->mbx.stats.msgs_tx++; igb_write_mbx_pf()
378 * @hw: pointer to the HW structure
387 static s32 igb_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size, igb_read_mbx_pf() argument
394 ret_val = igb_obtain_mbx_lock_pf(hw, vf_number); igb_read_mbx_pf()
406 hw->mbx.stats.msgs_rx++; igb_read_mbx_pf()
414 * @hw: pointer to the HW structure
416 * Initializes the hw->mbx struct to correct values for pf mailbox
418 s32 igb_init_mbx_params_pf(struct e1000_hw *hw) igb_init_mbx_params_pf() argument
420 struct e1000_mbx_info *mbx = &hw->mbx; igb_init_mbx_params_pf()
/linux-4.4.14/drivers/ide/
H A Dide-legacy.c5 static void ide_legacy_init_one(struct ide_hw **hws, struct ide_hw *hw, ide_legacy_init_one() argument
35 ide_std_init_ports(hw, base, ctl); ide_legacy_init_one()
36 hw->irq = irq; ide_legacy_init_one()
37 hw->config = config; ide_legacy_init_one()
39 hws[port_no] = hw; ide_legacy_init_one()
44 struct ide_hw hw[2], *hws[] = { NULL, NULL }; ide_legacy_device_add() local
46 memset(&hw, 0, sizeof(hw)); ide_legacy_device_add()
49 ide_legacy_init_one(hws, &hw[0], 0, d, config); ide_legacy_device_add()
50 ide_legacy_init_one(hws, &hw[1], 1, d, config); ide_legacy_device_add()
H A Dide-4drives.c34 struct ide_hw hw, *hws[] = { &hw, &hw }; ide_4drives_init() local
52 memset(&hw, 0, sizeof(hw)); ide_4drives_init()
54 ide_std_init_ports(&hw, base, ctl); ide_4drives_init()
55 hw.irq = 14; ide_4drives_init()
H A Drapide.c18 static void rapide_setup_ports(struct ide_hw *hw, void __iomem *base, rapide_setup_ports() argument
25 hw->io_ports_array[i] = port; rapide_setup_ports()
28 hw->io_ports.ctl_addr = (unsigned long)ctrl; rapide_setup_ports()
29 hw->irq = irq; rapide_setup_ports()
37 struct ide_hw hw, *hws[] = { &hw }; rapide_probe() local
49 memset(&hw, 0, sizeof(hw)); rapide_probe()
50 rapide_setup_ports(&hw, base, base + 0x818, 1 << 6, ec->irq); rapide_probe()
51 hw.dev = &ec->dev; rapide_probe()
/linux-4.4.14/drivers/tty/ipwireless/
H A Dhardware.c30 static void ipw_send_setup_packet(struct ipw_hardware *hw);
36 static void handle_received_CTRL_packet(struct ipw_hardware *hw,
238 /* Flag if hw is ready to send next packet */
403 static void do_send_fragment(struct ipw_hardware *hw, unsigned char *data, do_send_fragment() argument
410 BUG_ON(length > hw->ll_mtu); do_send_fragment()
415 spin_lock_irqsave(&hw->lock, flags); do_send_fragment()
417 hw->tx_ready = 0; do_send_fragment()
420 if (hw->hw_version == HW_VERSION_1) { do_send_fragment()
421 outw((unsigned short) length, hw->base_port + IODWR); do_send_fragment()
430 outw(raw_data, hw->base_port + IODWR); do_send_fragment()
433 outw(DCR_TXDONE, hw->base_port + IODCR); do_send_fragment()
434 } else if (hw->hw_version == HW_VERSION_2) { do_send_fragment()
435 outw((unsigned short) length, hw->base_port); do_send_fragment()
444 outw(raw_data, hw->base_port); do_send_fragment()
447 outw((unsigned short) 0xDEAD, hw->base_port); do_send_fragment()
450 writew(MEMRX_RX, &hw->memory_info_regs->memreg_rx); do_send_fragment()
453 spin_unlock_irqrestore(&hw->lock, flags); do_send_fragment()
458 static void do_send_packet(struct ipw_hardware *hw, struct ipw_tx_packet *packet) do_send_packet() argument
469 fragment_data_len = hw->ll_mtu - header_size; do_send_packet()
475 * to le just before it goes to hw do_send_packet()
498 do_send_fragment(hw, pkt.rawpkt, header_size + fragment_data_len); do_send_packet()
508 spin_lock_irqsave(&hw->lock, flags); do_send_packet()
509 list_add(&packet->queue, &hw->tx_queue[0]); do_send_packet()
510 hw->tx_queued++; do_send_packet()
511 spin_unlock_irqrestore(&hw->lock, flags); do_send_packet()
520 static void ipw_setup_hardware(struct ipw_hardware *hw) ipw_setup_hardware() argument
524 spin_lock_irqsave(&hw->lock, flags); ipw_setup_hardware()
525 if (hw->hw_version == HW_VERSION_1) { ipw_setup_hardware()
527 outw(DCR_RXRESET, hw->base_port + IODCR); ipw_setup_hardware()
529 outw(DCR_TXRESET, hw->base_port + IODCR); ipw_setup_hardware()
532 outw(IER_TXENABLED | IER_RXENABLED, hw->base_port + IOIER); ipw_setup_hardware()
538 unsigned short csr = readw(&hw->memregs_CCR->reg_config_and_status); ipw_setup_hardware()
541 writew(csr, &hw->memregs_CCR->reg_config_and_status); ipw_setup_hardware()
543 spin_unlock_irqrestore(&hw->lock, flags); ipw_setup_hardware()
554 static struct ipw_rx_packet *pool_allocate(struct ipw_hardware *hw, pool_allocate() argument
562 spin_lock_irqsave(&hw->lock, flags); pool_allocate()
563 if (!list_empty(&hw->rx_pool)) { pool_allocate()
564 packet = list_first_entry(&hw->rx_pool, pool_allocate()
566 hw->rx_pool_size--; pool_allocate()
567 spin_unlock_irqrestore(&hw->lock, flags); pool_allocate()
571 ipwireless_ppp_mru(hw->network) + 2; pool_allocate()
574 spin_unlock_irqrestore(&hw->lock, flags); pool_allocate()
608 static void pool_free(struct ipw_hardware *hw, struct ipw_rx_packet *packet) pool_free() argument
610 if (hw->rx_pool_size > 6) pool_free()
613 hw->rx_pool_size++; pool_free()
614 list_add(&packet->queue, &hw->rx_pool); pool_free()
618 static void queue_received_packet(struct ipw_hardware *hw, queue_received_packet() argument
640 &hw->packet_assembler[channel_idx]; queue_received_packet()
646 (*assem) = pool_allocate(hw, *assem, length); queue_received_packet()
664 spin_lock_irqsave(&hw->lock, flags); queue_received_packet()
665 hw->rx_bytes_queued += packet->length; queue_received_packet()
666 spin_unlock_irqrestore(&hw->lock, flags); queue_received_packet()
670 packet = pool_allocate(hw, NULL, length); queue_received_packet()
688 spin_lock_irqsave(&hw->lock, flags); queue_received_packet()
689 list_add_tail(&packet->queue, &hw->rx_queue); queue_received_packet()
691 hw->blocking_rx = queue_received_packet()
692 (hw->rx_bytes_queued >= IPWIRELESS_RX_QUEUE_SIZE); queue_received_packet()
694 spin_unlock_irqrestore(&hw->lock, flags); queue_received_packet()
695 schedule_work(&hw->work_rx); queue_received_packet()
704 struct ipw_hardware *hw = ipw_receive_data_work() local
708 spin_lock_irqsave(&hw->lock, flags); ipw_receive_data_work()
709 while (!list_empty(&hw->rx_queue)) { ipw_receive_data_work()
711 list_first_entry(&hw->rx_queue, ipw_receive_data_work()
714 if (hw->shutting_down) ipw_receive_data_work()
724 if (hw->network != NULL) { ipw_receive_data_work()
726 spin_unlock_irqrestore(&hw->lock, flags); ipw_receive_data_work()
732 hw->network, ipw_receive_data_work()
737 spin_lock_irqsave(&hw->lock, flags); ipw_receive_data_work()
740 hw->rx_bytes_queued -= packet->length; ipw_receive_data_work()
746 handle_received_CTRL_packet(hw, packet->channel_idx, ipw_receive_data_work()
751 pool_free(hw, packet); ipw_receive_data_work()
756 hw->blocking_rx = ipw_receive_data_work()
757 hw->rx_bytes_queued >= IPWIRELESS_RX_QUEUE_SIZE; ipw_receive_data_work()
758 if (hw->shutting_down) ipw_receive_data_work()
761 spin_unlock_irqrestore(&hw->lock, flags); ipw_receive_data_work()
764 static void handle_received_CTRL_packet(struct ipw_hardware *hw, handle_received_CTRL_packet() argument
798 hw->control_lines[channel_idx] |= changed_mask; handle_received_CTRL_packet()
800 hw->control_lines[channel_idx] &= ~changed_mask; handle_received_CTRL_packet()
801 if (hw->network) handle_received_CTRL_packet()
803 hw->network, handle_received_CTRL_packet()
805 hw->control_lines[channel_idx], handle_received_CTRL_packet()
810 static void handle_received_packet(struct ipw_hardware *hw, handle_received_packet() argument
831 queue_received_packet(hw, protocol, address, data, data_len, handle_received_packet()
835 handle_received_SETUP_packet(hw, address, data, data_len, handle_received_packet()
841 static void acknowledge_data_read(struct ipw_hardware *hw) acknowledge_data_read() argument
843 if (hw->hw_version == HW_VERSION_1) acknowledge_data_read()
844 outw(DCR_RXDONE, hw->base_port + IODCR); acknowledge_data_read()
847 &hw->memory_info_regs->memreg_pc_interrupt_ack); acknowledge_data_read()
853 static void do_receive_packet(struct ipw_hardware *hw) do_receive_packet() argument
861 if (hw->hw_version == HW_VERSION_1) { do_receive_packet()
862 len = inw(hw->base_port + IODRR); do_receive_packet()
863 if (len > hw->ll_mtu) { do_receive_packet()
866 outw(DCR_RXDONE | DCR_RXRESET, hw->base_port + IODCR); do_receive_packet()
871 __le16 raw_data = inw(hw->base_port + IODRR); do_receive_packet()
878 len = inw(hw->base_port); do_receive_packet()
879 if (len > hw->ll_mtu) { do_receive_packet()
883 &hw->memory_info_regs->memreg_pc_interrupt_ack); do_receive_packet()
888 __le16 raw_data = inw(hw->base_port); do_receive_packet()
896 inw(hw->base_port); do_receive_packet()
901 acknowledge_data_read(hw); do_receive_packet()
908 handle_received_packet(hw, (union nl_packet *) pkt, len); do_receive_packet()
913 static int get_current_packet_priority(struct ipw_hardware *hw) get_current_packet_priority() argument
921 return (hw->to_setup || hw->initializing get_current_packet_priority()
926 * return 1 if something has been received from hw
928 static int get_packets_from_hw(struct ipw_hardware *hw) get_packets_from_hw() argument
933 spin_lock_irqsave(&hw->lock, flags); get_packets_from_hw()
934 while (hw->rx_ready && !hw->blocking_rx) { get_packets_from_hw()
936 hw->rx_ready--; get_packets_from_hw()
937 spin_unlock_irqrestore(&hw->lock, flags); get_packets_from_hw()
939 do_receive_packet(hw); get_packets_from_hw()
941 spin_lock_irqsave(&hw->lock, flags); get_packets_from_hw()
943 spin_unlock_irqrestore(&hw->lock, flags); get_packets_from_hw()
954 static int send_pending_packet(struct ipw_hardware *hw, int priority_limit) send_pending_packet() argument
959 spin_lock_irqsave(&hw->lock, flags); send_pending_packet()
960 if (hw->tx_queued && hw->tx_ready) { send_pending_packet()
966 if (!list_empty(&hw->tx_queue[priority])) { send_pending_packet()
968 &hw->tx_queue[priority], send_pending_packet()
972 hw->tx_queued--; send_pending_packet()
979 hw->tx_queued = 0; send_pending_packet()
980 spin_unlock_irqrestore(&hw->lock, flags); send_pending_packet()
984 spin_unlock_irqrestore(&hw->lock, flags); send_pending_packet()
987 do_send_packet(hw, packet); send_pending_packet()
990 spin_lock_irqsave(&hw->lock, flags); send_pending_packet()
992 if (!list_empty(&hw->tx_queue[priority])) { send_pending_packet()
998 hw->tx_queued = 0; send_pending_packet()
1000 spin_unlock_irqrestore(&hw->lock, flags); send_pending_packet()
1010 struct ipw_hardware *hw = (struct ipw_hardware *) hw_; ipwireless_do_tasklet() local
1013 spin_lock_irqsave(&hw->lock, flags); ipwireless_do_tasklet()
1014 if (hw->shutting_down) { ipwireless_do_tasklet()
1015 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_do_tasklet()
1019 if (hw->to_setup == 1) { ipwireless_do_tasklet()
1023 hw->to_setup = 2; ipwireless_do_tasklet()
1024 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_do_tasklet()
1026 ipw_setup_hardware(hw); ipwireless_do_tasklet()
1027 ipw_send_setup_packet(hw); ipwireless_do_tasklet()
1029 send_pending_packet(hw, PRIO_SETUP + 1); ipwireless_do_tasklet()
1030 get_packets_from_hw(hw); ipwireless_do_tasklet()
1032 int priority_limit = get_current_packet_priority(hw); ipwireless_do_tasklet()
1035 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_do_tasklet()
1038 again = send_pending_packet(hw, priority_limit); ipwireless_do_tasklet()
1039 again |= get_packets_from_hw(hw); ipwireless_do_tasklet()
1047 static int is_card_present(struct ipw_hardware *hw) is_card_present() argument
1049 if (hw->hw_version == HW_VERSION_1) is_card_present()
1050 return inw(hw->base_port + IOIR) != 0xFFFF; is_card_present()
1052 return readl(&hw->memory_info_regs->memreg_card_present) == is_card_present()
1057 struct ipw_hardware *hw) ipwireless_handle_v1_interrupt()
1061 irqn = inw(hw->base_port + IOIR); ipwireless_handle_v1_interrupt()
1073 spin_lock_irqsave(&hw->lock, flags); ipwireless_handle_v1_interrupt()
1074 hw->tx_ready = 1; ipwireless_handle_v1_interrupt()
1075 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_handle_v1_interrupt()
1080 spin_lock_irqsave(&hw->lock, flags); ipwireless_handle_v1_interrupt()
1081 hw->rx_ready++; ipwireless_handle_v1_interrupt()
1082 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_handle_v1_interrupt()
1085 outw(ack, hw->base_port + IOIR); ipwireless_handle_v1_interrupt()
1086 tasklet_schedule(&hw->tasklet); ipwireless_handle_v1_interrupt()
1093 static void acknowledge_pcmcia_interrupt(struct ipw_hardware *hw) acknowledge_pcmcia_interrupt() argument
1095 unsigned short csr = readw(&hw->memregs_CCR->reg_config_and_status); acknowledge_pcmcia_interrupt()
1098 writew(csr, &hw->memregs_CCR->reg_config_and_status); acknowledge_pcmcia_interrupt()
1102 struct ipw_hardware *hw) ipwireless_handle_v2_v3_interrupt()
1112 unsigned short memtx = readw(hw->memreg_tx); ipwireless_handle_v2_v3_interrupt()
1115 readw(&hw->memory_info_regs->memreg_rx_done); ipwireless_handle_v2_v3_interrupt()
1123 if (hw->memreg_tx == &hw->memory_info_regs->memreg_tx_new) { ipwireless_handle_v2_v3_interrupt()
1124 memtx = readw(&hw->memory_info_regs->memreg_tx_old); ipwireless_handle_v2_v3_interrupt()
1128 hw->memreg_tx = ipwireless_handle_v2_v3_interrupt()
1129 &hw->memory_info_regs->memreg_tx_old; ipwireless_handle_v2_v3_interrupt()
1141 if (!is_card_present(hw)) { ipwireless_handle_v2_v3_interrupt()
1142 acknowledge_pcmcia_interrupt(hw); ipwireless_handle_v2_v3_interrupt()
1148 writew(memtx_serial, hw->memreg_tx); ipwireless_handle_v2_v3_interrupt()
1150 if (hw->serial_number_detected) { ipwireless_handle_v2_v3_interrupt()
1151 if (memtx_serial != hw->last_memtx_serial) { ipwireless_handle_v2_v3_interrupt()
1152 hw->last_memtx_serial = memtx_serial; ipwireless_handle_v2_v3_interrupt()
1153 spin_lock_irqsave(&hw->lock, flags); ipwireless_handle_v2_v3_interrupt()
1154 hw->rx_ready++; ipwireless_handle_v2_v3_interrupt()
1155 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_handle_v2_v3_interrupt()
1166 hw->serial_number_detected = 1; ipwireless_handle_v2_v3_interrupt()
1170 spin_lock_irqsave(&hw->lock, flags); ipwireless_handle_v2_v3_interrupt()
1171 hw->rx_ready++; ipwireless_handle_v2_v3_interrupt()
1172 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_handle_v2_v3_interrupt()
1178 writew(0, &hw->memory_info_regs->memreg_rx_done); ipwireless_handle_v2_v3_interrupt()
1179 spin_lock_irqsave(&hw->lock, flags); ipwireless_handle_v2_v3_interrupt()
1180 hw->tx_ready = 1; ipwireless_handle_v2_v3_interrupt()
1181 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_handle_v2_v3_interrupt()
1186 &hw->memory_info_regs->memreg_pc_interrupt_ack); ipwireless_handle_v2_v3_interrupt()
1188 acknowledge_pcmcia_interrupt(hw); ipwireless_handle_v2_v3_interrupt()
1191 tasklet_schedule(&hw->tasklet); ipwireless_handle_v2_v3_interrupt()
1193 if (hw->memreg_tx == &hw->memory_info_regs->memreg_tx_new) { ipwireless_handle_v2_v3_interrupt()
1194 if (hw->serial_number_detected) ipwireless_handle_v2_v3_interrupt()
1200 hw->memreg_tx = ipwireless_handle_v2_v3_interrupt()
1201 &hw->memory_info_regs->memreg_tx_old; ipwireless_handle_v2_v3_interrupt()
1224 static void flush_packets_to_hw(struct ipw_hardware *hw) flush_packets_to_hw() argument
1229 spin_lock_irqsave(&hw->lock, flags); flush_packets_to_hw()
1230 priority_limit = get_current_packet_priority(hw); flush_packets_to_hw()
1231 spin_unlock_irqrestore(&hw->lock, flags); flush_packets_to_hw()
1233 while (send_pending_packet(hw, priority_limit)); flush_packets_to_hw()
1236 static void send_packet(struct ipw_hardware *hw, int priority, send_packet() argument
1241 spin_lock_irqsave(&hw->lock, flags); send_packet()
1242 list_add_tail(&packet->queue, &hw->tx_queue[priority]); send_packet()
1243 hw->tx_queued++; send_packet()
1244 spin_unlock_irqrestore(&hw->lock, flags); send_packet()
1246 flush_packets_to_hw(hw); send_packet()
1293 int ipwireless_send_packet(struct ipw_hardware *hw, unsigned int channel_idx, ipwireless_send_packet() argument
1309 send_packet(hw, PRIO_DATA, packet); ipwireless_send_packet()
1313 static int set_control_line(struct ipw_hardware *hw, int prio, set_control_line() argument
1328 send_packet(hw, prio, &packet->header); set_control_line()
1333 static int set_DTR(struct ipw_hardware *hw, int priority, set_DTR() argument
1337 hw->control_lines[channel_idx] |= IPW_CONTROL_LINE_DTR; set_DTR()
1339 hw->control_lines[channel_idx] &= ~IPW_CONTROL_LINE_DTR; set_DTR()
1341 return set_control_line(hw, priority, channel_idx, COMCTRL_DTR, state); set_DTR()
1344 static int set_RTS(struct ipw_hardware *hw, int priority, set_RTS() argument
1348 hw->control_lines[channel_idx] |= IPW_CONTROL_LINE_RTS; set_RTS()
1350 hw->control_lines[channel_idx] &= ~IPW_CONTROL_LINE_RTS; set_RTS()
1352 return set_control_line(hw, priority, channel_idx, COMCTRL_RTS, state); set_RTS()
1355 int ipwireless_set_DTR(struct ipw_hardware *hw, unsigned int channel_idx, ipwireless_set_DTR() argument
1358 return set_DTR(hw, PRIO_CTRL, channel_idx, state); ipwireless_set_DTR()
1361 int ipwireless_set_RTS(struct ipw_hardware *hw, unsigned int channel_idx, ipwireless_set_RTS() argument
1364 return set_RTS(hw, PRIO_CTRL, channel_idx, state); ipwireless_set_RTS()
1398 static void __handle_setup_get_version_rsp(struct ipw_hardware *hw) __handle_setup_get_version_rsp() argument
1420 send_packet(hw, PRIO_SETUP, &config_packet->header); __handle_setup_get_version_rsp()
1430 send_packet(hw, PRIO_SETUP, &config_done_packet->header); __handle_setup_get_version_rsp()
1443 send_packet(hw, PRIO_SETUP, &open_packet->header); __handle_setup_get_version_rsp()
1449 ret = set_DTR(hw, PRIO_SETUP, channel_idx, __handle_setup_get_version_rsp()
1450 (hw->control_lines[channel_idx] & __handle_setup_get_version_rsp()
1458 ret = set_RTS(hw, PRIO_SETUP, channel_idx, __handle_setup_get_version_rsp()
1459 (hw->control_lines [channel_idx] & __handle_setup_get_version_rsp()
1482 send_packet(hw, PRIO_SETUP, &info_packet->header); __handle_setup_get_version_rsp()
1485 hw->to_setup = 0; __handle_setup_get_version_rsp()
1492 hw->to_setup = -1; __handle_setup_get_version_rsp()
1495 static void handle_setup_get_version_rsp(struct ipw_hardware *hw, handle_setup_get_version_rsp() argument
1498 del_timer(&hw->setup_timer); handle_setup_get_version_rsp()
1499 hw->initializing = 0; handle_setup_get_version_rsp()
1503 __handle_setup_get_version_rsp(hw); handle_setup_get_version_rsp()
1510 static void ipw_send_setup_packet(struct ipw_hardware *hw) ipw_send_setup_packet() argument
1523 send_packet(hw, PRIO_SETUP, &ver_packet->header); ipw_send_setup_packet()
1526 static void handle_received_SETUP_packet(struct ipw_hardware *hw, handle_received_SETUP_packet() argument
1541 if (hw->to_setup) handle_received_SETUP_packet()
1542 handle_setup_get_version_rsp(hw, handle_received_SETUP_packet()
1563 if (hw->to_setup) handle_received_SETUP_packet()
1577 send_packet(hw, PRIO_SETUP, &packet->header); handle_received_SETUP_packet()
1578 if (hw->reboot_callback) handle_received_SETUP_packet()
1579 hw->reboot_callback(hw->reboot_callback_data); handle_received_SETUP_packet()
1590 static void do_close_hardware(struct ipw_hardware *hw) do_close_hardware() argument
1594 if (hw->hw_version == HW_VERSION_1) { do_close_hardware()
1596 outw(0, hw->base_port + IOIER); do_close_hardware()
1599 irqn = inw(hw->base_port + IOIR); do_close_hardware()
1601 outw(IR_TXINTR, hw->base_port + IOIR); do_close_hardware()
1603 outw(IR_RXINTR, hw->base_port + IOIR); do_close_hardware()
1605 synchronize_irq(hw->irq); do_close_hardware()
1612 struct ipw_hardware *hw = ipwireless_hardware_create() local
1615 if (!hw) ipwireless_hardware_create()
1618 hw->irq = -1; ipwireless_hardware_create()
1619 hw->initializing = 1; ipwireless_hardware_create()
1620 hw->tx_ready = 1; ipwireless_hardware_create()
1621 hw->rx_bytes_queued = 0; ipwireless_hardware_create()
1622 hw->rx_pool_size = 0; ipwireless_hardware_create()
1623 hw->last_memtx_serial = (unsigned short) 0xffff; ipwireless_hardware_create()
1625 INIT_LIST_HEAD(&hw->tx_queue[i]); ipwireless_hardware_create()
1627 INIT_LIST_HEAD(&hw->rx_queue); ipwireless_hardware_create()
1628 INIT_LIST_HEAD(&hw->rx_pool); ipwireless_hardware_create()
1629 spin_lock_init(&hw->lock); ipwireless_hardware_create()
1630 tasklet_init(&hw->tasklet, ipwireless_do_tasklet, (unsigned long) hw); ipwireless_hardware_create()
1631 INIT_WORK(&hw->work_rx, ipw_receive_data_work); ipwireless_hardware_create()
1632 setup_timer(&hw->setup_timer, ipwireless_setup_timer, ipwireless_hardware_create()
1633 (unsigned long) hw); ipwireless_hardware_create()
1635 return hw; ipwireless_hardware_create()
1638 void ipwireless_init_hardware_v1(struct ipw_hardware *hw, ipwireless_init_hardware_v1() argument
1646 if (hw->removed) { ipwireless_init_hardware_v1()
1647 hw->removed = 0; ipwireless_init_hardware_v1()
1648 enable_irq(hw->irq); ipwireless_init_hardware_v1()
1650 hw->base_port = base_port; ipwireless_init_hardware_v1()
1651 hw->hw_version = (is_v2_card ? HW_VERSION_2 : HW_VERSION_1); ipwireless_init_hardware_v1()
1652 hw->ll_mtu = (hw->hw_version == HW_VERSION_1 ? LL_MTU_V1 : LL_MTU_V2); ipwireless_init_hardware_v1()
1653 hw->memregs_CCR = (struct MEMCCR __iomem *) ipwireless_init_hardware_v1()
1655 hw->memory_info_regs = (struct MEMINFREG __iomem *) common_memory; ipwireless_init_hardware_v1()
1656 hw->memreg_tx = &hw->memory_info_regs->memreg_tx_new; ipwireless_init_hardware_v1()
1657 hw->reboot_callback = reboot_callback; ipwireless_init_hardware_v1()
1658 hw->reboot_callback_data = reboot_callback_data; ipwireless_init_hardware_v1()
1661 void ipwireless_init_hardware_v2_v3(struct ipw_hardware *hw) ipwireless_init_hardware_v2_v3() argument
1663 hw->initializing = 1; ipwireless_init_hardware_v2_v3()
1664 hw->init_loops = 0; ipwireless_init_hardware_v2_v3()
1667 ipwireless_setup_timer((unsigned long) hw); ipwireless_init_hardware_v2_v3()
1672 struct ipw_hardware *hw = (struct ipw_hardware *) data; ipwireless_setup_timer() local
1674 hw->init_loops++; ipwireless_setup_timer()
1676 if (hw->init_loops == TL_SETUP_MAX_VERSION_QRY && ipwireless_setup_timer()
1677 hw->hw_version == HW_VERSION_2 && ipwireless_setup_timer()
1678 hw->memreg_tx == &hw->memory_info_regs->memreg_tx_new) { ipwireless_setup_timer()
1682 hw->memreg_tx = &hw->memory_info_regs->memreg_tx_old; ipwireless_setup_timer()
1683 hw->init_loops = 0; ipwireless_setup_timer()
1686 if (hw->init_loops == TL_SETUP_MAX_VERSION_QRY) { ipwireless_setup_timer()
1689 hw->initializing = 0; ipwireless_setup_timer()
1692 if (is_card_present(hw)) { ipwireless_setup_timer()
1695 spin_lock_irqsave(&hw->lock, flags); ipwireless_setup_timer()
1696 hw->to_setup = 1; ipwireless_setup_timer()
1697 hw->tx_ready = 1; ipwireless_setup_timer()
1698 spin_unlock_irqrestore(&hw->lock, flags); ipwireless_setup_timer()
1699 tasklet_schedule(&hw->tasklet); ipwireless_setup_timer()
1702 mod_timer(&hw->setup_timer, ipwireless_setup_timer()
1712 void ipwireless_stop_interrupts(struct ipw_hardware *hw) ipwireless_stop_interrupts() argument
1714 if (!hw->shutting_down) { ipwireless_stop_interrupts()
1716 hw->shutting_down = 1; ipwireless_stop_interrupts()
1717 del_timer(&hw->setup_timer); ipwireless_stop_interrupts()
1720 do_close_hardware(hw); ipwireless_stop_interrupts()
1724 void ipwireless_hardware_free(struct ipw_hardware *hw) ipwireless_hardware_free() argument
1730 ipwireless_stop_interrupts(hw); ipwireless_hardware_free()
1732 flush_work(&hw->work_rx); ipwireless_hardware_free()
1735 kfree(hw->packet_assembler[i]); ipwireless_hardware_free()
1738 list_for_each_entry_safe(tp, tq, &hw->tx_queue[i], queue) { ipwireless_hardware_free()
1743 list_for_each_entry_safe(rp, rq, &hw->rx_queue, queue) { ipwireless_hardware_free()
1748 list_for_each_entry_safe(rp, rq, &hw->rx_pool, queue) { ipwireless_hardware_free()
1752 kfree(hw); ipwireless_hardware_free()
1759 void ipwireless_associate_network(struct ipw_hardware *hw, ipwireless_associate_network() argument
1762 hw->network = network; ipwireless_associate_network()
1056 ipwireless_handle_v1_interrupt(int irq, struct ipw_hardware *hw) ipwireless_handle_v1_interrupt() argument
1101 ipwireless_handle_v2_v3_interrupt(int irq, struct ipw_hardware *hw) ipwireless_handle_v2_v3_interrupt() argument
/linux-4.4.14/sound/pci/emu10k1/
H A Demu10k1_callback.c39 static void lookup_voices(struct snd_emux *emux, struct snd_emu10k1 *hw,
49 static void set_fmmod(struct snd_emu10k1 *hw, struct snd_emux_voice *vp);
50 static void set_fm2frq2(struct snd_emu10k1 *hw, struct snd_emux_voice *vp);
51 static void set_filterQ(struct snd_emu10k1 *hw, struct snd_emux_voice *vp);
92 snd_emu10k1_synth_get_voice(struct snd_emu10k1 *hw) snd_emu10k1_synth_get_voice() argument
99 emu = hw->synth; snd_emu10k1_synth_get_voice()
101 lookup_voices(emu, hw, best, 1); /* no OFF voices */ snd_emu10k1_synth_get_voice()
132 struct snd_emu10k1 *hw; release_voice() local
134 hw = vp->hw; release_voice()
136 snd_emu10k1_ptr_write(hw, DCYSUSM, vp->ch, dcysusv); release_voice()
138 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, dcysusv); release_voice()
148 struct snd_emu10k1 *hw; terminate_voice() local
152 hw = vp->hw; terminate_voice()
153 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0x807f | DCYSUSV_CHANNELENABLE_MASK); terminate_voice()
168 struct snd_emu10k1 *hw; free_voice() local
170 hw = vp->hw; free_voice()
172 /* This can get called with hw == 0 */ free_voice()
175 if (hw && (vp->ch >= 0)) { free_voice()
176 snd_emu10k1_ptr_write(hw, IFATN, vp->ch, 0xff00); free_voice()
177 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0x807f | DCYSUSV_CHANNELENABLE_MASK); free_voice()
178 // snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0); free_voice()
179 snd_emu10k1_ptr_write(hw, VTFT, vp->ch, 0xffff); free_voice()
180 snd_emu10k1_ptr_write(hw, CVCF, vp->ch, 0xffff); free_voice()
181 snd_emu10k1_voice_free(hw, &hw->voices[vp->ch]); free_voice()
194 struct snd_emu10k1 *hw; update_voice() local
196 hw = vp->hw; update_voice()
198 snd_emu10k1_ptr_write(hw, IFATN_ATTENUATION, vp->ch, vp->avol); update_voice()
200 snd_emu10k1_ptr_write(hw, IP, vp->ch, vp->apitch); update_voice()
202 snd_emu10k1_ptr_write(hw, PTRX_FXSENDAMOUNT_A, vp->ch, vp->apan); update_voice()
203 snd_emu10k1_ptr_write(hw, PTRX_FXSENDAMOUNT_B, vp->ch, vp->aaux); update_voice()
206 set_fmmod(hw, vp); update_voice()
208 snd_emu10k1_ptr_write(hw, TREMFRQ, vp->ch, vp->reg.parm.tremfrq); update_voice()
210 set_fm2frq2(hw, vp); update_voice()
212 set_filterQ(hw, vp); update_voice()
221 lookup_voices(struct snd_emux *emu, struct snd_emu10k1 *hw, lookup_voices() argument
254 val = snd_emu10k1_ptr_read(hw, CVCF_CURRENTVOL, vp->ch); lookup_voices()
269 val = snd_emu10k1_ptr_read(hw, CCCA_CURRADDR, vp->ch); lookup_voices()
289 struct snd_emu10k1 *hw; get_voice() local
294 hw = emu->hw; get_voice()
296 lookup_voices(emu, hw, best, 0); get_voice()
303 if (snd_emu10k1_voice_alloc(hw, EMU10K1_SYNTH, 1, &hwvoice) < 0 || hwvoice == NULL) get_voice()
326 struct snd_emu10k1 *hw; start_voice() local
329 hw = vp->hw; start_voice()
339 if (snd_emu10k1_memblk_map(hw, emem) < 0) { start_voice()
340 /* dev_err(hw->card->devK, "emu: cannot map!\n"); */ start_voice()
351 if (hw->audigy) { start_voice()
354 snd_emu10k1_ptr_write(hw, A_FXRT1, ch, temp); start_voice()
358 snd_emu10k1_ptr_write(hw, FXRT, ch, temp); start_voice()
362 snd_emu10k1_ptr_write(hw, DCYSUSV, ch, 0x0000); start_voice()
363 snd_emu10k1_ptr_write(hw, VTFT, ch, 0x0000FFFF); start_voice()
364 snd_emu10k1_ptr_write(hw, CVCF, ch, 0x0000FFFF); start_voice()
365 snd_emu10k1_ptr_write(hw, PTRX, ch, 0); start_voice()
366 snd_emu10k1_ptr_write(hw, CPF, ch, 0); start_voice()
369 snd_emu10k1_ptr_write(hw, IP, vp->ch, vp->apitch); start_voice()
372 snd_emu10k1_ptr_write(hw, ENVVAL, ch, vp->reg.parm.moddelay); start_voice()
373 snd_emu10k1_ptr_write(hw, ATKHLDM, ch, vp->reg.parm.modatkhld); start_voice()
374 snd_emu10k1_ptr_write(hw, DCYSUSM, ch, vp->reg.parm.moddcysus); start_voice()
375 snd_emu10k1_ptr_write(hw, ENVVOL, ch, vp->reg.parm.voldelay); start_voice()
376 snd_emu10k1_ptr_write(hw, ATKHLDV, ch, vp->reg.parm.volatkhld); start_voice()
382 snd_emu10k1_ptr_write(hw, IFATN, vp->ch, temp); start_voice()
385 snd_emu10k1_ptr_write(hw, PEFE, ch, vp->reg.parm.pefe); start_voice()
388 snd_emu10k1_ptr_write(hw, LFOVAL1, ch, vp->reg.parm.lfo1delay); start_voice()
389 snd_emu10k1_ptr_write(hw, LFOVAL2, ch, vp->reg.parm.lfo2delay); start_voice()
392 set_fmmod(hw, vp); start_voice()
394 snd_emu10k1_ptr_write(hw, TREMFRQ, vp->ch, vp->reg.parm.tremfrq); start_voice()
396 set_fm2frq2(hw, vp); start_voice()
403 snd_emu10k1_ptr_write(hw, PSST, vp->ch, (temp << 24) | addr); start_voice()
411 snd_emu10k1_ptr_write(hw, DSL, ch, temp); start_voice()
414 snd_emu10k1_ptr_write(hw, Z1, ch, 0); start_voice()
415 snd_emu10k1_ptr_write(hw, Z2, ch, 0); start_voice()
418 temp = (hw->silent_page.addr << hw->address_mode) | (hw->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); start_voice()
419 snd_emu10k1_ptr_write(hw, MAPA, ch, temp); start_voice()
420 snd_emu10k1_ptr_write(hw, MAPB, ch, temp); start_voice()
434 snd_emu10k1_ptr_write(hw, CCR, ch, 0x1c << 16); start_voice()
435 snd_emu10k1_ptr_write(hw, CDE, ch, sample); start_voice()
436 snd_emu10k1_ptr_write(hw, CDF, ch, sample); start_voice()
439 temp = ((unsigned int)hw->silent_page.addr << hw_address_mode) | (hw->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0); start_voice()
440 snd_emu10k1_ptr_write(hw, MAPA, ch, temp); start_voice()
441 snd_emu10k1_ptr_write(hw, MAPB, ch, temp); start_voice()
447 snd_emu10k1_ptr_write(hw, CCR, ch, val); start_voice()
463 snd_emu10k1_ptr_write(hw, CCCA, ch, temp); start_voice()
467 snd_emu10k1_ptr_write(hw, VTFT, ch, temp | vp->ftarget); start_voice()
468 snd_emu10k1_ptr_write(hw, CVCF, ch, temp | 0xff00); start_voice()
479 struct snd_emu10k1 *hw; trigger_voice() local
482 hw = vp->hw; trigger_voice()
495 snd_emu10k1_ptr_write(hw, PTRX, vp->ch, temp); trigger_voice()
498 snd_emu10k1_ptr_write(hw, CPF, vp->ch, ptarget); trigger_voice()
501 snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, vp->reg.parm.voldcysus|DCYSUSV_CHANNELENABLE_MASK); trigger_voice()
508 set_fmmod(struct snd_emu10k1 *hw, struct snd_emux_voice *vp) set_fmmod() argument
521 snd_emu10k1_ptr_write(hw, FMMOD, vp->ch, fmmod); set_fmmod()
526 set_fm2frq2(struct snd_emu10k1 *hw, struct snd_emux_voice *vp) set_fm2frq2() argument
539 snd_emu10k1_ptr_write(hw, FM2FRQ2, vp->ch, fm2frq2); set_fm2frq2()
544 set_filterQ(struct snd_emu10k1 *hw, struct snd_emux_voice *vp) set_filterQ() argument
547 val = snd_emu10k1_ptr_read(hw, CCCA, vp->ch) & ~CCCA_RESONANCE; set_filterQ()
549 snd_emu10k1_ptr_write(hw, CCCA, vp->ch, val); set_filterQ()
H A Demu10k1_synth.c36 struct snd_emu10k1 *hw; snd_emu10k1_synth_probe() local
55 hw = arg->hwptr; snd_emu10k1_synth_probe()
56 emux->hw = hw; snd_emu10k1_synth_probe()
60 emux->memhdr = hw->memhdr; snd_emu10k1_synth_probe()
64 emux->midi_devidx = hw->audigy ? 2 : 1; snd_emu10k1_synth_probe()
73 spin_lock_irqsave(&hw->voice_lock, flags); snd_emu10k1_synth_probe()
74 hw->synth = emux; snd_emu10k1_synth_probe()
75 hw->get_synth_voice = snd_emu10k1_synth_get_voice; snd_emu10k1_synth_probe()
76 spin_unlock_irqrestore(&hw->voice_lock, flags); snd_emu10k1_synth_probe()
87 struct snd_emu10k1 *hw; snd_emu10k1_synth_remove() local
95 hw = emux->hw; snd_emu10k1_synth_remove()
96 spin_lock_irqsave(&hw->voice_lock, flags); snd_emu10k1_synth_remove()
97 hw->synth = NULL; snd_emu10k1_synth_remove()
98 hw->get_synth_voice = NULL; snd_emu10k1_synth_remove()
99 spin_unlock_irqrestore(&hw->voice_lock, flags); snd_emu10k1_synth_remove()
/linux-4.4.14/drivers/clk/tegra/
H A Dclk-periph.c24 static u8 clk_periph_get_parent(struct clk_hw *hw) clk_periph_get_parent() argument
26 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_get_parent()
28 struct clk_hw *mux_hw = &periph->mux.hw; clk_periph_get_parent()
30 __clk_hw_set_clk(mux_hw, hw); clk_periph_get_parent()
35 static int clk_periph_set_parent(struct clk_hw *hw, u8 index) clk_periph_set_parent() argument
37 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_set_parent()
39 struct clk_hw *mux_hw = &periph->mux.hw; clk_periph_set_parent()
41 __clk_hw_set_clk(mux_hw, hw); clk_periph_set_parent()
46 static unsigned long clk_periph_recalc_rate(struct clk_hw *hw, clk_periph_recalc_rate() argument
49 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_recalc_rate()
51 struct clk_hw *div_hw = &periph->divider.hw; clk_periph_recalc_rate()
53 __clk_hw_set_clk(div_hw, hw); clk_periph_recalc_rate()
58 static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate, clk_periph_round_rate() argument
61 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_round_rate()
63 struct clk_hw *div_hw = &periph->divider.hw; clk_periph_round_rate()
65 __clk_hw_set_clk(div_hw, hw); clk_periph_round_rate()
70 static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate, clk_periph_set_rate() argument
73 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_set_rate()
75 struct clk_hw *div_hw = &periph->divider.hw; clk_periph_set_rate()
77 __clk_hw_set_clk(div_hw, hw); clk_periph_set_rate()
82 static int clk_periph_is_enabled(struct clk_hw *hw) clk_periph_is_enabled() argument
84 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_is_enabled()
86 struct clk_hw *gate_hw = &periph->gate.hw; clk_periph_is_enabled()
88 __clk_hw_set_clk(gate_hw, hw); clk_periph_is_enabled()
93 static int clk_periph_enable(struct clk_hw *hw) clk_periph_enable() argument
95 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_enable()
97 struct clk_hw *gate_hw = &periph->gate.hw; clk_periph_enable()
99 __clk_hw_set_clk(gate_hw, hw); clk_periph_enable()
104 static void clk_periph_disable(struct clk_hw *hw) clk_periph_disable() argument
106 struct tegra_clk_periph *periph = to_clk_periph(hw); clk_periph_disable()
108 struct clk_hw *gate_hw = &periph->gate.hw; clk_periph_disable()
169 periph->hw.init = &init; _tegra_clk_register_periph()
177 clk = clk_register(NULL, &periph->hw); _tegra_clk_register_periph()
181 periph->mux.hw.clk = clk; _tegra_clk_register_periph()
182 periph->divider.hw.clk = div ? clk : NULL; _tegra_clk_register_periph()
183 periph->gate.hw.clk = clk; _tegra_clk_register_periph()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192c/
H A Dphy_common.c38 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl92c_phy_query_bb_reg() argument
40 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_query_bb_reg()
57 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw, rtl92c_phy_set_bb_reg() argument
60 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_set_bb_reg()
81 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, _rtl92c_phy_fw_rf_serial_read() argument
89 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw, _rtl92c_phy_fw_rf_serial_write() argument
97 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw, _rtl92c_phy_rf_serial_read() argument
100 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_rf_serial_read()
110 if (RT_CANNOT_IO(hw)) { _rtl92c_phy_rf_serial_read()
114 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92c_phy_rf_serial_read()
118 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92c_phy_rf_serial_read()
121 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92c_phy_rf_serial_read()
124 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92c_phy_rf_serial_read()
126 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92c_phy_rf_serial_read()
130 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, _rtl92c_phy_rf_serial_read()
133 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, _rtl92c_phy_rf_serial_read()
136 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, _rtl92c_phy_rf_serial_read()
139 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, _rtl92c_phy_rf_serial_read()
148 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, _rtl92c_phy_rf_serial_write() argument
154 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_rf_serial_write()
158 if (RT_CANNOT_IO(hw)) { _rtl92c_phy_rf_serial_write()
165 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92c_phy_rf_serial_write()
184 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw) _rtl92c_phy_bb_config_1t() argument
186 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); _rtl92c_phy_bb_config_1t()
187 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); _rtl92c_phy_bb_config_1t()
188 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); _rtl92c_phy_bb_config_1t()
189 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); _rtl92c_phy_bb_config_1t()
190 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); _rtl92c_phy_bb_config_1t()
191 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); _rtl92c_phy_bb_config_1t()
192 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); _rtl92c_phy_bb_config_1t()
193 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); _rtl92c_phy_bb_config_1t()
194 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); _rtl92c_phy_bb_config_1t()
195 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); _rtl92c_phy_bb_config_1t()
198 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw) rtl92c_phy_rf_config() argument
200 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_rf_config()
202 return rtlpriv->cfg->ops->phy_rf6052_config(hw); rtl92c_phy_rf_config()
206 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw) _rtl92c_phy_bb8192c_config_parafile() argument
208 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_bb8192c_config_parafile()
210 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92c_phy_bb8192c_config_parafile()
213 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw, _rtl92c_phy_bb8192c_config_parafile()
220 _rtl92c_phy_bb_config_1t(hw); _rtl92c_phy_bb8192c_config_parafile()
225 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw, _rtl92c_phy_bb8192c_config_parafile()
232 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw, _rtl92c_phy_bb8192c_config_parafile()
239 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); _rtl92c_phy_bb8192c_config_parafile()
246 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw, _rtl92c_store_pwrIndex_diffrate_offset() argument
250 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_store_pwrIndex_diffrate_offset()
402 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) rtl92c_phy_get_hw_reg_originalvalue() argument
404 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_get_hw_reg_originalvalue()
408 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); rtl92c_phy_get_hw_reg_originalvalue()
410 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); rtl92c_phy_get_hw_reg_originalvalue()
412 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); rtl92c_phy_get_hw_reg_originalvalue()
414 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); rtl92c_phy_get_hw_reg_originalvalue()
423 rtlphy->framesync = (u8)rtl_get_bbreg(hw, rtl92c_phy_get_hw_reg_originalvalue()
425 rtlphy->framesync_c34 = rtl_get_bbreg(hw, rtl92c_phy_get_hw_reg_originalvalue()
433 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) _rtl92c_phy_init_bb_rf_register_definition() argument
435 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_init_bb_rf_register_definition()
521 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) rtl92c_phy_get_txpower_level() argument
523 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_get_txpower_level()
525 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92c_phy_get_txpower_level()
530 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, rtl92c_phy_get_txpower_level()
534 if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, rtl92c_phy_get_txpower_level()
537 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, rtl92c_phy_get_txpower_level()
540 if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, rtl92c_phy_get_txpower_level()
543 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, rtl92c_phy_get_txpower_level()
548 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel, _rtl92c_get_txpower_index() argument
551 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_get_txpower_index()
553 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); _rtl92c_get_txpower_index()
573 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw, _rtl92c_ccxpower_index_check() argument
577 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_ccxpower_index_check()
584 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) rtl92c_phy_set_txpower_level() argument
586 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_set_txpower_level()
587 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92c_phy_set_txpower_level()
592 _rtl92c_get_txpower_index(hw, channel, rtl92c_phy_set_txpower_level()
594 _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0], rtl92c_phy_set_txpower_level()
596 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); rtl92c_phy_set_txpower_level()
597 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], rtl92c_phy_set_txpower_level()
602 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm) rtl92c_phy_update_txpower_dbm() argument
604 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_update_txpower_dbm()
606 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92c_phy_update_txpower_dbm()
609 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B, rtl92c_phy_update_txpower_dbm()
611 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G, rtl92c_phy_update_txpower_dbm()
629 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); rtl92c_phy_update_txpower_dbm()
634 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw, _rtl92c_phy_dbm_to_txpwr_idx() argument
666 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, _rtl92c_phy_txpwr_idx_to_dbm() argument
690 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw, rtl92c_phy_set_bw_mode() argument
693 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_set_bw_mode()
695 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_set_bw_mode()
701 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl92c_phy_set_bw_mode()
702 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw); rtl92c_phy_set_bw_mode()
712 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw) rtl92c_phy_sw_chnl_callback() argument
714 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_sw_chnl_callback()
715 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_sw_chnl_callback()
727 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, rtl92c_phy_sw_chnl_callback()
742 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw) rtl92c_phy_sw_chnl() argument
744 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_sw_chnl()
746 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_sw_chnl()
757 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { rtl92c_phy_sw_chnl()
758 rtl92c_phy_sw_chnl_callback(hw); rtl92c_phy_sw_chnl()
771 static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel) _rtl92c_phy_sw_rf_seting() argument
773 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_sw_rf_seting()
775 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92c_phy_sw_rf_seting()
779 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, _rtl92c_phy_sw_rf_seting()
783 (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1, _rtl92c_phy_sw_rf_seting()
785 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, _rtl92c_phy_sw_rf_seting()
814 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, _rtl92c_phy_sw_chnl_step_by_step() argument
818 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_sw_chnl_step_by_step()
884 rtl92c_phy_set_txpower_level(hw, channel); _rtl92c_phy_sw_chnl_step_by_step()
904 rtl_set_rfreg(hw, (enum radio_path)rfpath, _rtl92c_phy_sw_chnl_step_by_step()
909 _rtl92c_phy_sw_rf_seting(hw, channel); _rtl92c_phy_sw_chnl_step_by_step()
925 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath) rtl8192_phy_check_is_legal_rfpath() argument
931 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) _rtl92c_phy_path_a_iqk() argument
936 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); _rtl92c_phy_path_a_iqk()
937 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); _rtl92c_phy_path_a_iqk()
938 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); _rtl92c_phy_path_a_iqk()
939 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, _rtl92c_phy_path_a_iqk()
943 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); _rtl92c_phy_path_a_iqk()
944 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); _rtl92c_phy_path_a_iqk()
945 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); _rtl92c_phy_path_a_iqk()
946 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); _rtl92c_phy_path_a_iqk()
949 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); _rtl92c_phy_path_a_iqk()
950 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl92c_phy_path_a_iqk()
951 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92c_phy_path_a_iqk()
955 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92c_phy_path_a_iqk()
956 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92c_phy_path_a_iqk()
957 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92c_phy_path_a_iqk()
958 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl92c_phy_path_a_iqk()
974 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw) _rtl92c_phy_path_b_iqk() argument
979 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl92c_phy_path_b_iqk()
980 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl92c_phy_path_b_iqk()
982 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92c_phy_path_b_iqk()
983 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92c_phy_path_b_iqk()
984 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92c_phy_path_b_iqk()
985 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl92c_phy_path_b_iqk()
986 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl92c_phy_path_b_iqk()
1001 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl92c_phy_path_a_fill_iqk_matrix() argument
1011 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, _rtl92c_phy_path_a_fill_iqk_matrix()
1017 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); _rtl92c_phy_path_a_fill_iqk_matrix()
1018 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), _rtl92c_phy_path_a_fill_iqk_matrix()
1024 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, _rtl92c_phy_path_a_fill_iqk_matrix()
1026 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, _rtl92c_phy_path_a_fill_iqk_matrix()
1028 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), _rtl92c_phy_path_a_fill_iqk_matrix()
1033 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); _rtl92c_phy_path_a_fill_iqk_matrix()
1035 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); _rtl92c_phy_path_a_fill_iqk_matrix()
1037 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); _rtl92c_phy_path_a_fill_iqk_matrix()
1041 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw, _rtl92c_phy_path_b_fill_iqk_matrix() argument
1051 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, _rtl92c_phy_path_b_fill_iqk_matrix()
1057 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); _rtl92c_phy_path_b_fill_iqk_matrix()
1058 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), _rtl92c_phy_path_b_fill_iqk_matrix()
1064 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, _rtl92c_phy_path_b_fill_iqk_matrix()
1066 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, _rtl92c_phy_path_b_fill_iqk_matrix()
1068 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), _rtl92c_phy_path_b_fill_iqk_matrix()
1073 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); _rtl92c_phy_path_b_fill_iqk_matrix()
1075 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); _rtl92c_phy_path_b_fill_iqk_matrix()
1077 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); _rtl92c_phy_path_b_fill_iqk_matrix()
1081 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw, _rtl92c_phy_save_adda_registers() argument
1088 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); _rtl92c_phy_save_adda_registers()
1091 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw, _rtl92c_phy_save_mac_registers() argument
1094 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_save_mac_registers()
1102 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw, _rtl92c_phy_reload_adda_registers() argument
1109 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); _rtl92c_phy_reload_adda_registers()
1112 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw, _rtl92c_phy_reload_mac_registers() argument
1115 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_reload_mac_registers()
1123 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw, _rtl92c_phy_path_adda_on() argument
1132 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); _rtl92c_phy_path_adda_on()
1134 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn); _rtl92c_phy_path_adda_on()
1138 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn); _rtl92c_phy_path_adda_on()
1141 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw, _rtl92c_phy_mac_setting_calibration() argument
1144 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_mac_setting_calibration()
1155 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw) _rtl92c_phy_path_a_standby() argument
1157 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl92c_phy_path_a_standby()
1158 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl92c_phy_path_a_standby()
1159 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92c_phy_path_a_standby()
1162 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) _rtl92c_phy_pi_mode_switch() argument
1167 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); _rtl92c_phy_pi_mode_switch()
1168 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); _rtl92c_phy_pi_mode_switch()
1171 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw, _rtl92c_phy_simularity_compare() argument
1175 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92c_phy_simularity_compare()
1230 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, _rtl92c_phy_iq_calibrate() argument
1233 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_iq_calibrate()
1250 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); _rtl92c_phy_iq_calibrate()
1252 _rtl92c_phy_save_adda_registers(hw, adda_reg, _rtl92c_phy_iq_calibrate()
1254 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg, _rtl92c_phy_iq_calibrate()
1257 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t); _rtl92c_phy_iq_calibrate()
1260 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, _rtl92c_phy_iq_calibrate()
1265 _rtl92c_phy_pi_mode_switch(hw, true); _rtl92c_phy_iq_calibrate()
1267 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); _rtl92c_phy_iq_calibrate()
1268 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); _rtl92c_phy_iq_calibrate()
1269 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); _rtl92c_phy_iq_calibrate()
1271 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl92c_phy_iq_calibrate()
1272 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl92c_phy_iq_calibrate()
1273 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl92c_phy_iq_calibrate()
1275 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl92c_phy_iq_calibrate()
1276 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); _rtl92c_phy_iq_calibrate()
1278 _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg, _rtl92c_phy_iq_calibrate()
1280 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); _rtl92c_phy_iq_calibrate()
1282 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); _rtl92c_phy_iq_calibrate()
1283 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92c_phy_iq_calibrate()
1284 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl92c_phy_iq_calibrate()
1285 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl92c_phy_iq_calibrate()
1287 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t); _rtl92c_phy_iq_calibrate()
1289 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1291 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1293 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1295 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1300 result[t][0] = (rtl_get_bbreg(hw, 0xe94, _rtl92c_phy_iq_calibrate()
1304 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; _rtl92c_phy_iq_calibrate()
1309 _rtl92c_phy_path_a_standby(hw); _rtl92c_phy_iq_calibrate()
1310 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t); _rtl92c_phy_iq_calibrate()
1312 pathb_ok = _rtl92c_phy_path_b_iqk(hw); _rtl92c_phy_iq_calibrate()
1314 result[t][4] = (rtl_get_bbreg(hw, _rtl92c_phy_iq_calibrate()
1319 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1322 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1325 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1329 result[t][4] = (rtl_get_bbreg(hw, _rtl92c_phy_iq_calibrate()
1334 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92c_phy_iq_calibrate()
1338 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); _rtl92c_phy_iq_calibrate()
1339 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); _rtl92c_phy_iq_calibrate()
1340 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); _rtl92c_phy_iq_calibrate()
1341 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl92c_phy_iq_calibrate()
1342 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); _rtl92c_phy_iq_calibrate()
1344 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); _rtl92c_phy_iq_calibrate()
1347 _rtl92c_phy_pi_mode_switch(hw, false); _rtl92c_phy_iq_calibrate()
1348 _rtl92c_phy_reload_adda_registers(hw, adda_reg, _rtl92c_phy_iq_calibrate()
1350 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg, _rtl92c_phy_iq_calibrate()
1355 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, _rtl92c_phy_ap_calibrate() argument
1360 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, _rtl92c_phy_set_rfpath_switch() argument
1363 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl92c_phy_set_rfpath_switch()
1366 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); _rtl92c_phy_set_rfpath_switch()
1367 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); _rtl92c_phy_set_rfpath_switch()
1371 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl92c_phy_set_rfpath_switch()
1374 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, _rtl92c_phy_set_rfpath_switch()
1378 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); _rtl92c_phy_set_rfpath_switch()
1380 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); _rtl92c_phy_set_rfpath_switch()
1387 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) rtl92c_phy_iq_calibrate() argument
1389 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_iq_calibrate()
1391 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_iq_calibrate()
1413 _rtl92c_phy_reload_adda_registers(hw, rtl92c_phy_iq_calibrate()
1432 _rtl92c_phy_iq_calibrate(hw, result, i, true); rtl92c_phy_iq_calibrate()
1434 _rtl92c_phy_iq_calibrate(hw, result, i, false); rtl92c_phy_iq_calibrate()
1436 is12simular = _rtl92c_phy_simularity_compare(hw, rtl92c_phy_iq_calibrate()
1445 is13simular = _rtl92c_phy_simularity_compare(hw, rtl92c_phy_iq_calibrate()
1452 is23simular = _rtl92c_phy_simularity_compare(hw, rtl92c_phy_iq_calibrate()
1494 _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, rtl92c_phy_iq_calibrate()
1499 _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, rtl92c_phy_iq_calibrate()
1504 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg, rtl92c_phy_iq_calibrate()
1509 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw) rtl92c_phy_lc_calibrate() argument
1511 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_lc_calibrate()
1512 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_lc_calibrate()
1515 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true); rtl92c_phy_lc_calibrate()
1517 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false); rtl92c_phy_lc_calibrate()
1521 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) rtl92c_phy_ap_calibrate() argument
1523 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_ap_calibrate()
1525 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_ap_calibrate()
1530 _rtl92c_phy_ap_calibrate(hw, delta, true); rtl92c_phy_ap_calibrate()
1532 _rtl92c_phy_ap_calibrate(hw, delta, false); rtl92c_phy_ap_calibrate()
1536 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) rtl92c_phy_set_rfpath_switch() argument
1538 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_phy_set_rfpath_switch()
1541 _rtl92c_phy_set_rfpath_switch(hw, bmain, true); rtl92c_phy_set_rfpath_switch()
1543 _rtl92c_phy_set_rfpath_switch(hw, bmain, false); rtl92c_phy_set_rfpath_switch()
1547 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) rtl92c_phy_set_io_cmd() argument
1549 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_set_io_cmd()
1580 rtl92c_phy_set_io(hw); rtl92c_phy_set_io_cmd()
1586 void rtl92c_phy_set_io(struct ieee80211_hw *hw) rtl92c_phy_set_io() argument
1588 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_phy_set_io()
1598 rtl92c_dm_write_dig(hw); rtl92c_phy_set_io()
1599 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); rtl92c_phy_set_io()
1604 rtl92c_dm_write_dig(hw); rtl92c_phy_set_io()
1617 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw) rtl92ce_phy_set_rf_on() argument
1619 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92ce_phy_set_rf_on()
1630 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw) _rtl92c_phy_set_rf_sleep() argument
1634 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl92c_phy_set_rf_sleep()
1637 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92c_phy_set_rf_sleep()
1639 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl92c_phy_set_rf_sleep()
1642 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); _rtl92c_phy_set_rf_sleep()
1644 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); _rtl92c_phy_set_rf_sleep()
H A Dphy_common.h39 #define RT_CANNOT_IO(hw) false
188 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
190 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
192 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
195 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
196 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
197 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
198 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
200 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
201 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
203 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
204 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
206 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
208 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
209 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
210 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
211 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
213 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
214 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
215 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
216 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
218 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
220 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
222 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
223 void rtl92c_phy_set_io(struct ieee80211_hw *hw);
224 void rtl92c_bb_block_on(struct ieee80211_hw *hw);
226 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
229 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
232 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
233 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
234 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
237 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw);
238 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
240 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
243 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
245 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
248 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
249 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
252 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
H A Ddm_common.c165 void dm_restorepowerindex(struct ieee80211_hw *hw) dm_restorepowerindex() argument
167 struct rtl_priv *rtlpriv = rtl_priv(hw); dm_restorepowerindex()
176 void dm_writepowerindex(struct ieee80211_hw *hw, u8 value) dm_writepowerindex() argument
178 struct rtl_priv *rtlpriv = rtl_priv(hw); dm_writepowerindex()
186 void dm_savepowerindex(struct ieee80211_hw *hw) dm_savepowerindex() argument
188 struct rtl_priv *rtlpriv = rtl_priv(hw); dm_savepowerindex()
199 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) rtl92c_dm_initial_gain_min_pwdb() argument
201 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_initial_gain_min_pwdb()
227 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) rtl92c_dm_false_alarm_counter_statistics() argument
230 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_false_alarm_counter_statistics()
233 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics()
236 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics()
240 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics()
243 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics()
254 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); rtl92c_dm_false_alarm_counter_statistics()
255 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); rtl92c_dm_false_alarm_counter_statistics()
258 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); rtl92c_dm_false_alarm_counter_statistics()
266 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); rtl92c_dm_false_alarm_counter_statistics()
267 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); rtl92c_dm_false_alarm_counter_statistics()
268 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); rtl92c_dm_false_alarm_counter_statistics()
269 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); rtl92c_dm_false_alarm_counter_statistics()
283 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw) rtl92c_dm_ctrl_initgain_by_fa() argument
285 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_ctrl_initgain_by_fa()
307 rtl92c_dm_write_dig(hw); rtl92c_dm_ctrl_initgain_by_fa()
310 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) rtl92c_dm_ctrl_initgain_by_rssi() argument
312 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_ctrl_initgain_by_rssi()
389 rtl92c_dm_write_dig(hw); rtl92c_dm_ctrl_initgain_by_rssi()
392 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) rtl92c_dm_initial_gain_multi_sta() argument
395 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_initial_gain_multi_sta()
397 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_initial_gain_multi_sta()
413 rtl92c_dm_write_dig(hw); rtl92c_dm_initial_gain_multi_sta()
423 rtl92c_dm_write_dig(hw); rtl92c_dm_initial_gain_multi_sta()
429 rtl92c_dm_ctrl_initgain_by_fa(hw); rtl92c_dm_initial_gain_multi_sta()
434 rtl92c_dm_write_dig(hw); rtl92c_dm_initial_gain_multi_sta()
443 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw) rtl92c_dm_initial_gain_sta() argument
445 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_initial_gain_sta()
457 rtl92c_dm_initial_gain_min_pwdb(hw); rtl92c_dm_initial_gain_sta()
460 rtl92c_dm_ctrl_initgain_by_rssi(hw); rtl92c_dm_initial_gain_sta()
468 rtl92c_dm_write_dig(hw); rtl92c_dm_initial_gain_sta()
472 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) rtl92c_dm_cck_packet_detection_thresh() argument
474 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_cck_packet_detection_thresh()
478 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw); rtl92c_dm_cck_packet_detection_thresh()
504 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); rtl92c_dm_cck_packet_detection_thresh()
506 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); rtl92c_dm_cck_packet_detection_thresh()
512 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) rtl92c_dm_ctrl_initgain_by_twoport() argument
514 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_ctrl_initgain_by_twoport()
516 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_ctrl_initgain_by_twoport()
528 rtl92c_dm_initial_gain_sta(hw); rtl92c_dm_ctrl_initgain_by_twoport()
529 rtl92c_dm_initial_gain_multi_sta(hw); rtl92c_dm_ctrl_initgain_by_twoport()
530 rtl92c_dm_cck_packet_detection_thresh(hw); rtl92c_dm_ctrl_initgain_by_twoport()
536 static void rtl92c_dm_dig(struct ieee80211_hw *hw) rtl92c_dm_dig() argument
538 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_dig()
545 rtl92c_dm_ctrl_initgain_by_twoport(hw); rtl92c_dm_dig()
548 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw) rtl92c_dm_init_dynamic_txpower() argument
550 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_init_dynamic_txpower()
554 dm_savepowerindex(hw); rtl92c_dm_init_dynamic_txpower()
563 void rtl92c_dm_write_dig(struct ieee80211_hw *hw) rtl92c_dm_write_dig() argument
565 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_write_dig()
583 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, rtl92c_dm_write_dig()
585 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, rtl92c_dm_write_dig()
599 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw) rtl92c_dm_pwdb_monitor() argument
601 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_pwdb_monitor()
602 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_pwdb_monitor()
627 * rtl8192c_set_rssi_cmd(hw, param); rtl92c_dm_pwdb_monitor()
633 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw) rtl92c_dm_init_edca_turbo() argument
635 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_init_edca_turbo()
642 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw) rtl92c_dm_check_edca_turbo() argument
644 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_check_edca_turbo()
645 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_dm_check_edca_turbo()
646 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_check_edca_turbo()
715 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, rtl92c_dm_check_edca_turbo()
727 *hw) rtl92c_dm_txpower_tracking_callback_thermalmeter()
729 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_txpower_tracking_callback_thermalmeter()
730 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_dm_txpower_tracking_callback_thermalmeter()
732 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); rtl92c_dm_txpower_tracking_callback_thermalmeter()
747 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f); rtl92c_dm_txpower_tracking_callback_thermalmeter()
754 rtl92c_phy_ap_calibrate(hw, (thermalvalue - rtl92c_dm_txpower_tracking_callback_thermalmeter()
762 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, rtl92c_dm_txpower_tracking_callback_thermalmeter()
778 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, rtl92c_dm_txpower_tracking_callback_thermalmeter()
796 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; rtl92c_dm_txpower_tracking_callback_thermalmeter()
862 rtl92c_phy_lc_calibrate(hw); rtl92c_dm_txpower_tracking_callback_thermalmeter()
1006 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1010 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1014 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1018 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1021 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1025 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1027 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1103 rtl_set_bbreg(hw, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1108 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1112 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1116 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1119 rtl_set_bbreg(hw, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1124 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1126 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, rtl92c_dm_txpower_tracking_callback_thermalmeter()
1135 rtl92c_phy_iq_calibrate(hw, false); rtl92c_dm_txpower_tracking_callback_thermalmeter()
1147 struct ieee80211_hw *hw) rtl92c_dm_initialize_txpower_tracking_thermalmeter()
1149 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_initialize_txpower_tracking_thermalmeter()
1159 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) rtl92c_dm_initialize_txpower_tracking() argument
1161 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw); rtl92c_dm_initialize_txpower_tracking()
1164 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw) rtl92c_dm_txpower_tracking_directcall() argument
1166 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw); rtl92c_dm_txpower_tracking_directcall()
1170 struct ieee80211_hw *hw) rtl92c_dm_check_txpower_tracking_thermal_meter()
1172 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_check_txpower_tracking_thermal_meter()
1178 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK, rtl92c_dm_check_txpower_tracking_thermal_meter()
1187 rtl92c_dm_txpower_tracking_directcall(hw); rtl92c_dm_check_txpower_tracking_thermal_meter()
1192 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw) rtl92c_dm_check_txpower_tracking() argument
1194 rtl92c_dm_check_txpower_tracking_thermal_meter(hw); rtl92c_dm_check_txpower_tracking()
1198 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) rtl92c_dm_init_rate_adaptive_mask() argument
1200 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_init_rate_adaptive_mask()
1214 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw) rtl92c_dm_init_dynamic_bb_powersaving() argument
1216 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_init_dynamic_bb_powersaving()
1226 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal) rtl92c_dm_rf_saving() argument
1228 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_rf_saving()
1232 rtlpriv->reg_874 = (rtl_get_bbreg(hw, rtl92c_dm_rf_saving()
1236 rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, rtl92c_dm_rf_saving()
1239 rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, rtl92c_dm_rf_saving()
1242 rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & rtl92c_dm_rf_saving()
1270 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl92c_dm_rf_saving()
1272 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); rtl92c_dm_rf_saving()
1273 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, rtl92c_dm_rf_saving()
1275 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl92c_dm_rf_saving()
1277 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3); rtl92c_dm_rf_saving()
1278 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); rtl92c_dm_rf_saving()
1279 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); rtl92c_dm_rf_saving()
1281 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, rtl92c_dm_rf_saving()
1283 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), rtl92c_dm_rf_saving()
1285 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, rtl92c_dm_rf_saving()
1287 rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74); rtl92c_dm_rf_saving()
1288 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); rtl92c_dm_rf_saving()
1296 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw) rtl92c_dm_dynamic_bb_powersaving() argument
1298 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_dynamic_bb_powersaving()
1300 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_dynamic_bb_powersaving()
1301 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_dm_dynamic_bb_powersaving()
1334 ;/* rtl92c_dm_1r_cca(hw); */ rtl92c_dm_dynamic_bb_powersaving()
1336 rtl92c_dm_rf_saving(hw, false); rtl92c_dm_dynamic_bb_powersaving()
1339 void rtl92c_dm_init(struct ieee80211_hw *hw) rtl92c_dm_init() argument
1341 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_init()
1348 rtl_dm_diginit(hw, 0x20); rtl92c_dm_init()
1351 rtl92c_dm_init_dynamic_txpower(hw); rtl92c_dm_init()
1353 rtl92c_dm_init_edca_turbo(hw); rtl92c_dm_init()
1354 rtl92c_dm_init_rate_adaptive_mask(hw); rtl92c_dm_init()
1356 rtl92c_dm_initialize_txpower_tracking(hw); rtl92c_dm_init()
1357 rtl92c_dm_init_dynamic_bb_powersaving(hw); rtl92c_dm_init()
1364 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw) rtl92c_dm_dynamic_txpower() argument
1366 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_dynamic_txpower()
1368 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl92c_dm_dynamic_txpower()
1430 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); rtl92c_dm_dynamic_txpower()
1433 dm_restorepowerindex(hw); rtl92c_dm_dynamic_txpower()
1436 dm_writepowerindex(hw, 0x14); rtl92c_dm_dynamic_txpower()
1439 dm_writepowerindex(hw, 0x10); rtl92c_dm_dynamic_txpower()
1444 void rtl92c_dm_watchdog(struct ieee80211_hw *hw) rtl92c_dm_watchdog() argument
1446 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_dm_watchdog()
1447 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl92c_dm_watchdog()
1451 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, rtl92c_dm_watchdog()
1453 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, rtl92c_dm_watchdog()
1462 rtl92c_dm_pwdb_monitor(hw); rtl92c_dm_watchdog()
1463 rtl92c_dm_dig(hw); rtl92c_dm_watchdog()
1464 rtl92c_dm_false_alarm_counter_statistics(hw); rtl92c_dm_watchdog()
1465 rtl92c_dm_dynamic_bb_powersaving(hw); rtl92c_dm_watchdog()
1466 rtl92c_dm_dynamic_txpower(hw); rtl92c_dm_watchdog()
1467 rtl92c_dm_check_txpower_tracking(hw); rtl92c_dm_watchdog()
1468 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */ rtl92c_dm_watchdog()
1469 rtl92c_dm_bt_coexist(hw); rtl92c_dm_watchdog()
1470 rtl92c_dm_check_edca_turbo(hw); rtl92c_dm_watchdog()
1475 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw) rtl92c_bt_rssi_state_change() argument
1477 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_bt_rssi_state_change()
1478 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_bt_rssi_state_change()
1526 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw) rtl92c_bt_state_change() argument
1528 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_bt_state_change()
1529 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_bt_state_change()
1612 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw) rtl92c_bt_wifi_connect_change() argument
1614 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_bt_wifi_connect_change()
1630 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw) rtl92c_bt_set_normal() argument
1632 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_bt_set_normal()
1633 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_bt_set_normal()
1665 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte) rtl92c_bt_ant_isolation() argument
1667 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_bt_ant_isolation()
1668 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_bt_ant_isolation()
1700 rtl92c_bt_set_normal(hw); rtl92c_bt_ant_isolation()
1707 rtlpriv->cfg->ops->set_rfreg(hw, rtl92c_bt_ant_isolation()
1712 rtlpriv->cfg->ops->set_rfreg(hw, rtl92c_bt_ant_isolation()
1731 rtl92c_phy_set_txpower_level(hw, rtl92c_bt_ant_isolation()
1736 static void rtl92c_check_bt_change(struct ieee80211_hw *hw) rtl92c_check_bt_change() argument
1738 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl92c_check_bt_change()
1739 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_check_bt_change()
1740 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl92c_check_bt_change()
1748 rtl92c_bt_ant_isolation(hw, tmp1byte); rtl92c_check_bt_change()
1751 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0, rtl92c_check_bt_change()
1759 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw) rtl92c_dm_bt_coexist() argument
1761 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); rtl92c_dm_bt_coexist()
1770 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw); rtl92c_dm_bt_coexist()
1771 bt_state_change = rtl92c_bt_state_change(hw); rtl92c_dm_bt_coexist()
1772 rssi_state_change = rtl92c_bt_rssi_state_change(hw); rtl92c_dm_bt_coexist()
1775 rtl92c_check_bt_change(hw); rtl92c_dm_bt_coexist()
726 rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) rtl92c_dm_txpower_tracking_callback_thermalmeter() argument
1146 rtl92c_dm_initialize_txpower_tracking_thermalmeter( struct ieee80211_hw *hw) rtl92c_dm_initialize_txpower_tracking_thermalmeter() argument
1169 rtl92c_dm_check_txpower_tracking_thermal_meter( struct ieee80211_hw *hw) rtl92c_dm_check_txpower_tracking_thermal_meter() argument
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/
H A Dps.h31 bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
34 bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
35 bool rtl_ps_disable_nic(struct ieee80211_hw *hw);
36 void rtl_ips_nic_off(struct ieee80211_hw *hw);
37 void rtl_ips_nic_on(struct ieee80211_hw *hw);
39 void rtl_lps_enter(struct ieee80211_hw *hw);
40 void rtl_lps_leave(struct ieee80211_hw *hw);
42 void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode);
44 void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len);
47 void rtl_swlps_rf_awake(struct ieee80211_hw *hw);
48 void rtl_swlps_rf_sleep(struct ieee80211_hw *hw);
49 void rtl_p2p_ps_cmd(struct ieee80211_hw *hw , u8 p2p_ps_state);
50 void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len);
H A Defuse.h96 void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
97 void efuse_initialize(struct ieee80211_hw *hw);
98 u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
99 int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
100 void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
101 void read_efuse(struct ieee80211_hw *hw, u16 _offset,
103 void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
105 void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
107 bool efuse_shadow_update(struct ieee80211_hw *hw);
108 bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
109 void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
110 void efuse_force_write_vendor_Id(struct ieee80211_hw *hw);
111 void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
H A Dpci.c61 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, _rtl_mac_to_hwqueue() argument
64 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_mac_to_hwqueue()
80 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) _rtl_pci_update_default_setting() argument
82 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_update_default_setting()
83 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl_pci_update_default_setting()
84 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); _rtl_pci_update_default_setting()
85 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_update_default_setting()
195 struct ieee80211_hw *hw, _rtl_pci_platform_switch_device_pci_aspm()
198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_platform_switch_device_pci_aspm()
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_pci_platform_switch_device_pci_aspm()
210 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) _rtl_pci_switch_clk_req() argument
212 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_switch_clk_req()
213 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_pci_switch_clk_req()
222 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) rtl_pci_disable_aspm() argument
224 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_disable_aspm()
225 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_disable_aspm()
226 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl_pci_disable_aspm()
227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_disable_aspm()
249 _rtl_pci_switch_clk_req(hw, 0x0); rtl_pci_disable_aspm()
260 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); rtl_pci_disable_aspm()
276 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) rtl_pci_enable_aspm() argument
278 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_enable_aspm()
279 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_enable_aspm()
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl_pci_enable_aspm()
281 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_enable_aspm()
325 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); rtl_pci_enable_aspm()
328 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & rtl_pci_enable_aspm()
335 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) rtl_pci_get_amd_l1_patch() argument
337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_get_amd_l1_patch()
356 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, rtl_pci_check_buddy_priv() argument
359 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_check_buddy_priv()
360 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_check_buddy_priv()
399 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) rtl_pci_get_linkcontrol_field() argument
401 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_get_linkcontrol_field()
416 struct ieee80211_hw *hw) rtl_pci_parse_configuration()
418 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_parse_configuration()
419 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_parse_configuration()
439 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) rtl_pci_init_aspm() argument
441 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl_pci_init_aspm()
443 _rtl_pci_update_default_setting(hw); rtl_pci_init_aspm()
447 rtl_pci_enable_aspm(hw); rtl_pci_init_aspm()
454 struct ieee80211_hw *hw) _rtl_pci_io_handler_init()
456 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_io_handler_init()
470 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, _rtl_update_earlymode_info() argument
473 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_update_earlymode_info()
475 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_update_earlymode_info()
511 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) _rtl_pci_tx_chk_waitq() argument
513 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_tx_chk_waitq()
514 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl_pci_tx_chk_waitq()
515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_tx_chk_waitq()
518 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_pci_tx_chk_waitq()
553 _rtl_update_earlymode_info(hw, skb, _rtl_pci_tx_chk_waitq()
556 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); _rtl_pci_tx_chk_waitq()
562 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) _rtl_pci_tx_isr() argument
564 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_tx_isr()
565 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_tx_isr()
582 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { _rtl_pci_tx_isr()
588 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) _rtl_pci_tx_isr()
649 ieee80211_tx_status_irqsafe(hw, skb); _rtl_pci_tx_isr()
658 ieee80211_wake_queue(hw, _rtl_pci_tx_isr()
674 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, _rtl_pci_init_one_rxdesc() argument
678 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_init_one_rxdesc()
679 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_init_one_rxdesc()
702 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, _rtl_pci_init_one_rxdesc()
706 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, _rtl_pci_init_one_rxdesc()
709 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, _rtl_pci_init_one_rxdesc()
712 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, _rtl_pci_init_one_rxdesc()
732 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, _rtl_pci_rx_to_mac80211() argument
736 if (unlikely(!rtl_action_proc(hw, skb, false))) { _rtl_pci_rx_to_mac80211()
749 ieee80211_rx_irqsafe(hw, uskb); _rtl_pci_rx_to_mac80211()
751 ieee80211_rx_irqsafe(hw, skb); _rtl_pci_rx_to_mac80211()
757 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) _rtl_pci_hs_interrupt() argument
759 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_hs_interrupt()
760 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_hs_interrupt()
767 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) _rtl_pci_rx_interrupt() argument
769 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_rx_interrupt()
770 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_rx_interrupt()
800 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, _rtl_pci_rx_interrupt()
830 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, _rtl_pci_rx_interrupt()
834 rtlpriv->cfg->ops->rx_check_dma_ok(hw, _rtl_pci_rx_interrupt()
858 rtlpriv->cfg->ops->rx_command_packet(hw, stats, skb)) { _rtl_pci_rx_interrupt()
885 rtl_is_special_data(hw, skb, false, true); _rtl_pci_rx_interrupt()
888 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); _rtl_pci_rx_interrupt()
893 rtl_beacon_statistic(hw, skb); _rtl_pci_rx_interrupt()
894 rtl_p2p_info(hw, (void *)skb->data, skb->len); _rtl_pci_rx_interrupt()
896 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); _rtl_pci_rx_interrupt()
897 rtl_recognize_peer(hw, (void *)skb->data, skb->len); _rtl_pci_rx_interrupt()
905 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); _rtl_pci_rx_interrupt()
929 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, _rtl_pci_rx_interrupt()
933 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, _rtl_pci_rx_interrupt()
938 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, _rtl_pci_rx_interrupt()
951 struct ieee80211_hw *hw = dev_id; _rtl_pci_interrupt() local
952 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_interrupt()
953 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_interrupt()
954 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_pci_interrupt()
964 rtlpriv->cfg->ops->disable_interrupt(hw); _rtl_pci_interrupt()
967 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); _rtl_pci_interrupt()
1001 _rtl_pci_tx_isr(hw, MGNT_QUEUE); _rtl_pci_interrupt()
1007 _rtl_pci_tx_isr(hw, HIGH_QUEUE); _rtl_pci_interrupt()
1015 _rtl_pci_tx_isr(hw, BK_QUEUE); _rtl_pci_interrupt()
1023 _rtl_pci_tx_isr(hw, BE_QUEUE); _rtl_pci_interrupt()
1031 _rtl_pci_tx_isr(hw, VI_QUEUE); _rtl_pci_interrupt()
1039 _rtl_pci_tx_isr(hw, VO_QUEUE); _rtl_pci_interrupt()
1048 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); _rtl_pci_interrupt()
1055 _rtl_pci_rx_interrupt(hw); _rtl_pci_interrupt()
1061 _rtl_pci_rx_interrupt(hw); _rtl_pci_interrupt()
1066 _rtl_pci_rx_interrupt(hw); _rtl_pci_interrupt()
1090 _rtl_pci_hs_interrupt(hw); _rtl_pci_interrupt()
1098 rtlpriv->cfg->ops->enable_interrupt(hw); _rtl_pci_interrupt()
1103 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) _rtl_pci_irq_tasklet() argument
1105 _rtl_pci_tx_chk_waitq(hw); _rtl_pci_irq_tasklet()
1108 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) _rtl_pci_prepare_bcn_tasklet() argument
1110 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_prepare_bcn_tasklet()
1111 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_prepare_bcn_tasklet()
1112 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl_pci_prepare_bcn_tasklet()
1140 pskb = ieee80211_beacon_get(hw, mac->vif); _rtl_pci_prepare_bcn_tasklet()
1149 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, _rtl_pci_prepare_bcn_tasklet()
1157 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, _rtl_pci_prepare_bcn_tasklet()
1160 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, _rtl_pci_prepare_bcn_tasklet()
1166 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) _rtl_pci_init_trx_var() argument
1168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_init_trx_var()
1169 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_init_trx_var()
1184 *because we just need first desc in hw beacon. _rtl_pci_init_trx_var()
1192 if (!rtl_priv(hw)->use_new_trx_flow) _rtl_pci_init_trx_var()
1199 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, _rtl_pci_init_struct() argument
1202 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_init_struct()
1203 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); _rtl_pci_init_struct()
1204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_init_struct()
1205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_pci_init_struct()
1210 rtlhal->hw = hw; _rtl_pci_init_struct()
1214 _rtl_pci_init_trx_var(hw); _rtl_pci_init_struct()
1231 (unsigned long)hw); _rtl_pci_init_struct()
1234 (unsigned long)hw); _rtl_pci_init_struct()
1239 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, _rtl_pci_init_tx_ring() argument
1242 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_init_tx_ring()
1243 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_init_tx_ring()
1299 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], _rtl_pci_init_tx_ring()
1308 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) _rtl_pci_init_rx_ring() argument
1310 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_init_rx_ring()
1311 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_init_rx_ring()
1334 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, _rtl_pci_init_rx_ring()
1359 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, _rtl_pci_init_rx_ring()
1364 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, _rtl_pci_init_rx_ring()
1370 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, _rtl_pci_free_tx_ring() argument
1373 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_free_tx_ring()
1374 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_free_tx_ring()
1409 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) _rtl_pci_free_rx_ring() argument
1411 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_free_rx_ring()
1412 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_free_rx_ring()
1444 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) _rtl_pci_init_trx_ring() argument
1446 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); _rtl_pci_init_trx_ring()
1454 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); _rtl_pci_init_trx_ring()
1460 ret = _rtl_pci_init_tx_ring(hw, i, _rtl_pci_init_trx_ring()
1470 _rtl_pci_free_rx_ring(hw, rxring_idx); _rtl_pci_init_trx_ring()
1475 _rtl_pci_free_tx_ring(hw, i); _rtl_pci_init_trx_ring()
1480 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) _rtl_pci_deinit_trx_ring() argument
1486 _rtl_pci_free_rx_ring(hw, rxring_idx); _rtl_pci_deinit_trx_ring()
1490 _rtl_pci_free_tx_ring(hw, i); _rtl_pci_deinit_trx_ring()
1495 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) rtl_pci_reset_trx_ring() argument
1497 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_reset_trx_ring()
1498 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_reset_trx_ring()
1524 rtlpriv->cfg->ops->set_desc(hw, rtl_pci_reset_trx_ring()
1529 rtlpriv->cfg->ops->set_desc(hw, rtl_pci_reset_trx_ring()
1533 rtlpriv->cfg->ops->set_desc(hw, rtl_pci_reset_trx_ring()
1537 rtlpriv->cfg->ops->set_desc(hw, rtl_pci_reset_trx_ring()
1543 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, rtl_pci_reset_trx_ring()
1587 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, rtl_pci_tx_chk_waitq_insert() argument
1591 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_tx_chk_waitq_insert()
1610 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) rtl_pci_tx_chk_waitq_insert()
1626 static int rtl_pci_tx(struct ieee80211_hw *hw, rtl_pci_tx() argument
1631 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_tx()
1638 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); rtl_pci_tx()
1643 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_tx()
1651 rtl_tx_mgmt_proc(hw, skb); rtl_pci_tx()
1659 rtl_action_proc(hw, skb, true); rtl_pci_tx()
1700 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { rtl_pci_tx()
1722 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); rtl_pci_tx()
1724 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, rtl_pci_tx()
1730 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, rtl_pci_tx()
1733 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, rtl_pci_tx()
1744 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); rtl_pci_tx()
1749 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); rtl_pci_tx()
1754 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) rtl_pci_flush() argument
1756 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_flush()
1757 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_flush()
1758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl_pci_flush()
1759 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); rtl_pci_flush()
1792 static void rtl_pci_deinit(struct ieee80211_hw *hw) rtl_pci_deinit() argument
1794 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_deinit()
1795 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_deinit()
1797 _rtl_pci_deinit_trx_ring(hw); rtl_pci_deinit()
1808 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) rtl_pci_init() argument
1810 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_init()
1813 _rtl_pci_init_struct(hw, pdev); rtl_pci_init()
1815 err = _rtl_pci_init_trx_ring(hw); rtl_pci_init()
1825 static int rtl_pci_start(struct ieee80211_hw *hw) rtl_pci_start() argument
1827 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_start()
1828 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl_pci_start()
1829 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_start()
1830 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl_pci_start()
1834 rtl_pci_reset_trx_ring(hw); rtl_pci_start()
1842 err = rtlpriv->cfg->ops->hw_init(hw); rtl_pci_start()
1849 rtlpriv->cfg->ops->enable_interrupt(hw); rtl_pci_start()
1852 rtl_init_rx_config(hw); rtl_pci_start()
1865 static void rtl_pci_stop(struct ieee80211_hw *hw) rtl_pci_stop() argument
1867 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_stop()
1868 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); rtl_pci_stop()
1869 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); rtl_pci_stop()
1870 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl_pci_stop()
1884 rtlpriv->cfg->ops->disable_interrupt(hw); rtl_pci_stop()
1901 rtlpriv->cfg->ops->hw_disable(hw); rtl_pci_stop()
1905 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); rtl_pci_stop()
1911 rtl_pci_enable_aspm(hw); rtl_pci_stop()
1915 struct ieee80211_hw *hw) _rtl_pci_find_adapter()
1917 struct rtl_priv *rtlpriv = rtl_priv(hw); _rtl_pci_find_adapter()
1918 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); _rtl_pci_find_adapter()
1919 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); _rtl_pci_find_adapter()
2081 rtl_pci_get_linkcontrol_field(hw); _rtl_pci_find_adapter()
2086 rtl_pci_get_amd_l1_patch(hw); _rtl_pci_find_adapter()
2107 rtl_pci_parse_configuration(pdev, hw); _rtl_pci_find_adapter()
2113 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) rtl_pci_intr_mode_msi() argument
2115 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_intr_mode_msi()
2116 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_intr_mode_msi()
2125 IRQF_SHARED, KBUILD_MODNAME, hw); rtl_pci_intr_mode_msi()
2138 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) rtl_pci_intr_mode_legacy() argument
2140 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_intr_mode_legacy()
2141 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_intr_mode_legacy()
2146 IRQF_SHARED, KBUILD_MODNAME, hw); rtl_pci_intr_mode_legacy()
2156 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) rtl_pci_intr_mode_decide() argument
2158 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_intr_mode_decide()
2163 ret = rtl_pci_intr_mode_msi(hw); rtl_pci_intr_mode_decide()
2165 ret = rtl_pci_intr_mode_legacy(hw); rtl_pci_intr_mode_decide()
2167 ret = rtl_pci_intr_mode_legacy(hw); rtl_pci_intr_mode_decide()
2175 struct ieee80211_hw *hw = NULL; rtl_pci_probe() local
2201 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + rtl_pci_probe()
2203 if (!hw) { rtl_pci_probe()
2210 SET_IEEE80211_DEV(hw, &pdev->dev); rtl_pci_probe()
2211 pci_set_drvdata(pdev, hw); rtl_pci_probe()
2213 rtlpriv = hw->priv; rtl_pci_probe()
2214 rtlpriv->hw = hw; rtl_pci_probe()
2238 rtl_dbgp_flag_init(hw); rtl_pci_probe()
2274 if (!_rtl_pci_find_adapter(pdev, hw)) { rtl_pci_probe()
2280 _rtl_pci_io_handler_init(&pdev->dev, hw); rtl_pci_probe()
2283 rtlpriv->cfg->ops->read_eeprom_info(hw); rtl_pci_probe()
2285 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { rtl_pci_probe()
2290 rtlpriv->cfg->ops->init_sw_leds(hw); rtl_pci_probe()
2293 rtl_pci_init_aspm(hw); rtl_pci_probe()
2296 err = rtl_init_core(hw); rtl_pci_probe()
2304 err = rtl_pci_init(hw, pdev); rtl_pci_probe()
2310 err = ieee80211_register_hw(hw); rtl_pci_probe()
2313 "Can't register mac80211 hw.\n"); rtl_pci_probe()
2327 rtl_init_rfkill(hw); /* Init PCI sw */ rtl_pci_probe()
2330 err = rtl_pci_intr_mode_decide(hw); rtl_pci_probe()
2334 wiphy_name(hw->wiphy)); rtl_pci_probe()
2344 rtl_deinit_core(hw); rtl_pci_probe()
2354 if (hw) rtl_pci_probe()
2355 ieee80211_free_hw(hw); rtl_pci_probe()
2365 struct ieee80211_hw *hw = pci_get_drvdata(pdev); rtl_pci_disconnect() local
2366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); rtl_pci_disconnect()
2367 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_disconnect()
2379 ieee80211_unregister_hw(hw); rtl_pci_disconnect()
2382 rtl_deinit_deferred_work(hw); rtl_pci_disconnect()
2383 rtlpriv->intf_ops->adapter_stop(hw); rtl_pci_disconnect()
2385 rtlpriv->cfg->ops->disable_interrupt(hw); rtl_pci_disconnect()
2388 rtl_deinit_rfkill(hw); rtl_pci_disconnect()
2390 rtl_pci_deinit(hw); rtl_pci_disconnect()
2391 rtl_deinit_core(hw); rtl_pci_disconnect()
2392 rtlpriv->cfg->ops->deinit_sw_vars(hw); rtl_pci_disconnect()
2396 free_irq(rtlpci->pdev->irq, hw); rtl_pci_disconnect()
2411 rtl_pci_disable_aspm(hw); rtl_pci_disconnect()
2415 ieee80211_free_hw(hw); rtl_pci_disconnect()
2438 struct ieee80211_hw *hw = pci_get_drvdata(pdev); rtl_pci_suspend() local
2439 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_suspend()
2441 rtlpriv->cfg->ops->hw_suspend(hw); rtl_pci_suspend()
2442 rtl_deinit_rfkill(hw); rtl_pci_suspend()
2451 struct ieee80211_hw *hw = pci_get_drvdata(pdev); rtl_pci_resume() local
2452 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl_pci_resume()
2454 rtlpriv->cfg->ops->hw_resume(hw); rtl_pci_resume()
2455 rtl_init_rfkill(hw); rtl_pci_resume()
194 _rtl_pci_platform_switch_device_pci_aspm( struct ieee80211_hw *hw, u8 value) _rtl_pci_platform_switch_device_pci_aspm() argument
415 rtl_pci_parse_configuration(struct pci_dev *pdev, struct ieee80211_hw *hw) rtl_pci_parse_configuration() argument
453 _rtl_pci_io_handler_init(struct device *dev, struct ieee80211_hw *hw) _rtl_pci_io_handler_init() argument
1914 _rtl_pci_find_adapter(struct pci_dev *pdev, struct ieee80211_hw *hw) _rtl_pci_find_adapter() argument
/linux-4.4.14/drivers/net/ethernet/micrel/
H A Dksz884x.c1339 * @hw: Pointer to hardware structure.
1353 struct ksz_hw *hw; member in struct:ksz_port
1403 * @hw: Hardware structure.
1427 struct ksz_hw hw; member in struct:dev_info
1499 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt) hw_ack_intr() argument
1501 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS); hw_ack_intr()
1504 static inline void hw_dis_intr(struct ksz_hw *hw) hw_dis_intr() argument
1506 hw->intr_blocked = hw->intr_mask; hw_dis_intr()
1507 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); hw_dis_intr()
1508 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE); hw_dis_intr()
1511 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt) hw_set_intr() argument
1513 hw->intr_set = interrupt; hw_set_intr()
1514 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE); hw_set_intr()
1517 static inline void hw_ena_intr(struct ksz_hw *hw) hw_ena_intr() argument
1519 hw->intr_blocked = 0; hw_ena_intr()
1520 hw_set_intr(hw, hw->intr_mask); hw_ena_intr()
1523 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit) hw_dis_intr_bit() argument
1525 hw->intr_mask &= ~(bit); hw_dis_intr_bit()
1528 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt) hw_turn_off_intr() argument
1532 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); hw_turn_off_intr()
1533 hw->intr_set = read_intr & ~interrupt; hw_turn_off_intr()
1534 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); hw_turn_off_intr()
1535 hw_dis_intr_bit(hw, interrupt); hw_turn_off_intr()
1540 * @hw: The hardware instance.
1546 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit) hw_turn_on_intr() argument
1548 hw->intr_mask |= bit; hw_turn_on_intr()
1550 if (!hw->intr_blocked) hw_turn_on_intr()
1551 hw_set_intr(hw, hw->intr_mask); hw_turn_on_intr()
1554 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt) hw_ena_intr_bit() argument
1558 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); hw_ena_intr_bit()
1559 hw->intr_set = read_intr | interrupt; hw_ena_intr_bit()
1560 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); hw_ena_intr_bit()
1563 static inline void hw_read_intr(struct ksz_hw *hw, uint *status) hw_read_intr() argument
1565 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS); hw_read_intr()
1566 *status = *status & hw->intr_set; hw_read_intr()
1569 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt) hw_restore_intr() argument
1572 hw_ena_intr(hw); hw_restore_intr()
1583 static uint hw_block_intr(struct ksz_hw *hw) hw_block_intr() argument
1587 if (!hw->intr_blocked) { hw_block_intr()
1588 hw_dis_intr(hw); hw_block_intr()
1589 interrupt = hw->intr_blocked; hw_block_intr()
1658 #define HW_DELAY(hw, reg) \
1661 dummy = readw(hw->io + reg); \
1666 * @hw: The hardware instance.
1674 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data) sw_r_table() argument
1681 interrupt = hw_block_intr(hw); sw_r_table()
1683 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); sw_r_table()
1684 HW_DELAY(hw, KS884X_IACR_OFFSET); sw_r_table()
1685 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); sw_r_table()
1687 hw_restore_intr(hw, interrupt); sw_r_table()
1692 * @hw: The hardware instance.
1701 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi, sw_w_table_64() argument
1709 interrupt = hw_block_intr(hw); sw_w_table_64()
1711 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET); sw_w_table_64()
1712 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET); sw_w_table_64()
1714 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); sw_w_table_64()
1715 HW_DELAY(hw, KS884X_IACR_OFFSET); sw_w_table_64()
1717 hw_restore_intr(hw, interrupt); sw_w_table_64()
1722 * @hw: The hardware instance.
1734 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr, sw_w_sta_mac_table() argument
1755 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo); sw_w_sta_mac_table()
1760 * @hw: The hardware instance.
1771 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid, sw_r_vlan_table() argument
1776 sw_r_table(hw, TABLE_VLAN, addr, &data); sw_r_vlan_table()
1789 * @hw: The hardware instance.
1797 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt) port_r_mib_cnt() argument
1806 interrupt = hw_block_intr(hw); port_r_mib_cnt()
1809 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); port_r_mib_cnt()
1810 HW_DELAY(hw, KS884X_IACR_OFFSET); port_r_mib_cnt()
1813 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); port_r_mib_cnt()
1823 hw_restore_intr(hw, interrupt); port_r_mib_cnt()
1828 * @hw: The hardware instance.
1835 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt) port_r_mib_pkt() argument
1845 interrupt = hw_block_intr(hw); port_r_mib_pkt()
1850 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); port_r_mib_pkt()
1851 HW_DELAY(hw, KS884X_IACR_OFFSET); port_r_mib_pkt()
1852 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); port_r_mib_pkt()
1854 hw_restore_intr(hw, interrupt); port_r_mib_pkt()
1874 * @hw: The hardware instance.
1883 static int port_r_cnt(struct ksz_hw *hw, int port) port_r_cnt() argument
1885 struct ksz_port_mib *mib = &hw->port_mib[port]; port_r_cnt()
1889 port_r_mib_cnt(hw, port, mib->cnt_ptr, port_r_cnt()
1893 if (hw->mib_cnt > PORT_COUNTER_NUM) port_r_cnt()
1894 port_r_mib_pkt(hw, port, mib->dropped, port_r_cnt()
1902 * @hw: The hardware instance.
1908 static void port_init_cnt(struct ksz_hw *hw, int port) port_init_cnt() argument
1910 struct ksz_port_mib *mib = &hw->port_mib[port]; port_init_cnt()
1915 port_r_mib_cnt(hw, port, mib->cnt_ptr, port_init_cnt()
1919 if (hw->mib_cnt > PORT_COUNTER_NUM) port_init_cnt()
1920 port_r_mib_pkt(hw, port, mib->dropped, port_init_cnt()
1932 * @hw: The hardware instance.
1942 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits) port_chk() argument
1949 data = readw(hw->io + addr); port_chk()
1955 * @hw: The hardware instance.
1963 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits, port_cfg() argument
1971 data = readw(hw->io + addr); port_cfg()
1976 writew(data, hw->io + addr); port_cfg()
1981 * @hw: The hardware instance.
1991 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift) port_chk_shift() argument
1996 data = readw(hw->io + addr); port_chk_shift()
2003 * @hw: The hardware instance.
2011 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift, port_cfg_shift() argument
2017 data = readw(hw->io + addr); port_cfg_shift()
2023 writew(data, hw->io + addr); port_cfg_shift()
2028 * @hw: The hardware instance.
2035 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data) port_r8() argument
2041 *data = readb(hw->io + addr); port_r8()
2046 * @hw: The hardware instance.
2053 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data) port_r16() argument
2059 *data = readw(hw->io + addr); port_r16()
2064 * @hw: The hardware instance.
2071 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data) port_w16() argument
2077 writew(data, hw->io + addr); port_w16()
2082 * @hw: The hardware instance.
2091 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits) sw_chk() argument
2095 data = readw(hw->io + addr); sw_chk()
2101 * @hw: The hardware instance.
2108 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set) sw_cfg() argument
2112 data = readw(hw->io + addr); sw_cfg()
2117 writew(data, hw->io + addr); sw_cfg()
2122 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set) port_cfg_broad_storm() argument
2124 port_cfg(hw, p, port_cfg_broad_storm()
2128 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p) port_chk_broad_storm() argument
2130 return port_chk(hw, p, port_chk_broad_storm()
2142 * @hw: The hardware instance.
2147 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) sw_cfg_broad_storm() argument
2155 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); sw_cfg_broad_storm()
2158 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); sw_cfg_broad_storm()
2163 * @hw: The hardware instance.
2168 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent) sw_get_broad_storm() argument
2173 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); sw_get_broad_storm()
2183 * @hw: The hardware instance.
2188 static void sw_dis_broad_storm(struct ksz_hw *hw, int port) sw_dis_broad_storm() argument
2190 port_cfg_broad_storm(hw, port, 0); sw_dis_broad_storm()
2195 * @hw: The hardware instance.
2200 static void sw_ena_broad_storm(struct ksz_hw *hw, int port) sw_ena_broad_storm() argument
2202 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); sw_ena_broad_storm()
2203 port_cfg_broad_storm(hw, port, 1); sw_ena_broad_storm()
2208 * @hw: The hardware instance.
2212 static void sw_init_broad_storm(struct ksz_hw *hw) sw_init_broad_storm() argument
2216 hw->ksz_switch->broad_per = 1; sw_init_broad_storm()
2217 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); sw_init_broad_storm()
2219 sw_dis_broad_storm(hw, port); sw_init_broad_storm()
2220 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1); sw_init_broad_storm()
2225 * @hw: The hardware instance.
2231 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) hw_cfg_broad_storm() argument
2236 sw_cfg_broad_storm(hw, percent); hw_cfg_broad_storm()
2237 sw_get_broad_storm(hw, &percent); hw_cfg_broad_storm()
2238 hw->ksz_switch->broad_per = percent; hw_cfg_broad_storm()
2243 * @hw: The hardware instance.
2248 static void sw_dis_prio_rate(struct ksz_hw *hw, int port) sw_dis_prio_rate() argument
2254 writel(0, hw->io + addr); sw_dis_prio_rate()
2259 * @hw: The hardware instance.
2263 static void sw_init_prio_rate(struct ksz_hw *hw) sw_init_prio_rate() argument
2267 struct ksz_switch *sw = hw->ksz_switch; sw_init_prio_rate()
2274 sw_dis_prio_rate(hw, port); sw_init_prio_rate()
2280 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set) port_cfg_back_pressure() argument
2282 port_cfg(hw, p, port_cfg_back_pressure()
2286 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set) port_cfg_force_flow_ctrl() argument
2288 port_cfg(hw, p, port_cfg_force_flow_ctrl()
2292 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p) port_chk_back_pressure() argument
2294 return port_chk(hw, p, port_chk_back_pressure()
2298 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p) port_chk_force_flow_ctrl() argument
2300 return port_chk(hw, p, port_chk_force_flow_ctrl()
2306 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set) port_cfg_rx() argument
2308 port_cfg(hw, p, port_cfg_rx()
2312 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set) port_cfg_tx() argument
2314 port_cfg(hw, p, port_cfg_tx()
2318 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set) sw_cfg_fast_aging() argument
2320 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set); sw_cfg_fast_aging()
2323 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw) sw_flush_dyn_mac_table() argument
2325 if (!(hw->overrides & FAST_AGING)) { sw_flush_dyn_mac_table()
2326 sw_cfg_fast_aging(hw, 1); sw_flush_dyn_mac_table()
2328 sw_cfg_fast_aging(hw, 0); sw_flush_dyn_mac_table()
2334 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert) port_cfg_ins_tag() argument
2336 port_cfg(hw, p, port_cfg_ins_tag()
2340 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove) port_cfg_rmv_tag() argument
2342 port_cfg(hw, p, port_cfg_rmv_tag()
2346 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p) port_chk_ins_tag() argument
2348 return port_chk(hw, p, port_chk_ins_tag()
2352 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p) port_chk_rmv_tag() argument
2354 return port_chk(hw, p, port_chk_rmv_tag()
2358 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set) port_cfg_dis_non_vid() argument
2360 port_cfg(hw, p, port_cfg_dis_non_vid()
2364 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set) port_cfg_in_filter() argument
2366 port_cfg(hw, p, port_cfg_in_filter()
2370 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p) port_chk_dis_non_vid() argument
2372 return port_chk(hw, p, port_chk_dis_non_vid()
2376 static inline int port_chk_in_filter(struct ksz_hw *hw, int p) port_chk_in_filter() argument
2378 return port_chk(hw, p, port_chk_in_filter()
2384 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set) port_cfg_mirror_sniffer() argument
2386 port_cfg(hw, p, port_cfg_mirror_sniffer()
2390 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set) port_cfg_mirror_rx() argument
2392 port_cfg(hw, p, port_cfg_mirror_rx()
2396 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set) port_cfg_mirror_tx() argument
2398 port_cfg(hw, p, port_cfg_mirror_tx()
2402 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set) sw_cfg_mirror_rx_tx() argument
2404 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set); sw_cfg_mirror_rx_tx()
2407 static void sw_init_mirror(struct ksz_hw *hw) sw_init_mirror() argument
2412 port_cfg_mirror_sniffer(hw, port, 0); sw_init_mirror()
2413 port_cfg_mirror_rx(hw, port, 0); sw_init_mirror()
2414 port_cfg_mirror_tx(hw, port, 0); sw_init_mirror()
2416 sw_cfg_mirror_rx_tx(hw, 0); sw_init_mirror()
2419 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set) sw_cfg_unk_def_deliver() argument
2421 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET, sw_cfg_unk_def_deliver()
2425 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw) sw_cfg_chk_unk_def_deliver() argument
2427 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET, sw_cfg_chk_unk_def_deliver()
2431 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set) sw_cfg_unk_def_port() argument
2433 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set); sw_cfg_unk_def_port()
2436 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port) sw_chk_unk_def_port() argument
2438 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0); sw_chk_unk_def_port()
2443 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set) port_cfg_diffserv() argument
2445 port_cfg(hw, p, port_cfg_diffserv()
2449 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set) port_cfg_802_1p() argument
2451 port_cfg(hw, p, port_cfg_802_1p()
2455 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set) port_cfg_replace_vid() argument
2457 port_cfg(hw, p, port_cfg_replace_vid()
2461 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set) port_cfg_prio() argument
2463 port_cfg(hw, p, port_cfg_prio()
2467 static inline int port_chk_diffserv(struct ksz_hw *hw, int p) port_chk_diffserv() argument
2469 return port_chk(hw, p, port_chk_diffserv()
2473 static inline int port_chk_802_1p(struct ksz_hw *hw, int p) port_chk_802_1p() argument
2475 return port_chk(hw, p, port_chk_802_1p()
2479 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p) port_chk_replace_vid() argument
2481 return port_chk(hw, p, port_chk_replace_vid()
2485 static inline int port_chk_prio(struct ksz_hw *hw, int p) port_chk_prio() argument
2487 return port_chk(hw, p, port_chk_prio()
2493 * @hw: The hardware instance.
2498 static void sw_dis_diffserv(struct ksz_hw *hw, int port) sw_dis_diffserv() argument
2500 port_cfg_diffserv(hw, port, 0); sw_dis_diffserv()
2505 * @hw: The hardware instance.
2510 static void sw_dis_802_1p(struct ksz_hw *hw, int port) sw_dis_802_1p() argument
2512 port_cfg_802_1p(hw, port, 0); sw_dis_802_1p()
2517 * @hw: The hardware instance.
2521 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set) sw_cfg_replace_null_vid() argument
2523 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set); sw_cfg_replace_null_vid()
2528 * @hw: The hardware instance.
2537 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set) sw_cfg_replace_vid() argument
2539 port_cfg_replace_vid(hw, port, set); sw_cfg_replace_vid()
2544 * @hw: The hardware instance.
2550 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio) sw_cfg_port_based() argument
2557 hw->ksz_switch->port_cfg[port].port_prio = prio; sw_cfg_port_based()
2559 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data); sw_cfg_port_based()
2562 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data); sw_cfg_port_based()
2567 * @hw: The hardware instance.
2573 static void sw_dis_multi_queue(struct ksz_hw *hw, int port) sw_dis_multi_queue() argument
2575 port_cfg_prio(hw, port, 0); sw_dis_multi_queue()
2580 * @hw: The hardware instance.
2584 static void sw_init_prio(struct ksz_hw *hw) sw_init_prio() argument
2588 struct ksz_switch *sw = hw->ksz_switch; sw_init_prio()
2612 sw_dis_multi_queue(hw, port); sw_init_prio()
2613 sw_dis_diffserv(hw, port); sw_init_prio()
2614 sw_dis_802_1p(hw, port); sw_init_prio()
2615 sw_cfg_replace_vid(hw, port, 0); sw_init_prio()
2618 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio); sw_init_prio()
2620 sw_cfg_replace_null_vid(hw, 0); sw_init_prio()
2625 * @hw: The hardware instance.
2631 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid) port_get_def_vid() argument
2637 *vid = readw(hw->io + addr); port_get_def_vid()
2642 * @hw: The hardware instance.
2646 static void sw_init_vlan(struct ksz_hw *hw) sw_init_vlan() argument
2650 struct ksz_switch *sw = hw->ksz_switch; sw_init_vlan()
2654 sw_r_vlan_table(hw, entry, sw_init_vlan()
2661 port_get_def_vid(hw, port, &sw->port_cfg[port].vid); sw_init_vlan()
2668 * @hw: The hardware instance.
2674 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member) sw_cfg_port_base_vlan() argument
2682 data = readb(hw->io + addr); sw_cfg_port_base_vlan()
2685 writeb(data, hw->io + addr); sw_cfg_port_base_vlan()
2687 hw->ksz_switch->port_cfg[port].member = member; sw_cfg_port_base_vlan()
2692 * @hw: The hardware instance.
2697 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr) sw_get_addr() argument
2702 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i); sw_get_addr()
2703 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i); sw_get_addr()
2709 * @hw: The hardware instance.
2714 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr) sw_set_addr() argument
2719 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i); sw_set_addr()
2720 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i); sw_set_addr()
2726 * @hw: The hardware instance.
2730 static void sw_set_global_ctrl(struct ksz_hw *hw) sw_set_global_ctrl() argument
2735 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); sw_set_global_ctrl()
2737 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); sw_set_global_ctrl()
2739 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET); sw_set_global_ctrl()
2748 if (hw->overrides & FAST_AGING) sw_set_global_ctrl()
2752 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET); sw_set_global_ctrl()
2754 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); sw_set_global_ctrl()
2758 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); sw_set_global_ctrl()
2772 * @hw: The hardware instance.
2778 static void port_set_stp_state(struct ksz_hw *hw, int port, int state) port_set_stp_state() argument
2782 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data); port_set_stp_state()
2819 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data); port_set_stp_state()
2820 hw->ksz_switch->port_cfg[port].stp_state = state; port_set_stp_state()
2830 * @hw: The hardware instance.
2834 static void sw_clr_sta_mac_table(struct ksz_hw *hw) sw_clr_sta_mac_table() argument
2840 entry = &hw->ksz_switch->mac_table[i]; sw_clr_sta_mac_table()
2841 sw_w_sta_mac_table(hw, i, sw_clr_sta_mac_table()
2850 * @hw: The hardware instance.
2854 static void sw_init_stp(struct ksz_hw *hw) sw_init_stp() argument
2858 entry = &hw->ksz_switch->mac_table[STP_ENTRY]; sw_init_stp()
2868 sw_w_sta_mac_table(hw, STP_ENTRY, sw_init_stp()
2876 * @hw: The hardware instance.
2880 static void sw_block_addr(struct ksz_hw *hw) sw_block_addr() argument
2886 entry = &hw->ksz_switch->mac_table[i]; sw_block_addr()
2888 sw_w_sta_mac_table(hw, i, sw_block_addr()
2904 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_ctrl() argument
2906 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); hw_r_phy_ctrl()
2909 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data) hw_w_phy_ctrl() argument
2911 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); hw_w_phy_ctrl()
2914 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_link_stat() argument
2916 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET); hw_r_phy_link_stat()
2919 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_auto_neg() argument
2921 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); hw_r_phy_auto_neg()
2924 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data) hw_w_phy_auto_neg() argument
2926 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); hw_w_phy_auto_neg()
2929 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_rem_cap() argument
2931 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET); hw_r_phy_rem_cap()
2934 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_crossover() argument
2936 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); hw_r_phy_crossover()
2939 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data) hw_w_phy_crossover() argument
2941 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); hw_w_phy_crossover()
2944 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_polarity() argument
2946 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); hw_r_phy_polarity()
2949 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data) hw_w_phy_polarity() argument
2951 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); hw_w_phy_polarity()
2954 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data) hw_r_phy_link_md() argument
2956 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); hw_r_phy_link_md()
2959 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data) hw_w_phy_link_md() argument
2961 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); hw_w_phy_link_md()
2966 * @hw: The hardware instance.
2973 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val) hw_r_phy() argument
2978 *val = readw(hw->io + phy); hw_r_phy()
2983 * @hw: The hardware instance.
2990 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val) hw_w_phy() argument
2995 writew(val, hw->io + phy); hw_w_phy()
3014 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio) drop_gpio() argument
3018 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); drop_gpio()
3020 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); drop_gpio()
3023 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio) raise_gpio() argument
3027 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); raise_gpio()
3029 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); raise_gpio()
3032 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio) state_gpio() argument
3036 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); state_gpio()
3040 static void eeprom_clk(struct ksz_hw *hw) eeprom_clk() argument
3042 raise_gpio(hw, EEPROM_SERIAL_CLOCK); eeprom_clk()
3044 drop_gpio(hw, EEPROM_SERIAL_CLOCK); eeprom_clk()
3048 static u16 spi_r(struct ksz_hw *hw) spi_r() argument
3054 raise_gpio(hw, EEPROM_SERIAL_CLOCK); spi_r()
3057 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0; spi_r()
3059 drop_gpio(hw, EEPROM_SERIAL_CLOCK); spi_r()
3065 static void spi_w(struct ksz_hw *hw, u16 data) spi_w() argument
3070 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : spi_w()
3071 drop_gpio(hw, EEPROM_DATA_OUT); spi_w()
3072 eeprom_clk(hw); spi_w()
3076 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg) spi_reg() argument
3081 raise_gpio(hw, EEPROM_DATA_OUT); spi_reg()
3082 eeprom_clk(hw); spi_reg()
3086 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : spi_reg()
3087 drop_gpio(hw, EEPROM_DATA_OUT); spi_reg()
3088 eeprom_clk(hw); spi_reg()
3093 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : spi_reg()
3094 drop_gpio(hw, EEPROM_DATA_OUT); spi_reg()
3095 eeprom_clk(hw); spi_reg()
3112 * @hw: The hardware instance.
3119 static u16 eeprom_read(struct ksz_hw *hw, u8 reg) eeprom_read() argument
3123 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); eeprom_read()
3125 spi_reg(hw, AT93C_READ, reg); eeprom_read()
3126 data = spi_r(hw); eeprom_read()
3128 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); eeprom_read()
3135 * @hw: The hardware instance.
3141 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data) eeprom_write() argument
3145 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); eeprom_write()
3148 spi_reg(hw, AT93C_CODE, AT93C_WR_ON); eeprom_write()
3149 drop_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3153 raise_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3154 spi_reg(hw, AT93C_ERASE, reg); eeprom_write()
3155 drop_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3159 raise_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3164 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); eeprom_write()
3165 drop_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3169 raise_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3170 spi_reg(hw, AT93C_WRITE, reg); eeprom_write()
3171 spi_w(hw, data); eeprom_write()
3172 drop_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3176 raise_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3181 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); eeprom_write()
3182 drop_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3186 raise_gpio(hw, EEPROM_CHIP_SELECT); eeprom_write()
3187 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF); eeprom_write()
3189 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); eeprom_write()
3212 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx) set_flow_ctrl() argument
3217 rx_cfg = hw->rx_cfg; set_flow_ctrl()
3218 tx_cfg = hw->tx_cfg; set_flow_ctrl()
3220 hw->rx_cfg |= DMA_RX_FLOW_ENABLE; set_flow_ctrl()
3222 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE; set_flow_ctrl()
3224 hw->tx_cfg |= DMA_TX_FLOW_ENABLE; set_flow_ctrl()
3226 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; set_flow_ctrl()
3227 if (hw->enabled) { set_flow_ctrl()
3228 if (rx_cfg != hw->rx_cfg) set_flow_ctrl()
3229 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); set_flow_ctrl()
3230 if (tx_cfg != hw->tx_cfg) set_flow_ctrl()
3231 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); set_flow_ctrl()
3235 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port, determine_flow_ctrl() argument
3241 if (hw->overrides & PAUSE_FLOW_CTRL) determine_flow_ctrl()
3259 if (!hw->ksz_switch) determine_flow_ctrl()
3260 set_flow_ctrl(hw, rx, tx); determine_flow_ctrl()
3263 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port, port_cfg_change() argument
3266 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) && port_cfg_change()
3267 !(hw->overrides & PAUSE_FLOW_CTRL)) { port_cfg_change()
3268 u32 cfg = hw->tx_cfg; port_cfg_change()
3272 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; port_cfg_change()
3273 if (hw->enabled && cfg != hw->tx_cfg) port_cfg_change()
3274 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); port_cfg_change()
3290 struct ksz_hw *hw = port->hw; port_get_link_speed() local
3299 interrupt = hw_block_intr(hw); port_get_link_speed()
3302 info = &hw->port_info[p]; port_get_link_speed()
3303 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); port_get_link_speed()
3304 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status); port_get_link_speed()
3335 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET, port_get_link_speed()
3337 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET, port_get_link_speed()
3339 determine_flow_ctrl(hw, port, data, status); port_get_link_speed()
3340 if (hw->ksz_switch) { port_get_link_speed()
3341 port_cfg_back_pressure(hw, p, port_get_link_speed()
3345 port_cfg_change(hw, port, info, status); port_get_link_speed()
3353 hw->port_mib[p].link_down = 1; port_get_link_speed()
3357 hw->port_mib[p].state = (u8) info->state; port_get_link_speed()
3363 hw_restore_intr(hw, interrupt); port_get_link_speed()
3377 struct ksz_hw *hw = port->hw; port_set_link_speed() local
3385 info = &hw->port_info[p]; port_set_link_speed()
3387 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); port_set_link_speed()
3388 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status); port_set_link_speed()
3417 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data); port_set_link_speed()
3430 struct ksz_hw *hw = port->hw; port_force_link_speed() local
3438 hw_r_phy_ctrl(hw, phy, &data); port_force_link_speed()
3450 hw_w_phy_ctrl(hw, phy, data); port_force_link_speed()
3456 struct ksz_hw *hw = port->hw; port_set_power_saving() local
3461 port_cfg(hw, p, port_set_power_saving()
3471 * @hw: The hardware instance.
3477 static int hw_chk_wol_pme_status(struct ksz_hw *hw) hw_chk_wol_pme_status() argument
3479 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); hw_chk_wol_pme_status()
3491 * @hw: The hardware instance.
3495 static void hw_clr_wol_pme_status(struct ksz_hw *hw) hw_clr_wol_pme_status() argument
3497 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); hw_clr_wol_pme_status()
3512 * @hw: The hardware instance.
3517 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set) hw_cfg_wol_pme() argument
3519 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); hw_cfg_wol_pme()
3536 * @hw: The hardware instance.
3542 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set) hw_cfg_wol() argument
3546 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET); hw_cfg_wol()
3551 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET); hw_cfg_wol()
3556 * @hw: The hardware instance.
3565 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size, hw_set_wol_frame() argument
3582 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); hw_set_wol_frame()
3583 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); hw_set_wol_frame()
3595 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i hw_set_wol_frame()
3608 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len - hw_set_wol_frame()
3612 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i); hw_set_wol_frame()
3617 * @hw: The hardware instance.
3622 static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr) hw_add_wol_arp() argument
3636 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern); hw_add_wol_arp()
3641 * @hw: The hardware instance.
3645 static void hw_add_wol_bcast(struct ksz_hw *hw) hw_add_wol_bcast() argument
3650 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern); hw_add_wol_bcast()
3655 * @hw: The hardware instance.
3663 static void hw_add_wol_mcast(struct ksz_hw *hw) hw_add_wol_mcast() argument
3668 memcpy(&pattern[3], &hw->override_addr[3], 3); hw_add_wol_mcast()
3669 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern); hw_add_wol_mcast()
3674 * @hw: The hardware instance.
3681 static void hw_add_wol_ucast(struct ksz_hw *hw) hw_add_wol_ucast() argument
3685 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr); hw_add_wol_ucast()
3690 * @hw: The hardware instance.
3696 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr) hw_enable_wol() argument
3698 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC)); hw_enable_wol()
3699 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST)); hw_enable_wol()
3700 hw_add_wol_ucast(hw); hw_enable_wol()
3701 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST)); hw_enable_wol()
3702 hw_add_wol_mcast(hw); hw_enable_wol()
3703 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST)); hw_enable_wol()
3704 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP)); hw_enable_wol()
3705 hw_add_wol_arp(hw, net_addr); hw_enable_wol()
3710 * @hw: The hardware instance.
3717 static int hw_init(struct ksz_hw *hw) hw_init() argument
3724 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET); hw_init()
3727 data = readw(hw->io + KS884X_CHIP_ID_OFFSET); hw_init()
3740 hw->features |= SMALL_PACKET_TX_BUG; hw_init()
3742 hw->features |= HALF_DUPLEX_SIGNAL_BUG; hw_init()
3749 * @hw: The hardware instance.
3753 static void hw_reset(struct ksz_hw *hw) hw_reset() argument
3755 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET); hw_reset()
3761 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); hw_reset()
3766 * @hw: The hardware instance.
3770 static void hw_setup(struct ksz_hw *hw) hw_setup() argument
3776 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET); hw_setup()
3779 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET); hw_setup()
3783 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE | hw_setup()
3787 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST | hw_setup()
3789 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST; hw_setup()
3792 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP); hw_setup()
3794 if (hw->all_multi) hw_setup()
3795 hw->rx_cfg |= DMA_RX_ALL_MULTICAST; hw_setup()
3796 if (hw->promiscuous) hw_setup()
3797 hw->rx_cfg |= DMA_RX_PROMISCUOUS; hw_setup()
3802 * @hw: The hardware instance.
3806 static void hw_setup_intr(struct ksz_hw *hw) hw_setup_intr() argument
3808 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN; hw_setup_intr()
3863 * @hw: The hardware instance.
3869 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr) hw_set_desc_base() argument
3872 writel(tx_addr, hw->io + KS_DMA_TX_ADDR); hw_set_desc_base()
3873 writel(rx_addr, hw->io + KS_DMA_RX_ADDR); hw_set_desc_base()
3883 static inline void hw_resume_rx(struct ksz_hw *hw) hw_resume_rx() argument
3885 writel(DMA_START, hw->io + KS_DMA_RX_START); hw_resume_rx()
3890 * @hw: The hardware instance.
3894 static void hw_start_rx(struct ksz_hw *hw) hw_start_rx() argument
3896 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); hw_start_rx()
3899 hw->intr_mask |= KS884X_INT_RX_STOPPED; hw_start_rx()
3901 writel(DMA_START, hw->io + KS_DMA_RX_START); hw_start_rx()
3902 hw_ack_intr(hw, KS884X_INT_RX_STOPPED); hw_start_rx()
3903 hw->rx_stop++; hw_start_rx()
3906 if (0 == hw->rx_stop) hw_start_rx()
3907 hw->rx_stop = 2; hw_start_rx()
3912 * @hw: The hardware instance.
3916 static void hw_stop_rx(struct ksz_hw *hw) hw_stop_rx() argument
3918 hw->rx_stop = 0; hw_stop_rx()
3919 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED); hw_stop_rx()
3920 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL); hw_stop_rx()
3925 * @hw: The hardware instance.
3929 static void hw_start_tx(struct ksz_hw *hw) hw_start_tx() argument
3931 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); hw_start_tx()
3936 * @hw: The hardware instance.
3940 static void hw_stop_tx(struct ksz_hw *hw) hw_stop_tx() argument
3942 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL); hw_stop_tx()
3947 * @hw: The hardware instance.
3951 static void hw_disable(struct ksz_hw *hw) hw_disable() argument
3953 hw_stop_rx(hw); hw_disable()
3954 hw_stop_tx(hw); hw_disable()
3955 hw->enabled = 0; hw_disable()
3960 * @hw: The hardware instance.
3964 static void hw_enable(struct ksz_hw *hw) hw_enable() argument
3966 hw_start_tx(hw); hw_enable()
3967 hw_start_rx(hw); hw_enable()
3968 hw->enabled = 1; hw_enable()
3973 * @hw: The hardware instance.
3981 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical) hw_alloc_pkt() argument
3984 if (hw->tx_desc_info.avail <= 1) hw_alloc_pkt()
3988 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur); hw_alloc_pkt()
3989 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1; hw_alloc_pkt()
3992 ++hw->tx_int_cnt; hw_alloc_pkt()
3993 hw->tx_size += length; hw_alloc_pkt()
3996 if (hw->tx_size >= MAX_TX_HELD_SIZE) hw_alloc_pkt()
3997 hw->tx_int_cnt = hw->tx_int_mask + 1; hw_alloc_pkt()
3999 if (physical > hw->tx_desc_info.avail) hw_alloc_pkt()
4002 return hw->tx_desc_info.avail; hw_alloc_pkt()
4007 * @hw: The hardware instance.
4011 static void hw_send_pkt(struct ksz_hw *hw) hw_send_pkt() argument
4013 struct ksz_desc *cur = hw->tx_desc_info.cur; hw_send_pkt()
4018 if (hw->tx_int_cnt > hw->tx_int_mask) { hw_send_pkt()
4020 hw->tx_int_cnt = 0; hw_send_pkt()
4021 hw->tx_size = 0; hw_send_pkt()
4025 cur->sw.buf.tx.dest_port = hw->dst_ports; hw_send_pkt()
4029 writel(0, hw->io + KS_DMA_TX_START); hw_send_pkt()
4042 * @hw: The hardware instance.
4047 static void hw_set_addr(struct ksz_hw *hw) hw_set_addr() argument
4052 writeb(hw->override_addr[MAC_ADDR_ORDER(i)], hw_set_addr()
4053 hw->io + KS884X_ADDR_0_OFFSET + i); hw_set_addr()
4055 sw_set_addr(hw, hw->override_addr); hw_set_addr()
4060 * @hw: The hardware instance.
4064 static void hw_read_addr(struct ksz_hw *hw) hw_read_addr() argument
4069 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io + hw_read_addr()
4072 if (!hw->mac_override) { hw_read_addr()
4073 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN); hw_read_addr()
4074 if (empty_addr(hw->override_addr)) { hw_read_addr()
4075 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN); hw_read_addr()
4076 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS, hw_read_addr()
4078 hw->override_addr[5] += hw->id; hw_read_addr()
4079 hw_set_addr(hw); hw_read_addr()
4084 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr) hw_ena_add_addr() argument
4103 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO); hw_ena_add_addr()
4104 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI); hw_ena_add_addr()
4107 static void hw_set_add_addr(struct ksz_hw *hw) hw_set_add_addr() argument
4112 if (empty_addr(hw->address[i])) hw_set_add_addr()
4113 writel(0, hw->io + ADD_ADDR_INCR * i + hw_set_add_addr()
4116 hw_ena_add_addr(hw, i, hw->address[i]); hw_set_add_addr()
4120 static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr) hw_add_addr() argument
4125 if (ether_addr_equal(hw->override_addr, mac_addr)) hw_add_addr()
4127 for (i = 0; i < hw->addr_list_size; i++) { hw_add_addr()
4128 if (ether_addr_equal(hw->address[i], mac_addr)) hw_add_addr()
4130 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i])) hw_add_addr()
4134 memcpy(hw->address[j], mac_addr, ETH_ALEN); hw_add_addr()
4135 hw_ena_add_addr(hw, j, hw->address[j]); hw_add_addr()
4141 static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr) hw_del_addr() argument
4145 for (i = 0; i < hw->addr_list_size; i++) { hw_del_addr()
4146 if (ether_addr_equal(hw->address[i], mac_addr)) { hw_del_addr()
4147 eth_zero_addr(hw->address[i]); hw_del_addr()
4148 writel(0, hw->io + ADD_ADDR_INCR * i + hw_del_addr()
4158 * @hw: The hardware instance.
4162 static void hw_clr_multicast(struct ksz_hw *hw) hw_clr_multicast() argument
4167 hw->multi_bits[i] = 0; hw_clr_multicast()
4169 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); hw_clr_multicast()
4175 * @hw: The hardware instance.
4180 static void hw_set_grp_addr(struct ksz_hw *hw) hw_set_grp_addr() argument
4187 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE); hw_set_grp_addr()
4189 for (i = 0; i < hw->multi_list_size; i++) { hw_set_grp_addr()
4190 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f; hw_set_grp_addr()
4193 hw->multi_bits[index] |= (u8) value; hw_set_grp_addr()
4197 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET + hw_set_grp_addr()
4203 * @hw: The hardware instance.
4208 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast) hw_set_multicast() argument
4211 hw_stop_rx(hw); hw_set_multicast()
4214 hw->rx_cfg |= DMA_RX_ALL_MULTICAST; hw_set_multicast()
4216 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST; hw_set_multicast()
4218 if (hw->enabled) hw_set_multicast()
4219 hw_start_rx(hw); hw_set_multicast()
4224 * @hw: The hardware instance.
4229 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom) hw_set_promiscuous() argument
4232 hw_stop_rx(hw); hw_set_promiscuous()
4235 hw->rx_cfg |= DMA_RX_PROMISCUOUS; hw_set_promiscuous()
4237 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS; hw_set_promiscuous()
4239 if (hw->enabled) hw_set_promiscuous()
4240 hw_start_rx(hw); hw_set_promiscuous()
4245 * @hw: The hardware instance.
4250 static void sw_enable(struct ksz_hw *hw, int enable) sw_enable() argument
4255 if (hw->dev_count > 1) { sw_enable()
4257 sw_cfg_port_base_vlan(hw, port, sw_enable()
4259 port_set_stp_state(hw, port, STP_STATE_DISABLED); sw_enable()
4261 sw_cfg_port_base_vlan(hw, port, PORT_MASK); sw_enable()
4262 port_set_stp_state(hw, port, STP_STATE_FORWARDING); sw_enable()
4265 if (hw->dev_count > 1) sw_enable()
4266 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); sw_enable()
4268 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING); sw_enable()
4272 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET); sw_enable()
4277 * @hw: The hardware instance.
4281 static void sw_setup(struct ksz_hw *hw) sw_setup() argument
4285 sw_set_global_ctrl(hw); sw_setup()
4288 sw_init_broad_storm(hw); sw_setup()
4289 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE); sw_setup()
4291 sw_ena_broad_storm(hw, port); sw_setup()
4293 sw_init_prio(hw); sw_setup()
4295 sw_init_mirror(hw); sw_setup()
4297 sw_init_prio_rate(hw); sw_setup()
4299 sw_init_vlan(hw); sw_setup()
4301 if (hw->features & STP_SUPPORT) sw_setup()
4302 sw_init_stp(hw); sw_setup()
4303 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, sw_setup()
4305 hw->overrides |= PAUSE_FLOW_CTRL; sw_setup()
4306 sw_enable(hw, 1); sw_setup()
4394 struct ksz_hw *hw = &adapter->hw; ksz_alloc_desc() local
4399 hw->rx_desc_info.size * hw->rx_desc_info.alloc + ksz_alloc_desc()
4400 hw->tx_desc_info.size * hw->tx_desc_info.alloc + ksz_alloc_desc()
4420 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *) ksz_alloc_desc()
4422 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys; ksz_alloc_desc()
4423 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size; ksz_alloc_desc()
4424 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *) ksz_alloc_desc()
4426 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset; ksz_alloc_desc()
4428 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0)) ksz_alloc_desc()
4430 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1)) ksz_alloc_desc()
4462 struct ksz_hw *hw = &adapter->hw; ksz_init_rx_buffers() local
4463 struct ksz_desc_info *info = &hw->rx_desc_info; ksz_init_rx_buffers()
4465 for (i = 0; i < hw->rx_desc_info.alloc; i++) { ksz_init_rx_buffers()
4499 struct ksz_hw *hw = &adapter->hw; ksz_alloc_mem() local
4502 hw->rx_desc_info.alloc = NUM_OF_RX_DESC; ksz_alloc_mem()
4503 hw->tx_desc_info.alloc = NUM_OF_TX_DESC; ksz_alloc_mem()
4506 hw->tx_int_cnt = 0; ksz_alloc_mem()
4507 hw->tx_int_mask = NUM_OF_TX_DESC / 4; ksz_alloc_mem()
4508 if (hw->tx_int_mask > 8) ksz_alloc_mem()
4509 hw->tx_int_mask = 8; ksz_alloc_mem()
4510 while (hw->tx_int_mask) { ksz_alloc_mem()
4511 hw->tx_int_cnt++; ksz_alloc_mem()
4512 hw->tx_int_mask >>= 1; ksz_alloc_mem()
4514 if (hw->tx_int_cnt) { ksz_alloc_mem()
4515 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1; ksz_alloc_mem()
4516 hw->tx_int_cnt = 0; ksz_alloc_mem()
4520 hw->rx_desc_info.size = ksz_alloc_mem()
4523 hw->tx_desc_info.size = ksz_alloc_mem()
4526 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc)) ksz_alloc_mem()
4528 ksz_check_desc_num(&hw->rx_desc_info); ksz_alloc_mem()
4529 ksz_check_desc_num(&hw->tx_desc_info); ksz_alloc_mem()
4547 struct ksz_hw *hw = &adapter->hw; ksz_free_desc() local
4550 hw->rx_desc_info.ring_virt = NULL; ksz_free_desc()
4551 hw->tx_desc_info.ring_virt = NULL; ksz_free_desc()
4552 hw->rx_desc_info.ring_phys = 0; ksz_free_desc()
4553 hw->tx_desc_info.ring_phys = 0; ksz_free_desc()
4567 kfree(hw->rx_desc_info.ring); ksz_free_desc()
4568 hw->rx_desc_info.ring = NULL; ksz_free_desc()
4569 kfree(hw->tx_desc_info.ring); ksz_free_desc()
4570 hw->tx_desc_info.ring = NULL; ksz_free_desc()
4604 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, ksz_free_mem()
4608 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, ksz_free_mem()
4615 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt, get_mib_counters() argument
4625 port_mib = &hw->port_mib[port]; get_mib_counters()
4626 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++) get_mib_counters()
4644 struct ksz_hw *hw = &hw_priv->hw; send_packet() local
4645 struct ksz_desc_info *info = &hw->tx_desc_info; send_packet()
4654 if (hw->dev_count > 1) send_packet()
4655 hw->dst_ports = 1 << priv->port.first_port; send_packet()
4685 ++hw->tx_int_cnt; send_packet()
4732 hw_send_pkt(hw); send_packet()
4749 struct ksz_hw *hw = &hw_priv->hw; transmit_cleanup() local
4750 struct ksz_desc_info *info = &hw->tx_desc_info; transmit_cleanup()
4805 struct ksz_hw *hw = &hw_priv->hw; tx_done() local
4810 for (port = 0; port < hw->dev_count; port++) { tx_done()
4811 struct net_device *dev = hw->port_info[port].pdev; tx_done()
4842 struct ksz_hw *hw = &hw_priv->hw; netdev_tx() local
4847 if (hw->features & SMALL_PACKET_TX_BUG) { netdev_tx()
4870 left = hw_alloc_pkt(hw, skb->len, num); netdev_tx()
4916 struct ksz_hw *hw = &hw_priv->hw; netdev_tx_timeout() local
4919 if (hw->dev_count > 1) { netdev_tx_timeout()
4930 hw_dis_intr(hw); netdev_tx_timeout()
4931 hw_disable(hw); netdev_tx_timeout()
4934 hw_reset_pkts(&hw->rx_desc_info); netdev_tx_timeout()
4935 hw_reset_pkts(&hw->tx_desc_info); netdev_tx_timeout()
4938 hw_reset(hw); netdev_tx_timeout()
4940 hw_set_desc_base(hw, netdev_tx_timeout()
4941 hw->tx_desc_info.ring_phys, netdev_tx_timeout()
4942 hw->rx_desc_info.ring_phys); netdev_tx_timeout()
4943 hw_set_addr(hw); netdev_tx_timeout()
4944 if (hw->all_multi) netdev_tx_timeout()
4945 hw_set_multicast(hw, hw->all_multi); netdev_tx_timeout()
4946 else if (hw->multi_list_size) netdev_tx_timeout()
4947 hw_set_grp_addr(hw); netdev_tx_timeout()
4949 if (hw->dev_count > 1) { netdev_tx_timeout()
4950 hw_set_add_addr(hw); netdev_tx_timeout()
4954 port_set_stp_state(hw, port, netdev_tx_timeout()
4957 port_dev = hw->port_info[port].pdev; netdev_tx_timeout()
4959 port_set_stp_state(hw, port, netdev_tx_timeout()
4964 hw_enable(hw); netdev_tx_timeout()
4965 hw_ena_intr(hw); netdev_tx_timeout()
4991 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw, rx_proc() argument
5029 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP)) rx_proc()
5046 struct ksz_hw *hw = &hw_priv->hw; dev_rcv_packets() local
5047 struct net_device *dev = hw->port_info[0].pdev; dev_rcv_packets()
5048 struct ksz_desc_info *info = &hw->rx_desc_info; dev_rcv_packets()
5063 if (rx_proc(dev, hw, desc, status)) dev_rcv_packets()
5082 struct ksz_hw *hw = &hw_priv->hw; port_rcv_packets() local
5083 struct net_device *dev = hw->port_info[0].pdev; port_rcv_packets()
5084 struct ksz_desc_info *info = &hw->rx_desc_info; port_rcv_packets()
5097 if (hw->dev_count > 1) { port_rcv_packets()
5101 dev = hw->port_info[p].pdev; port_rcv_packets()
5108 if (rx_proc(dev, hw, desc, status)) port_rcv_packets()
5127 struct ksz_hw *hw = &hw_priv->hw; dev_rcv_special() local
5128 struct net_device *dev = hw->port_info[0].pdev; dev_rcv_special()
5129 struct ksz_desc_info *info = &hw->rx_desc_info; dev_rcv_special()
5142 if (hw->dev_count > 1) { dev_rcv_special()
5146 dev = hw->port_info[p].pdev; dev_rcv_special()
5161 if (rx_proc(dev, hw, desc, status)) dev_rcv_special()
5185 struct ksz_hw *hw = &hw_priv->hw; rx_proc_task() local
5187 if (!hw->enabled) rx_proc_task()
5192 hw_resume_rx(hw); rx_proc_task()
5196 hw_turn_on_intr(hw, KS884X_INT_RX_MASK); rx_proc_task()
5199 hw_ack_intr(hw, KS884X_INT_RX); rx_proc_task()
5207 struct ksz_hw *hw = &hw_priv->hw; tx_proc_task() local
5209 hw_ack_intr(hw, KS884X_INT_TX_MASK); tx_proc_task()
5215 hw_turn_on_intr(hw, KS884X_INT_TX); tx_proc_task()
5219 static inline void handle_rx_stop(struct ksz_hw *hw) handle_rx_stop() argument
5222 if (0 == hw->rx_stop) handle_rx_stop()
5223 hw->intr_mask &= ~KS884X_INT_RX_STOPPED; handle_rx_stop()
5224 else if (hw->rx_stop > 1) { handle_rx_stop()
5225 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) { handle_rx_stop()
5226 hw_start_rx(hw); handle_rx_stop()
5228 hw->intr_mask &= ~KS884X_INT_RX_STOPPED; handle_rx_stop()
5229 hw->rx_stop = 0; handle_rx_stop()
5233 hw->rx_stop++; handle_rx_stop()
5251 struct ksz_hw *hw = &hw_priv->hw; netdev_intr() local
5255 hw_read_intr(hw, &int_enable); netdev_intr()
5264 hw_ack_intr(hw, int_enable); netdev_intr()
5265 int_enable &= hw->intr_mask; netdev_intr()
5268 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK); netdev_intr()
5273 hw_dis_intr_bit(hw, KS884X_INT_RX); netdev_intr()
5279 hw_resume_rx(hw); netdev_intr()
5285 hw->features |= LINK_INT_WORKING; netdev_intr()
5290 handle_rx_stop(hw); netdev_intr()
5297 hw->intr_mask &= ~KS884X_INT_TX_STOPPED; netdev_intr()
5299 data = readl(hw->io + KS_DMA_TX_CTRL); netdev_intr()
5306 hw_ena_intr(hw); netdev_intr()
5325 hw_dis_intr(&hw_priv->hw); netdev_netpoll()
5330 static void bridge_change(struct ksz_hw *hw) bridge_change() argument
5334 struct ksz_switch *sw = hw->ksz_switch; bridge_change()
5338 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); bridge_change()
5339 sw_block_addr(hw); bridge_change()
5347 sw_cfg_port_base_vlan(hw, port, member); bridge_change()
5365 struct ksz_hw *hw = &hw_priv->hw; netdev_close() local
5373 if (hw->dev_count > 1) { netdev_close()
5374 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED); netdev_close()
5377 if (hw->features & STP_SUPPORT) { netdev_close()
5379 if (hw->ksz_switch->member & pi) { netdev_close()
5380 hw->ksz_switch->member &= ~pi; netdev_close()
5381 bridge_change(hw); netdev_close()
5386 hw_del_addr(hw, dev->dev_addr); netdev_close()
5391 --hw->all_multi; netdev_close()
5393 --hw->promiscuous; netdev_close()
5400 hw_dis_intr(hw); netdev_close()
5401 hw_disable(hw); netdev_close()
5402 hw_clr_multicast(hw); netdev_close()
5412 hw_reset_pkts(&hw->rx_desc_info); netdev_close()
5413 hw_reset_pkts(&hw->tx_desc_info); netdev_close()
5416 if (hw->features & STP_SUPPORT) netdev_close()
5417 sw_clr_sta_mac_table(hw); netdev_close()
5423 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw) hw_cfg_huge_frame() argument
5425 if (hw->ksz_switch) { hw_cfg_huge_frame()
5428 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); hw_cfg_huge_frame()
5429 if (hw->features & RX_HUGE_FRAME) hw_cfg_huge_frame()
5433 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); hw_cfg_huge_frame()
5435 if (hw->features & RX_HUGE_FRAME) { hw_cfg_huge_frame()
5436 hw->rx_cfg |= DMA_RX_ERROR; hw_cfg_huge_frame()
5439 hw->rx_cfg &= ~DMA_RX_ERROR; hw_cfg_huge_frame()
5440 if (hw->dev_count > 1) hw_cfg_huge_frame()
5451 struct ksz_hw *hw = &hw_priv->hw; prepare_hardware() local
5464 hw->promiscuous = 0; prepare_hardware()
5465 hw->all_multi = 0; prepare_hardware()
5466 hw->multi_list_size = 0; prepare_hardware()
5468 hw_reset(hw); prepare_hardware()
5470 hw_set_desc_base(hw, prepare_hardware()
5471 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys); prepare_hardware()
5472 hw_set_addr(hw); prepare_hardware()
5473 hw_cfg_huge_frame(hw_priv, hw); prepare_hardware()
5503 struct ksz_hw *hw = &hw_priv->hw; netdev_open() local
5521 for (i = 0; i < hw->mib_port_cnt; i++) { netdev_open()
5527 hw->port_mib[i].state = media_disconnected; netdev_open()
5528 port_init_cnt(hw, i); netdev_open()
5530 if (hw->ksz_switch) netdev_open()
5531 hw->port_mib[HOST_PORT].state = media_connected; netdev_open()
5533 hw_add_wol_bcast(hw); netdev_open()
5534 hw_cfg_wol_pme(hw, 0); netdev_open()
5535 hw_clr_wol_pme_status(&hw_priv->hw); netdev_open()
5545 hw->port_info[p].partner = 0xFF; netdev_open()
5546 hw->port_info[p].state = media_disconnected; netdev_open()
5550 if (hw->dev_count > 1) { netdev_open()
5551 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE); netdev_open()
5553 hw_add_addr(hw, dev->dev_addr); netdev_open()
5563 hw_setup_intr(hw); netdev_open()
5564 hw_enable(hw); netdev_open()
5565 hw_ena_intr(hw); netdev_open()
5567 if (hw->mib_port_cnt) netdev_open()
5608 struct ksz_hw *hw = &priv->adapter->hw; netdev_query_statistics() local
5625 mib = &hw->port_mib[p]; netdev_query_statistics()
5664 struct ksz_hw *hw = &hw_priv->hw; netdev_set_mac_address() local
5669 hw_del_addr(hw, dev->dev_addr); netdev_set_mac_address()
5671 hw->mac_override = 1; netdev_set_mac_address()
5672 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN); netdev_set_mac_address()
5677 interrupt = hw_block_intr(hw); netdev_set_mac_address()
5680 hw_add_addr(hw, dev->dev_addr); netdev_set_mac_address()
5682 hw_set_addr(hw); netdev_set_mac_address()
5683 hw_restore_intr(hw, interrupt); netdev_set_mac_address()
5689 struct ksz_hw *hw, int promiscuous) dev_set_promiscuous()
5692 u8 prev_state = hw->promiscuous; dev_set_promiscuous()
5695 ++hw->promiscuous; dev_set_promiscuous()
5697 --hw->promiscuous; dev_set_promiscuous()
5701 if (hw->promiscuous <= 1 && prev_state <= 1) dev_set_promiscuous()
5702 hw_set_promiscuous(hw, hw->promiscuous); dev_set_promiscuous()
5708 if ((hw->features & STP_SUPPORT) && !promiscuous && dev_set_promiscuous()
5710 struct ksz_switch *sw = hw->ksz_switch; dev_set_promiscuous()
5713 port_set_stp_state(hw, port, STP_STATE_DISABLED); dev_set_promiscuous()
5717 bridge_change(hw); dev_set_promiscuous()
5723 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw, dev_set_multicast() argument
5727 u8 all_multi = hw->all_multi; dev_set_multicast()
5730 ++hw->all_multi; dev_set_multicast()
5732 --hw->all_multi; dev_set_multicast()
5736 if (hw->all_multi <= 1 && all_multi <= 1) dev_set_multicast()
5737 hw_set_multicast(hw, hw->all_multi); dev_set_multicast()
5752 struct ksz_hw *hw = &hw_priv->hw; netdev_set_rx_mode() local
5756 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC)); netdev_set_rx_mode()
5758 if (hw_priv->hw.dev_count > 1) netdev_set_rx_mode()
5760 dev_set_multicast(priv, hw, multicast); netdev_set_rx_mode()
5763 if (hw_priv->hw.dev_count > 1) netdev_set_rx_mode()
5771 if (MAX_MULTICAST_LIST != hw->multi_list_size) { netdev_set_rx_mode()
5772 hw->multi_list_size = MAX_MULTICAST_LIST; netdev_set_rx_mode()
5773 ++hw->all_multi; netdev_set_rx_mode()
5774 hw_set_multicast(hw, hw->all_multi); netdev_set_rx_mode()
5782 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN); netdev_for_each_mc_addr()
5784 hw->multi_list_size = (u8) i;
5785 hw_set_grp_addr(hw);
5787 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5788 --hw->all_multi;
5789 hw_set_multicast(hw, hw->all_multi);
5791 hw->multi_list_size = 0;
5792 hw_clr_multicast(hw);
5800 struct ksz_hw *hw = &hw_priv->hw; netdev_change_mtu() local
5807 if (hw->dev_count > 1) netdev_change_mtu()
5818 hw->features |= RX_HUGE_FRAME; netdev_change_mtu()
5821 hw->features &= ~RX_HUGE_FRAME; netdev_change_mtu()
5845 struct ksz_hw *hw = &hw_priv->hw; netdev_ioctl() local
5865 hw_r_phy(hw, port->linked->port_id, data->reg_num, netdev_ioctl()
5876 hw_w_phy(hw, port->linked->port_id, data->reg_num, netdev_ioctl()
5907 struct ksz_hw *hw = port->hw; mdio_read() local
5910 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out); mdio_read()
5927 struct ksz_hw *hw = port->hw; mdio_write() local
5932 hw_w_phy(hw, pi, reg_num << 1, val); mdio_write()
6138 struct ksz_hw *hw = &hw_priv->hw; netdev_get_regs() local
6151 *buf = readl(hw->io + len); netdev_get_regs()
6208 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr); netdev_set_wol()
6277 eeprom_data[i] = eeprom_read(&hw_priv->hw, i); netdev_get_eeprom()
6309 eeprom_data[i] = eeprom_read(&hw_priv->hw, i); netdev_set_eeprom()
6315 eeprom_write(&hw_priv->hw, i, eeprom_data[i]); netdev_set_eeprom()
6333 struct ksz_hw *hw = &hw_priv->hw; netdev_get_pauseparam() local
6335 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1; netdev_get_pauseparam()
6336 if (!hw->ksz_switch) { netdev_get_pauseparam()
6338 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0; netdev_get_pauseparam()
6340 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0; netdev_get_pauseparam()
6343 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, netdev_get_pauseparam()
6346 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, netdev_get_pauseparam()
6366 struct ksz_hw *hw = &hw_priv->hw; netdev_set_pauseparam() local
6375 hw->overrides &= ~PAUSE_FLOW_CTRL; netdev_set_pauseparam()
6377 if (hw->ksz_switch) { netdev_set_pauseparam()
6378 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, netdev_set_pauseparam()
6380 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, netdev_set_pauseparam()
6385 hw->overrides |= PAUSE_FLOW_CTRL; netdev_set_pauseparam()
6386 if (hw->ksz_switch) { netdev_set_pauseparam()
6387 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, netdev_set_pauseparam()
6389 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, netdev_set_pauseparam()
6392 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause); netdev_set_pauseparam()
6411 struct ksz_hw *hw = &hw_priv->hw; netdev_get_ringparam() local
6414 ring->tx_pending = hw->tx_desc_info.alloc; netdev_get_ringparam()
6416 ring->rx_pending = hw->rx_desc_info.alloc; netdev_get_ringparam()
6474 struct ksz_hw *hw = &hw_priv->hw; netdev_get_strings() local
6478 ETH_GSTRING_LEN * hw->mib_cnt); netdev_get_strings()
6494 struct ksz_hw *hw = &hw_priv->hw; netdev_get_sset_count() local
6498 return hw->mib_cnt; netdev_get_sset_count()
6517 struct ksz_hw *hw = &hw_priv->hw; netdev_get_ethtool_stats() local
6529 if (media_connected == hw->port_mib[p].state) { netdev_get_ethtool_stats()
6555 } else if (hw->port_mib[p].cnt_ptr) { netdev_get_ethtool_stats()
6563 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter); netdev_get_ethtool_stats()
6564 n = hw->mib_cnt; netdev_get_ethtool_stats()
6586 struct ksz_hw *hw = &hw_priv->hw; netdev_set_features() local
6592 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP; netdev_set_features()
6594 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP); netdev_set_features()
6596 if (hw->enabled) netdev_set_features()
6597 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); netdev_set_features()
6645 struct ksz_hw *hw = &hw_priv->hw; mib_read_work() local
6650 for (i = 0; i < hw->mib_port_cnt; i++) { mib_read_work()
6651 mib = &hw->port_mib[i]; mib_read_work()
6657 if (port_r_cnt(hw, i)) mib_read_work()
6671 next_jiffies += HZ * 1 * hw->mib_port_cnt; mib_read_work()
6693 hw_clr_wol_pme_status(&hw_priv->hw); mib_monitor()
6696 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) { mib_monitor()
6716 struct ksz_hw *hw = &hw_priv->hw; dev_monitor() local
6719 if (!(hw->features & LINK_INT_WORKING)) dev_monitor()
6873 hw_priv->hw.override_addr[j++] = (u8) num; get_mac_addr()
6874 hw_priv->hw.override_addr[5] += get_mac_addr()
6875 hw_priv->hw.id; get_mac_addr()
6877 hw_priv->hw.ksz_switch->other_addr[j++] = get_mac_addr()
6879 hw_priv->hw.ksz_switch->other_addr[5] += get_mac_addr()
6880 hw_priv->hw.id; get_mac_addr()
6888 hw_priv->hw.mac_override = 1; get_mac_addr()
6894 static void read_other_addr(struct ksz_hw *hw) read_other_addr() argument
6898 struct ksz_switch *sw = hw->ksz_switch; read_other_addr()
6901 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR); read_other_addr()
6921 struct ksz_hw *hw; pcidev_init() local
6963 hw = &hw_priv->hw; pcidev_init()
6965 hw->io = ioremap(reg_base, reg_len); pcidev_init()
6966 if (!hw->io) pcidev_init()
6969 cnt = hw_init(hw); pcidev_init()
6980 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq); pcidev_init()
6983 hw->dev_count = 1; pcidev_init()
6986 hw->addr_list_size = 0; pcidev_init()
6987 hw->mib_cnt = PORT_COUNTER_NUM; pcidev_init()
6988 hw->mib_port_cnt = 1; pcidev_init()
6993 hw->overrides |= FAST_AGING; pcidev_init()
6995 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM; pcidev_init()
6999 hw->dev_count = SWITCH_PORT_NUM; pcidev_init()
7000 hw->addr_list_size = SWITCH_PORT_NUM - 1; pcidev_init()
7004 if (1 == hw->dev_count) { pcidev_init()
7008 hw->mib_port_cnt = TOTAL_PORT_NUM; pcidev_init()
7009 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL); pcidev_init()
7010 if (!hw->ksz_switch) pcidev_init()
7013 sw = hw->ksz_switch; pcidev_init()
7015 for (i = 0; i < hw->mib_port_cnt; i++) pcidev_init()
7016 hw->port_mib[i].mib_start = 0; pcidev_init()
7018 hw->parent = hw_priv; pcidev_init()
7026 hw_priv->hw.id = net_device_present; pcidev_init()
7038 hw_read_addr(hw); pcidev_init()
7041 if (hw->dev_count > 1) { pcidev_init()
7042 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN); pcidev_init()
7043 read_other_addr(hw); pcidev_init()
7048 hw_setup(hw); pcidev_init()
7049 if (hw->ksz_switch) pcidev_init()
7050 sw_setup(hw); pcidev_init()
7062 for (i = 0; i < hw->dev_count; i++) { pcidev_init()
7079 port->hw = hw; pcidev_init()
7080 port->linked = &hw->port_info[port->first_port]; pcidev_init()
7083 hw->port_info[pi].port_id = pi; pcidev_init()
7084 hw->port_info[pi].pdev = dev; pcidev_init()
7085 hw->port_info[pi].state = media_disconnected; pcidev_init()
7088 dev->mem_start = (unsigned long) hw->io; pcidev_init()
7092 memcpy(dev->dev_addr, hw_priv->hw.override_addr, pcidev_init()
7096 if (ether_addr_equal(sw->other_addr, hw->override_addr)) pcidev_init()
7112 for (i = 0; i < hw->dev_count; i++) { pcidev_init()
7121 kfree(hw->ksz_switch); pcidev_init()
7124 iounmap(hw->io); pcidev_init()
7143 for (i = 0; i < hw_priv->hw.dev_count; i++) { pcidev_exit()
7147 if (hw_priv->hw.io) pcidev_exit()
7148 iounmap(hw_priv->hw.io); pcidev_exit()
7150 kfree(hw_priv->hw.ksz_switch); pcidev_exit()
7161 struct ksz_hw *hw = &hw_priv->hw; pcidev_resume() local
7168 hw_cfg_wol_pme(hw, 0); pcidev_resume()
7169 for (i = 0; i < hw->dev_count; i++) { pcidev_resume()
7187 struct ksz_hw *hw = &hw_priv->hw; pcidev_suspend() local
7192 for (i = 0; i < hw->dev_count; i++) { pcidev_suspend()
7203 hw_enable_wol(hw, hw_priv->wol_enable, net_addr); pcidev_suspend()
7204 hw_cfg_wol_pme(hw, 1); pcidev_suspend()
5688 dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv, struct ksz_hw *hw, int promiscuous) dev_set_promiscuous() argument
/linux-4.4.14/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_common.c25 * @hw: pointer to hardware structure
30 s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw) fm10k_get_bus_info_generic() argument
35 link_cap = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_LINK_CAP); fm10k_get_bus_info_generic()
39 hw->bus_caps.width = fm10k_bus_width_pcie_x1; fm10k_get_bus_info_generic()
42 hw->bus_caps.width = fm10k_bus_width_pcie_x2; fm10k_get_bus_info_generic()
45 hw->bus_caps.width = fm10k_bus_width_pcie_x4; fm10k_get_bus_info_generic()
48 hw->bus_caps.width = fm10k_bus_width_pcie_x8; fm10k_get_bus_info_generic()
51 hw->bus_caps.width = fm10k_bus_width_unknown; fm10k_get_bus_info_generic()
57 hw->bus_caps.speed = fm10k_bus_speed_2500; fm10k_get_bus_info_generic()
60 hw->bus_caps.speed = fm10k_bus_speed_5000; fm10k_get_bus_info_generic()
63 hw->bus_caps.speed = fm10k_bus_speed_8000; fm10k_get_bus_info_generic()
66 hw->bus_caps.speed = fm10k_bus_speed_unknown; fm10k_get_bus_info_generic()
71 device_cap = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_DEV_CAP); fm10k_get_bus_info_generic()
75 hw->bus_caps.payload = fm10k_bus_payload_128; fm10k_get_bus_info_generic()
78 hw->bus_caps.payload = fm10k_bus_payload_256; fm10k_get_bus_info_generic()
81 hw->bus_caps.payload = fm10k_bus_payload_512; fm10k_get_bus_info_generic()
84 hw->bus_caps.payload = fm10k_bus_payload_unknown; fm10k_get_bus_info_generic()
89 link_status = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_LINK_STATUS); fm10k_get_bus_info_generic()
93 hw->bus.width = fm10k_bus_width_pcie_x1; fm10k_get_bus_info_generic()
96 hw->bus.width = fm10k_bus_width_pcie_x2; fm10k_get_bus_info_generic()
99 hw->bus.width = fm10k_bus_width_pcie_x4; fm10k_get_bus_info_generic()
102 hw->bus.width = fm10k_bus_width_pcie_x8; fm10k_get_bus_info_generic()
105 hw->bus.width = fm10k_bus_width_unknown; fm10k_get_bus_info_generic()
111 hw->bus.speed = fm10k_bus_speed_2500; fm10k_get_bus_info_generic()
114 hw->bus.speed = fm10k_bus_speed_5000; fm10k_get_bus_info_generic()
117 hw->bus.speed = fm10k_bus_speed_8000; fm10k_get_bus_info_generic()
120 hw->bus.speed = fm10k_bus_speed_unknown; fm10k_get_bus_info_generic()
125 device_control = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_DEV_CTRL); fm10k_get_bus_info_generic()
129 hw->bus.payload = fm10k_bus_payload_128; fm10k_get_bus_info_generic()
132 hw->bus.payload = fm10k_bus_payload_256; fm10k_get_bus_info_generic()
135 hw->bus.payload = fm10k_bus_payload_512; fm10k_get_bus_info_generic()
138 hw->bus.payload = fm10k_bus_payload_unknown; fm10k_get_bus_info_generic()
145 static u16 fm10k_get_pcie_msix_count_generic(struct fm10k_hw *hw) fm10k_get_pcie_msix_count_generic() argument
150 msix_count = fm10k_read_pci_cfg_word(hw, FM10K_PCI_MSIX_MSG_CTRL); fm10k_get_pcie_msix_count_generic()
164 * @hw: pointer to the hardware structure
168 s32 fm10k_get_invariants_generic(struct fm10k_hw *hw) fm10k_get_invariants_generic() argument
170 struct fm10k_mac_info *mac = &hw->mac; fm10k_get_invariants_generic()
176 mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw); fm10k_get_invariants_generic()
183 * @hw: pointer to hardware structure
188 s32 fm10k_start_hw_generic(struct fm10k_hw *hw) fm10k_start_hw_generic() argument
191 hw->mac.tx_ready = true; fm10k_start_hw_generic()
198 * @hw: pointer to hardware structure
202 s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt) fm10k_disable_queues_generic() argument
208 hw->mac.tx_ready = false; fm10k_disable_queues_generic()
212 reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); fm10k_disable_queues_generic()
213 fm10k_write_reg(hw, FM10K_TXDCTL(i), fm10k_disable_queues_generic()
215 reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); fm10k_disable_queues_generic()
216 fm10k_write_reg(hw, FM10K_RXQCTL(i), fm10k_disable_queues_generic()
220 fm10k_write_flush(hw); fm10k_disable_queues_generic()
230 reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); fm10k_disable_queues_generic()
232 reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); fm10k_disable_queues_generic()
250 * @hw: pointer to hardware structure
253 s32 fm10k_stop_hw_generic(struct fm10k_hw *hw) fm10k_stop_hw_generic() argument
255 return fm10k_disable_queues_generic(hw, hw->mac.max_queues); fm10k_stop_hw_generic()
260 * @hw: pointer to the hardware structure
266 u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr, fm10k_read_hw_stats_32b() argument
269 u32 delta = fm10k_read_reg(hw, addr) - stat->base_l; fm10k_read_hw_stats_32b()
271 if (FM10K_REMOVED(hw->hw_addr)) fm10k_read_hw_stats_32b()
279 * @hw: pointer to the hardware structure
287 static u64 fm10k_read_hw_stats_48b(struct fm10k_hw *hw, u32 addr, fm10k_read_hw_stats_48b() argument
295 count_h = fm10k_read_reg(hw, addr + 1); fm10k_read_hw_stats_48b()
300 count_l = fm10k_read_reg(hw, addr); fm10k_read_hw_stats_48b()
301 count_h = fm10k_read_reg(hw, addr + 1); fm10k_read_hw_stats_48b()
333 * @hw: pointer to the hardware structure
340 static void fm10k_update_hw_stats_tx_q(struct fm10k_hw *hw, fm10k_update_hw_stats_tx_q() argument
348 id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx)); fm10k_update_hw_stats_tx_q()
352 tx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPTC(idx), fm10k_update_hw_stats_tx_q()
356 tx_bytes = fm10k_read_hw_stats_48b(hw, fm10k_update_hw_stats_tx_q()
362 id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx)); fm10k_update_hw_stats_tx_q()
384 * @hw: pointer to the hardware structure
391 static void fm10k_update_hw_stats_rx_q(struct fm10k_hw *hw, fm10k_update_hw_stats_rx_q() argument
399 id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx)); fm10k_update_hw_stats_rx_q()
403 rx_drops = fm10k_read_hw_stats_32b(hw, FM10K_QPRDC(idx), fm10k_update_hw_stats_rx_q()
406 rx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPRC(idx), fm10k_update_hw_stats_rx_q()
410 rx_bytes = fm10k_read_hw_stats_48b(hw, fm10k_update_hw_stats_rx_q()
416 id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx)); fm10k_update_hw_stats_rx_q()
440 * @hw: pointer to the hardware structure
448 void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q, fm10k_update_hw_stats_q() argument
454 fm10k_update_hw_stats_tx_q(hw, q, idx); fm10k_update_hw_stats_q()
455 fm10k_update_hw_stats_rx_q(hw, q, idx); fm10k_update_hw_stats_q()
461 * @hw: pointer to the hardware structure
481 * @hw: pointer to hardware structure
487 s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready) fm10k_get_host_state_generic() argument
489 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_get_host_state_generic()
490 struct fm10k_mac_info *mac = &hw->mac; fm10k_get_host_state_generic()
492 u32 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(0)); fm10k_get_host_state_generic()
495 mbx->ops.process(hw, mbx); fm10k_get_host_state_generic()
506 if (hw->mac.tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) { fm10k_get_host_state_generic()
H A Dfm10k_common.h29 u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg);
32 u32 fm10k_read_reg(struct fm10k_hw *hw, int reg);
35 #define fm10k_write_reg(hw, reg, val) \
37 u32 __iomem *hw_addr = ACCESS_ONCE((hw)->hw_addr); \
43 #define fm10k_write_sw_reg(hw, reg, val) \
45 u32 __iomem *sw_addr = ACCESS_ONCE((hw)->sw_addr); \
51 #define fm10k_write_flush(hw) fm10k_read_reg((hw), FM10K_CTRL)
52 s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw);
53 s32 fm10k_get_invariants_generic(struct fm10k_hw *hw);
54 s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt);
55 s32 fm10k_start_hw_generic(struct fm10k_hw *hw);
56 s32 fm10k_stop_hw_generic(struct fm10k_hw *hw);
57 u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,
60 void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,
64 s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready);
H A Dfm10k_pf.c26 * @hw: pointer to hardware structure
31 static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) fm10k_reset_hw_pf() argument
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); fm10k_reset_hw_pf()
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0); fm10k_reset_hw_pf()
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); fm10k_reset_hw_pf()
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); fm10k_reset_hw_pf()
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); fm10k_reset_hw_pf()
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); fm10k_reset_hw_pf()
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); fm10k_reset_hw_pf()
63 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2); fm10k_reset_hw_pf()
69 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); fm10k_reset_hw_pf()
72 fm10k_write_flush(hw); fm10k_reset_hw_pf()
76 reg = fm10k_read_reg(hw, FM10K_IP); fm10k_reset_hw_pf()
86 * @hw: pointer to hardware structure
90 static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) fm10k_is_ari_hierarchy_pf() argument
92 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); fm10k_is_ari_hierarchy_pf()
99 * @hw: pointer to hardware structure
102 static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) fm10k_init_hw_pf() argument
108 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); fm10k_init_hw_pf()
109 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), fm10k_init_hw_pf()
114 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); fm10k_init_hw_pf()
117 fm10k_write_reg(hw, FM10K_ITR2(0), 0); fm10k_init_hw_pf()
120 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); fm10k_init_hw_pf()
124 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); fm10k_init_hw_pf()
127 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); fm10k_init_hw_pf()
131 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); fm10k_init_hw_pf()
135 fm10k_write_reg(hw, FM10K_TQDLOC(i), fm10k_init_hw_pf()
138 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); fm10k_init_hw_pf()
141 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), fm10k_init_hw_pf()
146 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), fm10k_init_hw_pf()
154 switch (hw->bus.speed) { fm10k_init_hw_pf()
170 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); fm10k_init_hw_pf()
171 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); fm10k_init_hw_pf()
182 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); fm10k_init_hw_pf()
185 hw->mac.max_queues = FM10K_MAX_QUEUES_PF; fm10k_init_hw_pf()
188 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; fm10k_init_hw_pf()
195 * @hw: pointer to hardware structure
205 static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) fm10k_update_vlan_pf() argument
238 vlan_table = fm10k_read_reg(hw, reg); fm10k_update_vlan_pf()
246 fm10k_write_reg(hw, reg, vlan_table ^ mask); fm10k_update_vlan_pf()
254 * @hw: pointer to the HW structure
258 static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) fm10k_read_mac_addr_pf() argument
264 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); fm10k_read_mac_addr_pf()
274 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); fm10k_read_mac_addr_pf()
285 hw->mac.perm_addr[i] = perm_addr[i]; fm10k_read_mac_addr_pf()
286 hw->mac.addr[i] = perm_addr[i]; fm10k_read_mac_addr_pf()
294 * @hw: pointer to the HW structure
299 bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) fm10k_glort_valid_pf() argument
301 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; fm10k_glort_valid_pf()
303 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); fm10k_glort_valid_pf()
308 * @hw: pointer to the HW structure
318 static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, fm10k_update_xc_addr_pf() argument
321 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_update_xc_addr_pf()
329 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) fm10k_update_xc_addr_pf()
350 return mbx->ops.enqueue_tx(hw, mbx, msg); fm10k_update_xc_addr_pf()
355 * @hw: pointer to the HW structure
365 static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, fm10k_update_uc_addr_pf() argument
372 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); fm10k_update_uc_addr_pf()
377 * @hw: pointer to the HW structure
386 static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, fm10k_update_mc_addr_pf() argument
393 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); fm10k_update_mc_addr_pf()
398 * @hw: pointer to hardware structure
406 static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) fm10k_update_xcast_mode_pf() argument
408 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_update_xcast_mode_pf()
414 if (!fm10k_glort_valid_pf(hw, glort)) fm10k_update_xcast_mode_pf()
428 return mbx->ops.enqueue_tx(hw, mbx, msg); fm10k_update_xcast_mode_pf()
433 * @hw: pointer to hardware structure
439 static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) fm10k_update_int_moderator_pf() argument
444 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); fm10k_update_int_moderator_pf()
448 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) fm10k_update_int_moderator_pf()
453 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); fm10k_update_int_moderator_pf()
456 if (!hw->iov.num_vfs) fm10k_update_int_moderator_pf()
457 fm10k_write_reg(hw, FM10K_ITR2(0), i); fm10k_update_int_moderator_pf()
460 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); fm10k_update_int_moderator_pf()
465 * @hw: pointer to the HW structure
472 static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, fm10k_update_lport_state_pf() argument
475 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_update_lport_state_pf()
483 if (!fm10k_glort_valid_pf(hw, glort)) fm10k_update_lport_state_pf()
495 return mbx->ops.enqueue_tx(hw, mbx, msg); fm10k_update_lport_state_pf()
500 * @hw: pointer to hardware structure
507 static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, fm10k_configure_dglort_map_pf() argument
536 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); fm10k_configure_dglort_map_pf()
537 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); fm10k_configure_dglort_map_pf()
552 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); fm10k_configure_dglort_map_pf()
555 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); fm10k_configure_dglort_map_pf()
578 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); fm10k_configure_dglort_map_pf()
579 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); fm10k_configure_dglort_map_pf()
584 u16 fm10k_queues_per_pool(struct fm10k_hw *hw) fm10k_queues_per_pool() argument
586 u16 num_pools = hw->iov.num_pools; fm10k_queues_per_pool()
592 u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) fm10k_vf_queue_index() argument
594 u16 num_vfs = hw->iov.num_vfs; fm10k_vf_queue_index()
597 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); fm10k_vf_queue_index()
602 static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) fm10k_vectors_per_pool() argument
604 u16 num_pools = hw->iov.num_pools; fm10k_vectors_per_pool()
610 static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) fm10k_vf_vector_index() argument
614 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; fm10k_vf_vector_index()
621 * @hw: pointer to the HW structure
628 static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, fm10k_iov_assign_resources_pf() argument
632 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; fm10k_iov_assign_resources_pf()
640 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) fm10k_iov_assign_resources_pf()
644 hw->iov.num_vfs = num_vfs; fm10k_iov_assign_resources_pf()
645 hw->iov.num_pools = num_pools; fm10k_iov_assign_resources_pf()
649 qpp = fm10k_queues_per_pool(hw); fm10k_iov_assign_resources_pf()
650 vpp = fm10k_vectors_per_pool(hw); fm10k_iov_assign_resources_pf()
653 vf_q_idx = fm10k_vf_queue_index(hw, 0); fm10k_iov_assign_resources_pf()
658 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); fm10k_iov_assign_resources_pf()
659 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); fm10k_iov_assign_resources_pf()
660 fm10k_write_reg(hw, FM10K_TC_CREDIT(i), fm10k_iov_assign_resources_pf()
666 fm10k_write_reg(hw, FM10K_MBMEM(i), 0); fm10k_iov_assign_resources_pf()
669 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); fm10k_iov_assign_resources_pf()
670 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); fm10k_iov_assign_resources_pf()
674 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); fm10k_iov_assign_resources_pf()
675 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | fm10k_iov_assign_resources_pf()
677 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); fm10k_iov_assign_resources_pf()
685 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); fm10k_iov_assign_resources_pf()
687 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); fm10k_iov_assign_resources_pf()
691 fm10k_write_reg(hw, FM10K_ITR2(0), fm10k_iov_assign_resources_pf()
692 fm10k_vf_vector_index(hw, num_vfs - 1)); fm10k_iov_assign_resources_pf()
701 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); fm10k_iov_assign_resources_pf()
702 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), fm10k_iov_assign_resources_pf()
705 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), fm10k_iov_assign_resources_pf()
708 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), fm10k_iov_assign_resources_pf()
713 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); fm10k_iov_assign_resources_pf()
714 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); fm10k_iov_assign_resources_pf()
719 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); fm10k_iov_assign_resources_pf()
720 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); fm10k_iov_assign_resources_pf()
726 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); fm10k_iov_assign_resources_pf()
727 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); fm10k_iov_assign_resources_pf()
736 * @hw: pointer to the HW structure
743 static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) fm10k_iov_configure_tc_pf() argument
750 if (vf_idx >= hw->iov.num_vfs) fm10k_iov_configure_tc_pf()
754 switch (hw->bus.speed) { fm10k_iov_configure_tc_pf()
788 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); fm10k_iov_configure_tc_pf()
789 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); fm10k_iov_configure_tc_pf()
790 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); fm10k_iov_configure_tc_pf()
797 * @hw: pointer to the HW structure
803 static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) fm10k_iov_assign_int_moderator_pf() argument
808 if (vf_idx >= hw->iov.num_vfs) fm10k_iov_assign_int_moderator_pf()
812 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); fm10k_iov_assign_int_moderator_pf()
813 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); fm10k_iov_assign_int_moderator_pf()
817 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) fm10k_iov_assign_int_moderator_pf()
822 if (vf_idx == (hw->iov.num_vfs - 1)) fm10k_iov_assign_int_moderator_pf()
823 fm10k_write_reg(hw, FM10K_ITR2(0), i); fm10k_iov_assign_int_moderator_pf()
825 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); fm10k_iov_assign_int_moderator_pf()
832 * @hw: pointer to the HW structure
837 static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, fm10k_iov_assign_default_mac_vlan_pf() argument
846 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) fm10k_iov_assign_default_mac_vlan_pf()
850 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; fm10k_iov_assign_default_mac_vlan_pf()
851 queues_per_pool = fm10k_queues_per_pool(hw); fm10k_iov_assign_default_mac_vlan_pf()
855 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); fm10k_iov_assign_default_mac_vlan_pf()
859 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); fm10k_iov_assign_default_mac_vlan_pf()
860 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); fm10k_iov_assign_default_mac_vlan_pf()
875 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); fm10k_iov_assign_default_mac_vlan_pf()
878 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); fm10k_iov_assign_default_mac_vlan_pf()
887 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); fm10k_iov_assign_default_mac_vlan_pf()
903 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); fm10k_iov_assign_default_mac_vlan_pf()
904 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); fm10k_iov_assign_default_mac_vlan_pf()
915 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); fm10k_iov_assign_default_mac_vlan_pf()
918 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); fm10k_iov_assign_default_mac_vlan_pf()
924 * @hw: pointer to the HW structure
929 static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, fm10k_iov_reset_resources_pf() argument
939 if (vf_idx >= hw->iov.num_vfs) fm10k_iov_reset_resources_pf()
943 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32)); fm10k_iov_reset_resources_pf()
948 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); fm10k_iov_reset_resources_pf()
951 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); fm10k_iov_reset_resources_pf()
952 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); fm10k_iov_reset_resources_pf()
955 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; fm10k_iov_reset_resources_pf()
956 queues_per_pool = fm10k_queues_per_pool(hw); fm10k_iov_reset_resources_pf()
961 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); fm10k_iov_reset_resources_pf()
962 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); fm10k_iov_reset_resources_pf()
966 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); fm10k_iov_reset_resources_pf()
982 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); fm10k_iov_reset_resources_pf()
983 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); fm10k_iov_reset_resources_pf()
984 fm10k_write_reg(hw, FM10K_RXDCTL(i), fm10k_iov_reset_resources_pf()
987 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); fm10k_iov_reset_resources_pf()
991 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); fm10k_iov_reset_resources_pf()
992 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); fm10k_iov_reset_resources_pf()
993 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), fm10k_iov_reset_resources_pf()
998 hw->mac.ops.update_int_moderator(hw); fm10k_iov_reset_resources_pf()
1000 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); fm10k_iov_reset_resources_pf()
1003 if (vf_idx == (hw->iov.num_vfs - 1)) fm10k_iov_reset_resources_pf()
1004 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); fm10k_iov_reset_resources_pf()
1006 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); fm10k_iov_reset_resources_pf()
1010 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); fm10k_iov_reset_resources_pf()
1014 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); fm10k_iov_reset_resources_pf()
1016 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); fm10k_iov_reset_resources_pf()
1018 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); fm10k_iov_reset_resources_pf()
1020 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); fm10k_iov_reset_resources_pf()
1021 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); fm10k_iov_reset_resources_pf()
1036 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); fm10k_iov_reset_resources_pf()
1037 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); fm10k_iov_reset_resources_pf()
1038 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); fm10k_iov_reset_resources_pf()
1039 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); fm10k_iov_reset_resources_pf()
1044 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); fm10k_iov_reset_resources_pf()
1045 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); fm10k_iov_reset_resources_pf()
1053 * @hw: pointer to hardware structure
1061 static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, fm10k_iov_set_lport_pf() argument
1065 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; fm10k_iov_set_lport_pf()
1068 if (!fm10k_glort_valid_pf(hw, glort)) fm10k_iov_set_lport_pf()
1079 * @hw: pointer to hardware structure
1085 static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, fm10k_iov_reset_lport_pf() argument
1093 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); fm10k_iov_reset_lport_pf()
1097 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); fm10k_iov_reset_lport_pf()
1107 * @hw: pointer to hardware structure
1113 static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, fm10k_iov_update_stats_pf() argument
1120 qpp = fm10k_queues_per_pool(hw); fm10k_iov_update_stats_pf()
1121 idx = fm10k_vf_queue_index(hw, vf_idx); fm10k_iov_update_stats_pf()
1122 fm10k_update_hw_stats_q(hw, q, idx, qpp); fm10k_iov_update_stats_pf()
1125 static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw, fm10k_iov_report_timestamp_pf() argument
1135 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); fm10k_iov_report_timestamp_pf()
1140 * @hw: Pointer to hardware structure
1148 s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, fm10k_iov_msg_msix_pf() argument
1154 return hw->iov.ops.assign_int_moderator(hw, vf_idx); fm10k_iov_msg_msix_pf()
1159 * @hw: Pointer to hardware structure
1177 * @hw: Pointer to hardware structure
1185 s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, fm10k_iov_msg_mac_vlan_pf() argument
1222 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set); fm10k_iov_msg_mac_vlan_pf()
1248 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, fm10k_iov_msg_mac_vlan_pf()
1274 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, fm10k_iov_msg_mac_vlan_pf()
1322 * @hw: Pointer to hardware structure
1330 s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, fm10k_iov_msg_lport_state_pf() argument
1356 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); fm10k_iov_msg_lport_state_pf()
1363 err = fm10k_update_lport_state_pf(hw, vf_info->glort, fm10k_iov_msg_lport_state_pf()
1375 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); fm10k_iov_msg_lport_state_pf()
1383 mbx->ops.enqueue_tx(hw, mbx, msg); fm10k_iov_msg_lport_state_pf()
1388 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, fm10k_iov_msg_lport_state_pf()
1409 * @hw: pointer to hardware structure
1415 static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, fm10k_update_hw_stats_pf() argument
1422 id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); fm10k_update_hw_stats_pf()
1426 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, fm10k_update_hw_stats_pf()
1428 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); fm10k_update_hw_stats_pf()
1429 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); fm10k_update_hw_stats_pf()
1430 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); fm10k_update_hw_stats_pf()
1431 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); fm10k_update_hw_stats_pf()
1432 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, fm10k_update_hw_stats_pf()
1434 loopback_drop = fm10k_read_hw_stats_32b(hw, fm10k_update_hw_stats_pf()
1437 nodesc_drop = fm10k_read_hw_stats_32b(hw, fm10k_update_hw_stats_pf()
1443 id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); fm10k_update_hw_stats_pf()
1474 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); fm10k_update_hw_stats_pf()
1479 * @hw: pointer to hardware structure
1485 static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, fm10k_rebind_hw_stats_pf() argument
1499 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); fm10k_rebind_hw_stats_pf()
1502 fm10k_update_hw_stats_pf(hw, stats); fm10k_rebind_hw_stats_pf()
1507 * @hw: pointer to hardware structure
1513 static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) fm10k_set_dma_mask_pf() argument
1518 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); fm10k_set_dma_mask_pf()
1523 * @hw: pointer to hardware structure
1532 static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, fm10k_get_fault_pf() argument
1548 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); fm10k_get_fault_pf()
1553 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); fm10k_get_fault_pf()
1555 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); fm10k_get_fault_pf()
1556 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); fm10k_get_fault_pf()
1559 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); fm10k_get_fault_pf()
1576 * @hw: pointer to hardware structure
1579 static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) fm10k_request_lport_map_pf() argument
1581 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_request_lport_map_pf()
1588 return mbx->ops.enqueue_tx(hw, mbx, msg); fm10k_request_lport_map_pf()
1593 * @hw: pointer to hardware structure
1600 static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) fm10k_get_host_state_pf() argument
1606 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); fm10k_get_host_state_pf()
1611 ret_val = fm10k_get_host_state_generic(hw, switch_ready); fm10k_get_host_state_pf()
1616 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE) fm10k_get_host_state_pf()
1617 ret_val = fm10k_request_lport_map_pf(hw); fm10k_get_host_state_pf()
1631 * @hw: Pointer to hardware structure
1638 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, fm10k_msg_lport_map_pf() argument
1663 hw->mac.dglort_map = dglort_map; fm10k_msg_lport_map_pf()
1675 * @hw: Pointer to hardware structure
1681 s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, fm10k_msg_update_pvid_pf() argument
1698 if (!fm10k_glort_valid_pf(hw, glort)) fm10k_msg_update_pvid_pf()
1706 hw->mac.default_vid = pvid; fm10k_msg_update_pvid_pf()
1717 * the hw struct.
1735 * @hw: Pointer to hardware structure
1742 s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, fm10k_msg_err_pf() argument
1755 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); fm10k_msg_err_pf()
1756 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); fm10k_msg_err_pf()
1757 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); fm10k_msg_err_pf()
1760 hw->swapi.status = le32_to_cpu(err_msg.status); fm10k_msg_err_pf()
1775 * @hw: pointer to hardware structure
1786 static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb) fm10k_adjust_systime_pf() argument
1791 if (!hw->sw_addr) fm10k_adjust_systime_pf()
1818 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust); fm10k_adjust_systime_pf()
1825 * @hw: pointer to the hardware structure
1833 static u64 fm10k_read_systime_pf(struct fm10k_hw *hw) fm10k_read_systime_pf() argument
1837 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); fm10k_read_systime_pf()
1841 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME); fm10k_read_systime_pf()
1842 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); fm10k_read_systime_pf()
1893 static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) fm10k_get_invariants_pf() argument
1895 fm10k_get_invariants_generic(hw); fm10k_get_invariants_pf()
1897 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); fm10k_get_invariants_pf()
H A Dfm10k_iov.c25 static s32 fm10k_iov_msg_error(struct fm10k_hw *hw, u32 **results, fm10k_iov_msg_error() argument
29 struct fm10k_intfc *interface = hw->back; fm10k_iov_msg_error()
35 return fm10k_tlv_msg_error(hw, results, mbx); fm10k_iov_msg_error()
48 struct fm10k_hw *hw = &interface->hw; fm10k_iov_event() local
65 if (!(fm10k_read_reg(hw, FM10K_EICR) & FM10K_EICR_VFLR)) fm10k_iov_event()
70 vflre = fm10k_read_reg(hw, FM10K_PFVFLRE(0)); fm10k_iov_event()
72 vflre |= fm10k_read_reg(hw, FM10K_PFVFLRE(1)); fm10k_iov_event()
74 vflre |= fm10k_read_reg(hw, FM10K_PFVFLRE(0)); fm10k_iov_event()
84 hw->iov.ops.reset_resources(hw, vf_info); fm10k_iov_event()
85 vf_info->mbx.ops.connect(hw, &vf_info->mbx); fm10k_iov_event()
97 struct fm10k_hw *hw = &interface->hw; fm10k_iov_mbx() local
130 if (vf_info->vf_flags && !fm10k_glort_valid_pf(hw, glort)) fm10k_iov_mbx()
131 hw->iov.ops.reset_lport(hw, vf_info); fm10k_iov_mbx()
135 hw->iov.ops.reset_resources(hw, vf_info); fm10k_iov_mbx()
136 mbx->ops.connect(hw, mbx); fm10k_iov_mbx()
140 if (!hw->mbx.ops.tx_ready(&hw->mbx, FM10K_VFMBX_MSG_MTU)) { fm10k_iov_mbx()
147 mbx->ops.process(hw, mbx); fm10k_iov_mbx()
174 struct fm10k_hw *hw = &interface->hw; fm10k_iov_suspend() local
181 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_vf_rss), fm10k_iov_suspend()
188 hw->iov.ops.reset_resources(hw, vf_info); fm10k_iov_suspend()
189 hw->iov.ops.reset_lport(hw, vf_info); fm10k_iov_suspend()
198 struct fm10k_hw *hw = &interface->hw; fm10k_iov_resume() local
209 hw->iov.ops.assign_resources(hw, num_vfs, num_vfs); fm10k_iov_resume()
212 dglort.glort = hw->mac.dglort_map & FM10K_DGLORTMAP_NONE; fm10k_iov_resume()
215 dglort.rss_l = fls(fm10k_queues_per_pool(hw) - 1); fm10k_iov_resume()
216 dglort.queue_b = fm10k_vf_queue_index(hw, 0); fm10k_iov_resume()
217 dglort.vsi_l = fls(hw->iov.total_vfs - 1); fm10k_iov_resume()
220 hw->mac.ops.configure_dglort_map(hw, &dglort); fm10k_iov_resume()
227 if (i == ((~hw->mac.dglort_map) >> FM10K_DGLORTMAP_MASK_SHIFT)) fm10k_iov_resume()
231 hw->iov.ops.set_lport(hw, vf_info, i, fm10k_iov_resume()
235 hw->iov.ops.assign_default_mac_vlan(hw, vf_info); fm10k_iov_resume()
238 vf_info->mbx.ops.connect(hw, &vf_info->mbx); fm10k_iov_resume()
247 struct fm10k_hw *hw = &interface->hw; fm10k_iov_update_pvid() local
249 u16 vf_idx = (glort - hw->mac.dglort_map) & FM10K_DGLORTMAP_NONE; fm10k_iov_update_pvid()
263 hw->iov.ops.assign_default_mac_vlan(hw, vf_info); fm10k_iov_update_pvid()
288 struct fm10k_hw *hw = &interface->hw; fm10k_iov_alloc_data() local
297 if (!hw->iov.ops.assign_resources) fm10k_iov_alloc_data()
322 err = fm10k_pfvf_mbx_init(hw, &vf_info->mbx, iov_mbx_data, i); fm10k_iov_alloc_data()
406 struct fm10k_hw *hw = &interface->hw; fm10k_reset_vf_info() local
412 hw->iov.ops.reset_lport(hw, vf_info); fm10k_reset_vf_info()
415 hw->iov.ops.assign_default_mac_vlan(hw, vf_info); fm10k_reset_vf_info()
418 hw->iov.ops.set_lport(hw, vf_info, vf_info->vf_idx, fm10k_reset_vf_info()
452 struct fm10k_hw *hw = &interface->hw; fm10k_ndo_set_vf_vlan() local
473 hw->mac.ops.update_vlan(hw, FM10K_VLAN_ALL, vf_info->vsi, false); fm10k_ndo_set_vf_vlan()
485 struct fm10k_hw *hw = &interface->hw; fm10k_ndo_set_vf_bw() local
499 hw->iov.ops.configure_tc(hw, vf_idx, rate); fm10k_ndo_set_vf_bw()
H A Dfm10k_pci.c48 u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg) fm10k_read_pci_cfg_word() argument
50 struct fm10k_intfc *interface = hw->back; fm10k_read_pci_cfg_word()
53 if (FM10K_REMOVED(hw->hw_addr)) fm10k_read_pci_cfg_word()
58 fm10k_write_flush(hw); fm10k_read_pci_cfg_word()
63 u32 fm10k_read_reg(struct fm10k_hw *hw, int reg) fm10k_read_reg() argument
65 u32 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); fm10k_read_reg()
73 struct fm10k_intfc *interface = hw->back; fm10k_read_reg()
76 hw->hw_addr = NULL; fm10k_read_reg()
86 struct fm10k_hw *hw = &interface->hw; fm10k_hw_ready() local
88 fm10k_write_flush(hw); fm10k_hw_ready()
90 return FM10K_REMOVED(hw->hw_addr) ? -ENODEV : 0; fm10k_hw_ready()
128 if (netif_device_present(netdev) || interface->hw.hw_addr) fm10k_detach_subtask()
142 struct fm10k_hw *hw = &interface->hw; fm10k_reinit() local
166 err = hw->mac.ops.reset_hw(hw) ? : hw->mac.ops.init_hw(hw); fm10k_reinit()
174 if (hw->mac.type == fm10k_mac_vf) { fm10k_reinit()
175 if (is_valid_ether_addr(hw->mac.perm_addr)) { fm10k_reinit()
176 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); fm10k_reinit()
177 ether_addr_copy(netdev->perm_addr, hw->mac.perm_addr); fm10k_reinit()
178 ether_addr_copy(netdev->dev_addr, hw->mac.perm_addr); fm10k_reinit()
182 if (hw->mac.vlan_override) fm10k_reinit()
222 struct fm10k_hw *hw = &interface->hw; fm10k_configure_swpri_map() local
229 if (hw->mac.type != fm10k_mac_pf) fm10k_configure_swpri_map()
234 fm10k_write_reg(hw, FM10K_SWPRI_MAP(i), fm10k_configure_swpri_map()
244 struct fm10k_hw *hw = &interface->hw; fm10k_watchdog_update_host_state() local
264 err = hw->mac.ops.get_host_state(hw, &interface->host_ready); fm10k_watchdog_update_host_state()
330 struct fm10k_hw *hw = &interface->hw; fm10k_update_stats() local
391 hw->mac.ops.update_hw_stats(hw, &interface->stats); fm10k_update_stats()
393 for (i = 0; i < hw->mac.max_queues; i++) { fm10k_update_stats()
541 struct fm10k_hw *hw = &interface->hw; fm10k_configure_tx_ring() local
549 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0); fm10k_configure_tx_ring()
550 fm10k_write_flush(hw); fm10k_configure_tx_ring()
555 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); fm10k_configure_tx_ring()
556 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32); fm10k_configure_tx_ring()
557 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size); fm10k_configure_tx_ring()
560 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0); fm10k_configure_tx_ring()
561 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0); fm10k_configure_tx_ring()
572 txint = ring->q_vector->v_idx + NON_Q_VECTORS(hw); fm10k_configure_tx_ring()
576 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint); fm10k_configure_tx_ring()
579 fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx), fm10k_configure_tx_ring()
583 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl); fm10k_configure_tx_ring()
596 struct fm10k_hw *hw = &interface->hw; fm10k_enable_tx_ring() local
602 if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE) fm10k_enable_tx_ring()
608 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)); fm10k_enable_tx_ring()
645 struct fm10k_hw *hw = &interface->hw; fm10k_configure_rx_ring() local
655 fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), 0); fm10k_configure_rx_ring()
656 fm10k_write_flush(hw); fm10k_configure_rx_ring()
661 fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32)); fm10k_configure_rx_ring()
662 fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32); fm10k_configure_rx_ring()
663 fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size); fm10k_configure_rx_ring()
666 fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0); fm10k_configure_rx_ring()
667 fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0); fm10k_configure_rx_ring()
682 fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl); fm10k_configure_rx_ring()
692 fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl); fm10k_configure_rx_ring()
695 ring->vid = hw->mac.default_vid; fm10k_configure_rx_ring()
698 if (test_bit(hw->mac.default_vid, interface->active_vlans)) fm10k_configure_rx_ring()
703 rxint = ring->q_vector->v_idx + NON_Q_VECTORS(hw); fm10k_configure_rx_ring()
707 fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint); fm10k_configure_rx_ring()
710 fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl); fm10k_configure_rx_ring()
724 struct fm10k_hw *hw = &interface->hw; fm10k_update_rx_drop_en() local
741 fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl); fm10k_update_rx_drop_en()
754 struct fm10k_hw *hw = &interface->hw; fm10k_configure_dglort() local
760 fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]); fm10k_configure_dglort()
764 fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]); fm10k_configure_dglort()
779 fm10k_write_reg(hw, FM10K_MRQC(0), mrqc); fm10k_configure_dglort()
785 hw->mac.ops.configure_dglort_map(hw, &dglort); fm10k_configure_dglort()
794 hw->mac.ops.configure_dglort_map(hw, &dglort); fm10k_configure_dglort()
807 hw->mac.ops.configure_dglort_map(hw, &dglort); fm10k_configure_dglort()
857 struct fm10k_hw *hw = &interface->hw; fm10k_msix_mbx_vf() local
858 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_msix_mbx_vf()
861 fm10k_write_reg(hw, FM10K_VFITR(FM10K_MBX_VECTOR), fm10k_msix_mbx_vf()
866 mbx->ops.process(hw, mbx); fm10k_msix_mbx_vf()
870 hw->mac.get_host_state = 1; fm10k_msix_mbx_vf()
903 struct fm10k_hw *hw = &interface->hw; fm10k_handle_fault() local
972 hw->iov.ops.reset_lport(hw, vf_info); fm10k_handle_fault()
973 hw->iov.ops.reset_resources(hw, vf_info); fm10k_handle_fault()
976 hw->iov.ops.set_lport(hw, vf_info, vf, fm10k_handle_fault()
980 vf_info->mbx.ops.connect(hw, &vf_info->mbx); fm10k_handle_fault()
986 struct fm10k_hw *hw = &interface->hw; fm10k_report_fault() local
998 err = hw->mac.ops.get_fault(hw, type, &fault); fm10k_report_fault()
1011 struct fm10k_hw *hw = &interface->hw; fm10k_reset_drop_on_empty() local
1019 maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(7)); fm10k_reset_drop_on_empty()
1021 fm10k_write_reg(hw, FM10K_MAXHOLDQ(7), maxholdq); fm10k_reset_drop_on_empty()
1026 fm10k_write_reg(hw, FM10K_RXDCTL(q), rxdctl); fm10k_reset_drop_on_empty()
1042 maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(q / 32)); fm10k_reset_drop_on_empty()
1044 fm10k_write_reg(hw, FM10K_MAXHOLDQ(q / 32), maxholdq); fm10k_reset_drop_on_empty()
1051 struct fm10k_hw *hw = &interface->hw; fm10k_msix_mbx_pf() local
1052 struct fm10k_mbx_info *mbx = &hw->mbx; fm10k_msix_mbx_pf()
1056 eicr = fm10k_read_reg(hw, FM10K_EICR); fm10k_msix_mbx_pf()
1057 fm10k_write_reg(hw, FM10K_EICR, eicr & (FM10K_EICR_MAILBOX | fm10k_msix_mbx_pf()
1069 mbx->ops.process(hw, mbx); fm10k_msix_mbx_pf()
1082 hw->mac.dglort_map = FM10K_DGLORTMAP_NONE; fm10k_msix_mbx_pf()
1086 hw->mac.get_host_state = 1; fm10k_msix_mbx_pf()
1092 fm10k_write_reg(hw, FM10K_ITR(FM10K_MBX_VECTOR), fm10k_msix_mbx_pf()
1101 struct fm10k_hw *hw = &interface->hw; fm10k_mbx_free_irq() local
1105 hw->mbx.ops.disconnect(hw, &hw->mbx); fm10k_mbx_free_irq()
1108 if (hw->mac.type == fm10k_mac_pf) { fm10k_mbx_free_irq()
1109 fm10k_write_reg(hw, FM10K_EIMR, fm10k_mbx_free_irq()
1123 fm10k_write_reg(hw, itr_reg, FM10K_ITR_MASK_SET); fm10k_mbx_free_irq()
1128 static s32 fm10k_mbx_mac_addr(struct fm10k_hw *hw, u32 **results, fm10k_mbx_mac_addr() argument
1131 bool vlan_override = hw->mac.vlan_override; fm10k_mbx_mac_addr()
1132 u16 default_vid = hw->mac.default_vid; fm10k_mbx_mac_addr()
1136 err = fm10k_msg_mac_vlan_vf(hw, results, mbx); fm10k_mbx_mac_addr()
1140 interface = container_of(hw, struct fm10k_intfc, hw); fm10k_mbx_mac_addr()
1143 if (is_valid_ether_addr(hw->mac.perm_addr) && fm10k_mbx_mac_addr()
1144 memcmp(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN)) fm10k_mbx_mac_addr()
1148 if ((vlan_override != hw->mac.vlan_override) || fm10k_mbx_mac_addr()
1149 (default_vid != hw->mac.default_vid)) fm10k_mbx_mac_addr()
1155 static s32 fm10k_1588_msg_vf(struct fm10k_hw *hw, u32 **results, fm10k_1588_msg_vf() argument
1167 interface = container_of(hw, struct fm10k_intfc, hw); fm10k_1588_msg_vf()
1175 static s32 fm10k_mbx_error(struct fm10k_hw *hw, u32 **results, fm10k_mbx_error() argument
1181 interface = container_of(hw, struct fm10k_intfc, hw); fm10k_mbx_error()
1202 struct fm10k_hw *hw = &interface->hw; fm10k_mbx_request_irq_vf() local
1209 err = hw->mbx.ops.register_handlers(&hw->mbx, vf_mbx_data); fm10k_mbx_request_irq_vf()
1223 fm10k_write_reg(hw, FM10K_VFINT_MAP, itr); fm10k_mbx_request_irq_vf()
1226 fm10k_write_reg(hw, FM10K_VFITR(entry->entry), FM10K_ITR_ENABLE); fm10k_mbx_request_irq_vf()
1231 static s32 fm10k_lport_map(struct fm10k_hw *hw, u32 **results, fm10k_lport_map() argument
1235 u32 dglort_map = hw->mac.dglort_map; fm10k_lport_map()
1238 err = fm10k_msg_lport_map_pf(hw, results, mbx); fm10k_lport_map()
1242 interface = container_of(hw, struct fm10k_intfc, hw); fm10k_lport_map()
1245 if (dglort_map != hw->mac.dglort_map) fm10k_lport_map()
1251 static s32 fm10k_update_pvid(struct fm10k_hw *hw, u32 **results, fm10k_update_pvid() argument
1269 if (!fm10k_glort_valid_pf(hw, glort)) fm10k_update_pvid()
1276 interface = container_of(hw, struct fm10k_intfc, hw); fm10k_update_pvid()
1284 if (pvid != hw->mac.default_vid) fm10k_update_pvid()
1287 hw->mac.default_vid = pvid; fm10k_update_pvid()
1292 static s32 fm10k_1588_msg_pf(struct fm10k_hw *hw, u32 **results, fm10k_1588_msg_pf() argument
1307 interface = container_of(hw, struct fm10k_intfc, hw); fm10k_1588_msg_pf()
1321 if (!fm10k_glort_valid_pf(hw, sglort)) fm10k_1588_msg_pf()
1338 vf_idx = (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE) - sglort; fm10k_1588_msg_pf()
1345 err = hw->iov.ops.report_timestamp(hw, &iov_data->vf_info[vf_idx], fm10k_1588_msg_pf()
1369 struct fm10k_hw *hw = &interface->hw; fm10k_mbx_request_irq_pf() local
1377 err = hw->mbx.ops.register_handlers(&hw->mbx, pf_mbx_data); fm10k_mbx_request_irq_pf()
1391 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_PCIeFault), other_itr); fm10k_mbx_request_irq_pf()
1392 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_SwitchUpDown), other_itr); fm10k_mbx_request_irq_pf()
1393 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_SRAM), other_itr); fm10k_mbx_request_irq_pf()
1394 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_MaxHoldTime), other_itr); fm10k_mbx_request_irq_pf()
1395 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_VFLR), other_itr); fm10k_mbx_request_irq_pf()
1398 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_Mailbox), mbx_itr); fm10k_mbx_request_irq_pf()
1401 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) | fm10k_mbx_request_irq_pf()
1411 fm10k_write_reg(hw, FM10K_ITR(entry->entry), FM10K_ITR_ENABLE); fm10k_mbx_request_irq_pf()
1418 struct fm10k_hw *hw = &interface->hw; fm10k_mbx_request_irq() local
1422 if (hw->mac.type == fm10k_mac_pf) fm10k_mbx_request_irq()
1429 err = hw->mbx.ops.connect(hw, &hw->mbx); fm10k_mbx_request_irq()
1443 struct fm10k_hw *hw = &interface->hw; fm10k_qv_free_irq() local
1446 entry = &interface->msix_entries[NON_Q_VECTORS(hw) + vector]; fm10k_qv_free_irq()
1476 struct fm10k_hw *hw = &interface->hw; fm10k_qv_request_irq() local
1481 entry = &interface->msix_entries[NON_Q_VECTORS(hw)]; fm10k_qv_request_irq()
1503 q_vector->itr = (hw->mac.type == fm10k_mac_pf) ? fm10k_qv_request_irq()
1549 struct fm10k_hw *hw = &interface->hw; fm10k_up() local
1552 hw->mac.ops.start_hw(hw); fm10k_up()
1561 hw->mac.ops.update_int_moderator(hw); fm10k_up()
1576 hw->mac.get_host_state = 1; fm10k_up()
1594 struct fm10k_hw *hw = &interface->hw; fm10k_down() local
1619 hw->mac.ops.stop_hw(hw); fm10k_down()
1638 struct fm10k_hw *hw = &interface->hw; fm10k_sw_init() local
1646 hw->back = interface; fm10k_sw_init()
1647 hw->hw_addr = interface->uc_addr; fm10k_sw_init()
1650 hw->vendor_id = pdev->vendor; fm10k_sw_init()
1651 hw->device_id = pdev->device; fm10k_sw_init()
1652 hw->revision_id = pdev->revision; fm10k_sw_init()
1653 hw->subsystem_vendor_id = pdev->subsystem_vendor; fm10k_sw_init()
1654 hw->subsystem_device_id = pdev->subsystem_device; fm10k_sw_init()
1656 /* Setup hw api */ fm10k_sw_init()
1657 memcpy(&hw->mac.ops, fi->mac_ops, sizeof(hw->mac.ops)); fm10k_sw_init()
1658 hw->mac.type = fi->mac; fm10k_sw_init()
1662 memcpy(&hw->iov.ops, fi->iov_ops, sizeof(hw->iov.ops)); fm10k_sw_init()
1667 fi->get_invariants(hw); fm10k_sw_init()
1670 if (hw->mac.ops.get_bus_info) fm10k_sw_init()
1671 hw->mac.ops.get_bus_info(hw); fm10k_sw_init()
1674 if (hw->mac.ops.set_dma_mask) fm10k_sw_init()
1675 hw->mac.ops.set_dma_mask(hw, dma_get_mask(&pdev->dev)); fm10k_sw_init()
1687 err = hw->mac.ops.reset_hw(hw) ? : hw->mac.ops.init_hw(hw); fm10k_sw_init()
1694 hw->mac.ops.update_hw_stats(hw, &interface->stats); fm10k_sw_init()
1697 pci_sriov_set_totalvfs(pdev, hw->iov.total_vfs); fm10k_sw_init()
1700 eth_random_addr(hw->mac.addr); fm10k_sw_init()
1703 err = hw->mac.ops.read_mac_addr(hw); fm10k_sw_init()
1711 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); fm10k_sw_init()
1712 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); fm10k_sw_init()
1720 if (fm10k_read_reg(hw, FM10K_CTRL) & FM10K_CTRL_BAR4_ALLOWED) fm10k_sw_init()
1723 hw->sw_addr = interface->sw_addr; fm10k_sw_init()
1726 if (hw->mac.type != fm10k_mac_pf) { fm10k_sw_init()
1771 struct fm10k_hw *hw = &interface->hw; fm10k_slot_warn() local
1809 hw->bus.width, fm10k_slot_warn()
1814 (hw->bus.payload == fm10k_bus_payload_128 ? "128B" : fm10k_slot_warn()
1815 hw->bus.payload == fm10k_bus_payload_256 ? "256B" : fm10k_slot_warn()
1816 hw->bus.payload == fm10k_bus_payload_512 ? "512B" : fm10k_slot_warn()
1819 switch (hw->bus_caps.speed) { fm10k_slot_warn()
1822 expected_gts = 2 * hw->bus_caps.width; fm10k_slot_warn()
1826 expected_gts = 4 * hw->bus_caps.width; fm10k_slot_warn()
1830 expected_gts = 8 * hw->bus_caps.width; fm10k_slot_warn()
1844 (hw->bus_caps.speed == fm10k_bus_speed_2500 ? "2.5GT/s " : fm10k_slot_warn()
1845 hw->bus_caps.speed == fm10k_bus_speed_5000 ? "5.0GT/s " : fm10k_slot_warn()
1846 hw->bus_caps.speed == fm10k_bus_speed_8000 ? "8.0GT/s " : ""), fm10k_slot_warn()
1847 hw->bus_caps.width); fm10k_slot_warn()
2049 struct fm10k_hw *hw = &interface->hw; fm10k_resume() local
2070 hw->hw_addr = interface->uc_addr; fm10k_resume()
2073 err = hw->mac.ops.init_hw(&interface->hw); fm10k_resume()
2078 hw->mac.ops.rebind_hw_stats(hw, &interface->stats); fm10k_resume()
2223 interface->hw.hw_addr = interface->uc_addr; fm10k_io_slot_reset()
2247 struct fm10k_hw *hw = &interface->hw; fm10k_io_resume() local
2251 hw->mac.ops.init_hw(&interface->hw); fm10k_io_resume()
2254 hw->mac.ops.rebind_hw_stats(hw, &interface->stats); fm10k_io_resume()
/linux-4.4.14/drivers/net/wireless/orinoco/
H A Dhermes.c77 #define DMSG(stuff...) do {printk(KERN_DEBUG "hermes @ %p: " , hw->iobase); \
105 static int hermes_issue_cmd(struct hermes *hw, u16 cmd, u16 param0, hermes_issue_cmd() argument
112 reg = hermes_read_regn(hw, CMD); hermes_issue_cmd()
116 reg = hermes_read_regn(hw, CMD); hermes_issue_cmd()
121 hermes_write_regn(hw, PARAM2, param2); hermes_issue_cmd()
122 hermes_write_regn(hw, PARAM1, param1); hermes_issue_cmd()
123 hermes_write_regn(hw, PARAM0, param0); hermes_issue_cmd()
124 hermes_write_regn(hw, CMD, cmd); hermes_issue_cmd()
134 static int hermes_doicmd_wait(struct hermes *hw, u16 cmd, hermes_doicmd_wait() argument
142 err = hermes_issue_cmd(hw, cmd, parm0, parm1, parm2); hermes_doicmd_wait()
146 reg = hermes_read_regn(hw, EVSTAT); hermes_doicmd_wait()
151 reg = hermes_read_regn(hw, EVSTAT); hermes_doicmd_wait()
154 hermes_write_regn(hw, SWSUPPORT0, HERMES_MAGIC); hermes_doicmd_wait()
156 if (!hermes_present(hw)) { hermes_doicmd_wait()
158 hw->iobase); hermes_doicmd_wait()
166 hw->iobase, reg); hermes_doicmd_wait()
171 status = hermes_read_regn(hw, STATUS); hermes_doicmd_wait()
174 resp->resp0 = hermes_read_regn(hw, RESP0); hermes_doicmd_wait()
175 resp->resp1 = hermes_read_regn(hw, RESP1); hermes_doicmd_wait()
176 resp->resp2 = hermes_read_regn(hw, RESP2); hermes_doicmd_wait()
179 hermes_write_regn(hw, EVACK, HERMES_EV_CMD); hermes_doicmd_wait()
187 void hermes_struct_init(struct hermes *hw, void __iomem *address, hermes_struct_init() argument
190 hw->iobase = address; hermes_struct_init()
191 hw->reg_spacing = reg_spacing; hermes_struct_init()
192 hw->inten = 0x0; hermes_struct_init()
193 hw->eeprom_pda = false; hermes_struct_init()
194 hw->ops = &hermes_ops_local; hermes_struct_init()
198 static int hermes_init(struct hermes *hw) hermes_init() argument
205 hw->inten = 0x0; hermes_init()
206 hermes_write_regn(hw, INTEN, 0); hermes_init()
207 hermes_write_regn(hw, EVACK, 0xffff); hermes_init()
216 reg = hermes_read_regn(hw, CMD); hermes_init()
224 reg = hermes_read_regn(hw, CMD); hermes_init()
233 reg = hermes_read_regn(hw, EVSTAT); hermes_init()
234 hermes_write_regn(hw, EVACK, reg); hermes_init()
238 err = hermes_doicmd_wait(hw, HERMES_CMD_INIT, 0, 0, 0, NULL); hermes_init()
252 static int hermes_docmd_wait(struct hermes *hw, u16 cmd, u16 parm0, hermes_docmd_wait() argument
260 err = hermes_issue_cmd(hw, cmd, parm0, 0, 0); hermes_docmd_wait()
262 if (!hermes_present(hw)) { hermes_docmd_wait()
266 "0x%04x.\n", hw->iobase, cmd); hermes_docmd_wait()
272 hw->iobase, err, cmd); hermes_docmd_wait()
276 reg = hermes_read_regn(hw, EVSTAT); hermes_docmd_wait()
281 reg = hermes_read_regn(hw, EVSTAT); hermes_docmd_wait()
284 if (!hermes_present(hw)) { hermes_docmd_wait()
287 hw->iobase, cmd); hermes_docmd_wait()
294 "command 0x%04x completion.\n", hw->iobase, cmd); hermes_docmd_wait()
299 status = hermes_read_regn(hw, STATUS); hermes_docmd_wait()
302 resp->resp0 = hermes_read_regn(hw, RESP0); hermes_docmd_wait()
303 resp->resp1 = hermes_read_regn(hw, RESP1); hermes_docmd_wait()
304 resp->resp2 = hermes_read_regn(hw, RESP2); hermes_docmd_wait()
307 hermes_write_regn(hw, EVACK, HERMES_EV_CMD); hermes_docmd_wait()
316 static int hermes_allocate(struct hermes *hw, u16 size, u16 *fid) hermes_allocate() argument
325 err = hermes_docmd_wait(hw, HERMES_CMD_ALLOC, size, NULL); hermes_allocate()
329 reg = hermes_read_regn(hw, EVSTAT); hermes_allocate()
334 reg = hermes_read_regn(hw, EVSTAT); hermes_allocate()
337 if (!hermes_present(hw)) { hermes_allocate()
340 hw->iobase); hermes_allocate()
347 hw->iobase); hermes_allocate()
351 *fid = hermes_read_regn(hw, ALLOCFID); hermes_allocate()
352 hermes_write_regn(hw, EVACK, HERMES_EV_ALLOC); hermes_allocate()
366 static int hermes_bap_seek(struct hermes *hw, int bap, u16 id, u16 offset) hermes_bap_seek() argument
378 reg = hermes_read_reg(hw, oreg); hermes_bap_seek()
382 reg = hermes_read_reg(hw, oreg); hermes_bap_seek()
389 hermes_write_reg(hw, sreg, id); hermes_bap_seek()
390 hermes_write_reg(hw, oreg, offset); hermes_bap_seek()
394 reg = hermes_read_reg(hw, oreg); hermes_bap_seek()
398 reg = hermes_read_reg(hw, oreg); hermes_bap_seek()
403 "reg=0x%x id=0x%x offset=0x%x\n", hw->iobase, bap, hermes_bap_seek()
425 static int hermes_bap_pread(struct hermes *hw, int bap, void *buf, int len, hermes_bap_pread() argument
434 err = hermes_bap_seek(hw, bap, id, offset); hermes_bap_pread()
439 hermes_read_words(hw, dreg, buf, len / 2); hermes_bap_pread()
453 static int hermes_bap_pwrite(struct hermes *hw, int bap, const void *buf, hermes_bap_pwrite() argument
462 err = hermes_bap_seek(hw, bap, id, offset); hermes_bap_pwrite()
467 hermes_write_bytes(hw, dreg, buf, len); hermes_bap_pwrite()
481 static int hermes_read_ltv(struct hermes *hw, int bap, u16 rid, hermes_read_ltv() argument
492 err = hermes_docmd_wait(hw, HERMES_CMD_ACCESS, rid, NULL); hermes_read_ltv()
496 err = hermes_bap_seek(hw, bap, rid, 0); hermes_read_ltv()
500 rlength = hermes_read_reg(hw, dreg); hermes_read_ltv()
505 rtype = hermes_read_reg(hw, dreg); hermes_read_ltv()
513 hw->iobase, __func__, rid, rtype); hermes_read_ltv()
517 "(rid=0x%04x, len=0x%04x)\n", hw->iobase, hermes_read_ltv()
521 hermes_read_words(hw, dreg, buf, nwords); hermes_read_ltv()
526 static int hermes_write_ltv(struct hermes *hw, int bap, u16 rid, hermes_write_ltv() argument
536 err = hermes_bap_seek(hw, bap, rid, 0); hermes_write_ltv()
540 hermes_write_reg(hw, dreg, length); hermes_write_ltv()
541 hermes_write_reg(hw, dreg, rid); hermes_write_ltv()
545 hermes_write_bytes(hw, dreg, value, count << 1); hermes_write_ltv()
547 err = hermes_docmd_wait(hw, HERMES_CMD_ACCESS | HERMES_CMD_WRITE, hermes_write_ltv()
556 hermes_aux_setaddr(struct hermes *hw, u32 addr) hermes_aux_setaddr() argument
558 hermes_write_reg(hw, HERMES_AUXPAGE, (u16) (addr >> 7)); hermes_aux_setaddr()
559 hermes_write_reg(hw, HERMES_AUXOFFSET, (u16) (addr & 0x7F)); hermes_aux_setaddr()
563 hermes_aux_control(struct hermes *hw, int enabled) hermes_aux_control() argument
570 if (hermes_read_reg(hw, HERMES_CONTROL) == desired_state) hermes_aux_control()
573 hermes_write_reg(hw, HERMES_PARAM0, HERMES_AUX_PW0); hermes_aux_control()
574 hermes_write_reg(hw, HERMES_PARAM1, HERMES_AUX_PW1); hermes_aux_control()
575 hermes_write_reg(hw, HERMES_PARAM2, HERMES_AUX_PW2); hermes_aux_control()
576 hermes_write_reg(hw, HERMES_CONTROL, action); hermes_aux_control()
580 if (hermes_read_reg(hw, HERMES_CONTROL) == hermes_aux_control()
597 static int hermesi_program_init(struct hermes *hw, u32 offset) hermesi_program_init() argument
602 /*hw->inten = 0x0;*/ hermesi_program_init()
603 /*hermes_write_regn(hw, INTEN, 0);*/ hermesi_program_init()
604 /*hermes_set_irqmask(hw, 0);*/ hermesi_program_init()
607 hermes_write_regn(hw, EVACK, 0xFFFF); hermesi_program_init()
610 err = hw->ops->init_cmd_wait(hw, hermesi_program_init()
616 err = hw->ops->init_cmd_wait(hw, hermesi_program_init()
622 err = hermes_aux_control(hw, 1); hermesi_program_init()
629 err = hw->ops->init_cmd_wait(hw, hermesi_program_init()
646 static int hermesi_program_end(struct hermes *hw) hermesi_program_end() argument
652 rc = hw->ops->cmd_wait(hw, HERMES_PROGRAM_DISABLE, 0, &resp); hermesi_program_end()
662 err = hermes_aux_control(hw, 0); hermesi_program_end()
666 hermes_write_regn(hw, EVACK, 0xFFFF); hermesi_program_end()
669 (void) hw->ops->init_cmd_wait(hw, 0x0000 | HERMES_CMD_INIT, hermesi_program_end()
675 static int hermes_program_bytes(struct hermes *hw, const char *data, hermes_program_bytes() argument
681 hermes_aux_setaddr(hw, addr); hermes_program_bytes()
682 hermes_write_bytes(hw, HERMES_AUXDATA, data, len); hermes_program_bytes()
687 static int hermes_read_pda(struct hermes *hw, __le16 *pda, u32 pda_addr, hermes_read_pda() argument
695 if (hw->eeprom_pda) { hermes_read_pda()
699 ret = hw->ops->cmd_wait(hw, HERMES_CMD_READMIF, 0, NULL); hermes_read_pda()
714 ret = hermes_aux_control(hw, 1); hermes_read_pda()
720 hermes_aux_setaddr(hw, pda_addr); hermes_read_pda()
721 hermes_read_words(hw, HERMES_AUXDATA, data, data_len / 2); hermes_read_pda()
724 ret = hermes_aux_control(hw, 0); hermes_read_pda()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723com/
H A Dphy_common.h29 #define RT_CANNOT_IO(hw) false
48 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
50 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
53 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
55 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
58 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
61 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw);
68 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
73 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg,
75 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw,
77 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw,
80 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw,
82 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
84 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw,
86 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw);
87 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode);
H A Dphy_common.c33 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw, rtl8723_phy_query_bb_reg() argument
36 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_query_bb_reg()
52 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, rtl8723_phy_set_bb_reg() argument
55 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_set_bb_reg()
88 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw, rtl8723_phy_rf_serial_read() argument
91 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_rf_serial_read()
101 if (RT_CANNOT_IO(hw)) { rtl8723_phy_rf_serial_read()
105 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); rtl8723_phy_rf_serial_read()
109 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); rtl8723_phy_rf_serial_read()
112 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, rtl8723_phy_rf_serial_read()
115 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); rtl8723_phy_rf_serial_read()
117 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, rtl8723_phy_rf_serial_read()
121 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, rtl8723_phy_rf_serial_read()
124 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, rtl8723_phy_rf_serial_read()
127 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, rtl8723_phy_rf_serial_read()
130 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, rtl8723_phy_rf_serial_read()
139 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw, rtl8723_phy_rf_serial_write() argument
145 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_rf_serial_write()
149 if (RT_CANNOT_IO(hw)) { rtl8723_phy_rf_serial_write()
156 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); rtl8723_phy_rf_serial_write()
164 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, rtl8723_phy_txpwr_idx_to_dbm() argument
188 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw) rtl8723_phy_init_bb_rf_reg_def() argument
190 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_init_bb_rf_reg_def()
302 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, rtl8723_phy_path_a_fill_iqk_matrix() argument
314 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, rtl8723_phy_path_a_fill_iqk_matrix()
320 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); rtl8723_phy_path_a_fill_iqk_matrix()
321 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), rtl8723_phy_path_a_fill_iqk_matrix()
327 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, rtl8723_phy_path_a_fill_iqk_matrix()
329 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, rtl8723_phy_path_a_fill_iqk_matrix()
331 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), rtl8723_phy_path_a_fill_iqk_matrix()
336 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); rtl8723_phy_path_a_fill_iqk_matrix()
338 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); rtl8723_phy_path_a_fill_iqk_matrix()
340 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); rtl8723_phy_path_a_fill_iqk_matrix()
345 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg, rtl8723_save_adda_registers() argument
351 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); rtl8723_save_adda_registers()
355 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw, rtl8723_phy_save_mac_registers() argument
358 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_save_mac_registers()
367 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw, rtl8723_phy_reload_adda_registers() argument
374 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); rtl8723_phy_reload_adda_registers()
378 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw, rtl8723_phy_reload_mac_registers() argument
381 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_reload_mac_registers()
390 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, rtl8723_phy_path_adda_on() argument
393 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); rtl8723_phy_path_adda_on()
401 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); rtl8723_phy_path_adda_on()
403 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); rtl8723_phy_path_adda_on()
408 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); rtl8723_phy_path_adda_on()
412 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); rtl8723_phy_path_adda_on()
416 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw, rtl8723_phy_mac_setting_calibration() argument
419 struct rtl_priv *rtlpriv = rtl_priv(hw); rtl8723_phy_mac_setting_calibration()
431 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw) rtl8723_phy_path_a_standby() argument
433 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); rtl8723_phy_path_a_standby()
434 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); rtl8723_phy_path_a_standby()
435 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); rtl8723_phy_path_a_standby()
439 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) rtl8723_phy_pi_mode_switch() argument
444 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); rtl8723_phy_pi_mode_switch()
445 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); rtl8723_phy_pi_mode_switch()
/linux-4.4.14/drivers/net/wireless/b43/
H A Drfkill.h7 void b43_rfkill_poll(struct ieee80211_hw *hw);
/linux-4.4.14/drivers/net/wireless/b43legacy/
H A Drfkill.h7 void b43legacy_rfkill_poll(struct ieee80211_hw *hw);
/linux-4.4.14/drivers/net/ethernet/intel/ixgbevf/
H A Dvf.c32 * @hw: pointer to hardware structure
39 static s32 ixgbevf_start_hw_vf(struct ixgbe_hw *hw) ixgbevf_start_hw_vf() argument
42 hw->adapter_stopped = false; ixgbevf_start_hw_vf()
49 * @hw: pointer to hardware structure
54 static s32 ixgbevf_init_hw_vf(struct ixgbe_hw *hw) ixgbevf_init_hw_vf() argument
56 s32 status = hw->mac.ops.start_hw(hw); ixgbevf_init_hw_vf()
58 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); ixgbevf_init_hw_vf()
65 * @hw: pointer to hardware structure
70 static s32 ixgbevf_reset_hw_vf(struct ixgbe_hw *hw) ixgbevf_reset_hw_vf() argument
72 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_reset_hw_vf()
79 hw->mac.ops.stop_adapter(hw); ixgbevf_reset_hw_vf()
82 hw->api_version = ixgbe_mbox_api_10; ixgbevf_reset_hw_vf()
84 IXGBE_WRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST); ixgbevf_reset_hw_vf()
85 IXGBE_WRITE_FLUSH(hw); ixgbevf_reset_hw_vf()
88 while (!mbx->ops.check_for_rst(hw) && timeout) { ixgbevf_reset_hw_vf()
100 mbx->ops.write_posted(hw, msgbuf, 1); ixgbevf_reset_hw_vf()
108 ret_val = mbx->ops.read_posted(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN); ixgbevf_reset_hw_vf()
120 ether_addr_copy(hw->mac.perm_addr, addr); ixgbevf_reset_hw_vf()
121 hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD]; ixgbevf_reset_hw_vf()
128 * @hw: pointer to hardware structure
135 static s32 ixgbevf_stop_hw_vf(struct ixgbe_hw *hw) ixgbevf_stop_hw_vf() argument
144 hw->adapter_stopped = true; ixgbevf_stop_hw_vf()
147 number_of_queues = hw->mac.max_rx_queues; ixgbevf_stop_hw_vf()
149 reg_val = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)); ixgbevf_stop_hw_vf()
152 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); ixgbevf_stop_hw_vf()
156 IXGBE_WRITE_FLUSH(hw); ixgbevf_stop_hw_vf()
159 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); ixgbevf_stop_hw_vf()
162 IXGBE_READ_REG(hw, IXGBE_VTEICR); ixgbevf_stop_hw_vf()
165 number_of_queues = hw->mac.max_tx_queues; ixgbevf_stop_hw_vf()
167 reg_val = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i)); ixgbevf_stop_hw_vf()
170 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), reg_val); ixgbevf_stop_hw_vf()
179 * @hw: pointer to hardware structure
189 static s32 ixgbevf_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) ixgbevf_mta_vector() argument
193 switch (hw->mac.mc_filter_type) { ixgbevf_mta_vector()
217 * @hw: pointer to the HW structure
220 static s32 ixgbevf_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr) ixgbevf_get_mac_addr_vf() argument
222 ether_addr_copy(mac_addr, hw->mac.perm_addr); ixgbevf_get_mac_addr_vf()
227 static s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr) ixgbevf_set_uc_addr_vf() argument
229 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_set_uc_addr_vf()
244 ret_val = mbx->ops.write_posted(hw, msgbuf, 3); ixgbevf_set_uc_addr_vf()
247 ret_val = mbx->ops.read_posted(hw, msgbuf, 3); ixgbevf_set_uc_addr_vf()
270 int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues) ixgbevf_get_reta_locked() argument
288 if (hw->api_version != ixgbe_mbox_api_12 || ixgbevf_get_reta_locked()
289 hw->mac.type >= ixgbe_mac_X550_vf) ixgbevf_get_reta_locked()
294 err = hw->mbx.ops.write_posted(hw, msgbuf, 1); ixgbevf_get_reta_locked()
299 err = hw->mbx.ops.read_posted(hw, msgbuf, dwords + 1); ixgbevf_get_reta_locked()
330 * @hw: pointer to the HW structure
338 int ixgbevf_get_rss_key_locked(struct ixgbe_hw *hw, u8 *rss_key) ixgbevf_get_rss_key_locked() argument
349 if (hw->api_version != ixgbe_mbox_api_12 || ixgbevf_get_rss_key_locked()
350 hw->mac.type >= ixgbe_mac_X550_vf) ixgbevf_get_rss_key_locked()
354 err = hw->mbx.ops.write_posted(hw, msgbuf, 1); ixgbevf_get_rss_key_locked()
359 err = hw->mbx.ops.read_posted(hw, msgbuf, 11); ixgbevf_get_rss_key_locked()
384 * @hw: pointer to hardware structure
389 static s32 ixgbevf_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, ixgbevf_set_rar_vf() argument
392 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_set_rar_vf()
400 ret_val = mbx->ops.write_posted(hw, msgbuf, 3); ixgbevf_set_rar_vf()
403 ret_val = mbx->ops.read_posted(hw, msgbuf, 3); ixgbevf_set_rar_vf()
410 ixgbevf_get_mac_addr_vf(hw, hw->mac.addr); ixgbevf_set_rar_vf()
415 static void ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, ixgbevf_write_msg_read_ack() argument
418 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_write_msg_read_ack()
420 s32 retval = mbx->ops.write_posted(hw, msg, size); ixgbevf_write_msg_read_ack()
423 mbx->ops.read_posted(hw, retmsg, size); ixgbevf_write_msg_read_ack()
428 * @hw: pointer to the HW structure
433 static s32 ixgbevf_update_mc_addr_list_vf(struct ixgbe_hw *hw, ixgbevf_update_mc_addr_list_vf() argument
463 vector_list[i++] = ixgbevf_mta_vector(hw, ha->addr); netdev_for_each_mc_addr()
466 ixgbevf_write_msg_read_ack(hw, msgbuf, IXGBE_VFMAILBOX_SIZE);
473 * @hw: pointer to the HW structure
479 static s32 ixgbevf_update_xcast_mode(struct ixgbe_hw *hw, ixgbevf_update_xcast_mode() argument
482 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_update_xcast_mode()
486 switch (hw->api_version) { ixgbevf_update_xcast_mode()
496 err = mbx->ops.write_posted(hw, msgbuf, 2); ixgbevf_update_xcast_mode()
500 err = mbx->ops.read_posted(hw, msgbuf, 2); ixgbevf_update_xcast_mode()
513 * @hw: pointer to the HW structure
518 static s32 ixgbevf_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, ixgbevf_set_vfta_vf() argument
521 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_set_vfta_vf()
530 err = mbx->ops.write_posted(hw, msgbuf, 2); ixgbevf_set_vfta_vf()
534 err = mbx->ops.read_posted(hw, msgbuf, 2); ixgbevf_set_vfta_vf()
551 * @hw: pointer to hardware structure
559 static s32 ixgbevf_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbevf_setup_mac_link_vf() argument
568 * @hw: pointer to hardware structure
575 static s32 ixgbevf_check_mac_link_vf(struct ixgbe_hw *hw, ixgbevf_check_mac_link_vf() argument
580 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_check_mac_link_vf()
581 struct ixgbe_mac_info *mac = &hw->mac; ixgbevf_check_mac_link_vf()
587 if (!mbx->ops.check_for_rst(hw) || !mbx->timeout) ixgbevf_check_mac_link_vf()
594 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); ixgbevf_check_mac_link_vf()
606 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); ixgbevf_check_mac_link_vf()
628 if (mbx->ops.read(hw, &in_msg, 1)) ixgbevf_check_mac_link_vf()
656 * @hw: pointer to the HW structure
659 void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size) ixgbevf_rlpml_set_vf() argument
665 ixgbevf_write_msg_read_ack(hw, msgbuf, 2); ixgbevf_rlpml_set_vf()
670 * @hw: pointer to the HW structure
673 int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api) ixgbevf_negotiate_api_version() argument
682 err = hw->mbx.ops.write_posted(hw, msg, 3); ixgbevf_negotiate_api_version()
685 err = hw->mbx.ops.read_posted(hw, msg, 3); ixgbevf_negotiate_api_version()
692 hw->api_version = api; ixgbevf_negotiate_api_version()
702 int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs, ixgbevf_get_queues() argument
709 switch (hw->api_version) { ixgbevf_get_queues()
720 err = hw->mbx.ops.write_posted(hw, msg, 5); ixgbevf_get_queues()
723 err = hw->mbx.ops.read_posted(hw, msg, 5); ixgbevf_get_queues()
736 hw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES]; ixgbevf_get_queues()
737 if (hw->mac.max_tx_queues == 0 || ixgbevf_get_queues()
738 hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES) ixgbevf_get_queues()
739 hw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES; ixgbevf_get_queues()
741 hw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES]; ixgbevf_get_queues()
742 if (hw->mac.max_rx_queues == 0 || ixgbevf_get_queues()
743 hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES) ixgbevf_get_queues()
744 hw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES; ixgbevf_get_queues()
748 if (*num_tcs > hw->mac.max_rx_queues) ixgbevf_get_queues()
753 if (*default_tc >= hw->mac.max_tx_queues) ixgbevf_get_queues()
H A Dmbx.c32 * @hw: pointer to the HW structure
36 static s32 ixgbevf_poll_for_msg(struct ixgbe_hw *hw) ixgbevf_poll_for_msg() argument
38 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_poll_for_msg()
41 while (countdown && mbx->ops.check_for_msg(hw)) { ixgbevf_poll_for_msg()
55 * @hw: pointer to the HW structure
59 static s32 ixgbevf_poll_for_ack(struct ixgbe_hw *hw) ixgbevf_poll_for_ack() argument
61 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_poll_for_ack()
64 while (countdown && mbx->ops.check_for_ack(hw)) { ixgbevf_poll_for_ack()
78 * @hw: pointer to the HW structure
85 static s32 ixgbevf_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size) ixgbevf_read_posted_mbx() argument
87 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_read_posted_mbx()
93 ret_val = ixgbevf_poll_for_msg(hw); ixgbevf_read_posted_mbx()
97 ret_val = mbx->ops.read(hw, msg, size); ixgbevf_read_posted_mbx()
104 * @hw: pointer to the HW structure
111 static s32 ixgbevf_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size) ixgbevf_write_posted_mbx() argument
113 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_write_posted_mbx()
121 ret_val = mbx->ops.write(hw, msg, size); ixgbevf_write_posted_mbx()
125 ret_val = ixgbevf_poll_for_ack(hw); ixgbevf_write_posted_mbx()
132 * @hw: pointer to the HW structure
137 static u32 ixgbevf_read_v2p_mailbox(struct ixgbe_hw *hw) ixgbevf_read_v2p_mailbox() argument
139 u32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX); ixgbevf_read_v2p_mailbox()
141 v2p_mailbox |= hw->mbx.v2p_mailbox; ixgbevf_read_v2p_mailbox()
142 hw->mbx.v2p_mailbox |= v2p_mailbox & IXGBE_VFMAILBOX_R2C_BITS; ixgbevf_read_v2p_mailbox()
149 * @hw: pointer to the HW structure
155 static s32 ixgbevf_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask) ixgbevf_check_for_bit_vf() argument
157 u32 v2p_mailbox = ixgbevf_read_v2p_mailbox(hw); ixgbevf_check_for_bit_vf()
163 hw->mbx.v2p_mailbox &= ~mask; ixgbevf_check_for_bit_vf()
170 * @hw: pointer to the HW structure
174 static s32 ixgbevf_check_for_msg_vf(struct ixgbe_hw *hw) ixgbevf_check_for_msg_vf() argument
178 if (!ixgbevf_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFSTS)) { ixgbevf_check_for_msg_vf()
180 hw->mbx.stats.reqs++; ixgbevf_check_for_msg_vf()
188 * @hw: pointer to the HW structure
192 static s32 ixgbevf_check_for_ack_vf(struct ixgbe_hw *hw) ixgbevf_check_for_ack_vf() argument
196 if (!ixgbevf_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFACK)) { ixgbevf_check_for_ack_vf()
198 hw->mbx.stats.acks++; ixgbevf_check_for_ack_vf()
206 * @hw: pointer to the HW structure
210 static s32 ixgbevf_check_for_rst_vf(struct ixgbe_hw *hw) ixgbevf_check_for_rst_vf() argument
214 if (!ixgbevf_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD | ixgbevf_check_for_rst_vf()
217 hw->mbx.stats.rsts++; ixgbevf_check_for_rst_vf()
225 * @hw: pointer to the HW structure
229 static s32 ixgbevf_obtain_mbx_lock_vf(struct ixgbe_hw *hw) ixgbevf_obtain_mbx_lock_vf() argument
234 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_VFU); ixgbevf_obtain_mbx_lock_vf()
237 if (ixgbevf_read_v2p_mailbox(hw) & IXGBE_VFMAILBOX_VFU) ixgbevf_obtain_mbx_lock_vf()
245 * @hw: pointer to the HW structure
251 static s32 ixgbevf_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size) ixgbevf_write_mbx_vf() argument
257 ret_val = ixgbevf_obtain_mbx_lock_vf(hw); ixgbevf_write_mbx_vf()
262 ixgbevf_check_for_msg_vf(hw); ixgbevf_write_mbx_vf()
263 ixgbevf_check_for_ack_vf(hw); ixgbevf_write_mbx_vf()
267 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_VFMBMEM, i, msg[i]); ixgbevf_write_mbx_vf()
270 hw->mbx.stats.msgs_tx++; ixgbevf_write_mbx_vf()
273 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_REQ); ixgbevf_write_mbx_vf()
281 * @hw: pointer to the HW structure
287 static s32 ixgbevf_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size) ixgbevf_read_mbx_vf() argument
293 ret_val = ixgbevf_obtain_mbx_lock_vf(hw); ixgbevf_read_mbx_vf()
299 msg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_VFMBMEM, i); ixgbevf_read_mbx_vf()
302 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_ACK); ixgbevf_read_mbx_vf()
305 hw->mbx.stats.msgs_rx++; ixgbevf_read_mbx_vf()
313 * @hw: pointer to the HW structure
315 * Initializes the hw->mbx struct to correct values for VF mailbox
317 static s32 ixgbevf_init_mbx_params_vf(struct ixgbe_hw *hw) ixgbevf_init_mbx_params_vf() argument
319 struct ixgbe_mbx_info *mbx = &hw->mbx; ixgbevf_init_mbx_params_vf()
/linux-4.4.14/drivers/video/fbdev/matrox/
H A Dmatroxfb_DAC1064.c94 minfo->hw.DACclk[0] = m; DAC1064_setpclk()
95 minfo->hw.DACclk[1] = n; DAC1064_setpclk()
96 minfo->hw.DACclk[2] = p; DAC1064_setpclk()
103 struct matrox_hw_state *hw = &minfo->hw; DAC1064_setmclk() local
109 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); DBG()
110 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); DBG()
111 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); DBG()
114 mx = hw->MXoptionReg | 0x00000004;
142 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);
143 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);
144 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);
160 hw->MXoptionReg = mx;
168 struct matrox_hw_state *hw = &minfo->hw; g450_set_plls() local
172 c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */ g450_set_plls()
174 hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */ g450_set_plls()
179 hw->DACreg[POS1064_XPWRCTRL] &= ~0x10; /* Powerdown CRTC2 */ g450_set_plls()
193 hw->DACreg[POS1064_XPWRCTRL] |= 0x02; g450_set_plls()
195 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); g450_set_plls()
199 hw->DACreg[POS1064_XPIXCLKCTRL] &= ~M1064_XPIXCLKCTRL_PLL_UP; g450_set_plls()
201 hw->DACreg[POS1064_XPIXCLKCTRL] |= M1064_XPIXCLKCTRL_PLL_UP; g450_set_plls()
203 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); g450_set_plls()
206 if (c2_ctl != hw->crtc2.ctl) { g450_set_plls()
207 hw->crtc2.ctl = c2_ctl; g450_set_plls()
217 hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-50 */ g450_set_plls()
219 hw->DACreg[POS1064_XPANMODE] = 0x08; /* 34-62 */ g450_set_plls()
221 hw->DACreg[POS1064_XPANMODE] = 0x10; /* 42-78 */ g450_set_plls()
223 hw->DACreg[POS1064_XPANMODE] = 0x18; /* 62-92 */ g450_set_plls()
225 hw->DACreg[POS1064_XPANMODE] = 0x20; /* 74-108 */ g450_set_plls()
227 hw->DACreg[POS1064_XPANMODE] = 0x28; /* 94-122 */ g450_set_plls()
229 hw->DACreg[POS1064_XPANMODE] = 0x30; /* 108-132 */ g450_set_plls()
231 hw->DACreg[POS1064_XPANMODE] = 0x38; /* 120-168 */ g450_set_plls()
236 hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-54 */ g450_set_plls()
238 hw->DACreg[POS1064_XPANMODE] = 0x08; /* 38-70 */ g450_set_plls()
240 hw->DACreg[POS1064_XPANMODE] = 0x10; /* 56-96 */ g450_set_plls()
242 hw->DACreg[POS1064_XPANMODE] = 0x18; /* 80-114 */ g450_set_plls()
244 hw->DACreg[POS1064_XPANMODE] = 0x20; /* 102-144 */ g450_set_plls()
246 hw->DACreg[POS1064_XPANMODE] = 0x28; /* 132-166 */ g450_set_plls()
248 hw->DACreg[POS1064_XPANMODE] = 0x30; /* 154-182 */ g450_set_plls()
250 hw->DACreg[POS1064_XPANMODE] = 0x38; /* 170-204 */ g450_set_plls()
258 struct matrox_hw_state *hw = &minfo->hw; DAC1064_global_init() local
260 hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK; DAC1064_global_init()
261 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN; DAC1064_global_init()
262 hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL; DAC1064_global_init()
265 hw->DACreg[POS1064_XPWRCTRL] = 0x1F; /* powerup everything */ DAC1064_global_init()
266 hw->DACreg[POS1064_XOUTPUTCONN] = 0x00; /* disable outputs */ DAC1064_global_init()
267 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; DAC1064_global_init()
271 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01; /* enable output; CRTC1/2 selection is in CRTC2 ctl */ DAC1064_global_init()
274 hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN; DAC1064_global_init()
279 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04; DAC1064_global_init()
283 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08; DAC1064_global_init()
285 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C; DAC1064_global_init()
289 hw->DACreg[POS1064_XPWRCTRL] &= ~0x01; /* Poweroff DAC2 */ DAC1064_global_init()
294 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20; DAC1064_global_init()
297 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x40; DAC1064_global_init()
306 hw->DACreg[POS1064_XPWRCTRL] &= ~0x04; /* Poweroff TMDS */ DAC1064_global_init()
316 hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_EXT; DAC1064_global_init()
317 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12; DAC1064_global_init()
319 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12; DAC1064_global_init()
321 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12; DAC1064_global_init()
323 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS; DAC1064_global_init()
326 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; DAC1064_global_init()
332 struct matrox_hw_state *hw = &minfo->hw; DAC1064_global_restore() local
334 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); DAC1064_global_restore()
335 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]); DAC1064_global_restore()
341 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); DAC1064_global_restore()
342 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]); DAC1064_global_restore()
343 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]); DAC1064_global_restore()
350 struct matrox_hw_state *hw = &minfo->hw; DAC1064_init_1() local
354 memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs)); DAC1064_init_1()
358 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; DAC1064_init_1()
362 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; DAC1064_init_1()
364 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; DAC1064_init_1()
367 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_24BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; DAC1064_init_1()
370 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_32BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; DAC1064_init_1()
375 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl; DAC1064_init_1()
376 hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK; DAC1064_init_1()
377 hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XGENCTRL_NO_SYNC_ON_GREEN; DAC1064_init_1()
378 hw->DACreg[POS1064_XCURADDL] = 0; DAC1064_init_1()
379 hw->DACreg[POS1064_XCURADDH] = 0; DAC1064_init_1()
387 struct matrox_hw_state *hw = &minfo->hw; DAC1064_init_2() local
395 hw->DACpal[i * 3 + 0] = i; DBG()
396 hw->DACpal[i * 3 + 1] = i; DBG()
397 hw->DACpal[i * 3 + 2] = i; DBG()
405 hw->DACpal[i * 3 + 0] = i << 3;
406 hw->DACpal[i * 3 + 1] = i << 3;
407 hw->DACpal[i * 3 + 2] = i << 3;
409 hw->DACpal[(i + 128) * 3 + 0] = i << 3;
410 hw->DACpal[(i + 128) * 3 + 1] = i << 3;
411 hw->DACpal[(i + 128) * 3 + 2] = i << 3;
417 hw->DACpal[i * 3 + 0] = i << 3;
418 hw->DACpal[i * 3 + 1] = i << 2;
419 hw->DACpal[i * 3 + 2] = i << 3;
423 memset(hw->DACpal, 0, 768);
430 struct matrox_hw_state *hw = &minfo->hw; DAC1064_restore_1() local
438 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) || DBG()
439 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) || DBG()
440 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) { DBG()
441 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]); DBG()
442 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]); DBG()
443 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]); DBG()
450 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);
470 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]); DAC1064_restore_2()
475 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]); DAC1064_restore_2()
492 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]); m1064_compute()
537 struct matrox_hw_state *hw = &minfo->hw; MGA1064_init() local
544 hw->MiscOutReg = 0xCB; MGA1064_init()
546 hw->MiscOutReg &= ~0x40; MGA1064_init()
548 hw->MiscOutReg &= ~0x80; MGA1064_init()
550 hw->CRTCEXT[3] |= 0x40; MGA1064_init()
560 struct matrox_hw_state *hw = &minfo->hw; MGAG100_init() local
565 hw->MXoptionReg &= ~0x2000; MGAG100_init()
568 hw->MiscOutReg = 0xEF; MGAG100_init()
570 hw->MiscOutReg &= ~0x40; MGAG100_init()
572 hw->MiscOutReg &= ~0x80; MGAG100_init()
574 hw->CRTCEXT[3] |= 0x40; MGAG100_init()
673 struct matrox_hw_state *hw = &minfo->hw; MGA1064_preinit() local
688 hw->MXoptionReg &= 0xC0000100; MGA1064_preinit()
689 hw->MXoptionReg |= 0x00094E20; MGA1064_preinit()
691 hw->MXoptionReg &= ~0x00000100; MGA1064_preinit()
693 hw->MXoptionReg &= ~0x40000000; MGA1064_preinit()
695 hw->MXoptionReg |= 0x20000000; MGA1064_preinit()
696 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); MGA1064_preinit()
719 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); g450_mclk_init()
721 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); g450_mclk_init()
739 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); g450_mclk_init()
741 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); g450_mclk_init()
748 minfo->hw.MXoptionReg &= ~0x001F8000; g450_memory_init()
749 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); g450_memory_init()
752 minfo->hw.MXoptionReg &= ~0x00207E00; g450_memory_init()
753 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; g450_memory_init()
754 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); g450_memory_init()
775 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; g450_memory_init()
776 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); g450_memory_init()
794 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */ g450_preinit()
795 minfo->hw.MXoptionReg &= 0xC0000100; g450_preinit()
796 minfo->hw.MXoptionReg |= 0x00000020; g450_preinit()
798 minfo->hw.MXoptionReg &= ~0x00000100; g450_preinit()
800 minfo->hw.MXoptionReg &= ~0x40000000; g450_preinit()
802 minfo->hw.MXoptionReg |= 0x20000000; g450_preinit()
803 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040; g450_preinit()
804 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); g450_preinit()
842 struct matrox_hw_state *hw = &minfo->hw; MGAG100_preinit() local
892 hw->MXoptionReg &= 0xC0000100;
893 hw->MXoptionReg |= 0x00000020;
895 hw->MXoptionReg &= ~0x00000100;
897 hw->MXoptionReg &= ~0x40000000;
899 hw->MXoptionReg |= 0x20000000;
900 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
908 hw->MXoptionReg |= 0x1080;
909 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
931 hw->MXoptionReg &= ~0x1000;
934 hw->MXoptionReg |= 0x00078020;
941 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
943 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
945 hw->MXoptionReg |= 0x4000;
953 hw->MXoptionReg |= 0x00078020;
961 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
963 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
965 hw->MXoptionReg |= 0x4000;
973 hw->MXoptionReg |= 0x00040020;
975 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
982 struct matrox_hw_state *hw = &minfo->hw; MGAG100_reset() local
1001 hw->MXoptionReg |= 0x40; /* FIXME... */ DBG()
1002 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); DBG()
1009 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
1010 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
1011 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
1040 struct matrox_hw_state *hw = &minfo->hw; MGA1064_restore() local
1048 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); MGA1064_restore()
1058 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); MGA1064_restore()
1067 struct matrox_hw_state *hw = &minfo->hw; MGAG100_restore() local
1075 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); MGAG100_restore()
1081 mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]); MGAG100_restore()
1084 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); MGAG100_restore()
/linux-4.4.14/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c472 int intelfbhw_active_pipe(const struct intelfb_hwstate *hw) intelfbhw_active_pipe() argument
477 if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) { intelfbhw_active_pipe()
478 pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); intelfbhw_active_pipe()
483 if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) { intelfbhw_active_pipe()
484 pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); intelfbhw_active_pipe()
517 struct intelfb_hwstate *hw, int flag) intelfbhw_read_hw_state()
525 if (!hw || !dinfo) intelfbhw_read_hw_state()
529 hw->vga0_divisor = INREG(VGA0_DIVISOR); intelfbhw_read_hw_state()
530 hw->vga1_divisor = INREG(VGA1_DIVISOR); intelfbhw_read_hw_state()
531 hw->vga_pd = INREG(VGAPD); intelfbhw_read_hw_state()
532 hw->dpll_a = INREG(DPLL_A); intelfbhw_read_hw_state()
533 hw->dpll_b = INREG(DPLL_B); intelfbhw_read_hw_state()
534 hw->fpa0 = INREG(FPA0); intelfbhw_read_hw_state()
535 hw->fpa1 = INREG(FPA1); intelfbhw_read_hw_state()
536 hw->fpb0 = INREG(FPB0); intelfbhw_read_hw_state()
537 hw->fpb1 = INREG(FPB1); intelfbhw_read_hw_state()
545 hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); intelfbhw_read_hw_state()
546 hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); intelfbhw_read_hw_state()
553 hw->htotal_a = INREG(HTOTAL_A); intelfbhw_read_hw_state()
554 hw->hblank_a = INREG(HBLANK_A); intelfbhw_read_hw_state()
555 hw->hsync_a = INREG(HSYNC_A); intelfbhw_read_hw_state()
556 hw->vtotal_a = INREG(VTOTAL_A); intelfbhw_read_hw_state()
557 hw->vblank_a = INREG(VBLANK_A); intelfbhw_read_hw_state()
558 hw->vsync_a = INREG(VSYNC_A); intelfbhw_read_hw_state()
559 hw->src_size_a = INREG(SRC_SIZE_A); intelfbhw_read_hw_state()
560 hw->bclrpat_a = INREG(BCLRPAT_A); intelfbhw_read_hw_state()
561 hw->htotal_b = INREG(HTOTAL_B); intelfbhw_read_hw_state()
562 hw->hblank_b = INREG(HBLANK_B); intelfbhw_read_hw_state()
563 hw->hsync_b = INREG(HSYNC_B); intelfbhw_read_hw_state()
564 hw->vtotal_b = INREG(VTOTAL_B); intelfbhw_read_hw_state()
565 hw->vblank_b = INREG(VBLANK_B); intelfbhw_read_hw_state()
566 hw->vsync_b = INREG(VSYNC_B); intelfbhw_read_hw_state()
567 hw->src_size_b = INREG(SRC_SIZE_B); intelfbhw_read_hw_state()
568 hw->bclrpat_b = INREG(BCLRPAT_B); intelfbhw_read_hw_state()
573 hw->adpa = INREG(ADPA); intelfbhw_read_hw_state()
574 hw->dvoa = INREG(DVOA); intelfbhw_read_hw_state()
575 hw->dvob = INREG(DVOB); intelfbhw_read_hw_state()
576 hw->dvoc = INREG(DVOC); intelfbhw_read_hw_state()
577 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); intelfbhw_read_hw_state()
578 hw->dvob_srcdim = INREG(DVOB_SRCDIM); intelfbhw_read_hw_state()
579 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); intelfbhw_read_hw_state()
580 hw->lvds = INREG(LVDS); intelfbhw_read_hw_state()
585 hw->pipe_a_conf = INREG(PIPEACONF); intelfbhw_read_hw_state()
586 hw->pipe_b_conf = INREG(PIPEBCONF); intelfbhw_read_hw_state()
587 hw->disp_arb = INREG(DISPARB); intelfbhw_read_hw_state()
592 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); intelfbhw_read_hw_state()
593 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); intelfbhw_read_hw_state()
594 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); intelfbhw_read_hw_state()
595 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); intelfbhw_read_hw_state()
601 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); intelfbhw_read_hw_state()
602 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); intelfbhw_read_hw_state()
608 hw->cursor_size = INREG(CURSOR_SIZE); intelfbhw_read_hw_state()
613 hw->disp_a_ctrl = INREG(DSPACNTR); intelfbhw_read_hw_state()
614 hw->disp_b_ctrl = INREG(DSPBCNTR); intelfbhw_read_hw_state()
615 hw->disp_a_base = INREG(DSPABASE); intelfbhw_read_hw_state()
616 hw->disp_b_base = INREG(DSPBBASE); intelfbhw_read_hw_state()
617 hw->disp_a_stride = INREG(DSPASTRIDE); intelfbhw_read_hw_state()
618 hw->disp_b_stride = INREG(DSPBSTRIDE); intelfbhw_read_hw_state()
623 hw->vgacntrl = INREG(VGACNTRL); intelfbhw_read_hw_state()
628 hw->add_id = INREG(ADD_ID); intelfbhw_read_hw_state()
634 hw->swf0x[i] = INREG(SWF00 + (i << 2)); intelfbhw_read_hw_state()
635 hw->swf1x[i] = INREG(SWF10 + (i << 2)); intelfbhw_read_hw_state()
637 hw->swf3x[i] = INREG(SWF30 + (i << 2)); intelfbhw_read_hw_state()
641 hw->fence[i] = INREG(FENCE + (i << 2)); intelfbhw_read_hw_state()
643 hw->instpm = INREG(INSTPM); intelfbhw_read_hw_state()
644 hw->mem_mode = INREG(MEM_MODE); intelfbhw_read_hw_state()
645 hw->fw_blc_0 = INREG(FW_BLC_0); intelfbhw_read_hw_state()
646 hw->fw_blc_1 = INREG(FW_BLC_1); intelfbhw_read_hw_state()
648 hw->hwstam = INREG16(HWSTAM); intelfbhw_read_hw_state()
649 hw->ier = INREG16(IER); intelfbhw_read_hw_state()
650 hw->iir = INREG16(IIR); intelfbhw_read_hw_state()
651 hw->imr = INREG16(IMR); intelfbhw_read_hw_state()
711 struct intelfb_hwstate *hw) intelfbhw_print_hw_state()
718 if (!hw) intelfbhw_print_hw_state()
721 printk("hw state dump start\n"); intelfbhw_print_hw_state()
722 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); intelfbhw_print_hw_state()
723 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); intelfbhw_print_hw_state()
724 printk(" VGAPD: 0x%08x\n", hw->vga_pd); intelfbhw_print_hw_state()
725 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
726 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
727 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
729 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); intelfbhw_print_hw_state()
736 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
737 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
738 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
740 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); intelfbhw_print_hw_state()
746 printk(" DPLL_A: 0x%08x\n", hw->dpll_a); intelfbhw_print_hw_state()
747 printk(" DPLL_B: 0x%08x\n", hw->dpll_b); intelfbhw_print_hw_state()
748 printk(" FPA0: 0x%08x\n", hw->fpa0); intelfbhw_print_hw_state()
749 printk(" FPA1: 0x%08x\n", hw->fpa1); intelfbhw_print_hw_state()
750 printk(" FPB0: 0x%08x\n", hw->fpb0); intelfbhw_print_hw_state()
751 printk(" FPB1: 0x%08x\n", hw->fpb1); intelfbhw_print_hw_state()
753 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
754 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
755 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
757 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); intelfbhw_print_hw_state()
764 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
765 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
766 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; intelfbhw_print_hw_state()
768 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); intelfbhw_print_hw_state()
778 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]); intelfbhw_print_hw_state()
781 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]); intelfbhw_print_hw_state()
784 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); intelfbhw_print_hw_state()
785 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); intelfbhw_print_hw_state()
786 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); intelfbhw_print_hw_state()
787 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); intelfbhw_print_hw_state()
788 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); intelfbhw_print_hw_state()
789 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); intelfbhw_print_hw_state()
790 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); intelfbhw_print_hw_state()
791 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); intelfbhw_print_hw_state()
792 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); intelfbhw_print_hw_state()
793 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); intelfbhw_print_hw_state()
794 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); intelfbhw_print_hw_state()
795 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); intelfbhw_print_hw_state()
796 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); intelfbhw_print_hw_state()
797 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); intelfbhw_print_hw_state()
798 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); intelfbhw_print_hw_state()
799 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); intelfbhw_print_hw_state()
801 printk(" ADPA: 0x%08x\n", hw->adpa); intelfbhw_print_hw_state()
802 printk(" DVOA: 0x%08x\n", hw->dvoa); intelfbhw_print_hw_state()
803 printk(" DVOB: 0x%08x\n", hw->dvob); intelfbhw_print_hw_state()
804 printk(" DVOC: 0x%08x\n", hw->dvoc); intelfbhw_print_hw_state()
805 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); intelfbhw_print_hw_state()
806 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); intelfbhw_print_hw_state()
807 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); intelfbhw_print_hw_state()
808 printk(" LVDS: 0x%08x\n", hw->lvds); intelfbhw_print_hw_state()
810 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); intelfbhw_print_hw_state()
811 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); intelfbhw_print_hw_state()
812 printk(" DISPARB: 0x%08x\n", hw->disp_arb); intelfbhw_print_hw_state()
814 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); intelfbhw_print_hw_state()
815 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); intelfbhw_print_hw_state()
816 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); intelfbhw_print_hw_state()
817 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); intelfbhw_print_hw_state()
821 printk("0x%08x", hw->cursor_a_palette[i]); intelfbhw_print_hw_state()
828 printk("0x%08x", hw->cursor_b_palette[i]); intelfbhw_print_hw_state()
834 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); intelfbhw_print_hw_state()
836 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); intelfbhw_print_hw_state()
837 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); intelfbhw_print_hw_state()
838 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); intelfbhw_print_hw_state()
839 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); intelfbhw_print_hw_state()
840 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); intelfbhw_print_hw_state()
841 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); intelfbhw_print_hw_state()
843 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); intelfbhw_print_hw_state()
844 printk(" ADD_ID: 0x%08x\n", hw->add_id); intelfbhw_print_hw_state()
848 hw->swf0x[i]); intelfbhw_print_hw_state()
852 hw->swf1x[i]); intelfbhw_print_hw_state()
856 hw->swf3x[i]); intelfbhw_print_hw_state()
860 hw->fence[i]); intelfbhw_print_hw_state()
862 printk(" INSTPM 0x%08x\n", hw->instpm); intelfbhw_print_hw_state()
863 printk(" MEM_MODE 0x%08x\n", hw->mem_mode); intelfbhw_print_hw_state()
864 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); intelfbhw_print_hw_state()
865 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); intelfbhw_print_hw_state()
867 printk(" HWSTAM 0x%04x\n", hw->hwstam); intelfbhw_print_hw_state()
868 printk(" IER 0x%04x\n", hw->ier); intelfbhw_print_hw_state()
869 printk(" IIR 0x%04x\n", hw->iir); intelfbhw_print_hw_state()
870 printk(" IMR 0x%04x\n", hw->imr); intelfbhw_print_hw_state()
871 printk("hw state dump end\n"); intelfbhw_print_hw_state()
1042 /* It is assumed that hw is filled in with the initial state information. */ intelfbhw_mode_to_hw()
1044 struct intelfb_hwstate *hw, intelfbhw_mode_to_hw()
1047 int pipe = intelfbhw_active_pipe(hw); intelfbhw_mode_to_hw()
1059 hw->vgacntrl |= VGA_DISABLE; intelfbhw_mode_to_hw()
1063 dpll = &hw->dpll_b; intelfbhw_mode_to_hw()
1064 fp0 = &hw->fpb0; intelfbhw_mode_to_hw()
1065 fp1 = &hw->fpb1; intelfbhw_mode_to_hw()
1066 hs = &hw->hsync_b; intelfbhw_mode_to_hw()
1067 hb = &hw->hblank_b; intelfbhw_mode_to_hw()
1068 ht = &hw->htotal_b; intelfbhw_mode_to_hw()
1069 vs = &hw->vsync_b; intelfbhw_mode_to_hw()
1070 vb = &hw->vblank_b; intelfbhw_mode_to_hw()
1071 vt = &hw->vtotal_b; intelfbhw_mode_to_hw()
1072 ss = &hw->src_size_b; intelfbhw_mode_to_hw()
1073 pipe_conf = &hw->pipe_b_conf; intelfbhw_mode_to_hw()
1075 dpll = &hw->dpll_a; intelfbhw_mode_to_hw()
1076 fp0 = &hw->fpa0; intelfbhw_mode_to_hw()
1077 fp1 = &hw->fpa1; intelfbhw_mode_to_hw()
1078 hs = &hw->hsync_a; intelfbhw_mode_to_hw()
1079 hb = &hw->hblank_a; intelfbhw_mode_to_hw()
1080 ht = &hw->htotal_a; intelfbhw_mode_to_hw()
1081 vs = &hw->vsync_a; intelfbhw_mode_to_hw()
1082 vb = &hw->vblank_a; intelfbhw_mode_to_hw()
1083 vt = &hw->vtotal_a; intelfbhw_mode_to_hw()
1084 ss = &hw->src_size_a; intelfbhw_mode_to_hw()
1085 pipe_conf = &hw->pipe_a_conf; intelfbhw_mode_to_hw()
1089 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; intelfbhw_mode_to_hw()
1096 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | intelfbhw_mode_to_hw()
1098 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | intelfbhw_mode_to_hw()
1102 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); intelfbhw_mode_to_hw()
1103 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); intelfbhw_mode_to_hw()
1106 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; intelfbhw_mode_to_hw()
1107 hw->adpa |= ADPA_DPMS_D0; intelfbhw_mode_to_hw()
1109 hw->adpa |= ADPA_DAC_ENABLE; intelfbhw_mode_to_hw()
1151 hw->dvob &= ~PORT_ENABLE; intelfbhw_mode_to_hw()
1152 hw->dvoc &= ~PORT_ENABLE; intelfbhw_mode_to_hw()
1155 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; intelfbhw_mode_to_hw()
1156 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; intelfbhw_mode_to_hw()
1157 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; intelfbhw_mode_to_hw()
1160 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; intelfbhw_mode_to_hw()
1163 hw->disp_a_ctrl |= DISPPLANE_15_16BPP; intelfbhw_mode_to_hw()
1166 hw->disp_a_ctrl |= DISPPLANE_16BPP; intelfbhw_mode_to_hw()
1169 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; intelfbhw_mode_to_hw()
1172 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); intelfbhw_mode_to_hw()
1173 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); intelfbhw_mode_to_hw()
1251 hw->disp_a_stride = dinfo->pitch; intelfbhw_mode_to_hw()
1252 DBG_MSG("pitch is %d\n", hw->disp_a_stride); intelfbhw_mode_to_hw()
1254 hw->disp_a_base = hw->disp_a_stride * var->yoffset + intelfbhw_mode_to_hw()
1257 hw->disp_a_base += dinfo->fb.offset << 12; intelfbhw_mode_to_hw()
1262 if (hw->disp_a_stride % stride_alignment != 0) { intelfbhw_mode_to_hw()
1264 hw->disp_a_stride, stride_alignment); intelfbhw_mode_to_hw()
1281 const struct intelfb_hwstate *hw, int blank) intelfbhw_program_mode()
1303 dinfo->pipe = intelfbhw_active_pipe(hw); intelfbhw_program_mode()
1306 dpll = &hw->dpll_b; intelfbhw_program_mode()
1307 fp0 = &hw->fpb0; intelfbhw_program_mode()
1308 fp1 = &hw->fpb1; intelfbhw_program_mode()
1309 pipe_conf = &hw->pipe_b_conf; intelfbhw_program_mode()
1310 hs = &hw->hsync_b; intelfbhw_program_mode()
1311 hb = &hw->hblank_b; intelfbhw_program_mode()
1312 ht = &hw->htotal_b; intelfbhw_program_mode()
1313 vs = &hw->vsync_b; intelfbhw_program_mode()
1314 vb = &hw->vblank_b; intelfbhw_program_mode()
1315 vt = &hw->vtotal_b; intelfbhw_program_mode()
1316 ss = &hw->src_size_b; intelfbhw_program_mode()
1330 dpll = &hw->dpll_a; intelfbhw_program_mode()
1331 fp0 = &hw->fpa0; intelfbhw_program_mode()
1332 fp1 = &hw->fpa1; intelfbhw_program_mode()
1333 pipe_conf = &hw->pipe_a_conf; intelfbhw_program_mode()
1334 hs = &hw->hsync_a; intelfbhw_program_mode()
1335 hb = &hw->hblank_a; intelfbhw_program_mode()
1336 ht = &hw->htotal_a; intelfbhw_program_mode()
1337 vs = &hw->vsync_a; intelfbhw_program_mode()
1338 vb = &hw->vblank_a; intelfbhw_program_mode()
1339 vt = &hw->vtotal_a; intelfbhw_program_mode()
1340 ss = &hw->src_size_a; intelfbhw_program_mode()
1413 OUTREG(DVOB, hw->dvob); intelfbhw_program_mode()
1414 OUTREG(DVOC, hw->dvoc); intelfbhw_program_mode()
1421 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); intelfbhw_program_mode()
1464 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); intelfbhw_program_mode()
1469 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); intelfbhw_program_mode()
1470 OUTREG(DSPASTRIDE, hw->disp_a_stride); intelfbhw_program_mode()
1471 OUTREG(DSPABASE, hw->disp_a_base); intelfbhw_program_mode()
1478 OUTREG(DSPABASE, hw->disp_a_base); intelfbhw_program_mode()
516 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, int flag) intelfbhw_read_hw_state() argument
710 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) intelfbhw_print_hw_state() argument
1043 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, struct fb_var_screeninfo *var) intelfbhw_mode_to_hw() argument
1280 intelfbhw_program_mode(struct intelfb_info *dinfo, const struct intelfb_hwstate *hw, int blank) intelfbhw_program_mode() argument
/linux-4.4.14/drivers/clk/mxs/
H A Dclk-pll.c21 * @hw: clk_hw for the pll
30 struct clk_hw hw; member in struct:clk_pll
36 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
38 static int clk_pll_prepare(struct clk_hw *hw) clk_pll_prepare() argument
40 struct clk_pll *pll = to_clk_pll(hw); clk_pll_prepare()
49 static void clk_pll_unprepare(struct clk_hw *hw) clk_pll_unprepare() argument
51 struct clk_pll *pll = to_clk_pll(hw); clk_pll_unprepare()
56 static int clk_pll_enable(struct clk_hw *hw) clk_pll_enable() argument
58 struct clk_pll *pll = to_clk_pll(hw); clk_pll_enable()
65 static void clk_pll_disable(struct clk_hw *hw) clk_pll_disable() argument
67 struct clk_pll *pll = to_clk_pll(hw); clk_pll_disable()
72 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, clk_pll_recalc_rate() argument
75 struct clk_pll *pll = to_clk_pll(hw); clk_pll_recalc_rate()
108 pll->hw.init = &init; mxs_clk_pll()
110 clk = clk_register(NULL, &pll->hw); mxs_clk_pll()
H A Dclk-div.c34 static inline struct clk_div *to_clk_div(struct clk_hw *hw) to_clk_div() argument
36 struct clk_divider *divider = container_of(hw, struct clk_divider, hw); to_clk_div()
41 static unsigned long clk_div_recalc_rate(struct clk_hw *hw, clk_div_recalc_rate() argument
44 struct clk_div *div = to_clk_div(hw); clk_div_recalc_rate()
46 return div->ops->recalc_rate(&div->divider.hw, parent_rate); clk_div_recalc_rate()
49 static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate, clk_div_round_rate() argument
52 struct clk_div *div = to_clk_div(hw); clk_div_round_rate()
54 return div->ops->round_rate(&div->divider.hw, rate, prate); clk_div_round_rate()
57 static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, clk_div_set_rate() argument
60 struct clk_div *div = to_clk_div(hw); clk_div_set_rate()
63 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); clk_div_set_rate()
101 div->divider.hw.init = &init; mxs_clk_div()
104 clk = clk_register(NULL, &div->divider.hw); mxs_clk_div()
/linux-4.4.14/sound/core/
H A Dhwdep.c58 struct snd_hwdep *hw = file->private_data; snd_hwdep_llseek() local
59 if (hw->ops.llseek) snd_hwdep_llseek()
60 return hw->ops.llseek(hw, file, offset, orig); snd_hwdep_llseek()
67 struct snd_hwdep *hw = file->private_data; snd_hwdep_read() local
68 if (hw->ops.read) snd_hwdep_read()
69 return hw->ops.read(hw, buf, count, offset); snd_hwdep_read()
76 struct snd_hwdep *hw = file->private_data; snd_hwdep_write() local
77 if (hw->ops.write) snd_hwdep_write()
78 return hw->ops.write(hw, buf, count, offset); snd_hwdep_write()
85 struct snd_hwdep *hw; snd_hwdep_open() local
90 hw = snd_lookup_minor_data(iminor(inode), snd_hwdep_open()
94 hw = snd_lookup_oss_minor_data(iminor(inode), snd_hwdep_open()
99 if (hw == NULL) snd_hwdep_open()
102 if (!try_module_get(hw->card->module)) { snd_hwdep_open()
103 snd_card_unref(hw->card); snd_hwdep_open()
108 add_wait_queue(&hw->open_wait, &wait); snd_hwdep_open()
109 mutex_lock(&hw->open_mutex); snd_hwdep_open()
111 if (hw->exclusive && hw->used > 0) { snd_hwdep_open()
115 if (!hw->ops.open) { snd_hwdep_open()
119 err = hw->ops.open(hw, file); snd_hwdep_open()
130 mutex_unlock(&hw->open_mutex); snd_hwdep_open()
132 mutex_lock(&hw->open_mutex); snd_hwdep_open()
133 if (hw->card->shutdown) { snd_hwdep_open()
142 remove_wait_queue(&hw->open_wait, &wait); snd_hwdep_open()
144 err = snd_card_file_add(hw->card, file); snd_hwdep_open()
146 file->private_data = hw; snd_hwdep_open()
147 hw->used++; snd_hwdep_open()
149 if (hw->ops.release) snd_hwdep_open()
150 hw->ops.release(hw, file); snd_hwdep_open()
153 mutex_unlock(&hw->open_mutex); snd_hwdep_open()
155 module_put(hw->card->module); snd_hwdep_open()
156 snd_card_unref(hw->card); snd_hwdep_open()
163 struct snd_hwdep *hw = file->private_data; snd_hwdep_release() local
164 struct module *mod = hw->card->module; snd_hwdep_release()
166 mutex_lock(&hw->open_mutex); snd_hwdep_release()
167 if (hw->ops.release) snd_hwdep_release()
168 err = hw->ops.release(hw, file); snd_hwdep_release()
169 if (hw->used > 0) snd_hwdep_release()
170 hw->used--; snd_hwdep_release()
171 mutex_unlock(&hw->open_mutex); snd_hwdep_release()
172 wake_up(&hw->open_wait); snd_hwdep_release()
174 snd_card_file_remove(hw->card, file); snd_hwdep_release()
181 struct snd_hwdep *hw = file->private_data; snd_hwdep_poll() local
182 if (hw->ops.poll) snd_hwdep_poll()
183 return hw->ops.poll(hw, file, wait); snd_hwdep_poll()
187 static int snd_hwdep_info(struct snd_hwdep *hw, snd_hwdep_info() argument
193 info.card = hw->card->number; snd_hwdep_info()
194 strlcpy(info.id, hw->id, sizeof(info.id)); snd_hwdep_info()
195 strlcpy(info.name, hw->name, sizeof(info.name)); snd_hwdep_info()
196 info.iface = hw->iface; snd_hwdep_info()
202 static int snd_hwdep_dsp_status(struct snd_hwdep *hw, snd_hwdep_dsp_status() argument
208 if (! hw->ops.dsp_status) snd_hwdep_dsp_status()
211 info.dsp_loaded = hw->dsp_loaded; snd_hwdep_dsp_status()
212 if ((err = hw->ops.dsp_status(hw, &info)) < 0) snd_hwdep_dsp_status()
219 static int snd_hwdep_dsp_load(struct snd_hwdep *hw, snd_hwdep_dsp_load() argument
225 if (! hw->ops.dsp_load) snd_hwdep_dsp_load()
231 if (hw->dsp_loaded & (1 << info.index)) snd_hwdep_dsp_load()
235 err = hw->ops.dsp_load(hw, &info); snd_hwdep_dsp_load()
238 hw->dsp_loaded |= (1 << info.index); snd_hwdep_dsp_load()
245 struct snd_hwdep *hw = file->private_data; snd_hwdep_ioctl() local
251 return snd_hwdep_info(hw, argp); snd_hwdep_ioctl()
253 return snd_hwdep_dsp_status(hw, argp); snd_hwdep_ioctl()
255 return snd_hwdep_dsp_load(hw, argp); snd_hwdep_ioctl()
257 if (hw->ops.ioctl) snd_hwdep_ioctl()
258 return hw->ops.ioctl(hw, file, cmd, arg); snd_hwdep_ioctl()
264 struct snd_hwdep *hw = file->private_data; snd_hwdep_mmap() local
265 if (hw->ops.mmap) snd_hwdep_mmap()
266 return hw->ops.mmap(hw, file, vma); snd_hwdep_mmap()
/linux-4.4.14/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c35 static s32 e1000_check_downshift(struct e1000_hw *hw);
36 static s32 e1000_check_polarity(struct e1000_hw *hw,
38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39 static void e1000_clear_vfta(struct e1000_hw *hw);
40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48 static s32 e1000_id_led_init(struct e1000_hw *hw);
49 static void e1000_init_rx_addrs(struct e1000_hw *hw);
50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57 static s32 e1000_set_phy_type(struct e1000_hw *hw);
58 static void e1000_phy_init_script(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83 static void e1000_release_eeprom(struct e1000_hw *hw);
84 static void e1000_standby_eeprom(struct e1000_hw *hw);
85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
113 * e1000_set_phy_type - Set the phy type member in the hw struct.
114 * @hw: Struct containing variables accessed by shared code
116 static s32 e1000_set_phy_type(struct e1000_hw *hw) e1000_set_phy_type() argument
118 if (hw->mac_type == e1000_undefined) e1000_set_phy_type()
121 switch (hw->phy_id) { e1000_set_phy_type()
127 hw->phy_type = e1000_phy_m88; e1000_set_phy_type()
130 if (hw->mac_type == e1000_82541 || e1000_set_phy_type()
131 hw->mac_type == e1000_82541_rev_2 || e1000_set_phy_type()
132 hw->mac_type == e1000_82547 || e1000_set_phy_type()
133 hw->mac_type == e1000_82547_rev_2) e1000_set_phy_type()
134 hw->phy_type = e1000_phy_igp; e1000_set_phy_type()
137 hw->phy_type = e1000_phy_8211; e1000_set_phy_type()
140 hw->phy_type = e1000_phy_8201; e1000_set_phy_type()
144 hw->phy_type = e1000_phy_undefined; e1000_set_phy_type()
153 * @hw: Struct containing variables accessed by shared code
155 static void e1000_phy_init_script(struct e1000_hw *hw) e1000_phy_init_script() argument
160 if (hw->phy_init_script) { e1000_phy_init_script()
166 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); e1000_phy_init_script()
169 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); e1000_phy_init_script()
172 e1000_write_phy_reg(hw, 0x0000, 0x0140); e1000_phy_init_script()
175 switch (hw->mac_type) { e1000_phy_init_script()
178 e1000_write_phy_reg(hw, 0x1F95, 0x0001); e1000_phy_init_script()
179 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); e1000_phy_init_script()
180 e1000_write_phy_reg(hw, 0x1F79, 0x0018); e1000_phy_init_script()
181 e1000_write_phy_reg(hw, 0x1F30, 0x1600); e1000_phy_init_script()
182 e1000_write_phy_reg(hw, 0x1F31, 0x0014); e1000_phy_init_script()
183 e1000_write_phy_reg(hw, 0x1F32, 0x161C); e1000_phy_init_script()
184 e1000_write_phy_reg(hw, 0x1F94, 0x0003); e1000_phy_init_script()
185 e1000_write_phy_reg(hw, 0x1F96, 0x003F); e1000_phy_init_script()
186 e1000_write_phy_reg(hw, 0x2010, 0x0008); e1000_phy_init_script()
191 e1000_write_phy_reg(hw, 0x1F73, 0x0099); e1000_phy_init_script()
197 e1000_write_phy_reg(hw, 0x0000, 0x3300); e1000_phy_init_script()
201 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); e1000_phy_init_script()
203 if (hw->mac_type == e1000_82547) { e1000_phy_init_script()
207 e1000_read_phy_reg(hw, e1000_phy_init_script()
212 e1000_read_phy_reg(hw, e1000_phy_init_script()
235 e1000_write_phy_reg(hw, e1000_phy_init_script()
238 e1000_write_phy_reg(hw, e1000_phy_init_script()
247 * e1000_set_mac_type - Set the mac type member in the hw struct.
248 * @hw: Struct containing variables accessed by shared code
250 s32 e1000_set_mac_type(struct e1000_hw *hw) e1000_set_mac_type() argument
252 switch (hw->device_id) { e1000_set_mac_type()
254 switch (hw->revision_id) { e1000_set_mac_type()
256 hw->mac_type = e1000_82542_rev2_0; e1000_set_mac_type()
259 hw->mac_type = e1000_82542_rev2_1; e1000_set_mac_type()
268 hw->mac_type = e1000_82543; e1000_set_mac_type()
274 hw->mac_type = e1000_82544; e1000_set_mac_type()
281 hw->mac_type = e1000_82540; e1000_set_mac_type()
285 hw->mac_type = e1000_82545; e1000_set_mac_type()
290 hw->mac_type = e1000_82545_rev_3; e1000_set_mac_type()
295 hw->mac_type = e1000_82546; e1000_set_mac_type()
303 hw->mac_type = e1000_82546_rev_3; e1000_set_mac_type()
308 hw->mac_type = e1000_82541; e1000_set_mac_type()
314 hw->mac_type = e1000_82541_rev_2; e1000_set_mac_type()
318 hw->mac_type = e1000_82547; e1000_set_mac_type()
321 hw->mac_type = e1000_82547_rev_2; e1000_set_mac_type()
324 hw->mac_type = e1000_ce4100; e1000_set_mac_type()
331 switch (hw->mac_type) { e1000_set_mac_type()
336 hw->asf_firmware_present = true; e1000_set_mac_type()
345 if (hw->mac_type == e1000_82543) e1000_set_mac_type()
346 hw->bad_tx_carr_stats_fd = true; e1000_set_mac_type()
348 if (hw->mac_type > e1000_82544) e1000_set_mac_type()
349 hw->has_smbus = true; e1000_set_mac_type()
356 * @hw: Struct containing variables accessed by shared code
358 void e1000_set_media_type(struct e1000_hw *hw) e1000_set_media_type() argument
362 if (hw->mac_type != e1000_82543) { e1000_set_media_type()
364 hw->tbi_compatibility_en = false; e1000_set_media_type()
367 switch (hw->device_id) { e1000_set_media_type()
370 hw->media_type = e1000_media_type_internal_serdes; e1000_set_media_type()
373 switch (hw->mac_type) { e1000_set_media_type()
376 hw->media_type = e1000_media_type_fiber; e1000_set_media_type()
379 hw->media_type = e1000_media_type_copper; e1000_set_media_type()
384 hw->media_type = e1000_media_type_fiber; e1000_set_media_type()
386 hw->tbi_compatibility_en = false; e1000_set_media_type()
388 hw->media_type = e1000_media_type_copper; e1000_set_media_type()
397 * @hw: Struct containing variables accessed by shared code
401 s32 e1000_reset_hw(struct e1000_hw *hw) e1000_reset_hw() argument
411 if (hw->mac_type == e1000_82542_rev2_0) { e1000_reset_hw()
413 e1000_pci_clear_mwi(hw); e1000_reset_hw()
429 hw->tbi_compatibility_on = false; e1000_reset_hw()
439 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { e1000_reset_hw()
452 switch (hw->mac_type) { e1000_reset_hw()
462 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); e1000_reset_hw()
479 switch (hw->mac_type) { e1000_reset_hw()
502 ret_val = e1000_get_auto_rd_done(hw); e1000_reset_hw()
509 if (hw->mac_type >= e1000_82540) { e1000_reset_hw()
515 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { e1000_reset_hw()
516 e1000_phy_init_script(hw); e1000_reset_hw()
533 if (hw->mac_type == e1000_82542_rev2_0) { e1000_reset_hw()
534 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) e1000_reset_hw()
535 e1000_pci_set_mwi(hw); e1000_reset_hw()
543 * @hw: Struct containing variables accessed by shared code
551 s32 e1000_init_hw(struct e1000_hw *hw) e1000_init_hw() argument
560 ret_val = e1000_id_led_init(hw); e1000_init_hw()
567 e1000_set_media_type(hw); e1000_init_hw()
571 if (hw->mac_type < e1000_82545_rev_3) e1000_init_hw()
573 e1000_clear_vfta(hw); e1000_init_hw()
576 if (hw->mac_type == e1000_82542_rev2_0) { e1000_init_hw()
578 e1000_pci_clear_mwi(hw); e1000_init_hw()
587 e1000_init_rx_addrs(hw); e1000_init_hw()
590 if (hw->mac_type == e1000_82542_rev2_0) { e1000_init_hw()
594 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) e1000_init_hw()
595 e1000_pci_set_mwi(hw); e1000_init_hw()
602 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); e1000_init_hw()
614 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { e1000_init_hw()
619 switch (hw->mac_type) { e1000_init_hw()
627 if (hw->bus_type == e1000_bus_type_pcix e1000_init_hw()
628 && e1000_pcix_get_mmrbc(hw) > 2048) e1000_init_hw()
629 e1000_pcix_set_mmrbc(hw, 2048); e1000_init_hw()
634 ret_val = e1000_setup_link(hw); e1000_init_hw()
637 if (hw->mac_type > e1000_82544) { e1000_init_hw()
650 e1000_clear_hw_cntrs(hw); e1000_init_hw()
652 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || e1000_init_hw()
653 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { e1000_init_hw()
667 * @hw: Struct containing variables accessed by shared code.
669 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) e1000_adjust_serdes_amplitude() argument
674 if (hw->media_type != e1000_media_type_internal_serdes) e1000_adjust_serdes_amplitude()
677 switch (hw->mac_type) { e1000_adjust_serdes_amplitude()
685 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, e1000_adjust_serdes_amplitude()
695 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); e1000_adjust_serdes_amplitude()
705 * @hw: Struct containing variables accessed by shared code
713 s32 e1000_setup_link(struct e1000_hw *hw) e1000_setup_link() argument
724 * control setting, then the variable hw->fc will e1000_setup_link()
727 if (hw->fc == E1000_FC_DEFAULT) { e1000_setup_link()
728 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, e1000_setup_link()
735 hw->fc = E1000_FC_NONE; e1000_setup_link()
738 hw->fc = E1000_FC_TX_PAUSE; e1000_setup_link()
740 hw->fc = E1000_FC_FULL; e1000_setup_link()
747 if (hw->mac_type == e1000_82542_rev2_0) e1000_setup_link()
748 hw->fc &= (~E1000_FC_TX_PAUSE); e1000_setup_link()
750 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) e1000_setup_link()
751 hw->fc &= (~E1000_FC_RX_PAUSE); e1000_setup_link()
753 hw->original_fc = hw->fc; e1000_setup_link()
755 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); e1000_setup_link()
764 if (hw->mac_type == e1000_82543) { e1000_setup_link()
765 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, e1000_setup_link()
777 ret_val = (hw->media_type == e1000_media_type_copper) ? e1000_setup_link()
778 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); e1000_setup_link()
791 ew32(FCTTV, hw->fc_pause_time); e1000_setup_link()
799 if (!(hw->fc & E1000_FC_TX_PAUSE)) { e1000_setup_link()
807 if (hw->fc_send_xon) { e1000_setup_link()
808 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); e1000_setup_link()
809 ew32(FCRTH, hw->fc_high_water); e1000_setup_link()
811 ew32(FCRTL, hw->fc_low_water); e1000_setup_link()
812 ew32(FCRTH, hw->fc_high_water); e1000_setup_link()
820 * @hw: Struct containing variables accessed by shared code
826 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) e1000_setup_fiber_serdes_link() argument
842 if (hw->media_type == e1000_media_type_fiber) e1000_setup_fiber_serdes_link()
843 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; e1000_setup_fiber_serdes_link()
845 ret_val = e1000_adjust_serdes_amplitude(hw); e1000_setup_fiber_serdes_link()
853 ret_val = e1000_set_vco_speed(hw); e1000_setup_fiber_serdes_link()
857 e1000_config_collision_dist(hw); e1000_setup_fiber_serdes_link()
875 switch (hw->fc) { e1000_setup_fiber_serdes_link()
919 hw->txcw = txcw; e1000_setup_fiber_serdes_link()
929 if (hw->media_type == e1000_media_type_internal_serdes || e1000_setup_fiber_serdes_link()
940 hw->autoneg_failed = 1; e1000_setup_fiber_serdes_link()
946 ret_val = e1000_check_for_link(hw); e1000_setup_fiber_serdes_link()
951 hw->autoneg_failed = 0; e1000_setup_fiber_serdes_link()
953 hw->autoneg_failed = 0; e1000_setup_fiber_serdes_link()
964 * @hw: Struct containing variables accessed by shared code
968 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) e1000_copper_link_rtl_setup() argument
973 ret_val = e1000_phy_reset(hw); e1000_copper_link_rtl_setup()
982 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) gbe_dhg_phy_setup() argument
987 switch (hw->phy_type) { gbe_dhg_phy_setup()
989 ret_val = e1000_copper_link_rtl_setup(hw); gbe_dhg_phy_setup()
1008 ret_val = e1000_copper_link_rtl_setup(hw); gbe_dhg_phy_setup()
1025 * @hw: Struct containing variables accessed by shared code
1029 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) e1000_copper_link_preconfig() argument
1040 if (hw->mac_type > e1000_82543) { e1000_copper_link_preconfig()
1048 ret_val = e1000_phy_hw_reset(hw); e1000_copper_link_preconfig()
1054 ret_val = e1000_detect_gig_phy(hw); e1000_copper_link_preconfig()
1059 e_dbg("Phy ID = %x\n", hw->phy_id); e1000_copper_link_preconfig()
1062 ret_val = e1000_set_phy_mode(hw); e1000_copper_link_preconfig()
1066 if ((hw->mac_type == e1000_82545_rev_3) || e1000_copper_link_preconfig()
1067 (hw->mac_type == e1000_82546_rev_3)) { e1000_copper_link_preconfig()
1069 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_copper_link_preconfig()
1072 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000_copper_link_preconfig()
1075 if (hw->mac_type <= e1000_82543 || e1000_copper_link_preconfig()
1076 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || e1000_copper_link_preconfig()
1077 hw->mac_type == e1000_82541_rev_2 e1000_copper_link_preconfig()
1078 || hw->mac_type == e1000_82547_rev_2) e1000_copper_link_preconfig()
1079 hw->phy_reset_disable = false; e1000_copper_link_preconfig()
1086 * @hw: Struct containing variables accessed by shared code
1088 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) e1000_copper_link_igp_setup() argument
1094 if (hw->phy_reset_disable) e1000_copper_link_igp_setup()
1097 ret_val = e1000_phy_reset(hw); e1000_copper_link_igp_setup()
1112 if (hw->phy_type == e1000_phy_igp) { e1000_copper_link_igp_setup()
1114 ret_val = e1000_set_d3_lplu_state(hw, false); e1000_copper_link_igp_setup()
1122 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); e1000_copper_link_igp_setup()
1126 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { e1000_copper_link_igp_setup()
1127 hw->dsp_config_state = e1000_dsp_config_disabled; e1000_copper_link_igp_setup()
1132 hw->mdix = 1; e1000_copper_link_igp_setup()
1135 hw->dsp_config_state = e1000_dsp_config_enabled; e1000_copper_link_igp_setup()
1138 switch (hw->mdix) { e1000_copper_link_igp_setup()
1151 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); e1000_copper_link_igp_setup()
1156 if (hw->autoneg) { e1000_copper_link_igp_setup()
1157 e1000_ms_type phy_ms_setting = hw->master_slave; e1000_copper_link_igp_setup()
1159 if (hw->ffe_config_state == e1000_ffe_config_active) e1000_copper_link_igp_setup()
1160 hw->ffe_config_state = e1000_ffe_config_enabled; e1000_copper_link_igp_setup()
1162 if (hw->dsp_config_state == e1000_dsp_config_activated) e1000_copper_link_igp_setup()
1163 hw->dsp_config_state = e1000_dsp_config_enabled; e1000_copper_link_igp_setup()
1169 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { e1000_copper_link_igp_setup()
1172 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_copper_link_igp_setup()
1178 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_copper_link_igp_setup()
1184 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); e1000_copper_link_igp_setup()
1189 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); e1000_copper_link_igp_setup()
1194 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); e1000_copper_link_igp_setup()
1199 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? e1000_copper_link_igp_setup()
1217 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); e1000_copper_link_igp_setup()
1227 * @hw: Struct containing variables accessed by shared code
1229 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) e1000_copper_link_mgp_setup() argument
1234 if (hw->phy_reset_disable) e1000_copper_link_mgp_setup()
1238 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_copper_link_mgp_setup()
1253 switch (hw->mdix) { e1000_copper_link_mgp_setup()
1276 if (hw->disable_polarity_correction == 1) e1000_copper_link_mgp_setup()
1278 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000_copper_link_mgp_setup()
1282 if (hw->phy_revision < M88E1011_I_REV_4) { e1000_copper_link_mgp_setup()
1287 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, e1000_copper_link_mgp_setup()
1294 if ((hw->phy_revision == E1000_REVISION_2) && e1000_copper_link_mgp_setup()
1295 (hw->phy_id == M88E1111_I_PHY_ID)) { e1000_copper_link_mgp_setup()
1299 ret_val = e1000_write_phy_reg(hw, e1000_copper_link_mgp_setup()
1310 ret_val = e1000_write_phy_reg(hw, e1000_copper_link_mgp_setup()
1319 ret_val = e1000_phy_reset(hw); e1000_copper_link_mgp_setup()
1330 * @hw: Struct containing variables accessed by shared code
1335 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) e1000_copper_link_autoneg() argument
1340 /* Perform some bounds checking on the hw->autoneg_advertised e1000_copper_link_autoneg()
1343 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; e1000_copper_link_autoneg()
1348 if (hw->autoneg_advertised == 0) e1000_copper_link_autoneg()
1349 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; e1000_copper_link_autoneg()
1352 if (hw->phy_type == e1000_phy_8201) e1000_copper_link_autoneg()
1353 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; e1000_copper_link_autoneg()
1356 ret_val = e1000_phy_setup_autoneg(hw); e1000_copper_link_autoneg()
1366 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); e1000_copper_link_autoneg()
1371 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); e1000_copper_link_autoneg()
1378 if (hw->wait_autoneg_complete) { e1000_copper_link_autoneg()
1379 ret_val = e1000_wait_autoneg(hw); e1000_copper_link_autoneg()
1387 hw->get_link_status = true; e1000_copper_link_autoneg()
1394 * @hw: Struct containing variables accessed by shared code
1405 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) e1000_copper_link_postconfig() argument
1409 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { e1000_copper_link_postconfig()
1410 e1000_config_collision_dist(hw); e1000_copper_link_postconfig()
1412 ret_val = e1000_config_mac_to_phy(hw); e1000_copper_link_postconfig()
1418 ret_val = e1000_config_fc_after_link_up(hw); e1000_copper_link_postconfig()
1425 if (hw->phy_type == e1000_phy_igp) { e1000_copper_link_postconfig()
1426 ret_val = e1000_config_dsp_after_link_change(hw, true); e1000_copper_link_postconfig()
1438 * @hw: Struct containing variables accessed by shared code
1442 static s32 e1000_setup_copper_link(struct e1000_hw *hw) e1000_setup_copper_link() argument
1449 ret_val = e1000_copper_link_preconfig(hw); e1000_setup_copper_link()
1453 if (hw->phy_type == e1000_phy_igp) { e1000_setup_copper_link()
1454 ret_val = e1000_copper_link_igp_setup(hw); e1000_setup_copper_link()
1457 } else if (hw->phy_type == e1000_phy_m88) { e1000_setup_copper_link()
1458 ret_val = e1000_copper_link_mgp_setup(hw); e1000_setup_copper_link()
1462 ret_val = gbe_dhg_phy_setup(hw); e1000_setup_copper_link()
1469 if (hw->autoneg) { e1000_setup_copper_link()
1473 ret_val = e1000_copper_link_autoneg(hw); e1000_setup_copper_link()
1481 ret_val = e1000_phy_force_speed_duplex(hw); e1000_setup_copper_link()
1492 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_setup_copper_link()
1495 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_setup_copper_link()
1501 ret_val = e1000_copper_link_postconfig(hw); e1000_setup_copper_link()
1517 * @hw: Struct containing variables accessed by shared code
1521 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) e1000_phy_setup_autoneg() argument
1528 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); e1000_phy_setup_autoneg()
1533 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); e1000_phy_setup_autoneg()
1536 else if (hw->phy_type == e1000_phy_8201) e1000_phy_setup_autoneg()
1553 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); e1000_phy_setup_autoneg()
1556 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { e1000_phy_setup_autoneg()
1562 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { e1000_phy_setup_autoneg()
1568 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { e1000_phy_setup_autoneg()
1574 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { e1000_phy_setup_autoneg()
1580 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { e1000_phy_setup_autoneg()
1586 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { e1000_phy_setup_autoneg()
1608 switch (hw->fc) { e1000_phy_setup_autoneg()
1623 * hw's ability to send PAUSE frames. e1000_phy_setup_autoneg()
1645 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); e1000_phy_setup_autoneg()
1651 if (hw->phy_type == e1000_phy_8201) { e1000_phy_setup_autoneg()
1654 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, e1000_phy_setup_autoneg()
1665 * @hw: Struct containing variables accessed by shared code
1667 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1669 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) e1000_phy_force_speed_duplex() argument
1679 hw->fc = E1000_FC_NONE; e1000_phy_force_speed_duplex()
1681 e_dbg("hw->fc = %d\n", hw->fc); e1000_phy_force_speed_duplex()
1694 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); e1000_phy_force_speed_duplex()
1703 if (hw->forced_speed_duplex == e1000_100_full || e1000_phy_force_speed_duplex()
1704 hw->forced_speed_duplex == e1000_10_full) { e1000_phy_force_speed_duplex()
1721 if (hw->forced_speed_duplex == e1000_100_full || e1000_phy_force_speed_duplex()
1722 hw->forced_speed_duplex == e1000_100_half) { e1000_phy_force_speed_duplex()
1736 e1000_config_collision_dist(hw); e1000_phy_force_speed_duplex()
1741 if (hw->phy_type == e1000_phy_m88) { e1000_phy_force_speed_duplex()
1743 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_phy_force_speed_duplex()
1752 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000_phy_force_speed_duplex()
1767 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); e1000_phy_force_speed_duplex()
1775 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); e1000_phy_force_speed_duplex()
1781 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); e1000_phy_force_speed_duplex()
1794 if (hw->wait_autoneg_complete) { e1000_phy_force_speed_duplex()
1805 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_phy_force_speed_duplex()
1810 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_phy_force_speed_duplex()
1818 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { e1000_phy_force_speed_duplex()
1822 ret_val = e1000_phy_reset_dsp(hw); e1000_phy_force_speed_duplex()
1839 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_phy_force_speed_duplex()
1844 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_phy_force_speed_duplex()
1850 if (hw->phy_type == e1000_phy_m88) { e1000_phy_force_speed_duplex()
1857 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, e1000_phy_force_speed_duplex()
1864 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, e1000_phy_force_speed_duplex()
1874 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_phy_force_speed_duplex()
1880 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); e1000_phy_force_speed_duplex()
1884 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) e1000_phy_force_speed_duplex()
1885 && (!hw->autoneg) e1000_phy_force_speed_duplex()
1886 && (hw->forced_speed_duplex == e1000_10_full e1000_phy_force_speed_duplex()
1887 || hw->forced_speed_duplex == e1000_10_half)) { e1000_phy_force_speed_duplex()
1888 ret_val = e1000_polarity_reversal_workaround(hw); e1000_phy_force_speed_duplex()
1898 * @hw: Struct containing variables accessed by shared code
1904 void e1000_config_collision_dist(struct e1000_hw *hw) e1000_config_collision_dist() argument
1908 if (hw->mac_type < e1000_82543) e1000_config_collision_dist()
1924 * @hw: Struct containing variables accessed by shared code
1931 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) e1000_config_mac_to_phy() argument
1940 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) e1000_config_mac_to_phy()
1950 switch (hw->phy_type) { e1000_config_mac_to_phy()
1952 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); e1000_config_mac_to_phy()
1966 e1000_config_collision_dist(hw); e1000_config_mac_to_phy()
1972 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, e1000_config_mac_to_phy()
1982 e1000_config_collision_dist(hw); e1000_config_mac_to_phy()
2001 * @hw: Struct containing variables accessed by shared code
2010 s32 e1000_force_mac_fc(struct e1000_hw *hw) e1000_force_mac_fc() argument
2023 * according to the "hw->fc" parameter. e1000_force_mac_fc()
2035 switch (hw->fc) { e1000_force_mac_fc()
2056 if (hw->mac_type == e1000_82542_rev2_0) e1000_force_mac_fc()
2065 * @hw: Struct containing variables accessed by shared code
2074 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) e1000_config_fc_after_link_up() argument
2087 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) e1000_config_fc_after_link_up()
2088 || ((hw->media_type == e1000_media_type_internal_serdes) e1000_config_fc_after_link_up()
2089 && (hw->autoneg_failed)) e1000_config_fc_after_link_up()
2090 || ((hw->media_type == e1000_media_type_copper) e1000_config_fc_after_link_up()
2091 && (!hw->autoneg))) { e1000_config_fc_after_link_up()
2092 ret_val = e1000_force_mac_fc(hw); e1000_config_fc_after_link_up()
2104 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { e1000_config_fc_after_link_up()
2109 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_config_fc_after_link_up()
2112 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_config_fc_after_link_up()
2123 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, e1000_config_fc_after_link_up()
2127 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, e1000_config_fc_after_link_up()
2176 if (hw->original_fc == E1000_FC_FULL) { e1000_config_fc_after_link_up()
2177 hw->fc = E1000_FC_FULL; e1000_config_fc_after_link_up()
2180 hw->fc = E1000_FC_RX_PAUSE; e1000_config_fc_after_link_up()
2198 hw->fc = E1000_FC_TX_PAUSE; e1000_config_fc_after_link_up()
2215 hw->fc = E1000_FC_RX_PAUSE; e1000_config_fc_after_link_up()
2241 else if ((hw->original_fc == E1000_FC_NONE || e1000_config_fc_after_link_up()
2242 hw->original_fc == E1000_FC_TX_PAUSE) || e1000_config_fc_after_link_up()
2243 hw->fc_strict_ieee) { e1000_config_fc_after_link_up()
2244 hw->fc = E1000_FC_NONE; e1000_config_fc_after_link_up()
2247 hw->fc = E1000_FC_RX_PAUSE; e1000_config_fc_after_link_up()
2257 e1000_get_speed_and_duplex(hw, &speed, &duplex); e1000_config_fc_after_link_up()
2265 hw->fc = E1000_FC_NONE; e1000_config_fc_after_link_up()
2270 ret_val = e1000_force_mac_fc(hw); e1000_config_fc_after_link_up()
2286 * @hw: pointer to the HW structure
2291 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) e1000_check_for_serdes_link_generic() argument
2310 if (hw->autoneg_failed == 0) { e1000_check_for_serdes_link_generic()
2311 hw->autoneg_failed = 1; e1000_check_for_serdes_link_generic()
2317 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); e1000_check_for_serdes_link_generic()
2325 ret_val = e1000_config_fc_after_link_up(hw); e1000_check_for_serdes_link_generic()
2337 ew32(TXCW, hw->txcw); e1000_check_for_serdes_link_generic()
2340 hw->serdes_has_link = true; e1000_check_for_serdes_link_generic()
2351 hw->serdes_has_link = true; e1000_check_for_serdes_link_generic()
2355 hw->serdes_has_link = false; e1000_check_for_serdes_link_generic()
2368 hw->serdes_has_link = true; e1000_check_for_serdes_link_generic()
2372 hw->serdes_has_link = false; e1000_check_for_serdes_link_generic()
2377 hw->serdes_has_link = false; e1000_check_for_serdes_link_generic()
2381 hw->serdes_has_link = false; e1000_check_for_serdes_link_generic()
2392 * @hw: Struct containing variables accessed by shared code
2397 s32 e1000_check_for_link(struct e1000_hw *hw) e1000_check_for_link() argument
2415 if ((hw->media_type == e1000_media_type_fiber) || e1000_check_for_link()
2416 (hw->media_type == e1000_media_type_internal_serdes)) { e1000_check_for_link()
2419 if (hw->media_type == e1000_media_type_fiber) { e1000_check_for_link()
2421 (hw->mac_type > e1000_check_for_link()
2424 hw->get_link_status = false; e1000_check_for_link()
2434 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { e1000_check_for_link()
2440 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_check_for_link()
2443 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_check_for_link()
2448 hw->get_link_status = false; e1000_check_for_link()
2452 e1000_check_downshift(hw); e1000_check_for_link()
2463 if ((hw->mac_type == e1000_82544 e1000_check_for_link()
2464 || hw->mac_type == e1000_82543) && (!hw->autoneg) e1000_check_for_link()
2465 && (hw->forced_speed_duplex == e1000_10_full e1000_check_for_link()
2466 || hw->forced_speed_duplex == e1000_10_half)) { e1000_check_for_link()
2469 e1000_polarity_reversal_workaround(hw); e1000_check_for_link()
2477 e1000_config_dsp_after_link_change(hw, false); e1000_check_for_link()
2484 if (!hw->autoneg) e1000_check_for_link()
2488 e1000_config_dsp_after_link_change(hw, true); e1000_check_for_link()
2498 if ((hw->mac_type >= e1000_82544) && e1000_check_for_link()
2499 (hw->mac_type != e1000_ce4100)) e1000_check_for_link()
2500 e1000_config_collision_dist(hw); e1000_check_for_link()
2502 ret_val = e1000_config_mac_to_phy(hw); e1000_check_for_link()
2515 ret_val = e1000_config_fc_after_link_up(hw); e1000_check_for_link()
2529 if (hw->tbi_compatibility_en) { e1000_check_for_link()
2532 e1000_get_speed_and_duplex(hw, &speed, &duplex); e1000_check_for_link()
2542 if (hw->tbi_compatibility_on) { e1000_check_for_link()
2549 hw->tbi_compatibility_on = false; e1000_check_for_link()
2558 if (!hw->tbi_compatibility_on) { e1000_check_for_link()
2559 hw->tbi_compatibility_on = true; e1000_check_for_link()
2568 if ((hw->media_type == e1000_media_type_fiber) || e1000_check_for_link()
2569 (hw->media_type == e1000_media_type_internal_serdes)) e1000_check_for_link()
2570 e1000_check_for_serdes_link_generic(hw); e1000_check_for_link()
2577 * @hw: Struct containing variables accessed by shared code
2583 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) e1000_get_speed_and_duplex() argument
2589 if (hw->mac_type >= e1000_82543) { e1000_get_speed_and_duplex()
2619 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { e1000_get_speed_and_duplex()
2620 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); e1000_get_speed_and_duplex()
2628 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); e1000_get_speed_and_duplex()
2644 * @hw: Struct containing variables accessed by shared code
2648 static s32 e1000_wait_autoneg(struct e1000_hw *hw) e1000_wait_autoneg() argument
2661 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_wait_autoneg()
2664 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_wait_autoneg()
2677 * @hw: Struct containing variables accessed by shared code
2680 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) e1000_raise_mdi_clk() argument
2692 * @hw: Struct containing variables accessed by shared code
2695 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) e1000_lower_mdi_clk() argument
2707 * @hw: Struct containing variables accessed by shared code
2713 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) e1000_shift_out_mdi_bits() argument
2746 e1000_raise_mdi_clk(hw, &ctrl); e1000_shift_out_mdi_bits()
2747 e1000_lower_mdi_clk(hw, &ctrl); e1000_shift_out_mdi_bits()
2755 * @hw: Struct containing variables accessed by shared code
2759 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) e1000_shift_in_mdi_bits() argument
2787 e1000_raise_mdi_clk(hw, &ctrl); e1000_shift_in_mdi_bits()
2788 e1000_lower_mdi_clk(hw, &ctrl); e1000_shift_in_mdi_bits()
2792 e1000_raise_mdi_clk(hw, &ctrl); e1000_shift_in_mdi_bits()
2797 e1000_lower_mdi_clk(hw, &ctrl); e1000_shift_in_mdi_bits()
2800 e1000_raise_mdi_clk(hw, &ctrl); e1000_shift_in_mdi_bits()
2801 e1000_lower_mdi_clk(hw, &ctrl); e1000_shift_in_mdi_bits()
2809 * @hw: Struct containing variables accessed by shared code
2815 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) e1000_read_phy_reg() argument
2822 if ((hw->phy_type == e1000_phy_igp) && e1000_read_phy_reg()
2824 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_read_phy_reg()
2832 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, e1000_read_phy_reg()
2839 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, e1000_read_phy_reg_ex() argument
2844 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; e1000_read_phy_reg_ex()
2851 if (hw->mac_type > e1000_82543) { e1000_read_phy_reg_ex()
2856 if (hw->mac_type == e1000_ce4100) { e1000_read_phy_reg_ex()
2916 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); e1000_read_phy_reg_ex()
2933 e1000_shift_out_mdi_bits(hw, mdic, 14); e1000_read_phy_reg_ex()
2939 *phy_data = e1000_shift_in_mdi_bits(hw); e1000_read_phy_reg_ex()
2947 * @hw: Struct containing variables accessed by shared code
2953 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) e1000_write_phy_reg() argument
2960 if ((hw->phy_type == e1000_phy_igp) && e1000_write_phy_reg()
2962 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_write_phy_reg()
2970 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, e1000_write_phy_reg()
2977 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, e1000_write_phy_reg_ex() argument
2982 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; e1000_write_phy_reg_ex()
2989 if (hw->mac_type > e1000_82543) { e1000_write_phy_reg_ex()
2995 if (hw->mac_type == e1000_ce4100) { e1000_write_phy_reg_ex()
3045 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); e1000_write_phy_reg_ex()
3058 e1000_shift_out_mdi_bits(hw, mdic, 32); e1000_write_phy_reg_ex()
3066 * @hw: Struct containing variables accessed by shared code
3070 s32 e1000_phy_hw_reset(struct e1000_hw *hw) e1000_phy_hw_reset() argument
3077 if (hw->mac_type > e1000_82543) { e1000_phy_hw_reset()
3109 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { e1000_phy_hw_reset()
3118 return e1000_get_phy_cfg_done(hw); e1000_phy_hw_reset()
3123 * @hw: Struct containing variables accessed by shared code
3128 s32 e1000_phy_reset(struct e1000_hw *hw) e1000_phy_reset() argument
3133 switch (hw->phy_type) { e1000_phy_reset()
3135 ret_val = e1000_phy_hw_reset(hw); e1000_phy_reset()
3140 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); e1000_phy_reset()
3145 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); e1000_phy_reset()
3153 if (hw->phy_type == e1000_phy_igp) e1000_phy_reset()
3154 e1000_phy_init_script(hw); e1000_phy_reset()
3161 * @hw: Struct containing variables accessed by shared code
3165 static s32 e1000_detect_gig_phy(struct e1000_hw *hw) e1000_detect_gig_phy() argument
3171 if (hw->phy_id != 0) e1000_detect_gig_phy()
3175 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); e1000_detect_gig_phy()
3179 hw->phy_id = (u32) (phy_id_high << 16); e1000_detect_gig_phy()
3181 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); e1000_detect_gig_phy()
3185 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); e1000_detect_gig_phy()
3186 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; e1000_detect_gig_phy()
3188 switch (hw->mac_type) { e1000_detect_gig_phy()
3190 if (hw->phy_id == M88E1000_E_PHY_ID) e1000_detect_gig_phy()
3194 if (hw->phy_id == M88E1000_I_PHY_ID) e1000_detect_gig_phy()
3202 if (hw->phy_id == M88E1011_I_PHY_ID) e1000_detect_gig_phy()
3206 if ((hw->phy_id == RTL8211B_PHY_ID) || e1000_detect_gig_phy()
3207 (hw->phy_id == RTL8201N_PHY_ID) || e1000_detect_gig_phy()
3208 (hw->phy_id == M88E1118_E_PHY_ID)) e1000_detect_gig_phy()
3215 if (hw->phy_id == IGP01E1000_I_PHY_ID) e1000_detect_gig_phy()
3219 e_dbg("Invalid MAC type %d\n", hw->mac_type); e1000_detect_gig_phy()
3222 phy_init_status = e1000_set_phy_type(hw); e1000_detect_gig_phy()
3225 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); e1000_detect_gig_phy()
3228 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); e1000_detect_gig_phy()
3234 * @hw: Struct containing variables accessed by shared code
3238 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) e1000_phy_reset_dsp() argument
3243 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); e1000_phy_reset_dsp()
3246 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); e1000_phy_reset_dsp()
3249 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); e1000_phy_reset_dsp()
3260 * @hw: Struct containing variables accessed by shared code
3265 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, e1000_phy_igp_get_info() argument
3273 * and it stored in the hw->speed_downgraded parameter. e1000_phy_igp_get_info()
3275 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; e1000_phy_igp_get_info()
3284 ret_val = e1000_check_polarity(hw, &polarity); e1000_phy_igp_get_info()
3290 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); e1000_phy_igp_get_info()
3303 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); e1000_phy_igp_get_info()
3315 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); e1000_phy_igp_get_info()
3339 * @hw: Struct containing variables accessed by shared code
3344 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, e1000_phy_m88_get_info() argument
3352 * and it stored in the hw->speed_downgraded parameter. e1000_phy_m88_get_info()
3354 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; e1000_phy_m88_get_info()
3356 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_phy_m88_get_info()
3372 ret_val = e1000_check_polarity(hw, &polarity); e1000_phy_m88_get_info()
3377 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); e1000_phy_m88_get_info()
3394 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); e1000_phy_m88_get_info()
3412 * @hw: Struct containing variables accessed by shared code
3417 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) e1000_phy_get_info() argument
3431 if (hw->media_type != e1000_media_type_copper) { e1000_phy_get_info()
3436 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_phy_get_info()
3440 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); e1000_phy_get_info()
3449 if (hw->phy_type == e1000_phy_igp) e1000_phy_get_info()
3450 return e1000_phy_igp_get_info(hw, phy_info); e1000_phy_get_info()
3451 else if ((hw->phy_type == e1000_phy_8211) || e1000_phy_get_info()
3452 (hw->phy_type == e1000_phy_8201)) e1000_phy_get_info()
3455 return e1000_phy_m88_get_info(hw, phy_info); e1000_phy_get_info()
3458 s32 e1000_validate_mdi_setting(struct e1000_hw *hw) e1000_validate_mdi_setting() argument
3460 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { e1000_validate_mdi_setting()
3462 hw->mdix = 1; e1000_validate_mdi_setting()
3470 * @hw: Struct containing variables accessed by shared code
3472 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3475 s32 e1000_init_eeprom_params(struct e1000_hw *hw) e1000_init_eeprom_params() argument
3477 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_init_eeprom_params()
3482 switch (hw->mac_type) { e1000_init_eeprom_params()
3547 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); e1000_init_eeprom_params()
3566 * @hw: Struct containing variables accessed by shared code
3569 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) e1000_raise_ee_clk() argument
3577 udelay(hw->eeprom.delay_usec); e1000_raise_ee_clk()
3582 * @hw: Struct containing variables accessed by shared code
3585 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) e1000_lower_ee_clk() argument
3593 udelay(hw->eeprom.delay_usec); e1000_lower_ee_clk()
3598 * @hw: Struct containing variables accessed by shared code
3602 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) e1000_shift_out_ee_bits() argument
3604 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_shift_out_ee_bits()
3636 e1000_raise_ee_clk(hw, &eecd); e1000_shift_out_ee_bits()
3637 e1000_lower_ee_clk(hw, &eecd); e1000_shift_out_ee_bits()
3650 * @hw: Struct containing variables accessed by shared code
3653 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) e1000_shift_in_ee_bits() argument
3673 e1000_raise_ee_clk(hw, &eecd); e1000_shift_in_ee_bits()
3681 e1000_lower_ee_clk(hw, &eecd); e1000_shift_in_ee_bits()
3689 * @hw: Struct containing variables accessed by shared code
3694 static s32 e1000_acquire_eeprom(struct e1000_hw *hw) e1000_acquire_eeprom() argument
3696 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_acquire_eeprom()
3702 if (hw->mac_type > e1000_82544) { e1000_acquire_eeprom()
3743 * @hw: Struct containing variables accessed by shared code
3745 static void e1000_standby_eeprom(struct e1000_hw *hw) e1000_standby_eeprom() argument
3747 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_standby_eeprom()
3790 * @hw: Struct containing variables accessed by shared code
3794 static void e1000_release_eeprom(struct e1000_hw *hw) e1000_release_eeprom() argument
3800 if (hw->eeprom.type == e1000_eeprom_spi) { e1000_release_eeprom()
3807 udelay(hw->eeprom.delay_usec); e1000_release_eeprom()
3808 } else if (hw->eeprom.type == e1000_eeprom_microwire) { e1000_release_eeprom()
3820 udelay(hw->eeprom.delay_usec); e1000_release_eeprom()
3826 udelay(hw->eeprom.delay_usec); e1000_release_eeprom()
3830 if (hw->mac_type > e1000_82544) { e1000_release_eeprom()
3838 * @hw: Struct containing variables accessed by shared code
3840 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) e1000_spi_eeprom_ready() argument
3852 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, e1000_spi_eeprom_ready()
3853 hw->eeprom.opcode_bits); e1000_spi_eeprom_ready()
3854 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); e1000_spi_eeprom_ready()
3861 e1000_standby_eeprom(hw); e1000_spi_eeprom_ready()
3877 * @hw: Struct containing variables accessed by shared code
3882 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) e1000_read_eeprom() argument
3886 ret = e1000_do_read_eeprom(hw, offset, words, data); e1000_read_eeprom()
3891 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, e1000_do_read_eeprom() argument
3894 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_do_read_eeprom()
3897 if (hw->mac_type == e1000_ce4100) { e1000_do_read_eeprom()
3918 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) e1000_do_read_eeprom()
3928 if (e1000_spi_eeprom_ready(hw)) { e1000_do_read_eeprom()
3929 e1000_release_eeprom(hw); e1000_do_read_eeprom()
3933 e1000_standby_eeprom(hw); e1000_do_read_eeprom()
3942 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); e1000_do_read_eeprom()
3943 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), e1000_do_read_eeprom()
3954 word_in = e1000_shift_in_ee_bits(hw, 16); e1000_do_read_eeprom()
3960 e1000_shift_out_ee_bits(hw, e1000_do_read_eeprom()
3963 e1000_shift_out_ee_bits(hw, (u16) (offset + i), e1000_do_read_eeprom()
3969 data[i] = e1000_shift_in_ee_bits(hw, 16); e1000_do_read_eeprom()
3970 e1000_standby_eeprom(hw); e1000_do_read_eeprom()
3975 e1000_release_eeprom(hw); e1000_do_read_eeprom()
3982 * @hw: Struct containing variables accessed by shared code
3988 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) e1000_validate_eeprom_checksum() argument
3994 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { e1000_validate_eeprom_checksum()
4003 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) e1000_validate_eeprom_checksum()
4017 * @hw: Struct containing variables accessed by shared code
4022 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) e1000_update_eeprom_checksum() argument
4028 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { e1000_update_eeprom_checksum()
4035 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { e1000_update_eeprom_checksum()
4044 * @hw: Struct containing variables accessed by shared code
4052 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) e1000_write_eeprom() argument
4056 ret = e1000_do_write_eeprom(hw, offset, words, data); e1000_write_eeprom()
4061 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, e1000_do_write_eeprom() argument
4064 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_do_write_eeprom()
4067 if (hw->mac_type == e1000_ce4100) { e1000_do_write_eeprom()
4083 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) e1000_do_write_eeprom()
4087 status = e1000_write_eeprom_microwire(hw, offset, words, data); e1000_do_write_eeprom()
4089 status = e1000_write_eeprom_spi(hw, offset, words, data); e1000_do_write_eeprom()
4094 e1000_release_eeprom(hw); e1000_do_write_eeprom()
4101 * @hw: Struct containing variables accessed by shared code
4106 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, e1000_write_eeprom_spi() argument
4109 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_write_eeprom_spi()
4115 if (e1000_spi_eeprom_ready(hw)) e1000_write_eeprom_spi()
4118 e1000_standby_eeprom(hw); e1000_write_eeprom_spi()
4121 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, e1000_write_eeprom_spi()
4124 e1000_standby_eeprom(hw); e1000_write_eeprom_spi()
4133 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); e1000_write_eeprom_spi()
4135 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), e1000_write_eeprom_spi()
4146 e1000_shift_out_ee_bits(hw, word_out, 16); e1000_write_eeprom_spi()
4155 e1000_standby_eeprom(hw); e1000_write_eeprom_spi()
4166 * @hw: Struct containing variables accessed by shared code
4171 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, e1000_write_eeprom_microwire() argument
4174 struct e1000_eeprom_info *eeprom = &hw->eeprom; e1000_write_eeprom_microwire()
4185 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, e1000_write_eeprom_microwire()
4188 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); e1000_write_eeprom_microwire()
4191 e1000_standby_eeprom(hw); e1000_write_eeprom_microwire()
4195 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, e1000_write_eeprom_microwire()
4198 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), e1000_write_eeprom_microwire()
4202 e1000_shift_out_ee_bits(hw, data[words_written], 16); e1000_write_eeprom_microwire()
4207 e1000_standby_eeprom(hw); e1000_write_eeprom_microwire()
4226 e1000_standby_eeprom(hw); e1000_write_eeprom_microwire()
4237 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, e1000_write_eeprom_microwire()
4240 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); e1000_write_eeprom_microwire()
4247 * @hw: Struct containing variables accessed by shared code
4252 s32 e1000_read_mac_addr(struct e1000_hw *hw) e1000_read_mac_addr() argument
4259 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { e1000_read_mac_addr()
4263 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); e1000_read_mac_addr()
4264 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); e1000_read_mac_addr()
4267 switch (hw->mac_type) { e1000_read_mac_addr()
4273 hw->perm_mac_addr[5] ^= 0x01; e1000_read_mac_addr()
4278 hw->mac_addr[i] = hw->perm_mac_addr[i]; e1000_read_mac_addr()
4284 * @hw: Struct containing variables accessed by shared code
4290 static void e1000_init_rx_addrs(struct e1000_hw *hw) e1000_init_rx_addrs() argument
4298 e1000_rar_set(hw, hw->mac_addr, 0); e1000_init_rx_addrs()
4305 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); e1000_init_rx_addrs()
4307 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); e1000_init_rx_addrs()
4314 * @hw: Struct containing variables accessed by shared code
4317 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) e1000_hash_mc_addr() argument
4324 switch (hw->mc_filter_type) { e1000_hash_mc_addr()
4353 * @hw: Struct containing variables accessed by shared code
4357 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) e1000_rar_set() argument
4386 switch (hw->mac_type) { e1000_rar_set()
4393 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); e1000_rar_set()
4395 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); e1000_rar_set()
4401 * @hw: Struct containing variables accessed by shared code
4405 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) e1000_write_vfta() argument
4409 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { e1000_write_vfta()
4410 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); e1000_write_vfta()
4411 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); e1000_write_vfta()
4413 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); e1000_write_vfta()
4416 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); e1000_write_vfta()
4423 * @hw: Struct containing variables accessed by shared code
4425 static void e1000_clear_vfta(struct e1000_hw *hw) e1000_clear_vfta() argument
4438 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); e1000_clear_vfta()
4443 static s32 e1000_id_led_init(struct e1000_hw *hw) e1000_id_led_init() argument
4452 if (hw->mac_type < e1000_82540) { e1000_id_led_init()
4458 hw->ledctl_default = ledctl; e1000_id_led_init()
4459 hw->ledctl_mode1 = hw->ledctl_default; e1000_id_led_init()
4460 hw->ledctl_mode2 = hw->ledctl_default; e1000_id_led_init()
4462 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { e1000_id_led_init()
4478 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); e1000_id_led_init()
4479 hw->ledctl_mode1 |= ledctl_on << (i << 3); e1000_id_led_init()
4484 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); e1000_id_led_init()
4485 hw->ledctl_mode1 |= ledctl_off << (i << 3); e1000_id_led_init()
4495 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); e1000_id_led_init()
4496 hw->ledctl_mode2 |= ledctl_on << (i << 3); e1000_id_led_init()
4501 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); e1000_id_led_init()
4502 hw->ledctl_mode2 |= ledctl_off << (i << 3); e1000_id_led_init()
4514 * @hw: Struct containing variables accessed by shared code
4518 s32 e1000_setup_led(struct e1000_hw *hw) e1000_setup_led() argument
4523 switch (hw->mac_type) { e1000_setup_led()
4535 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, e1000_setup_led()
4536 &hw->phy_spd_default); e1000_setup_led()
4539 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, e1000_setup_led()
4540 (u16) (hw->phy_spd_default & e1000_setup_led()
4546 if (hw->media_type == e1000_media_type_fiber) { e1000_setup_led()
4549 hw->ledctl_default = ledctl; e1000_setup_led()
4557 } else if (hw->media_type == e1000_media_type_copper) e1000_setup_led()
4558 ew32(LEDCTL, hw->ledctl_mode1); e1000_setup_led()
4567 * @hw: Struct containing variables accessed by shared code
4569 s32 e1000_cleanup_led(struct e1000_hw *hw) e1000_cleanup_led() argument
4573 switch (hw->mac_type) { e1000_cleanup_led()
4585 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, e1000_cleanup_led()
4586 hw->phy_spd_default); e1000_cleanup_led()
4592 ew32(LEDCTL, hw->ledctl_default); e1000_cleanup_led()
4601 * @hw: Struct containing variables accessed by shared code
4603 s32 e1000_led_on(struct e1000_hw *hw) e1000_led_on() argument
4607 switch (hw->mac_type) { e1000_led_on()
4616 if (hw->media_type == e1000_media_type_fiber) { e1000_led_on()
4627 if (hw->media_type == e1000_media_type_fiber) { e1000_led_on()
4631 } else if (hw->media_type == e1000_media_type_copper) { e1000_led_on()
4632 ew32(LEDCTL, hw->ledctl_mode2); e1000_led_on()
4645 * @hw: Struct containing variables accessed by shared code
4647 s32 e1000_led_off(struct e1000_hw *hw) e1000_led_off() argument
4651 switch (hw->mac_type) { e1000_led_off()
4660 if (hw->media_type == e1000_media_type_fiber) { e1000_led_off()
4671 if (hw->media_type == e1000_media_type_fiber) { e1000_led_off()
4675 } else if (hw->media_type == e1000_media_type_copper) { e1000_led_off()
4676 ew32(LEDCTL, hw->ledctl_mode1); e1000_led_off()
4689 * @hw: Struct containing variables accessed by shared code
4691 static void e1000_clear_hw_cntrs(struct e1000_hw *hw) e1000_clear_hw_cntrs() argument
4749 if (hw->mac_type < e1000_82543) e1000_clear_hw_cntrs()
4759 if (hw->mac_type <= e1000_82544) e1000_clear_hw_cntrs()
4769 * @hw: Struct containing variables accessed by shared code
4772 * hw->ifs_params_forced to true. However, you must initialize hw->
4776 void e1000_reset_adaptive(struct e1000_hw *hw) e1000_reset_adaptive() argument
4778 if (hw->adaptive_ifs) { e1000_reset_adaptive()
4779 if (!hw->ifs_params_forced) { e1000_reset_adaptive()
4780 hw->current_ifs_val = 0; e1000_reset_adaptive()
4781 hw->ifs_min_val = IFS_MIN; e1000_reset_adaptive()
4782 hw->ifs_max_val = IFS_MAX; e1000_reset_adaptive()
4783 hw->ifs_step_size = IFS_STEP; e1000_reset_adaptive()
4784 hw->ifs_ratio = IFS_RATIO; e1000_reset_adaptive()
4786 hw->in_ifs_mode = false; e1000_reset_adaptive()
4795 * @hw: Struct containing variables accessed by shared code
4802 void e1000_update_adaptive(struct e1000_hw *hw) e1000_update_adaptive() argument
4804 if (hw->adaptive_ifs) { e1000_update_adaptive()
4805 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { e1000_update_adaptive()
4806 if (hw->tx_packet_delta > MIN_NUM_XMITS) { e1000_update_adaptive()
4807 hw->in_ifs_mode = true; e1000_update_adaptive()
4808 if (hw->current_ifs_val < hw->ifs_max_val) { e1000_update_adaptive()
4809 if (hw->current_ifs_val == 0) e1000_update_adaptive()
4810 hw->current_ifs_val = e1000_update_adaptive()
4811 hw->ifs_min_val; e1000_update_adaptive()
4813 hw->current_ifs_val += e1000_update_adaptive()
4814 hw->ifs_step_size; e1000_update_adaptive()
4815 ew32(AIT, hw->current_ifs_val); e1000_update_adaptive()
4819 if (hw->in_ifs_mode e1000_update_adaptive()
4820 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { e1000_update_adaptive()
4821 hw->current_ifs_val = 0; e1000_update_adaptive()
4822 hw->in_ifs_mode = false; e1000_update_adaptive()
4833 * @hw: Struct containing variables accessed by shared code
4837 void e1000_get_bus_info(struct e1000_hw *hw) e1000_get_bus_info() argument
4841 switch (hw->mac_type) { e1000_get_bus_info()
4844 hw->bus_type = e1000_bus_type_pci; e1000_get_bus_info()
4845 hw->bus_speed = e1000_bus_speed_unknown; e1000_get_bus_info()
4846 hw->bus_width = e1000_bus_width_unknown; e1000_get_bus_info()
4850 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? e1000_get_bus_info()
4853 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { e1000_get_bus_info()
4854 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? e1000_get_bus_info()
4856 } else if (hw->bus_type == e1000_bus_type_pci) { e1000_get_bus_info()
4857 hw->bus_speed = (status & E1000_STATUS_PCI66) ? e1000_get_bus_info()
4862 hw->bus_speed = e1000_bus_speed_66; e1000_get_bus_info()
4865 hw->bus_speed = e1000_bus_speed_100; e1000_get_bus_info()
4868 hw->bus_speed = e1000_bus_speed_133; e1000_get_bus_info()
4871 hw->bus_speed = e1000_bus_speed_reserved; e1000_get_bus_info()
4875 hw->bus_width = (status & E1000_STATUS_BUS64) ? e1000_get_bus_info()
4883 * @hw: Struct containing variables accessed by shared code
4890 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) e1000_write_reg_io() argument
4892 unsigned long io_addr = hw->io_base; e1000_write_reg_io()
4893 unsigned long io_data = hw->io_base + 4; e1000_write_reg_io()
4895 e1000_io_write(hw, io_addr, offset); e1000_write_reg_io()
4896 e1000_io_write(hw, io_data, value); e1000_write_reg_io()
4901 * @hw: Struct containing variables accessed by shared code
4913 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, e1000_get_cable_length() argument
4924 if (hw->phy_type == e1000_phy_m88) { e1000_get_cable_length()
4926 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, e1000_get_cable_length()
4958 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ e1000_get_cable_length()
4971 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); e1000_get_cable_length()
5016 * @hw: Struct containing variables accessed by shared code
5029 static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_check_polarity() argument
5035 if (hw->phy_type == e1000_phy_m88) { e1000_check_polarity()
5037 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, e1000_check_polarity()
5045 } else if (hw->phy_type == e1000_phy_igp) { e1000_check_polarity()
5047 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, e1000_check_polarity()
5060 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, e1000_check_polarity()
5084 * @hw: Struct containing variables accessed by shared code
5096 static s32 e1000_check_downshift(struct e1000_hw *hw) e1000_check_downshift() argument
5101 if (hw->phy_type == e1000_phy_igp) { e1000_check_downshift()
5102 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, e1000_check_downshift()
5107 hw->speed_downgraded = e1000_check_downshift()
5109 } else if (hw->phy_type == e1000_phy_m88) { e1000_check_downshift()
5110 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, e1000_check_downshift()
5115 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> e1000_check_downshift()
5129 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw) e1000_1000Mb_check_cable_length() argument
5135 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); e1000_1000Mb_check_cable_length()
5139 if (hw->dsp_config_state != e1000_dsp_config_enabled) e1000_1000Mb_check_cable_length()
5144 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], e1000_1000Mb_check_cable_length()
5151 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], e1000_1000Mb_check_cable_length()
5156 hw->dsp_config_state = e1000_dsp_config_activated; e1000_1000Mb_check_cable_length()
5162 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); e1000_1000Mb_check_cable_length()
5168 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, e1000_1000Mb_check_cable_length()
5175 hw->ffe_config_state = e1000_ffe_config_active; e1000_1000Mb_check_cable_length()
5177 ret_val = e1000_write_phy_reg(hw, e1000_1000Mb_check_cable_length()
5196 * @hw: Struct containing variables accessed by shared code
5206 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) e1000_config_dsp_after_link_change() argument
5211 if (hw->phy_type != e1000_phy_igp) e1000_config_dsp_after_link_change()
5215 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); e1000_config_dsp_after_link_change()
5222 ret_val = e1000_1000Mb_check_cable_length(hw); e1000_config_dsp_after_link_change()
5227 if (hw->dsp_config_state == e1000_dsp_config_activated) { e1000_config_dsp_after_link_change()
5232 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); e1000_config_dsp_after_link_change()
5238 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); e1000_config_dsp_after_link_change()
5245 ret_val = e1000_write_phy_reg(hw, 0x0000, e1000_config_dsp_after_link_change()
5251 e1000_read_phy_reg(hw, dsp_reg_array[i], e1000_config_dsp_after_link_change()
5260 e1000_write_phy_reg(hw, dsp_reg_array[i], e1000_config_dsp_after_link_change()
5266 ret_val = e1000_write_phy_reg(hw, 0x0000, e1000_config_dsp_after_link_change()
5275 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); e1000_config_dsp_after_link_change()
5280 hw->dsp_config_state = e1000_dsp_config_enabled; e1000_config_dsp_after_link_change()
5283 if (hw->ffe_config_state == e1000_ffe_config_active) { e1000_config_dsp_after_link_change()
5288 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); e1000_config_dsp_after_link_change()
5294 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); e1000_config_dsp_after_link_change()
5301 ret_val = e1000_write_phy_reg(hw, 0x0000, e1000_config_dsp_after_link_change()
5306 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, e1000_config_dsp_after_link_change()
5311 ret_val = e1000_write_phy_reg(hw, 0x0000, e1000_config_dsp_after_link_change()
5320 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); e1000_config_dsp_after_link_change()
5325 hw->ffe_config_state = e1000_ffe_config_enabled; e1000_config_dsp_after_link_change()
5333 * @hw: Struct containing variables accessed by shared code
5339 static s32 e1000_set_phy_mode(struct e1000_hw *hw) e1000_set_phy_mode() argument
5344 if ((hw->mac_type == e1000_82545_rev_3) && e1000_set_phy_mode()
5345 (hw->media_type == e1000_media_type_copper)) { e1000_set_phy_mode()
5347 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, e1000_set_phy_mode()
5356 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, e1000_set_phy_mode()
5361 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, e1000_set_phy_mode()
5366 hw->phy_reset_disable = false; e1000_set_phy_mode()
5375 * @hw: Struct containing variables accessed by shared code
5386 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) e1000_set_d3_lplu_state() argument
5391 if (hw->phy_type != e1000_phy_igp) e1000_set_d3_lplu_state()
5398 if (hw->mac_type == e1000_82541_rev_2 e1000_set_d3_lplu_state()
5399 || hw->mac_type == e1000_82547_rev_2) { e1000_set_d3_lplu_state()
5401 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); e1000_set_d3_lplu_state()
5407 if (hw->mac_type == e1000_82541_rev_2 || e1000_set_d3_lplu_state()
5408 hw->mac_type == e1000_82547_rev_2) { e1000_set_d3_lplu_state()
5411 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, e1000_set_d3_lplu_state()
5422 if (hw->smart_speed == e1000_smart_speed_on) { e1000_set_d3_lplu_state()
5424 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state()
5431 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state()
5435 } else if (hw->smart_speed == e1000_smart_speed_off) { e1000_set_d3_lplu_state()
5437 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state()
5444 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state()
5449 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) e1000_set_d3_lplu_state()
5450 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) e1000_set_d3_lplu_state()
5451 || (hw->autoneg_advertised == e1000_set_d3_lplu_state()
5454 if (hw->mac_type == e1000_82541_rev_2 || e1000_set_d3_lplu_state()
5455 hw->mac_type == e1000_82547_rev_2) { e1000_set_d3_lplu_state()
5458 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, e1000_set_d3_lplu_state()
5466 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state()
5473 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, e1000_set_d3_lplu_state()
5484 * @hw: Struct containing variables accessed by shared code
5488 static s32 e1000_set_vco_speed(struct e1000_hw *hw) e1000_set_vco_speed() argument
5494 switch (hw->mac_type) { e1000_set_vco_speed()
5505 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); e1000_set_vco_speed()
5509 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); e1000_set_vco_speed()
5513 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); e1000_set_vco_speed()
5518 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); e1000_set_vco_speed()
5524 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); e1000_set_vco_speed()
5528 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); e1000_set_vco_speed()
5533 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); e1000_set_vco_speed()
5538 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); e1000_set_vco_speed()
5548 * @hw: Struct containing variables accessed by shared code
5553 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) e1000_enable_mng_pass_thru() argument
5557 if (hw->asf_firmware_present) { e1000_enable_mng_pass_thru()
5569 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) e1000_polarity_reversal_workaround() argument
5579 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); e1000_polarity_reversal_workaround()
5582 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); e1000_polarity_reversal_workaround()
5586 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); e1000_polarity_reversal_workaround()
5596 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_polarity_reversal_workaround()
5600 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_polarity_reversal_workaround()
5614 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); e1000_polarity_reversal_workaround()
5618 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); e1000_polarity_reversal_workaround()
5622 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); e1000_polarity_reversal_workaround()
5626 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); e1000_polarity_reversal_workaround()
5630 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); e1000_polarity_reversal_workaround()
5640 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_polarity_reversal_workaround()
5644 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); e1000_polarity_reversal_workaround()
5657 * @hw: Struct containing variables accessed by shared code
5663 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) e1000_get_auto_rd_done() argument
5671 * @hw: Struct containing variables accessed by shared code
5677 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) e1000_get_phy_cfg_done() argument
H A De1000_ethtool.c110 struct e1000_hw *hw = &adapter->hw; e1000_get_settings() local
112 if (hw->media_type == e1000_media_type_copper) { e1000_get_settings()
122 if (hw->autoneg == 1) { e1000_get_settings()
125 ecmd->advertising |= hw->autoneg_advertised; e1000_get_settings()
129 ecmd->phy_address = hw->phy_addr; e1000_get_settings()
131 if (hw->mac_type == e1000_82543) e1000_get_settings()
147 if (hw->mac_type >= e1000_82545) e1000_get_settings()
154 e1000_get_speed_and_duplex(hw, &adapter->link_speed, e1000_get_settings()
170 ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) || e1000_get_settings()
171 hw->autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE; e1000_get_settings()
174 if ((hw->media_type == e1000_media_type_copper) && e1000_get_settings()
181 if (hw->mdix == AUTO_ALL_MODES) e1000_get_settings()
184 ecmd->eth_tp_mdix_ctrl = hw->mdix; e1000_get_settings()
192 struct e1000_hw *hw = &adapter->hw; e1000_set_settings() local
199 if (hw->media_type != e1000_media_type_copper) e1000_set_settings()
213 hw->autoneg = 1; e1000_set_settings()
214 if (hw->media_type == e1000_media_type_fiber) e1000_set_settings()
215 hw->autoneg_advertised = ADVERTISED_1000baseT_Full | e1000_set_settings()
219 hw->autoneg_advertised = ecmd->advertising | e1000_set_settings()
222 ecmd->advertising = hw->autoneg_advertised; e1000_set_settings()
235 hw->mdix = AUTO_ALL_MODES; e1000_set_settings()
237 hw->mdix = ecmd->eth_tp_mdix_ctrl; e1000_set_settings()
263 adapter->hw.get_link_status = 1; e1000_get_link()
272 struct e1000_hw *hw = &adapter->hw; e1000_get_pauseparam() local
277 if (hw->fc == E1000_FC_RX_PAUSE) { e1000_get_pauseparam()
279 } else if (hw->fc == E1000_FC_TX_PAUSE) { e1000_get_pauseparam()
281 } else if (hw->fc == E1000_FC_FULL) { e1000_get_pauseparam()
291 struct e1000_hw *hw = &adapter->hw; e1000_set_pauseparam() local
300 hw->fc = E1000_FC_FULL; e1000_set_pauseparam()
302 hw->fc = E1000_FC_RX_PAUSE; e1000_set_pauseparam()
304 hw->fc = E1000_FC_TX_PAUSE; e1000_set_pauseparam()
306 hw->fc = E1000_FC_NONE; e1000_set_pauseparam()
308 hw->original_fc = hw->fc; e1000_set_pauseparam()
318 retval = ((hw->media_type == e1000_media_type_fiber) ? e1000_set_pauseparam()
319 e1000_setup_link(hw) : e1000_force_mac_fc(hw)); e1000_set_pauseparam()
349 struct e1000_hw *hw = &adapter->hw; e1000_get_regs() local
355 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; e1000_get_regs()
372 regs_buff[12] = hw->phy_type; /* PHY type (IGP=1, M88=0) */ e1000_get_regs()
373 if (hw->phy_type == e1000_phy_igp) { e1000_get_regs()
374 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_get_regs()
376 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A & e1000_get_regs()
379 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_get_regs()
381 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B & e1000_get_regs()
384 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_get_regs()
386 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C & e1000_get_regs()
389 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_get_regs()
391 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D & e1000_get_regs()
395 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); e1000_get_regs()
396 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS & e1000_get_regs()
399 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, e1000_get_regs()
401 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG & e1000_get_regs()
407 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); e1000_get_regs()
409 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); e1000_get_regs()
414 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); e1000_get_regs()
424 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); e1000_get_regs()
427 if (hw->mac_type >= e1000_82540 && e1000_get_regs()
428 hw->media_type == e1000_media_type_copper) { e1000_get_regs()
436 struct e1000_hw *hw = &adapter->hw; e1000_get_eeprom_len() local
438 return hw->eeprom.word_size * 2; e1000_get_eeprom_len()
445 struct e1000_hw *hw = &adapter->hw; e1000_get_eeprom() local
454 eeprom->magic = hw->vendor_id | (hw->device_id << 16); e1000_get_eeprom()
464 if (hw->eeprom.type == e1000_eeprom_spi) e1000_get_eeprom()
465 ret_val = e1000_read_eeprom(hw, first_word, e1000_get_eeprom()
470 ret_val = e1000_read_eeprom(hw, first_word + i, 1, e1000_get_eeprom()
492 struct e1000_hw *hw = &adapter->hw; e1000_set_eeprom() local
501 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) e1000_set_eeprom()
504 max_len = hw->eeprom.word_size * 2; e1000_set_eeprom()
518 ret_val = e1000_read_eeprom(hw, first_word, 1, e1000_set_eeprom()
526 ret_val = e1000_read_eeprom(hw, last_word, 1, e1000_set_eeprom()
539 ret_val = e1000_write_eeprom(hw, first_word, e1000_set_eeprom()
544 e1000_update_eeprom_checksum(hw); e1000_set_eeprom()
568 struct e1000_hw *hw = &adapter->hw; e1000_get_ringparam() local
569 e1000_mac_type mac_type = hw->mac_type; e1000_get_ringparam()
585 struct e1000_hw *hw = &adapter->hw; e1000_set_ringparam() local
586 e1000_mac_type mac_type = hw->mac_type; e1000_set_ringparam()
677 struct e1000_hw *hw = &adapter->hw; reg_pattern_test() local
681 u8 __iomem *address = hw->hw_addr + reg; reg_pattern_test()
702 struct e1000_hw *hw = &adapter->hw; reg_set_and_check() local
703 u8 __iomem *address = hw->hw_addr + reg; reg_set_and_check()
721 (hw->mac_type >= e1000_82543) \
730 (hw->mac_type >= e1000_82543) \
740 struct e1000_hw *hw = &adapter->hw; e1000_reg_test() local
784 if (hw->mac_type >= e1000_82543) { e1000_reg_test()
812 struct e1000_hw *hw = &adapter->hw; e1000_eeprom_test() local
820 if ((e1000_read_eeprom(hw, i, 1, &temp)) < 0) { e1000_eeprom_test()
838 struct e1000_hw *hw = &adapter->hw; e1000_test_intr() local
851 struct e1000_hw *hw = &adapter->hw; e1000_intr_test() local
866 e_info(hw, "testing %s interrupt\n", (shared_int ? e1000_intr_test()
995 struct e1000_hw *hw = &adapter->hw; e1000_setup_desc_rings() local
1091 (hw->mc_filter_type << E1000_RCTL_MO_SHIFT); e1000_setup_desc_rings()
1126 struct e1000_hw *hw = &adapter->hw; e1000_phy_disable_receiver() local
1129 e1000_write_phy_reg(hw, 29, 0x001F); e1000_phy_disable_receiver()
1130 e1000_write_phy_reg(hw, 30, 0x8FFC); e1000_phy_disable_receiver()
1131 e1000_write_phy_reg(hw, 29, 0x001A); e1000_phy_disable_receiver()
1132 e1000_write_phy_reg(hw, 30, 0x8FF0); e1000_phy_disable_receiver()
1137 struct e1000_hw *hw = &adapter->hw; e1000_phy_reset_clk_and_crs() local
1144 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); e1000_phy_reset_clk_and_crs()
1146 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_reg); e1000_phy_reset_clk_and_crs()
1152 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); e1000_phy_reset_clk_and_crs()
1154 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg); e1000_phy_reset_clk_and_crs()
1159 struct e1000_hw *hw = &adapter->hw; e1000_nonintegrated_phy_loopback() local
1175 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg); e1000_nonintegrated_phy_loopback()
1181 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg); e1000_nonintegrated_phy_loopback()
1184 e1000_phy_reset(hw); e1000_nonintegrated_phy_loopback()
1189 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100); e1000_nonintegrated_phy_loopback()
1201 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); e1000_nonintegrated_phy_loopback()
1203 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); e1000_nonintegrated_phy_loopback()
1209 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); e1000_nonintegrated_phy_loopback()
1213 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg); e1000_nonintegrated_phy_loopback()
1217 e1000_read_phy_reg(hw, 29, &phy_reg); e1000_nonintegrated_phy_loopback()
1226 struct e1000_hw *hw = &adapter->hw; e1000_integrated_phy_loopback() local
1230 hw->autoneg = false; e1000_integrated_phy_loopback()
1232 if (hw->phy_type == e1000_phy_m88) { e1000_integrated_phy_loopback()
1234 e1000_write_phy_reg(hw, e1000_integrated_phy_loopback()
1237 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); e1000_integrated_phy_loopback()
1239 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); e1000_integrated_phy_loopback()
1245 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); e1000_integrated_phy_loopback()
1255 if (hw->media_type == e1000_media_type_copper && e1000_integrated_phy_loopback()
1256 hw->phy_type == e1000_phy_m88) e1000_integrated_phy_loopback()
1272 if (hw->phy_type == e1000_phy_m88) e1000_integrated_phy_loopback()
1282 struct e1000_hw *hw = &adapter->hw; e1000_set_phy_loopback() local
1286 switch (hw->mac_type) { e1000_set_phy_loopback()
1288 if (hw->media_type == e1000_media_type_copper) { e1000_set_phy_loopback()
1315 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); e1000_set_phy_loopback()
1317 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); e1000_set_phy_loopback()
1326 struct e1000_hw *hw = &adapter->hw; e1000_setup_loopback_test() local
1329 if (hw->media_type == e1000_media_type_fiber || e1000_setup_loopback_test()
1330 hw->media_type == e1000_media_type_internal_serdes) { e1000_setup_loopback_test()
1331 switch (hw->mac_type) { e1000_setup_loopback_test()
1343 } else if (hw->media_type == e1000_media_type_copper) { e1000_setup_loopback_test()
1352 struct e1000_hw *hw = &adapter->hw; e1000_loopback_cleanup() local
1360 switch (hw->mac_type) { e1000_loopback_cleanup()
1366 hw->autoneg = true; e1000_loopback_cleanup()
1367 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); e1000_loopback_cleanup()
1370 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); e1000_loopback_cleanup()
1371 e1000_phy_reset(hw); e1000_loopback_cleanup()
1402 struct e1000_hw *hw = &adapter->hw; e1000_run_loopback_test() local
1489 struct e1000_hw *hw = &adapter->hw; e1000_link_test() local
1491 if (hw->media_type == e1000_media_type_internal_serdes) { e1000_link_test()
1494 hw->serdes_has_link = false; e1000_link_test()
1500 e1000_check_for_link(hw); e1000_link_test()
1501 if (hw->serdes_has_link) e1000_link_test()
1508 e1000_check_for_link(hw); e1000_link_test()
1509 if (hw->autoneg) /* if auto_neg is set wait for it */ e1000_link_test()
1534 struct e1000_hw *hw = &adapter->hw; e1000_diag_test() local
1542 u16 autoneg_advertised = hw->autoneg_advertised; e1000_diag_test()
1543 u8 forced_speed_duplex = hw->forced_speed_duplex; e1000_diag_test()
1544 u8 autoneg = hw->autoneg; e1000_diag_test()
1546 e_info(hw, "offline testing starting\n"); e1000_diag_test()
1578 hw->autoneg_advertised = autoneg_advertised; e1000_diag_test()
1579 hw->forced_speed_duplex = forced_speed_duplex; e1000_diag_test()
1580 hw->autoneg = autoneg; e1000_diag_test()
1587 e_info(hw, "online testing starting\n"); e1000_diag_test()
1606 struct e1000_hw *hw = &adapter->hw; e1000_wol_exclusion() local
1609 switch (hw->device_id) { e1000_wol_exclusion()
1662 struct e1000_hw *hw = &adapter->hw; e1000_get_wol() local
1675 switch (hw->device_id) { e1000_get_wol()
1701 struct e1000_hw *hw = &adapter->hw; e1000_set_wol() local
1710 switch (hw->device_id) { e1000_set_wol()
1743 struct e1000_hw *hw = &adapter->hw; e1000_set_phys_id() local
1747 e1000_setup_led(hw); e1000_set_phys_id()
1751 e1000_led_on(hw); e1000_set_phys_id()
1755 e1000_led_off(hw); e1000_set_phys_id()
1759 e1000_cleanup_led(hw); e1000_set_phys_id()
1770 if (adapter->hw.mac_type < e1000_82545) e1000_get_coalesce()
1785 struct e1000_hw *hw = &adapter->hw; e1000_set_coalesce() local
1787 if (hw->mac_type < e1000_82545) e1000_set_coalesce()
/linux-4.4.14/drivers/input/misc/
H A Dad714x.c216 struct ad714x_button_plat *hw = &ad714x->hw->button[idx]; ad714x_button_state_machine() local
221 if (((ad714x->h_state & hw->h_mask) == hw->h_mask) && ad714x_button_state_machine()
222 ((ad714x->l_state & hw->l_mask) == hw->l_mask)) { ad714x_button_state_machine()
224 input_report_key(sw->input, hw->keycode, 1); ad714x_button_state_machine()
231 if (((ad714x->h_state & hw->h_mask) != hw->h_mask) || ad714x_button_state_machine()
232 ((ad714x->l_state & hw->l_mask) != hw->l_mask)) { ad714x_button_state_machine()
234 input_report_key(sw->input, hw->keycode, 0); ad714x_button_state_machine()
251 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; ad714x_slider_cal_sensor_val() local
254 ad714x->read(ad714x, CDC_RESULT_S0 + hw->start_stage, ad714x_slider_cal_sensor_val()
255 &ad714x->adc_reg[hw->start_stage], ad714x_slider_cal_sensor_val()
256 hw->end_stage - hw->start_stage + 1); ad714x_slider_cal_sensor_val()
258 for (i = hw->start_stage; i <= hw->end_stage; i++) { ad714x_slider_cal_sensor_val()
269 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; ad714x_slider_cal_highest_stage() local
272 sw->highest_stage = ad714x_cal_highest_stage(ad714x, hw->start_stage, ad714x_slider_cal_highest_stage()
273 hw->end_stage); ad714x_slider_cal_highest_stage()
294 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; ad714x_slider_cal_abs_pos() local
297 sw->abs_pos = ad714x_cal_abs_pos(ad714x, hw->start_stage, hw->end_stage, ad714x_slider_cal_abs_pos()
298 sw->highest_stage, hw->max_coord); ad714x_slider_cal_abs_pos()
327 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; ad714x_slider_use_com_int() local
329 ad714x_use_com_int(ad714x, hw->start_stage, hw->end_stage); ad714x_slider_use_com_int()
334 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; ad714x_slider_use_thr_int() local
336 ad714x_use_thr_int(ad714x, hw->start_stage, hw->end_stage); ad714x_slider_use_thr_int()
341 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; ad714x_slider_state_machine() local
346 mask = ((1 << (hw->end_stage + 1)) - 1) - ((1 << hw->start_stage) - 1); ad714x_slider_state_machine()
410 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_cal_highest_stage() local
414 sw->highest_stage = ad714x_cal_highest_stage(ad714x, hw->start_stage, ad714x_wheel_cal_highest_stage()
415 hw->end_stage); ad714x_wheel_cal_highest_stage()
423 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_cal_sensor_val() local
426 ad714x->read(ad714x, CDC_RESULT_S0 + hw->start_stage, ad714x_wheel_cal_sensor_val()
427 &ad714x->adc_reg[hw->start_stage], ad714x_wheel_cal_sensor_val()
428 hw->end_stage - hw->start_stage + 1); ad714x_wheel_cal_sensor_val()
430 for (i = hw->start_stage; i <= hw->end_stage; i++) { ad714x_wheel_cal_sensor_val()
452 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_cal_abs_pos() local
454 int stage_num = hw->end_stage - hw->start_stage + 1; ad714x_wheel_cal_abs_pos()
463 (highest - hw->start_stage) + ad714x_wheel_cal_abs_pos()
465 (highest - hw->start_stage - 1) + ad714x_wheel_cal_abs_pos()
467 (highest - hw->start_stage + 1); ad714x_wheel_cal_abs_pos()
472 sw->abs_pos = ((hw->max_coord / (hw->end_stage - hw->start_stage)) * ad714x_wheel_cal_abs_pos()
475 if (sw->abs_pos > hw->max_coord) ad714x_wheel_cal_abs_pos()
476 sw->abs_pos = hw->max_coord; ad714x_wheel_cal_abs_pos()
483 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_cal_flt_pos() local
485 if (((sw->pre_highest_stage == hw->end_stage) && ad714x_wheel_cal_flt_pos()
486 (sw->highest_stage == hw->start_stage)) || ad714x_wheel_cal_flt_pos()
487 ((sw->pre_highest_stage == hw->start_stage) && ad714x_wheel_cal_flt_pos()
488 (sw->highest_stage == hw->end_stage))) ad714x_wheel_cal_flt_pos()
493 if (sw->flt_pos > hw->max_coord) ad714x_wheel_cal_flt_pos()
494 sw->flt_pos = hw->max_coord; ad714x_wheel_cal_flt_pos()
499 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_use_com_int() local
501 ad714x_use_com_int(ad714x, hw->start_stage, hw->end_stage); ad714x_wheel_use_com_int()
506 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_use_thr_int() local
508 ad714x_use_thr_int(ad714x, hw->start_stage, hw->end_stage); ad714x_wheel_use_thr_int()
513 struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx]; ad714x_wheel_state_machine() local
518 mask = ((1 << (hw->end_stage + 1)) - 1) - ((1 << hw->start_stage) - 1); ad714x_wheel_state_machine()
577 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_cal_sensor_val() local
580 ad714x->read(ad714x, CDC_RESULT_S0 + hw->x_start_stage, touchpad_cal_sensor_val()
581 &ad714x->adc_reg[hw->x_start_stage], touchpad_cal_sensor_val()
582 hw->x_end_stage - hw->x_start_stage + 1); touchpad_cal_sensor_val()
584 for (i = hw->x_start_stage; i <= hw->x_end_stage; i++) { touchpad_cal_sensor_val()
597 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_cal_highest_stage() local
601 hw->x_start_stage, hw->x_end_stage); touchpad_cal_highest_stage()
603 hw->y_start_stage, hw->y_end_stage); touchpad_cal_highest_stage()
618 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_check_second_peak() local
622 for (i = hw->x_start_stage; i < sw->x_highest_stage; i++) { touchpad_check_second_peak()
628 for (i = sw->x_highest_stage; i < hw->x_end_stage; i++) { touchpad_check_second_peak()
634 for (i = hw->y_start_stage; i < sw->y_highest_stage; i++) { touchpad_check_second_peak()
640 for (i = sw->y_highest_stage; i < hw->y_end_stage; i++) { touchpad_check_second_peak()
657 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_cal_abs_pos() local
660 sw->x_abs_pos = ad714x_cal_abs_pos(ad714x, hw->x_start_stage, touchpad_cal_abs_pos()
661 hw->x_end_stage, sw->x_highest_stage, hw->x_max_coord); touchpad_cal_abs_pos()
662 sw->y_abs_pos = ad714x_cal_abs_pos(ad714x, hw->y_start_stage, touchpad_cal_abs_pos()
663 hw->y_end_stage, sw->y_highest_stage, hw->y_max_coord); touchpad_cal_abs_pos()
702 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_check_endpoint() local
707 percent_sensor_diff = (ad714x->sensor_val[hw->x_start_stage] - touchpad_check_endpoint()
708 ad714x->sensor_val[hw->x_start_stage + 1]) * 100 / touchpad_check_endpoint()
709 ad714x->sensor_val[hw->x_start_stage + 1]; touchpad_check_endpoint()
714 ad714x->sensor_val[hw->x_start_stage + 1]; touchpad_check_endpoint()
718 (ad714x->sensor_val[hw->x_start_stage + 1] > touchpad_check_endpoint()
724 percent_sensor_diff = (ad714x->sensor_val[hw->x_end_stage] - touchpad_check_endpoint()
725 ad714x->sensor_val[hw->x_end_stage - 1]) * 100 / touchpad_check_endpoint()
726 ad714x->sensor_val[hw->x_end_stage - 1]; touchpad_check_endpoint()
731 ad714x->sensor_val[hw->x_end_stage - 1]; touchpad_check_endpoint()
735 (ad714x->sensor_val[hw->x_end_stage - 1] > touchpad_check_endpoint()
741 percent_sensor_diff = (ad714x->sensor_val[hw->y_start_stage] - touchpad_check_endpoint()
742 ad714x->sensor_val[hw->y_start_stage + 1]) * 100 / touchpad_check_endpoint()
743 ad714x->sensor_val[hw->y_start_stage + 1]; touchpad_check_endpoint()
748 ad714x->sensor_val[hw->y_start_stage + 1]; touchpad_check_endpoint()
752 (ad714x->sensor_val[hw->y_start_stage + 1] > touchpad_check_endpoint()
758 percent_sensor_diff = (ad714x->sensor_val[hw->y_end_stage] - touchpad_check_endpoint()
759 ad714x->sensor_val[hw->y_end_stage - 1]) * 100 / touchpad_check_endpoint()
760 ad714x->sensor_val[hw->y_end_stage - 1]; touchpad_check_endpoint()
765 ad714x->sensor_val[hw->y_end_stage - 1]; touchpad_check_endpoint()
769 (ad714x->sensor_val[hw->y_end_stage - 1] > touchpad_check_endpoint()
779 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_use_com_int() local
781 ad714x_use_com_int(ad714x, hw->x_start_stage, hw->x_end_stage); touchpad_use_com_int()
786 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; touchpad_use_thr_int() local
788 ad714x_use_thr_int(ad714x, hw->x_start_stage, hw->x_end_stage); touchpad_use_thr_int()
789 ad714x_use_thr_int(ad714x, hw->y_start_stage, hw->y_end_stage); touchpad_use_thr_int()
794 struct ad714x_touchpad_plat *hw = &ad714x->hw->touchpad[idx]; ad714x_touchpad_state_machine() local
799 mask = (((1 << (hw->x_end_stage + 1)) - 1) - ad714x_touchpad_state_machine()
800 ((1 << hw->x_start_stage) - 1)) + ad714x_touchpad_state_machine()
801 (((1 << (hw->y_end_stage + 1)) - 1) - ad714x_touchpad_state_machine()
802 ((1 << hw->y_start_stage) - 1)); ad714x_touchpad_state_machine()
925 ad714x->hw->stage_cfg_reg[i][j]); ad714x_hw_init()
930 ad714x->hw->sys_cfg_reg[i]); ad714x_hw_init()
949 for (i = 0; i < ad714x->hw->button_num; i++) ad714x_interrupt_thread()
951 for (i = 0; i < ad714x->hw->slider_num; i++) ad714x_interrupt_thread()
953 for (i = 0; i < ad714x->hw->wheel_num; i++) ad714x_interrupt_thread()
955 for (i = 0; i < ad714x->hw->touchpad_num; i++) ad714x_interrupt_thread()
1003 ad714x->hw = plat_data; ad714x_probe()
1009 drv_mem += sizeof(*sd_drv) * ad714x->hw->slider_num; ad714x_probe()
1011 drv_mem += sizeof(*wl_drv) * ad714x->hw->wheel_num; ad714x_probe()
1013 drv_mem += sizeof(*tp_drv) * ad714x->hw->touchpad_num; ad714x_probe()
1015 drv_mem += sizeof(*bt_drv) * ad714x->hw->button_num; ad714x_probe()
1026 /* initialize and request sw/hw resources */ ad714x_probe()
1032 if (ad714x->hw->slider_num > 0) { ad714x_probe()
1033 struct ad714x_slider_plat *sd_plat = ad714x->hw->slider; ad714x_probe()
1035 for (i = 0; i < ad714x->hw->slider_num; i++) { ad714x_probe()
1062 if (ad714x->hw->wheel_num > 0) { ad714x_probe()
1063 struct ad714x_wheel_plat *wl_plat = ad714x->hw->wheel; ad714x_probe()
1065 for (i = 0; i < ad714x->hw->wheel_num; i++) { ad714x_probe()
1092 if (ad714x->hw->touchpad_num > 0) { ad714x_probe()
1093 struct ad714x_touchpad_plat *tp_plat = ad714x->hw->touchpad; ad714x_probe()
1095 for (i = 0; i < ad714x->hw->touchpad_num; i++) { ad714x_probe()
1125 if (ad714x->hw->button_num > 0) { ad714x_probe()
1126 struct ad714x_button_plat *bt_plat = ad714x->hw->button; ad714x_probe()
1135 for (i = 0; i < ad714x->hw->button_num; i++) { ad714x_probe()
1175 data = ad714x->hw->sys_cfg_reg[AD714X_PWR_CTRL] | 0x3; ad714x_disable()
1193 ad714x->hw->sys_cfg_reg[AD714X_PWR_CTRL]); ad714x_enable()
/linux-4.4.14/drivers/clk/qcom/
H A Dclk-rcg2.c50 static int clk_rcg2_is_enabled(struct clk_hw *hw) clk_rcg2_is_enabled() argument
52 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_is_enabled()
63 static u8 clk_rcg2_get_parent(struct clk_hw *hw) clk_rcg2_get_parent() argument
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_get_parent()
66 int num_parents = clk_hw_get_num_parents(hw); clk_rcg2_get_parent()
83 __func__, clk_hw_get_name(hw)); clk_rcg2_get_parent()
91 struct clk_hw *hw = &rcg->clkr.hw; update_config() local
92 const char *name = clk_hw_get_name(hw); update_config()
113 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) clk_rcg2_set_parent() argument
115 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_set_parent()
153 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) clk_rcg2_recalc_rate() argument
155 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_recalc_rate()
179 static int _freq_tbl_determine_rate(struct clk_hw *hw, _freq_tbl_determine_rate() argument
184 struct clk_rcg2 *rcg = to_clk_rcg2(hw); _freq_tbl_determine_rate()
191 index = qcom_find_src_index(hw, rcg->parent_map, f->src); _freq_tbl_determine_rate()
195 clk_flags = clk_hw_get_flags(hw); _freq_tbl_determine_rate()
196 p = clk_hw_get_parent_by_index(hw, index); _freq_tbl_determine_rate()
219 static int clk_rcg2_determine_rate(struct clk_hw *hw, clk_rcg2_determine_rate() argument
222 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_determine_rate()
224 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req); clk_rcg2_determine_rate()
230 struct clk_hw *hw = &rcg->clkr.hw; clk_rcg2_configure() local
231 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); clk_rcg2_configure()
268 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate) __clk_rcg2_set_rate() argument
270 struct clk_rcg2 *rcg = to_clk_rcg2(hw); __clk_rcg2_set_rate()
280 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, clk_rcg2_set_rate() argument
283 return __clk_rcg2_set_rate(hw, rate); clk_rcg2_set_rate()
286 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, clk_rcg2_set_rate_and_parent() argument
289 return __clk_rcg2_set_rate(hw, rate); clk_rcg2_set_rate_and_parent()
303 static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) clk_rcg2_shared_force_enable() argument
305 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_shared_force_enable()
306 const char *name = clk_hw_get_name(hw); clk_rcg2_shared_force_enable()
317 ret = clk_rcg2_is_enabled(hw); clk_rcg2_shared_force_enable()
326 ret = __clk_rcg2_set_rate(hw, rate); clk_rcg2_shared_force_enable()
335 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, clk_rcg2_shared_set_rate() argument
338 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_shared_set_rate()
343 if (!__clk_is_enabled(hw->clk)) clk_rcg2_shared_set_rate()
346 return clk_rcg2_shared_force_enable(hw, rcg->current_freq); clk_rcg2_shared_set_rate()
350 clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) clk_rcg2_shared_recalc_rate() argument
352 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_shared_recalc_rate()
354 return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate); clk_rcg2_shared_recalc_rate()
357 static int clk_rcg2_shared_enable(struct clk_hw *hw) clk_rcg2_shared_enable() argument
359 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_shared_enable()
361 return clk_rcg2_shared_force_enable(hw, rcg->current_freq); clk_rcg2_shared_enable()
364 static void clk_rcg2_shared_disable(struct clk_hw *hw) clk_rcg2_shared_disable() argument
366 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_rcg2_shared_disable()
369 clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0); clk_rcg2_shared_disable()
409 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate, clk_edp_pixel_set_rate() argument
412 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_edp_pixel_set_rate()
448 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, clk_edp_pixel_set_rate_and_parent() argument
452 return clk_edp_pixel_set_rate(hw, rate, parent_rate); clk_edp_pixel_set_rate_and_parent()
455 static int clk_edp_pixel_determine_rate(struct clk_hw *hw, clk_edp_pixel_determine_rate() argument
458 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_edp_pixel_determine_rate()
465 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); clk_edp_pixel_determine_rate()
468 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); clk_edp_pixel_determine_rate()
509 static int clk_byte_determine_rate(struct clk_hw *hw, clk_byte_determine_rate() argument
512 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_byte_determine_rate()
514 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); clk_byte_determine_rate()
522 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); clk_byte_determine_rate()
533 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate, clk_byte_set_rate() argument
536 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_byte_set_rate()
549 static int clk_byte_set_rate_and_parent(struct clk_hw *hw, clk_byte_set_rate_and_parent() argument
553 return clk_byte_set_rate(hw, rate, parent_rate); clk_byte_set_rate_and_parent()
567 static int clk_byte2_determine_rate(struct clk_hw *hw, clk_byte2_determine_rate() argument
570 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_byte2_determine_rate()
590 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate, clk_byte2_set_rate() argument
593 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_byte2_set_rate()
596 int i, num_parents = clk_hw_get_num_parents(hw); clk_byte2_set_rate()
619 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw, clk_byte2_set_rate_and_parent() argument
623 return clk_byte2_set_rate(hw, rate, parent_rate); clk_byte2_set_rate_and_parent()
645 static int clk_pixel_determine_rate(struct clk_hw *hw, clk_pixel_determine_rate() argument
668 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, clk_pixel_set_rate() argument
671 struct clk_rcg2 *rcg = to_clk_rcg2(hw); clk_pixel_set_rate()
678 int i, num_parents = clk_hw_get_num_parents(hw); clk_pixel_set_rate()
710 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, clk_pixel_set_rate_and_parent() argument
713 return clk_pixel_set_rate(hw, rate, parent_rate); clk_pixel_set_rate_and_parent()
H A Dclk-regmap-divider.c21 static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw) to_clk_regmap_div() argument
23 return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr); to_clk_regmap_div()
26 static long div_round_rate(struct clk_hw *hw, unsigned long rate, div_round_rate() argument
29 struct clk_regmap_div *divider = to_clk_regmap_div(hw); div_round_rate()
31 return divider_round_rate(hw, rate, prate, NULL, divider->width, div_round_rate()
35 static int div_set_rate(struct clk_hw *hw, unsigned long rate, div_set_rate() argument
38 struct clk_regmap_div *divider = to_clk_regmap_div(hw); div_set_rate()
50 static unsigned long div_recalc_rate(struct clk_hw *hw, div_recalc_rate() argument
53 struct clk_regmap_div *divider = to_clk_regmap_div(hw); div_recalc_rate()
61 return divider_recalc_rate(hw, parent_rate, div, NULL, div_recalc_rate()
/linux-4.4.14/drivers/staging/wlan-ng/
H A Dprism2sta.c245 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_txframe() local
253 return hfa384x_drvr_txframe(hw, skb, p80211_hdr, p80211_wep); prism2sta_txframe()
282 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_mlmerequest() local
372 qualmsg->link.data = le16_to_cpu(hw->qual.CQ_currBSS); prism2sta_mlmerequest()
373 qualmsg->level.data = le16_to_cpu(hw->qual.ASL_currBSS); prism2sta_mlmerequest()
374 qualmsg->noise.data = le16_to_cpu(hw->qual.ANL_currFC); prism2sta_mlmerequest()
375 qualmsg->txrate.data = hw->txrate; prism2sta_mlmerequest()
412 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_ifstate() local
428 result = hfa384x_drvr_start(hw); prism2sta_ifstate()
442 hfa384x_cmd_initialize(hw); prism2sta_ifstate()
472 result = hfa384x_drvr_start(hw); prism2sta_ifstate()
490 hfa384x_drvr_stop(hw); prism2sta_ifstate()
501 hfa384x_drvr_stop(hw); prism2sta_ifstate()
506 hw->join_ap = 0; prism2sta_ifstate()
507 hw->join_retries = 60; prism2sta_ifstate()
541 hfa384x_drvr_stop(hw); prism2sta_ifstate()
586 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_getcardinfo() local
593 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_NICIDENTITY, prism2sta_getcardinfo()
594 &hw->ident_nic, prism2sta_getcardinfo()
602 hw->ident_nic.id = le16_to_cpu(hw->ident_nic.id); prism2sta_getcardinfo()
603 hw->ident_nic.variant = le16_to_cpu(hw->ident_nic.variant); prism2sta_getcardinfo()
604 hw->ident_nic.major = le16_to_cpu(hw->ident_nic.major); prism2sta_getcardinfo()
605 hw->ident_nic.minor = le16_to_cpu(hw->ident_nic.minor); prism2sta_getcardinfo()
608 hw->ident_nic.id, hw->ident_nic.major, prism2sta_getcardinfo()
609 hw->ident_nic.minor, hw->ident_nic.variant); prism2sta_getcardinfo()
612 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_PRIIDENTITY, prism2sta_getcardinfo()
613 &hw->ident_pri_fw, prism2sta_getcardinfo()
621 hw->ident_pri_fw.id = le16_to_cpu(hw->ident_pri_fw.id); prism2sta_getcardinfo()
622 hw->ident_pri_fw.variant = le16_to_cpu(hw->ident_pri_fw.variant); prism2sta_getcardinfo()
623 hw->ident_pri_fw.major = le16_to_cpu(hw->ident_pri_fw.major); prism2sta_getcardinfo()
624 hw->ident_pri_fw.minor = le16_to_cpu(hw->ident_pri_fw.minor); prism2sta_getcardinfo()
627 hw->ident_pri_fw.id, hw->ident_pri_fw.major, prism2sta_getcardinfo()
628 hw->ident_pri_fw.minor, hw->ident_pri_fw.variant); prism2sta_getcardinfo()
631 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STAIDENTITY, prism2sta_getcardinfo()
632 &hw->ident_sta_fw, prism2sta_getcardinfo()
639 if (hw->ident_nic.id < 0x8000) { prism2sta_getcardinfo()
647 hw->ident_sta_fw.id = le16_to_cpu(hw->ident_sta_fw.id); prism2sta_getcardinfo()
648 hw->ident_sta_fw.variant = le16_to_cpu(hw->ident_sta_fw.variant); prism2sta_getcardinfo()
649 hw->ident_sta_fw.major = le16_to_cpu(hw->ident_sta_fw.major); prism2sta_getcardinfo()
650 hw->ident_sta_fw.minor = le16_to_cpu(hw->ident_sta_fw.minor); prism2sta_getcardinfo()
653 hw->mm_mods = hw->ident_sta_fw.variant & (BIT(14) | BIT(15)); prism2sta_getcardinfo()
654 hw->ident_sta_fw.variant &= ~((u16) (BIT(14) | BIT(15))); prism2sta_getcardinfo()
656 if (hw->ident_sta_fw.id == 0x1f) { prism2sta_getcardinfo()
659 hw->ident_sta_fw.id, hw->ident_sta_fw.major, prism2sta_getcardinfo()
660 hw->ident_sta_fw.minor, hw->ident_sta_fw.variant); prism2sta_getcardinfo()
664 hw->ident_sta_fw.id, hw->ident_sta_fw.major, prism2sta_getcardinfo()
665 hw->ident_sta_fw.minor, hw->ident_sta_fw.variant); prism2sta_getcardinfo()
671 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_MFISUPRANGE, prism2sta_getcardinfo()
672 &hw->cap_sup_mfi, prism2sta_getcardinfo()
682 hw->cap_sup_mfi.role = le16_to_cpu(hw->cap_sup_mfi.role); prism2sta_getcardinfo()
683 hw->cap_sup_mfi.id = le16_to_cpu(hw->cap_sup_mfi.id); prism2sta_getcardinfo()
684 hw->cap_sup_mfi.variant = le16_to_cpu(hw->cap_sup_mfi.variant); prism2sta_getcardinfo()
685 hw->cap_sup_mfi.bottom = le16_to_cpu(hw->cap_sup_mfi.bottom); prism2sta_getcardinfo()
686 hw->cap_sup_mfi.top = le16_to_cpu(hw->cap_sup_mfi.top); prism2sta_getcardinfo()
690 hw->cap_sup_mfi.role, hw->cap_sup_mfi.id, prism2sta_getcardinfo()
691 hw->cap_sup_mfi.variant, hw->cap_sup_mfi.bottom, prism2sta_getcardinfo()
692 hw->cap_sup_mfi.top); prism2sta_getcardinfo()
695 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_CFISUPRANGE, prism2sta_getcardinfo()
696 &hw->cap_sup_cfi, prism2sta_getcardinfo()
706 hw->cap_sup_cfi.role = le16_to_cpu(hw->cap_sup_cfi.role); prism2sta_getcardinfo()
707 hw->cap_sup_cfi.id = le16_to_cpu(hw->cap_sup_cfi.id); prism2sta_getcardinfo()
708 hw->cap_sup_cfi.variant = le16_to_cpu(hw->cap_sup_cfi.variant); prism2sta_getcardinfo()
709 hw->cap_sup_cfi.bottom = le16_to_cpu(hw->cap_sup_cfi.bottom); prism2sta_getcardinfo()
710 hw->cap_sup_cfi.top = le16_to_cpu(hw->cap_sup_cfi.top); prism2sta_getcardinfo()
714 hw->cap_sup_cfi.role, hw->cap_sup_cfi.id, prism2sta_getcardinfo()
715 hw->cap_sup_cfi.variant, hw->cap_sup_cfi.bottom, prism2sta_getcardinfo()
716 hw->cap_sup_cfi.top); prism2sta_getcardinfo()
719 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_PRISUPRANGE, prism2sta_getcardinfo()
720 &hw->cap_sup_pri, prism2sta_getcardinfo()
730 hw->cap_sup_pri.role = le16_to_cpu(hw->cap_sup_pri.role); prism2sta_getcardinfo()
731 hw->cap_sup_pri.id = le16_to_cpu(hw->cap_sup_pri.id); prism2sta_getcardinfo()
732 hw->cap_sup_pri.variant = le16_to_cpu(hw->cap_sup_pri.variant); prism2sta_getcardinfo()
733 hw->cap_sup_pri.bottom = le16_to_cpu(hw->cap_sup_pri.bottom); prism2sta_getcardinfo()
734 hw->cap_sup_pri.top = le16_to_cpu(hw->cap_sup_pri.top); prism2sta_getcardinfo()
738 hw->cap_sup_pri.role, hw->cap_sup_pri.id, prism2sta_getcardinfo()
739 hw->cap_sup_pri.variant, hw->cap_sup_pri.bottom, prism2sta_getcardinfo()
740 hw->cap_sup_pri.top); prism2sta_getcardinfo()
743 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STASUPRANGE, prism2sta_getcardinfo()
744 &hw->cap_sup_sta, prism2sta_getcardinfo()
754 hw->cap_sup_sta.role = le16_to_cpu(hw->cap_sup_sta.role); prism2sta_getcardinfo()
755 hw->cap_sup_sta.id = le16_to_cpu(hw->cap_sup_sta.id); prism2sta_getcardinfo()
756 hw->cap_sup_sta.variant = le16_to_cpu(hw->cap_sup_sta.variant); prism2sta_getcardinfo()
757 hw->cap_sup_sta.bottom = le16_to_cpu(hw->cap_sup_sta.bottom); prism2sta_getcardinfo()
758 hw->cap_sup_sta.top = le16_to_cpu(hw->cap_sup_sta.top); prism2sta_getcardinfo()
760 if (hw->cap_sup_sta.id == 0x04) { prism2sta_getcardinfo()
763 hw->cap_sup_sta.role, hw->cap_sup_sta.id, prism2sta_getcardinfo()
764 hw->cap_sup_sta.variant, hw->cap_sup_sta.bottom, prism2sta_getcardinfo()
765 hw->cap_sup_sta.top); prism2sta_getcardinfo()
769 hw->cap_sup_sta.role, hw->cap_sup_sta.id, prism2sta_getcardinfo()
770 hw->cap_sup_sta.variant, hw->cap_sup_sta.bottom, prism2sta_getcardinfo()
771 hw->cap_sup_sta.top); prism2sta_getcardinfo()
775 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_PRI_CFIACTRANGES, prism2sta_getcardinfo()
776 &hw->cap_act_pri_cfi, prism2sta_getcardinfo()
786 hw->cap_act_pri_cfi.role = le16_to_cpu(hw->cap_act_pri_cfi.role); prism2sta_getcardinfo()
787 hw->cap_act_pri_cfi.id = le16_to_cpu(hw->cap_act_pri_cfi.id); prism2sta_getcardinfo()
788 hw->cap_act_pri_cfi.variant = le16_to_cpu(hw->cap_act_pri_cfi.variant); prism2sta_getcardinfo()
789 hw->cap_act_pri_cfi.bottom = le16_to_cpu(hw->cap_act_pri_cfi.bottom); prism2sta_getcardinfo()
790 hw->cap_act_pri_cfi.top = le16_to_cpu(hw->cap_act_pri_cfi.top); prism2sta_getcardinfo()
794 hw->cap_act_pri_cfi.role, hw->cap_act_pri_cfi.id, prism2sta_getcardinfo()
795 hw->cap_act_pri_cfi.variant, hw->cap_act_pri_cfi.bottom, prism2sta_getcardinfo()
796 hw->cap_act_pri_cfi.top); prism2sta_getcardinfo()
799 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STA_CFIACTRANGES, prism2sta_getcardinfo()
800 &hw->cap_act_sta_cfi, prism2sta_getcardinfo()
810 hw->cap_act_sta_cfi.role = le16_to_cpu(hw->cap_act_sta_cfi.role); prism2sta_getcardinfo()
811 hw->cap_act_sta_cfi.id = le16_to_cpu(hw->cap_act_sta_cfi.id); prism2sta_getcardinfo()
812 hw->cap_act_sta_cfi.variant = le16_to_cpu(hw->cap_act_sta_cfi.variant); prism2sta_getcardinfo()
813 hw->cap_act_sta_cfi.bottom = le16_to_cpu(hw->cap_act_sta_cfi.bottom); prism2sta_getcardinfo()
814 hw->cap_act_sta_cfi.top = le16_to_cpu(hw->cap_act_sta_cfi.top); prism2sta_getcardinfo()
818 hw->cap_act_sta_cfi.role, hw->cap_act_sta_cfi.id, prism2sta_getcardinfo()
819 hw->cap_act_sta_cfi.variant, hw->cap_act_sta_cfi.bottom, prism2sta_getcardinfo()
820 hw->cap_act_sta_cfi.top); prism2sta_getcardinfo()
823 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STA_MFIACTRANGES, prism2sta_getcardinfo()
824 &hw->cap_act_sta_mfi, prism2sta_getcardinfo()
834 hw->cap_act_sta_mfi.role = le16_to_cpu(hw->cap_act_sta_mfi.role); prism2sta_getcardinfo()
835 hw->cap_act_sta_mfi.id = le16_to_cpu(hw->cap_act_sta_mfi.id); prism2sta_getcardinfo()
836 hw->cap_act_sta_mfi.variant = le16_to_cpu(hw->cap_act_sta_mfi.variant); prism2sta_getcardinfo()
837 hw->cap_act_sta_mfi.bottom = le16_to_cpu(hw->cap_act_sta_mfi.bottom); prism2sta_getcardinfo()
838 hw->cap_act_sta_mfi.top = le16_to_cpu(hw->cap_act_sta_mfi.top); prism2sta_getcardinfo()
842 hw->cap_act_sta_mfi.role, hw->cap_act_sta_mfi.id, prism2sta_getcardinfo()
843 hw->cap_act_sta_mfi.variant, hw->cap_act_sta_mfi.bottom, prism2sta_getcardinfo()
844 hw->cap_act_sta_mfi.top); prism2sta_getcardinfo()
847 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_NICSERIALNUMBER, prism2sta_getcardinfo()
858 result = hfa384x_drvr_getconfig(hw, HFA384x_RID_CNFOWNMACADDR, prism2sta_getcardinfo()
869 hfa384x_drvr_getconfig16(hw, HFA384x_RID_PRIVACYOPTIMP, &temp); prism2sta_getcardinfo()
874 hfa384x_drvr_getconfig16(hw, HFA384x_RID_CNFDBMADJUST, &temp); prism2sta_getcardinfo()
875 hw->dbmadjust = temp; prism2sta_getcardinfo()
878 if (HFA384x_FIRMWARE_VERSION(hw->ident_sta_fw.major, prism2sta_getcardinfo()
879 hw->ident_sta_fw.minor, prism2sta_getcardinfo()
880 hw->ident_sta_fw.variant) < prism2sta_getcardinfo()
914 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_globalsetup() local
917 return hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFMAXDATALEN, prism2sta_globalsetup()
924 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_setmulticast() local
929 if (hw->state != HFA384x_STATE_RUNNING) prism2sta_setmulticast()
938 hfa384x_drvr_setconfig16_async(hw, HFA384x_RID_PROMISCMODE, prism2sta_setmulticast()
988 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_tallies() local
1002 dst = (u32 *) &hw->tallies; prism2sta_inf_tallies()
1007 dst = (u32 *) &hw->tallies; prism2sta_inf_tallies()
1035 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_scanresults() local
1061 result = hfa384x_drvr_setconfig(hw, prism2sta_inf_scanresults()
1090 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_hostscanresults() local
1099 kfree(hw->scanresults); prism2sta_inf_hostscanresults()
1101 hw->scanresults = kmemdup(inf, sizeof(hfa384x_InfFrame_t), GFP_ATOMIC); prism2sta_inf_hostscanresults()
1107 hw->scanflag = nbss; prism2sta_inf_hostscanresults()
1108 wake_up_interruptible(&hw->cmdq); prism2sta_inf_hostscanresults()
1131 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_chinforesults() local
1134 hw->channel_info.results.scanchannels = prism2sta_inf_chinforesults()
1142 if (!(hw->channel_info.results.scanchannels & (1 << i))) prism2sta_inf_chinforesults()
1151 chinforesult = &hw->channel_info.results.result[chan]; prism2sta_inf_chinforesults()
1166 atomic_set(&hw->channel_info.done, 2); prism2sta_inf_chinforesults()
1168 hw->channel_info.count = n; prism2sta_inf_chinforesults()
1173 hfa384x_t *hw = container_of(data, struct hfa384x, link_bh); prism2sta_processing_defer() local
1174 wlandevice_t *wlandev = hw->wlandev; prism2sta_processing_defer()
1183 while ((skb = skb_dequeue(&hw->authq))) { prism2sta_processing_defer()
1191 if (hw->link_status == hw->link_status_new) prism2sta_processing_defer()
1194 hw->link_status = hw->link_status_new; prism2sta_processing_defer()
1196 switch (hw->link_status) { prism2sta_processing_defer()
1225 if (hw->join_ap == 1) prism2sta_processing_defer()
1226 hw->join_ap = 2; prism2sta_processing_defer()
1227 hw->join_retries = 60; prism2sta_processing_defer()
1238 result = hfa384x_drvr_getconfig(hw, prism2sta_processing_defer()
1249 result = hfa384x_drvr_getconfig(hw, prism2sta_processing_defer()
1263 result = hfa384x_drvr_getconfig16(hw, prism2sta_processing_defer()
1280 prism2sta_commsqual_defer(&hw->commsqual_bh); prism2sta_processing_defer()
1323 result = hfa384x_drvr_getconfig(hw, prism2sta_processing_defer()
1332 result = hfa384x_drvr_getconfig(hw, prism2sta_processing_defer()
1343 hw->link_status = HFA384x_LINK_CONNECTED; prism2sta_processing_defer()
1378 hw->link_status = HFA384x_LINK_CONNECTED; prism2sta_processing_defer()
1392 if (hw->join_ap && --hw->join_retries > 0) { prism2sta_processing_defer()
1395 joinreq = hw->joinreq; prism2sta_processing_defer()
1397 hfa384x_drvr_setconfig(hw, prism2sta_processing_defer()
1417 "unknown linkstatus=0x%02x\n", hw->link_status); prism2sta_processing_defer()
1421 wlandev->linkstatus = (hw->link_status == HFA384x_LINK_CONNECTED); prism2sta_processing_defer()
1444 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_linkstatus() local
1446 hw->link_status_new = le16_to_cpu(inf->info.linkstatus.linkstatus); prism2sta_inf_linkstatus()
1448 schedule_work(&hw->link_bh); prism2sta_inf_linkstatus()
1472 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_assocstatus() local
1492 for (i = 0; i < hw->authlist.cnt; i++) prism2sta_inf_assocstatus()
1493 if (ether_addr_equal(rec.sta_addr, hw->authlist.addr[i])) prism2sta_inf_assocstatus()
1496 if (i >= hw->authlist.cnt) { prism2sta_inf_assocstatus()
1501 hw->authlist.assoc[i] = prism2sta_inf_assocstatus()
1533 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_authreq() local
1540 skb_queue_tail(&hw->authq, skb); prism2sta_inf_authreq()
1541 schedule_work(&hw->link_bh); prism2sta_inf_authreq()
1548 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_authreq_defer() local
1566 switch (hw->accessmode) { prism2sta_inf_authreq_defer()
1574 for (i = 0; i < hw->authlist.cnt; i++) prism2sta_inf_authreq_defer()
1576 hw->authlist.addr[i])) { prism2sta_inf_authreq_defer()
1604 if (hw->allow.modify == 0) { prism2sta_inf_authreq_defer()
1605 cnt = hw->allow.cnt; prism2sta_inf_authreq_defer()
1606 addr = hw->allow.addr[0]; prism2sta_inf_authreq_defer()
1608 cnt = hw->allow.cnt1; prism2sta_inf_authreq_defer()
1609 addr = hw->allow.addr1[0]; prism2sta_inf_authreq_defer()
1632 if (hw->deny.modify == 0) { prism2sta_inf_authreq_defer()
1633 cnt = hw->deny.cnt; prism2sta_inf_authreq_defer()
1634 addr = hw->deny.addr[0]; prism2sta_inf_authreq_defer()
1636 cnt = hw->deny.cnt1; prism2sta_inf_authreq_defer()
1637 addr = hw->deny.addr1[0]; prism2sta_inf_authreq_defer()
1663 for (i = 0; i < hw->authlist.cnt; i++) prism2sta_inf_authreq_defer()
1665 hw->authlist.addr[i])) prism2sta_inf_authreq_defer()
1668 if (i >= hw->authlist.cnt) { prism2sta_inf_authreq_defer()
1669 if (hw->authlist.cnt >= WLAN_AUTH_MAX) { prism2sta_inf_authreq_defer()
1673 hw->authlist.addr[hw->authlist.cnt], prism2sta_inf_authreq_defer()
1675 hw->authlist.cnt++; prism2sta_inf_authreq_defer()
1690 result = hfa384x_drvr_setconfig(hw, HFA384x_RID_AUTHENTICATESTA, prism2sta_inf_authreq_defer()
1694 hw->authlist.cnt--; prism2sta_inf_authreq_defer()
1722 hfa384x_t *hw = (hfa384x_t *) wlandev->priv; prism2sta_inf_psusercnt() local
1724 hw->psusercount = le16_to_cpu(inf->info.psusercnt.usercnt); prism2sta_inf_psusercnt()
1894 * also allocates the priv/hw structures.
1903 hfa384x_t *hw = NULL; create_wlan() local
1907 hw = kzalloc(sizeof(hfa384x_t), GFP_KERNEL); create_wlan()
1909 if (!wlandev || !hw) { create_wlan()
1912 kfree(hw); create_wlan()
1919 wlandev->priv = hw; create_wlan()
1931 hw->dot11_desired_bss_type = 1; create_wlan()
1938 hfa384x_t *hw = container_of(data, struct hfa384x, commsqual_bh); prism2sta_commsqual_defer() local
1939 wlandevice_t *wlandev = hw->wlandev; prism2sta_commsqual_defer()
1946 if (hw->wlandev->hwremoved) prism2sta_commsqual_defer()
1958 hw, HFA384x_RID_DBMCOMMSQUALITY, prism2sta_commsqual_defer()
1959 &hw->qual, HFA384x_RID_DBMCOMMSQUALITY_LEN); prism2sta_commsqual_defer()
1967 le16_to_cpu(hw->qual.CQ_currBSS), prism2sta_commsqual_defer()
1968 le16_to_cpu(hw->qual.ASL_currBSS), prism2sta_commsqual_defer()
1969 le16_to_cpu(hw->qual.ANL_currFC)); prism2sta_commsqual_defer()
1985 hw->txrate = 10; prism2sta_commsqual_defer()
1988 hw->txrate = 20; prism2sta_commsqual_defer()
1991 hw->txrate = 55; prism2sta_commsqual_defer()
1994 hw->txrate = 110; prism2sta_commsqual_defer()
2001 result = hfa384x_drvr_getconfig(hw, prism2sta_commsqual_defer()
2010 result = hfa384x_drvr_getconfig(hw, prism2sta_commsqual_defer()
2022 mod_timer(&hw->commsqual_timer, jiffies + HZ); prism2sta_commsqual_defer()
2027 hfa384x_t *hw = (hfa384x_t *) data; prism2sta_commsqual_timer() local
2029 schedule_work(&hw->commsqual_bh); prism2sta_commsqual_timer()
H A Dprism2usb.c65 hfa384x_t *hw = NULL; prism2sta_probe_usb() local
75 hw = wlandev->priv; prism2sta_probe_usb()
83 /* Initialize the hw data */ prism2sta_probe_usb()
84 hfa384x_create(hw, dev); prism2sta_probe_usb()
85 hw->wlandev = wlandev; prism2sta_probe_usb()
94 result = hfa384x_corereset(hw, prism2sta_probe_usb()
127 kfree(hw); prism2sta_probe_usb()
146 hfa384x_t *hw = wlandev->priv; prism2sta_disconnect_usb() local
148 if (!hw) prism2sta_disconnect_usb()
151 spin_lock_irqsave(&hw->ctlxq.lock, flags); prism2sta_disconnect_usb()
154 list_splice_init(&hw->ctlxq.reapable, &cleanlist); prism2sta_disconnect_usb()
155 list_splice_init(&hw->ctlxq.completing, &cleanlist); prism2sta_disconnect_usb()
156 list_splice_init(&hw->ctlxq.pending, &cleanlist); prism2sta_disconnect_usb()
157 list_splice_init(&hw->ctlxq.active, &cleanlist); prism2sta_disconnect_usb()
159 spin_unlock_irqrestore(&hw->ctlxq.lock, flags); prism2sta_disconnect_usb()
167 del_singleshot_timer_sync(&hw->throttle); prism2sta_disconnect_usb()
168 del_singleshot_timer_sync(&hw->reqtimer); prism2sta_disconnect_usb()
169 del_singleshot_timer_sync(&hw->resptimer); prism2sta_disconnect_usb()
174 usb_kill_urb(&hw->rx_urb); prism2sta_disconnect_usb()
175 usb_kill_urb(&hw->tx_urb); prism2sta_disconnect_usb()
176 usb_kill_urb(&hw->ctlx_urb); prism2sta_disconnect_usb()
178 tasklet_kill(&hw->completion_bh); prism2sta_disconnect_usb()
179 tasklet_kill(&hw->reaper_bh); prism2sta_disconnect_usb()
213 usb_put_dev(hw->usb); prism2sta_disconnect_usb()
215 hfa384x_destroy(hw); prism2sta_disconnect_usb()
216 kfree(hw); prism2sta_disconnect_usb()
229 hfa384x_t *hw = NULL; prism2sta_suspend() local
236 hw = wlandev->priv; prism2sta_suspend()
237 if (!hw) prism2sta_suspend()
242 usb_kill_urb(&hw->rx_urb); prism2sta_suspend()
243 usb_kill_urb(&hw->tx_urb); prism2sta_suspend()
244 usb_kill_urb(&hw->ctlx_urb); prism2sta_suspend()
252 hfa384x_t *hw = NULL; prism2sta_resume() local
259 hw = wlandev->priv; prism2sta_resume()
260 if (!hw) prism2sta_resume()
265 result = hfa384x_corereset(hw, prism2sta_resume()
270 hfa384x_destroy(hw); prism2sta_resume()
273 kfree(hw); prism2sta_resume()
/linux-4.4.14/drivers/net/ethernet/intel/igbvf/
H A Dmbx.c31 * @hw: pointer to the HW structure
35 static s32 e1000_poll_for_msg(struct e1000_hw *hw) e1000_poll_for_msg() argument
37 struct e1000_mbx_info *mbx = &hw->mbx; e1000_poll_for_msg()
43 while (countdown && mbx->ops.check_for_msg(hw)) { e1000_poll_for_msg()
57 * @hw: pointer to the HW structure
61 static s32 e1000_poll_for_ack(struct e1000_hw *hw) e1000_poll_for_ack() argument
63 struct e1000_mbx_info *mbx = &hw->mbx; e1000_poll_for_ack()
69 while (countdown && mbx->ops.check_for_ack(hw)) { e1000_poll_for_ack()
83 * @hw: pointer to the HW structure
90 static s32 e1000_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size) e1000_read_posted_mbx() argument
92 struct e1000_mbx_info *mbx = &hw->mbx; e1000_read_posted_mbx()
98 ret_val = e1000_poll_for_msg(hw); e1000_read_posted_mbx()
102 ret_val = mbx->ops.read(hw, msg, size); e1000_read_posted_mbx()
109 * @hw: pointer to the HW structure
116 static s32 e1000_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size) e1000_write_posted_mbx() argument
118 struct e1000_mbx_info *mbx = &hw->mbx; e1000_write_posted_mbx()
126 ret_val = mbx->ops.write(hw, msg, size); e1000_write_posted_mbx()
130 ret_val = e1000_poll_for_ack(hw); e1000_write_posted_mbx()
137 * @hw: pointer to the HW structure
142 static u32 e1000_read_v2p_mailbox(struct e1000_hw *hw) e1000_read_v2p_mailbox() argument
146 v2p_mailbox |= hw->dev_spec.vf.v2p_mailbox; e1000_read_v2p_mailbox()
147 hw->dev_spec.vf.v2p_mailbox |= v2p_mailbox & E1000_V2PMAILBOX_R2C_BITS; e1000_read_v2p_mailbox()
154 * @hw: pointer to the HW structure
160 static s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask) e1000_check_for_bit_vf() argument
162 u32 v2p_mailbox = e1000_read_v2p_mailbox(hw); e1000_check_for_bit_vf()
168 hw->dev_spec.vf.v2p_mailbox &= ~mask; e1000_check_for_bit_vf()
175 * @hw: pointer to the HW structure
179 static s32 e1000_check_for_msg_vf(struct e1000_hw *hw) e1000_check_for_msg_vf() argument
183 if (!e1000_check_for_bit_vf(hw, E1000_V2PMAILBOX_PFSTS)) { e1000_check_for_msg_vf()
185 hw->mbx.stats.reqs++; e1000_check_for_msg_vf()
193 * @hw: pointer to the HW structure
197 static s32 e1000_check_for_ack_vf(struct e1000_hw *hw) e1000_check_for_ack_vf() argument
201 if (!e1000_check_for_bit_vf(hw, E1000_V2PMAILBOX_PFACK)) { e1000_check_for_ack_vf()
203 hw->mbx.stats.acks++; e1000_check_for_ack_vf()
211 * @hw: pointer to the HW structure
215 static s32 e1000_check_for_rst_vf(struct e1000_hw *hw) e1000_check_for_rst_vf() argument
219 if (!e1000_check_for_bit_vf(hw, (E1000_V2PMAILBOX_RSTD | e1000_check_for_rst_vf()
222 hw->mbx.stats.rsts++; e1000_check_for_rst_vf()
230 * @hw: pointer to the HW structure
234 static s32 e1000_obtain_mbx_lock_vf(struct e1000_hw *hw) e1000_obtain_mbx_lock_vf() argument
242 if (e1000_read_v2p_mailbox(hw) & E1000_V2PMAILBOX_VFU) e1000_obtain_mbx_lock_vf()
250 * @hw: pointer to the HW structure
256 static s32 e1000_write_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size) e1000_write_mbx_vf() argument
262 err = e1000_obtain_mbx_lock_vf(hw); e1000_write_mbx_vf()
267 e1000_check_for_ack_vf(hw); e1000_write_mbx_vf()
268 e1000_check_for_msg_vf(hw); e1000_write_mbx_vf()
275 hw->mbx.stats.msgs_tx++; e1000_write_mbx_vf()
286 * @hw: pointer to the HW structure
292 static s32 e1000_read_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size) e1000_read_mbx_vf() argument
298 err = e1000_obtain_mbx_lock_vf(hw); e1000_read_mbx_vf()
310 hw->mbx.stats.msgs_rx++; e1000_read_mbx_vf()
318 * @hw: pointer to the HW structure
320 * Initializes the hw->mbx struct to correct values for VF mailbox
322 s32 e1000_init_mbx_params_vf(struct e1000_hw *hw) e1000_init_mbx_params_vf() argument
324 struct e1000_mbx_info *mbx = &hw->mbx; e1000_init_mbx_params_vf()
/linux-4.4.14/drivers/clk/st/
H A Dclk-flexgen.c19 struct clk_hw hw; member in struct:flexgen
33 #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
35 static int flexgen_enable(struct clk_hw *hw) flexgen_enable() argument
37 struct flexgen *flexgen = to_flexgen(hw); flexgen_enable()
38 struct clk_hw *pgate_hw = &flexgen->pgate.hw; flexgen_enable()
39 struct clk_hw *fgate_hw = &flexgen->fgate.hw; flexgen_enable()
41 __clk_hw_set_clk(pgate_hw, hw); flexgen_enable()
42 __clk_hw_set_clk(fgate_hw, hw); flexgen_enable()
48 pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); flexgen_enable()
52 static void flexgen_disable(struct clk_hw *hw) flexgen_disable() argument
54 struct flexgen *flexgen = to_flexgen(hw); flexgen_disable()
55 struct clk_hw *fgate_hw = &flexgen->fgate.hw; flexgen_disable()
58 __clk_hw_set_clk(fgate_hw, hw); flexgen_disable()
62 pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw)); flexgen_disable()
65 static int flexgen_is_enabled(struct clk_hw *hw) flexgen_is_enabled() argument
67 struct flexgen *flexgen = to_flexgen(hw); flexgen_is_enabled()
68 struct clk_hw *fgate_hw = &flexgen->fgate.hw; flexgen_is_enabled()
70 __clk_hw_set_clk(fgate_hw, hw); flexgen_is_enabled()
78 static u8 flexgen_get_parent(struct clk_hw *hw) flexgen_get_parent() argument
80 struct flexgen *flexgen = to_flexgen(hw); flexgen_get_parent()
81 struct clk_hw *mux_hw = &flexgen->mux.hw; flexgen_get_parent()
83 __clk_hw_set_clk(mux_hw, hw); flexgen_get_parent()
88 static int flexgen_set_parent(struct clk_hw *hw, u8 index) flexgen_set_parent() argument
90 struct flexgen *flexgen = to_flexgen(hw); flexgen_set_parent()
91 struct clk_hw *mux_hw = &flexgen->mux.hw; flexgen_set_parent()
93 __clk_hw_set_clk(mux_hw, hw); flexgen_set_parent()
104 static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate, flexgen_round_rate() argument
112 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { flexgen_round_rate()
120 static unsigned long flexgen_recalc_rate(struct clk_hw *hw, flexgen_recalc_rate() argument
123 struct flexgen *flexgen = to_flexgen(hw); flexgen_recalc_rate()
124 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; flexgen_recalc_rate()
125 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; flexgen_recalc_rate()
128 __clk_hw_set_clk(pdiv_hw, hw); flexgen_recalc_rate()
129 __clk_hw_set_clk(fdiv_hw, hw); flexgen_recalc_rate()
136 static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate, flexgen_set_rate() argument
139 struct flexgen *flexgen = to_flexgen(hw); flexgen_set_rate()
140 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; flexgen_set_rate()
141 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; flexgen_set_rate()
145 __clk_hw_set_clk(pdiv_hw, hw); flexgen_set_rate()
146 __clk_hw_set_clk(fdiv_hw, hw); flexgen_set_rate()
230 fgxbar->hw.init = &init; clk_register_flexgen()
232 clk = clk_register(NULL, &fgxbar->hw); clk_register_flexgen()
/linux-4.4.14/drivers/misc/
H A Dhpilo.c67 static int fifo_enqueue(struct ilo_hwinfo *hw, char *fifobar, int entry) fifo_enqueue() argument
73 spin_lock_irqsave(&hw->fifo_lock, flags); fifo_enqueue()
81 spin_unlock_irqrestore(&hw->fifo_lock, flags); fifo_enqueue()
86 static int fifo_dequeue(struct ilo_hwinfo *hw, char *fifobar, int *entry) fifo_dequeue() argument
93 spin_lock_irqsave(&hw->fifo_lock, flags); fifo_dequeue()
104 spin_unlock_irqrestore(&hw->fifo_lock, flags); fifo_dequeue()
109 static int fifo_check_recv(struct ilo_hwinfo *hw, char *fifobar) fifo_check_recv() argument
116 spin_lock_irqsave(&hw->fifo_lock, flags); fifo_check_recv()
120 spin_unlock_irqrestore(&hw->fifo_lock, flags); fifo_check_recv()
125 static int ilo_pkt_enqueue(struct ilo_hwinfo *hw, struct ccb *ccb, ilo_pkt_enqueue() argument
137 return fifo_enqueue(hw, fifobar, entry); ilo_pkt_enqueue()
140 static int ilo_pkt_dequeue(struct ilo_hwinfo *hw, struct ccb *ccb, ilo_pkt_dequeue() argument
155 ret = fifo_dequeue(hw, fifobar, &entry); ilo_pkt_dequeue()
169 static int ilo_pkt_recv(struct ilo_hwinfo *hw, struct ccb *ccb) ilo_pkt_recv() argument
173 return fifo_check_recv(hw, fifobar); ilo_pkt_recv()
232 /* complicated dance to tell the hw we are stopping */ ilo_ccb_close()
251 /* clear the hw ccb */ ilo_ccb_close()
258 static int ilo_ccb_setup(struct ilo_hwinfo *hw, struct ccb_data *data, int slot) ilo_ccb_setup() argument
271 data->dma_va = pci_alloc_consistent(hw->ilo_dev, data->dma_size, ilo_ccb_setup()
317 driver_ccb->ccb_u5.db_base = hw->db_vaddr + (slot << L2_DB_SIZE); ilo_ccb_setup()
318 ilo_ccb->ccb_u5.db_base = NULL; /* hw ccb's doorbell is not used */ ilo_ccb_setup()
323 static void ilo_ccb_open(struct ilo_hwinfo *hw, struct ccb_data *data, int slot) ilo_ccb_open() argument
330 (hw->ram_vaddr + (slot * ILOHW_CCB_SZ)); ilo_ccb_open()
336 ilo_pkt_enqueue(hw, driver_ccb, SENDQ, pkt_id, pkt_sz); ilo_ccb_open()
342 ilo_pkt_enqueue(hw, driver_ccb, RECVQ, pkt_id, pkt_sz); ilo_ccb_open()
348 static int ilo_ccb_verify(struct ilo_hwinfo *hw, struct ccb_data *data) ilo_ccb_verify() argument
355 if (ilo_pkt_dequeue(hw, driver_ccb, SENDQ, &pkt_id, NULL, NULL)) ilo_ccb_verify()
361 dev_err(&hw->ilo_dev->dev, "Open could not dequeue a packet\n"); ilo_ccb_verify()
365 ilo_pkt_enqueue(hw, driver_ccb, SENDQ, pkt_id, 0); ilo_ccb_verify()
382 static inline int get_device_outbound(struct ilo_hwinfo *hw) get_device_outbound() argument
384 return ioread32(&hw->mmio_vaddr[DB_OUT]); get_device_outbound()
392 static inline int is_device_reset(struct ilo_hwinfo *hw) is_device_reset() argument
395 return is_db_reset(get_device_outbound(hw)); is_device_reset()
398 static inline void clear_pending_db(struct ilo_hwinfo *hw, int clr) clear_pending_db() argument
400 iowrite32(clr, &hw->mmio_vaddr[DB_OUT]); clear_pending_db()
403 static inline void clear_device(struct ilo_hwinfo *hw) clear_device() argument
406 clear_pending_db(hw, -1); clear_device()
409 static inline void ilo_enable_interrupts(struct ilo_hwinfo *hw) ilo_enable_interrupts() argument
411 iowrite8(ioread8(&hw->mmio_vaddr[DB_IRQ]) | 1, &hw->mmio_vaddr[DB_IRQ]); ilo_enable_interrupts()
414 static inline void ilo_disable_interrupts(struct ilo_hwinfo *hw) ilo_disable_interrupts() argument
416 iowrite8(ioread8(&hw->mmio_vaddr[DB_IRQ]) & ~1, ilo_disable_interrupts()
417 &hw->mmio_vaddr[DB_IRQ]); ilo_disable_interrupts()
420 static void ilo_set_reset(struct ilo_hwinfo *hw) ilo_set_reset() argument
429 if (!hw->ccb_alloc[slot]) ilo_set_reset()
431 set_channel_reset(&hw->ccb_alloc[slot]->driver_ccb); ilo_set_reset()
441 struct ilo_hwinfo *hw = data->ilo_hw; ilo_read() local
462 found = ilo_pkt_dequeue(hw, driver_ccb, RECVQ, &pkt_id, ilo_read()
480 ilo_pkt_enqueue(hw, driver_ccb, RECVQ, pkt_id, desc_mem_sz(1)); ilo_read()
491 struct ilo_hwinfo *hw = data->ilo_hw; ilo_write() local
498 if (!ilo_pkt_dequeue(hw, driver_ccb, SENDQ, &pkt_id, &pkt_len, &pkt)) ilo_write()
511 ilo_pkt_enqueue(hw, driver_ccb, SENDQ, pkt_id, len); ilo_write()
536 struct ilo_hwinfo *hw; ilo_close() local
540 hw = container_of(ip->i_cdev, struct ilo_hwinfo, cdev); ilo_close()
542 spin_lock(&hw->open_lock); ilo_close()
544 if (hw->ccb_alloc[slot]->ccb_cnt == 1) { ilo_close()
548 spin_lock_irqsave(&hw->alloc_lock, flags); ilo_close()
549 hw->ccb_alloc[slot] = NULL; ilo_close()
550 spin_unlock_irqrestore(&hw->alloc_lock, flags); ilo_close()
552 ilo_ccb_close(hw->ilo_dev, data); ilo_close()
556 hw->ccb_alloc[slot]->ccb_cnt--; ilo_close()
558 spin_unlock(&hw->open_lock); ilo_close()
567 struct ilo_hwinfo *hw; ilo_open() local
571 hw = container_of(ip->i_cdev, struct ilo_hwinfo, cdev); ilo_open()
578 spin_lock(&hw->open_lock); ilo_open()
580 /* each fd private_data holds sw/hw view of ccb */ ilo_open()
581 if (hw->ccb_alloc[slot] == NULL) { ilo_open()
583 error = ilo_ccb_setup(hw, data, slot); ilo_open()
591 data->ilo_hw = hw; ilo_open()
594 /* write the ccb to hw */ ilo_open()
595 spin_lock_irqsave(&hw->alloc_lock, flags); ilo_open()
596 ilo_ccb_open(hw, data, slot); ilo_open()
597 hw->ccb_alloc[slot] = data; ilo_open()
598 spin_unlock_irqrestore(&hw->alloc_lock, flags); ilo_open()
601 error = ilo_ccb_verify(hw, data); ilo_open()
604 spin_lock_irqsave(&hw->alloc_lock, flags); ilo_open()
605 hw->ccb_alloc[slot] = NULL; ilo_open()
606 spin_unlock_irqrestore(&hw->alloc_lock, flags); ilo_open()
608 ilo_ccb_close(hw->ilo_dev, data); ilo_open()
616 if (fp->f_flags & O_EXCL || hw->ccb_alloc[slot]->ccb_excl) { ilo_open()
624 hw->ccb_alloc[slot]->ccb_cnt++; ilo_open()
629 spin_unlock(&hw->open_lock); ilo_open()
632 fp->private_data = hw->ccb_alloc[slot]; ilo_open()
649 struct ilo_hwinfo *hw = data; ilo_isr() local
652 spin_lock(&hw->alloc_lock); ilo_isr()
655 pending = get_device_outbound(hw); ilo_isr()
657 spin_unlock(&hw->alloc_lock); ilo_isr()
664 ilo_set_reset(hw); ilo_isr()
668 if (!hw->ccb_alloc[i]) ilo_isr()
671 wake_up_interruptible(&hw->ccb_alloc[i]->ccb_waitq); ilo_isr()
675 clear_pending_db(hw, pending); ilo_isr()
677 spin_unlock(&hw->alloc_lock); ilo_isr()
682 static void ilo_unmap_device(struct pci_dev *pdev, struct ilo_hwinfo *hw) ilo_unmap_device() argument
684 pci_iounmap(pdev, hw->db_vaddr); ilo_unmap_device()
685 pci_iounmap(pdev, hw->ram_vaddr); ilo_unmap_device()
686 pci_iounmap(pdev, hw->mmio_vaddr); ilo_unmap_device()
689 static int ilo_map_device(struct pci_dev *pdev, struct ilo_hwinfo *hw) ilo_map_device() argument
694 hw->mmio_vaddr = pci_iomap(pdev, 1, 0); ilo_map_device()
695 if (hw->mmio_vaddr == NULL) { ilo_map_device()
701 hw->ram_vaddr = pci_iomap(pdev, 2, max_ccb * ILOHW_CCB_SZ); ilo_map_device()
702 if (hw->ram_vaddr == NULL) { ilo_map_device()
708 hw->db_vaddr = pci_iomap(pdev, 3, max_ccb * ONE_DB_SIZE); ilo_map_device()
709 if (hw->db_vaddr == NULL) { ilo_map_device()
716 pci_iounmap(pdev, hw->ram_vaddr); ilo_map_device()
718 pci_iounmap(pdev, hw->mmio_vaddr); ilo_map_device()
/linux-4.4.14/drivers/clk/mediatek/
H A Dclk-gate.c26 static int mtk_cg_bit_is_cleared(struct clk_hw *hw) mtk_cg_bit_is_cleared() argument
28 struct mtk_clk_gate *cg = to_clk_gate(hw); mtk_cg_bit_is_cleared()
38 static int mtk_cg_bit_is_set(struct clk_hw *hw) mtk_cg_bit_is_set() argument
40 struct mtk_clk_gate *cg = to_clk_gate(hw); mtk_cg_bit_is_set()
50 static void mtk_cg_set_bit(struct clk_hw *hw) mtk_cg_set_bit() argument
52 struct mtk_clk_gate *cg = to_clk_gate(hw); mtk_cg_set_bit()
57 static void mtk_cg_clr_bit(struct clk_hw *hw) mtk_cg_clr_bit() argument
59 struct mtk_clk_gate *cg = to_clk_gate(hw); mtk_cg_clr_bit()
64 static int mtk_cg_enable(struct clk_hw *hw) mtk_cg_enable() argument
66 mtk_cg_clr_bit(hw); mtk_cg_enable()
71 static void mtk_cg_disable(struct clk_hw *hw) mtk_cg_disable() argument
73 mtk_cg_set_bit(hw); mtk_cg_disable()
76 static int mtk_cg_enable_inv(struct clk_hw *hw) mtk_cg_enable_inv() argument
78 mtk_cg_set_bit(hw); mtk_cg_enable_inv()
83 static void mtk_cg_disable_inv(struct clk_hw *hw) mtk_cg_disable_inv() argument
85 mtk_cg_clr_bit(hw); mtk_cg_disable_inv()
130 cg->hw.init = &init; mtk_clk_register_gate()
132 clk = clk_register(NULL, &cg->hw); mtk_clk_register_gate()
H A Dclk-apmixed.c28 struct clk_hw hw; member in struct:mtk_ref2usb_tx
32 static inline struct mtk_ref2usb_tx *to_mtk_ref2usb_tx(struct clk_hw *hw) to_mtk_ref2usb_tx() argument
34 return container_of(hw, struct mtk_ref2usb_tx, hw); to_mtk_ref2usb_tx()
37 static int mtk_ref2usb_tx_is_prepared(struct clk_hw *hw) mtk_ref2usb_tx_is_prepared() argument
39 struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw); mtk_ref2usb_tx_is_prepared()
44 static int mtk_ref2usb_tx_prepare(struct clk_hw *hw) mtk_ref2usb_tx_prepare() argument
46 struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw); mtk_ref2usb_tx_prepare()
64 static void mtk_ref2usb_tx_unprepare(struct clk_hw *hw) mtk_ref2usb_tx_unprepare() argument
66 struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw); mtk_ref2usb_tx_unprepare()
92 tx->hw.init = &init; mtk_clk_register_ref2usb_tx()
99 clk = clk_register(NULL, &tx->hw); mtk_clk_register_ref2usb_tx()
/linux-4.4.14/drivers/clk/imx/
H A Dclk-busy.c39 static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw) to_clk_busy_divider() argument
41 struct clk_divider *div = container_of(hw, struct clk_divider, hw); to_clk_busy_divider()
46 static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw, clk_busy_divider_recalc_rate() argument
49 struct clk_busy_divider *busy = to_clk_busy_divider(hw); clk_busy_divider_recalc_rate()
51 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); clk_busy_divider_recalc_rate()
54 static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate, clk_busy_divider_round_rate() argument
57 struct clk_busy_divider *busy = to_clk_busy_divider(hw); clk_busy_divider_round_rate()
59 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); clk_busy_divider_round_rate()
62 static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate, clk_busy_divider_set_rate() argument
65 struct clk_busy_divider *busy = to_clk_busy_divider(hw); clk_busy_divider_set_rate()
68 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); clk_busy_divider_set_rate()
108 busy->div.hw.init = &init; imx_clk_busy_divider()
110 clk = clk_register(NULL, &busy->div.hw); imx_clk_busy_divider()
124 static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw) to_clk_busy_mux() argument
126 struct clk_mux *mux = container_of(hw, struct clk_mux, hw); to_clk_busy_mux()
131 static u8 clk_busy_mux_get_parent(struct clk_hw *hw) clk_busy_mux_get_parent() argument
133 struct clk_busy_mux *busy = to_clk_busy_mux(hw); clk_busy_mux_get_parent()
135 return busy->mux_ops->get_parent(&busy->mux.hw); clk_busy_mux_get_parent()
138 static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index) clk_busy_mux_set_parent() argument
140 struct clk_busy_mux *busy = to_clk_busy_mux(hw); clk_busy_mux_set_parent()
143 ret = busy->mux_ops->set_parent(&busy->mux.hw, index); clk_busy_mux_set_parent()
182 busy->mux.hw.init = &init; imx_clk_busy_mux()
184 clk = clk_register(NULL, &busy->mux.hw); imx_clk_busy_mux()
H A Dclk-cpu.c18 struct clk_hw hw; member in struct:clk_cpu
25 static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw) to_clk_cpu() argument
27 return container_of(hw, struct clk_cpu, hw); to_clk_cpu()
30 static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw, clk_cpu_recalc_rate() argument
33 struct clk_cpu *cpu = to_clk_cpu(hw); clk_cpu_recalc_rate()
38 static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate, clk_cpu_round_rate() argument
41 struct clk_cpu *cpu = to_clk_cpu(hw); clk_cpu_round_rate()
46 static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate, clk_cpu_set_rate() argument
49 struct clk_cpu *cpu = to_clk_cpu(hw); clk_cpu_set_rate()
101 cpu->hw.init = &init; imx_clk_cpu()
103 clk = clk_register(NULL, &cpu->hw); imx_clk_cpu()
/linux-4.4.14/drivers/net/ethernet/atheros/atlx/
H A Datl2.c87 struct atl2_hw *hw = &adapter->hw; atl2_sw_init() local
91 hw->vendor_id = pdev->vendor; atl2_sw_init()
92 hw->device_id = pdev->device; atl2_sw_init()
93 hw->subsystem_vendor_id = pdev->subsystem_vendor; atl2_sw_init()
94 hw->subsystem_id = pdev->subsystem_device; atl2_sw_init()
95 hw->revision_id = pdev->revision; atl2_sw_init()
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); atl2_sw_init()
104 hw->phy_configured = false; atl2_sw_init()
105 hw->preamble_len = 7; atl2_sw_init()
106 hw->ipgt = 0x60; atl2_sw_init()
107 hw->min_ifg = 0x50; atl2_sw_init()
108 hw->ipgr1 = 0x40; atl2_sw_init()
109 hw->ipgr2 = 0x60; atl2_sw_init()
110 hw->retry_buf = 2; atl2_sw_init()
111 hw->max_retry = 0xf; atl2_sw_init()
112 hw->lcol = 0x37; atl2_sw_init()
113 hw->jam_ipg = 7; atl2_sw_init()
114 hw->fc_rxd_hi = 0; atl2_sw_init()
115 hw->fc_rxd_lo = 0; atl2_sw_init()
116 hw->max_frame_size = adapter->netdev->mtu; atl2_sw_init()
137 struct atl2_hw *hw = &adapter->hw; atl2_set_multi() local
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); atl2_set_multi()
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); atl2_set_multi()
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); atl2_set_multi()
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); atl2_set_multi()
161 hash_value = atl2_hash_mc_addr(hw, ha->addr); netdev_for_each_mc_addr()
162 atl2_hash_set(hw, hash_value); netdev_for_each_mc_addr()
187 struct atl2_hw *hw = &adapter->hw; atl2_configure() local
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); atl2_configure()
194 value = (((u32)hw->mac_addr[2]) << 24) | atl2_configure()
195 (((u32)hw->mac_addr[3]) << 16) | atl2_configure()
196 (((u32)hw->mac_addr[4]) << 8) | atl2_configure()
197 (((u32)hw->mac_addr[5])); atl2_configure()
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); atl2_configure()
199 value = (((u32)hw->mac_addr[0]) << 8) | atl2_configure()
200 (((u32)hw->mac_addr[1])); atl2_configure()
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); atl2_configure()
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, atl2_configure()
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, atl2_configure()
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, atl2_configure()
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, atl2_configure()
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); atl2_configure()
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); atl2_configure()
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); atl2_configure()
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); atl2_configure()
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); atl2_configure()
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << atl2_configure()
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << atl2_configure()
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << atl2_configure()
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << atl2_configure()
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); atl2_configure()
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | atl2_configure()
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << atl2_configure()
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << atl2_configure()
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); atl2_configure()
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); atl2_configure()
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); atl2_configure()
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); atl2_configure()
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + atl2_configure()
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); atl2_configure()
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); atl2_configure()
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); atl2_configure()
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); atl2_configure()
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); atl2_configure()
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); atl2_configure()
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); atl2_configure()
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR); atl2_configure()
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); atl2_configure()
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); atl2_configure()
348 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); atl2_irq_enable()
349 ATL2_WRITE_FLUSH(&adapter->hw); atl2_irq_enable()
358 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); atl2_irq_disable()
359 ATL2_WRITE_FLUSH(&adapter->hw); atl2_irq_disable()
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); atl2_vlan_mode()
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); atl2_vlan_mode()
479 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); atl2_intr_rx()
573 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); atl2_check_for_link()
574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); atl2_check_for_link()
594 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); atl2_clear_phy_int()
606 struct atl2_hw *hw = &adapter->hw; atl2_intr() local
609 status = ATL2_READ_REG(hw, REG_ISR); atl2_intr()
618 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); atl2_intr()
623 ATL2_WRITE_REG(hw, REG_ISR, 0); atl2_intr()
624 ATL2_WRITE_REG(hw, REG_IMR, 0); atl2_intr()
625 ATL2_WRITE_FLUSH(hw); atl2_intr()
633 ATL2_WRITE_REG(hw, REG_ISR, 0); atl2_intr()
634 ATL2_WRITE_REG(hw, REG_IMR, 0); atl2_intr()
635 ATL2_WRITE_FLUSH(hw); atl2_intr()
655 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); atl2_intr()
717 err = atl2_init_hw(&adapter->hw); atl2_open()
742 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); atl2_open()
743 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, atl2_open()
754 atl2_reset_hw(&adapter->hw); atl2_open()
770 atl2_reset_hw(&adapter->hw); atl2_down()
908 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, atl2_xmit_frame()
926 struct atl2_hw *hw = &adapter->hw; atl2_change_mtu() local
932 if (hw->max_frame_size != new_mtu) { atl2_change_mtu()
934 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + atl2_change_mtu()
960 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); atl2_set_mac()
962 atl2_set_mac_addr(&adapter->hw); atl2_set_mac()
979 if (atl2_read_phy_reg(&adapter->hw, atl2_mii_ioctl()
990 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, atl2_mii_ioctl()
1044 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); atl2_watchdog()
1045 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); atl2_watchdog()
1063 struct atl2_hw *hw = &adapter->hw; atl2_phy_config() local
1067 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); atl2_phy_config()
1068 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | atl2_phy_config()
1082 err = atl2_init_hw(&adapter->hw); atl2_up()
1100 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); atl2_up()
1101 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | atl2_up()
1131 struct atl2_hw *hw = &adapter->hw; atl2_setup_mac_ctrl() local
1148 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << atl2_setup_mac_ctrl()
1162 value |= (((u32)(adapter->hw.retry_buf & atl2_setup_mac_ctrl()
1165 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); atl2_setup_mac_ctrl()
1170 struct atl2_hw *hw = &adapter->hw; atl2_check_link() local
1177 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); atl2_check_link()
1178 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); atl2_check_link()
1183 value = ATL2_READ_REG(hw, REG_MAC_CTRL); atl2_check_link()
1185 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); atl2_check_link()
1194 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); atl2_check_link()
1197 switch (hw->MediaType) { atl2_check_link()
1240 value = ATL2_READ_REG(hw, REG_MAC_CTRL); atl2_check_link()
1242 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); atl2_check_link()
1384 adapter->hw.back = adapter; atl2_probe()
1389 adapter->hw.mem_rang = (u32)mmio_len; atl2_probe()
1390 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); atl2_probe()
1391 if (!adapter->hw.hw_addr) { atl2_probe()
1419 atl2_phy_init(&adapter->hw); atl2_probe()
1424 if (atl2_reset_hw(&adapter->hw)) { atl2_probe()
1430 atl2_read_mac_addr(&adapter->hw); atl2_probe()
1431 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); atl2_probe()
1465 iounmap(adapter->hw.hw_addr); atl2_probe()
1503 atl2_force_ps(&adapter->hw); atl2_remove()
1505 iounmap(adapter->hw.hw_addr); atl2_remove()
1517 struct atl2_hw *hw = &adapter->hw; atl2_suspend() local
1539 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); atl2_suspend()
1540 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); atl2_suspend()
1547 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); atl2_suspend()
1562 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); atl2_suspend()
1569 ctrl |= (((u32)adapter->hw.preamble_len & atl2_suspend()
1571 ctrl |= (((u32)(adapter->hw.retry_buf & atl2_suspend()
1579 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); atl2_suspend()
1582 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); atl2_suspend()
1584 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); atl2_suspend()
1585 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); atl2_suspend()
1587 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); atl2_suspend()
1596 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); atl2_suspend()
1597 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); atl2_suspend()
1600 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); atl2_suspend()
1602 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); atl2_suspend()
1603 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); atl2_suspend()
1605 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); atl2_suspend()
1607 hw->phy_configured = false; /* re-init PHY when resume */ atl2_suspend()
1616 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); atl2_suspend()
1619 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); atl2_suspend()
1621 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); atl2_suspend()
1622 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); atl2_suspend()
1624 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); atl2_suspend()
1626 atl2_force_ps(hw); atl2_suspend()
1627 hw->phy_configured = false; /* re-init PHY when resume */ atl2_suspend()
1661 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ atl2_resume()
1666 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); atl2_resume()
1674 atl2_reset_hw(&adapter->hw); atl2_resume()
1730 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) atl2_read_pci_cfg() argument
1732 struct atl2_adapter *adapter = hw->back; atl2_read_pci_cfg()
1736 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) atl2_write_pci_cfg() argument
1738 struct atl2_adapter *adapter = hw->back; atl2_write_pci_cfg()
1746 struct atl2_hw *hw = &adapter->hw; atl2_get_settings() local
1757 ecmd->advertising |= hw->autoneg_advertised; atl2_get_settings()
1782 struct atl2_hw *hw = &adapter->hw; atl2_set_settings() local
1794 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; atl2_set_settings()
1795 hw->autoneg_advertised = MY_ADV_MASK; atl2_set_settings()
1798 hw->MediaType = MEDIA_TYPE_100M_FULL; atl2_set_settings()
1799 hw->autoneg_advertised = ADVERTISE_100_FULL; atl2_set_settings()
1802 hw->MediaType = MEDIA_TYPE_100M_HALF; atl2_set_settings()
1803 hw->autoneg_advertised = ADVERTISE_100_HALF; atl2_set_settings()
1806 hw->MediaType = MEDIA_TYPE_10M_FULL; atl2_set_settings()
1807 hw->autoneg_advertised = ADVERTISE_10_FULL; atl2_set_settings()
1810 hw->MediaType = MEDIA_TYPE_10M_HALF; atl2_set_settings()
1811 hw->autoneg_advertised = ADVERTISE_10_HALF; atl2_set_settings()
1816 ecmd->advertising = hw->autoneg_advertised | atl2_set_settings()
1828 atl2_reset_hw(&adapter->hw); atl2_set_settings()
1856 struct atl2_hw *hw = &adapter->hw; atl2_get_regs() local
1862 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; atl2_get_regs()
1864 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); atl2_get_regs()
1865 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); atl2_get_regs()
1866 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); atl2_get_regs()
1867 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); atl2_get_regs()
1868 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); atl2_get_regs()
1869 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); atl2_get_regs()
1870 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); atl2_get_regs()
1871 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); atl2_get_regs()
1872 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); atl2_get_regs()
1873 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); atl2_get_regs()
1874 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); atl2_get_regs()
1875 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); atl2_get_regs()
1876 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); atl2_get_regs()
1877 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); atl2_get_regs()
1878 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); atl2_get_regs()
1879 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); atl2_get_regs()
1880 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); atl2_get_regs()
1881 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); atl2_get_regs()
1882 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); atl2_get_regs()
1883 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); atl2_get_regs()
1884 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); atl2_get_regs()
1885 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); atl2_get_regs()
1886 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); atl2_get_regs()
1887 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); atl2_get_regs()
1888 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); atl2_get_regs()
1889 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); atl2_get_regs()
1890 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); atl2_get_regs()
1891 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); atl2_get_regs()
1892 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); atl2_get_regs()
1893 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); atl2_get_regs()
1894 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); atl2_get_regs()
1895 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); atl2_get_regs()
1896 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); atl2_get_regs()
1897 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); atl2_get_regs()
1898 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); atl2_get_regs()
1899 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); atl2_get_regs()
1900 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); atl2_get_regs()
1901 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); atl2_get_regs()
1902 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); atl2_get_regs()
1904 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); atl2_get_regs()
1906 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); atl2_get_regs()
1914 if (!atl2_check_eeprom_exist(&adapter->hw)) atl2_get_eeprom_len()
1924 struct atl2_hw *hw = &adapter->hw; atl2_get_eeprom() local
1933 if (atl2_check_eeprom_exist(hw)) atl2_get_eeprom()
1936 eeprom->magic = hw->vendor_id | (hw->device_id << 16); atl2_get_eeprom()
1947 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { atl2_get_eeprom()
1965 struct atl2_hw *hw = &adapter->hw; atl2_set_eeprom() local
1974 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) atl2_set_eeprom()
1990 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { atl2_set_eeprom()
2001 if (!atl2_read_eeprom(hw, last_dword * 4, atl2_set_eeprom()
2012 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { atl2_set_eeprom()
2109 * hw - Struct containing variables accessed by shared code
2112 static s32 atl2_reset_hw(struct atl2_hw *hw) atl2_reset_hw() argument
2119 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); atl2_reset_hw()
2125 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); atl2_reset_hw()
2132 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ atl2_reset_hw()
2133 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ atl2_reset_hw()
2140 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); atl2_reset_hw()
2146 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); atl2_reset_hw()
2173 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) atl2_spi_read() argument
2178 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); atl2_spi_read()
2179 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); atl2_spi_read()
2194 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); atl2_spi_read()
2198 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); atl2_spi_read()
2202 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); atl2_spi_read()
2210 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); atl2_spi_read()
2219 static int get_permanent_address(struct atl2_hw *hw) get_permanent_address() argument
2227 if (is_valid_ether_addr(hw->perm_mac_addr)) get_permanent_address()
2233 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ get_permanent_address()
2240 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { get_permanent_address()
2265 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); get_permanent_address()
2278 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { get_permanent_address()
2300 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); get_permanent_address()
2304 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); get_permanent_address()
2305 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); get_permanent_address()
2310 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); get_permanent_address()
2320 * hw - Struct containing variables accessed by shared code
2322 static s32 atl2_read_mac_addr(struct atl2_hw *hw) atl2_read_mac_addr() argument
2324 if (get_permanent_address(hw)) { atl2_read_mac_addr()
2327 hw->perm_mac_addr[0] = 0x00; atl2_read_mac_addr()
2328 hw->perm_mac_addr[1] = 0x13; atl2_read_mac_addr()
2329 hw->perm_mac_addr[2] = 0x74; atl2_read_mac_addr()
2330 hw->perm_mac_addr[3] = 0x00; atl2_read_mac_addr()
2331 hw->perm_mac_addr[4] = 0x5c; atl2_read_mac_addr()
2332 hw->perm_mac_addr[5] = 0x38; atl2_read_mac_addr()
2335 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); atl2_read_mac_addr()
2343 * hw - Struct containing variables accessed by shared code
2353 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) atl2_hash_mc_addr() argument
2370 * hw - Struct containing variables accessed by shared code
2373 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) atl2_hash_set() argument
2389 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); atl2_hash_set()
2393 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); atl2_hash_set()
2399 static void atl2_init_pcie(struct atl2_hw *hw) atl2_init_pcie() argument
2403 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); atl2_init_pcie()
2406 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); atl2_init_pcie()
2409 static void atl2_init_flash_opcode(struct atl2_hw *hw) atl2_init_flash_opcode() argument
2411 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) atl2_init_flash_opcode()
2412 hw->flash_vendor = 0; /* ATMEL */ atl2_init_flash_opcode()
2415 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, atl2_init_flash_opcode()
2416 flash_table[hw->flash_vendor].cmdPROGRAM); atl2_init_flash_opcode()
2417 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, atl2_init_flash_opcode()
2418 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); atl2_init_flash_opcode()
2419 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, atl2_init_flash_opcode()
2420 flash_table[hw->flash_vendor].cmdCHIP_ERASE); atl2_init_flash_opcode()
2421 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, atl2_init_flash_opcode()
2422 flash_table[hw->flash_vendor].cmdRDID); atl2_init_flash_opcode()
2423 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, atl2_init_flash_opcode()
2424 flash_table[hw->flash_vendor].cmdWREN); atl2_init_flash_opcode()
2425 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, atl2_init_flash_opcode()
2426 flash_table[hw->flash_vendor].cmdRDSR); atl2_init_flash_opcode()
2427 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, atl2_init_flash_opcode()
2428 flash_table[hw->flash_vendor].cmdWRSR); atl2_init_flash_opcode()
2429 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, atl2_init_flash_opcode()
2430 flash_table[hw->flash_vendor].cmdREAD); atl2_init_flash_opcode()
2436 * hw - Struct containing variables accessed by shared code
2442 static s32 atl2_init_hw(struct atl2_hw *hw) atl2_init_hw() argument
2446 atl2_init_pcie(hw); atl2_init_hw()
2450 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); atl2_init_hw()
2451 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); atl2_init_hw()
2453 atl2_init_flash_opcode(hw); atl2_init_hw()
2455 ret_val = atl2_phy_init(hw); atl2_init_hw()
2463 * hw - Struct containing variables accessed by shared code
2467 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, atl2_get_speed_and_duplex() argument
2474 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); atl2_get_speed_and_duplex()
2502 * hw - Struct containing variables accessed by shared code
2505 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) atl2_read_phy_reg() argument
2515 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); atl2_read_phy_reg()
2521 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); atl2_read_phy_reg()
2536 * hw - Struct containing variables accessed by shared code
2540 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) atl2_write_phy_reg() argument
2550 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); atl2_write_phy_reg()
2556 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); atl2_write_phy_reg()
2572 * hw - Struct containing variables accessed by shared code
2574 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) atl2_phy_setup_autoneg_adv() argument
2596 switch (hw->MediaType) { atl2_phy_setup_autoneg_adv()
2603 hw->autoneg_advertised = atl2_phy_setup_autoneg_adv()
2611 hw->autoneg_advertised = ADVERTISE_100_FULL; atl2_phy_setup_autoneg_adv()
2615 hw->autoneg_advertised = ADVERTISE_100_HALF; atl2_phy_setup_autoneg_adv()
2619 hw->autoneg_advertised = ADVERTISE_10_FULL; atl2_phy_setup_autoneg_adv()
2623 hw->autoneg_advertised = ADVERTISE_10_HALF; atl2_phy_setup_autoneg_adv()
2630 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; atl2_phy_setup_autoneg_adv()
2632 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); atl2_phy_setup_autoneg_adv()
2643 * hw - Struct containing variables accessed by shared code
2647 static s32 atl2_phy_commit(struct atl2_hw *hw) atl2_phy_commit() argument
2653 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); atl2_phy_commit()
2660 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); atl2_phy_commit()
2673 static s32 atl2_phy_init(struct atl2_hw *hw) atl2_phy_init() argument
2678 if (hw->phy_configured) atl2_phy_init()
2682 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); atl2_phy_init()
2683 ATL2_WRITE_FLUSH(hw); atl2_phy_init()
2687 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); atl2_phy_init()
2688 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); atl2_phy_init()
2693 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); atl2_phy_init()
2699 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); atl2_phy_init()
2704 ret_val = atl2_phy_setup_autoneg_adv(hw); atl2_phy_init()
2709 ret_val = atl2_phy_commit(hw); atl2_phy_init()
2713 hw->phy_configured = true; atl2_phy_init()
2718 static void atl2_set_mac_addr(struct atl2_hw *hw) atl2_set_mac_addr() argument
2724 value = (((u32)hw->mac_addr[2]) << 24) | atl2_set_mac_addr()
2725 (((u32)hw->mac_addr[3]) << 16) | atl2_set_mac_addr()
2726 (((u32)hw->mac_addr[4]) << 8) | atl2_set_mac_addr()
2727 (((u32)hw->mac_addr[5])); atl2_set_mac_addr()
2728 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); atl2_set_mac_addr()
2730 value = (((u32)hw->mac_addr[0]) << 8) | atl2_set_mac_addr()
2731 (((u32)hw->mac_addr[1])); atl2_set_mac_addr()
2732 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); atl2_set_mac_addr()
2739 static int atl2_check_eeprom_exist(struct atl2_hw *hw) atl2_check_eeprom_exist() argument
2743 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); atl2_check_eeprom_exist()
2746 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); atl2_check_eeprom_exist()
2748 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); atl2_check_eeprom_exist()
2753 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) atl2_write_eeprom() argument
2758 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) atl2_read_eeprom() argument
2766 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); atl2_read_eeprom()
2768 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); atl2_read_eeprom()
2772 Control = ATL2_READ_REG(hw, REG_VPD_CAP); atl2_read_eeprom()
2778 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); atl2_read_eeprom()
2784 static void atl2_force_ps(struct atl2_hw *hw) atl2_force_ps() argument
2788 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); atl2_force_ps()
2789 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); atl2_force_ps()
2790 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); atl2_force_ps()
2792 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); atl2_force_ps()
2793 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); atl2_force_ps()
2794 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); atl2_force_ps()
2795 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); atl2_force_ps()
3025 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; atl2_check_options()
3026 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > atl2_check_options()
3059 adapter->hw.flash_vendor = (u8) val; atl2_check_options()
3062 adapter->hw.flash_vendor = (u8)(opt.def); atl2_check_options()
3076 adapter->hw.MediaType = (u16) val; atl2_check_options()
3079 adapter->hw.MediaType = (u16)(opt.def); atl2_check_options()
/linux-4.4.14/drivers/clk/ux500/
H A Dclk-prcmu.c17 #define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
20 struct clk_hw hw; member in struct:clk_prcmu
29 static int clk_prcmu_prepare(struct clk_hw *hw) clk_prcmu_prepare() argument
32 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_prepare()
41 static void clk_prcmu_unprepare(struct clk_hw *hw) clk_prcmu_unprepare() argument
43 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_unprepare()
46 clk_hw_get_name(hw)); clk_prcmu_unprepare()
51 static int clk_prcmu_is_prepared(struct clk_hw *hw) clk_prcmu_is_prepared() argument
53 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_is_prepared()
57 static int clk_prcmu_enable(struct clk_hw *hw) clk_prcmu_enable() argument
59 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_enable()
64 static void clk_prcmu_disable(struct clk_hw *hw) clk_prcmu_disable() argument
66 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_disable()
70 static int clk_prcmu_is_enabled(struct clk_hw *hw) clk_prcmu_is_enabled() argument
72 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_is_enabled()
76 static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw, clk_prcmu_recalc_rate() argument
79 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_recalc_rate()
83 static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate, clk_prcmu_round_rate() argument
86 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_round_rate()
90 static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate, clk_prcmu_set_rate() argument
93 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_set_rate()
97 static int clk_prcmu_opp_prepare(struct clk_hw *hw) clk_prcmu_opp_prepare() argument
100 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_prepare()
104 (char *)clk_hw_get_name(hw), clk_prcmu_opp_prepare()
108 __func__, clk_hw_get_name(hw)); clk_prcmu_opp_prepare()
117 (char *)clk_hw_get_name(hw)); clk_prcmu_opp_prepare()
126 static void clk_prcmu_opp_unprepare(struct clk_hw *hw) clk_prcmu_opp_unprepare() argument
128 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_unprepare()
132 clk_hw_get_name(hw)); clk_prcmu_opp_unprepare()
138 (char *)clk_hw_get_name(hw)); clk_prcmu_opp_unprepare()
145 static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw) clk_prcmu_opp_volt_prepare() argument
148 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_volt_prepare()
154 __func__, clk_hw_get_name(hw)); clk_prcmu_opp_volt_prepare()
171 static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw) clk_prcmu_opp_volt_unprepare() argument
173 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_volt_unprepare()
177 clk_hw_get_name(hw)); clk_prcmu_opp_volt_unprepare()
280 clk->hw.init = &clk_prcmu_init; clk_reg_prcmu()
282 clk_reg = clk_register(NULL, &clk->hw); clk_reg_prcmu()
/linux-4.4.14/drivers/clk/at91/
H A Dclk-usb.c29 struct clk_hw hw; member in struct:at91sam9x5_clk_usb
33 #define to_at91sam9x5_clk_usb(hw) \
34 container_of(hw, struct at91sam9x5_clk_usb, hw)
37 struct clk_hw hw; member in struct:at91rm9200_clk_usb
42 #define to_at91rm9200_clk_usb(hw) \
43 container_of(hw, struct at91rm9200_clk_usb, hw)
45 static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw, at91sam9x5_clk_usb_recalc_rate() argument
50 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9x5_clk_usb_recalc_rate()
59 static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw, at91sam9x5_clk_usb_determine_rate() argument
69 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { at91sam9x5_clk_usb_determine_rate()
72 parent = clk_hw_get_parent_by_index(hw, i); at91sam9x5_clk_usb_determine_rate()
110 static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) at91sam9x5_clk_usb_set_parent() argument
113 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9x5_clk_usb_set_parent()
125 static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw) at91sam9x5_clk_usb_get_parent() argument
127 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9x5_clk_usb_get_parent()
133 static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, at91sam9x5_clk_usb_set_rate() argument
137 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9x5_clk_usb_set_rate()
163 static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) at91sam9n12_clk_usb_enable() argument
165 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9n12_clk_usb_enable()
173 static void at91sam9n12_clk_usb_disable(struct clk_hw *hw) at91sam9n12_clk_usb_disable() argument
175 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9n12_clk_usb_disable()
182 static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw) at91sam9n12_clk_usb_is_enabled() argument
184 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); at91sam9n12_clk_usb_is_enabled()
218 usb->hw.init = &init; at91sam9x5_clk_register_usb()
221 clk = clk_register(NULL, &usb->hw); at91sam9x5_clk_register_usb()
246 usb->hw.init = &init; at91sam9n12_clk_register_usb()
249 clk = clk_register(NULL, &usb->hw); at91sam9n12_clk_register_usb()
256 static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw, at91rm9200_clk_usb_recalc_rate() argument
259 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); at91rm9200_clk_usb_recalc_rate()
272 static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, at91rm9200_clk_usb_round_rate() argument
275 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); at91rm9200_clk_usb_round_rate()
276 struct clk_hw *parent = clk_hw_get_parent(hw); at91rm9200_clk_usb_round_rate()
310 static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, at91rm9200_clk_usb_set_rate() argument
315 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); at91rm9200_clk_usb_set_rate()
361 usb->hw.init = &init; at91rm9200_clk_register_usb()
365 clk = clk_register(NULL, &usb->hw); at91rm9200_clk_register_usb()
/linux-4.4.14/drivers/regulator/
H A Dtps6524x-regulator.c143 static int __read_reg(struct tps6524x *hw, int reg) __read_reg() argument
169 error = spi_sync(hw->spi, &m); __read_reg()
173 dev_dbg(hw->dev, "read reg %d, data %x, status %x\n", __read_reg()
185 static int read_reg(struct tps6524x *hw, int reg) read_reg() argument
189 mutex_lock(&hw->lock); read_reg()
190 ret = __read_reg(hw, reg); read_reg()
191 mutex_unlock(&hw->lock); read_reg()
196 static int __write_reg(struct tps6524x *hw, int reg, int val) __write_reg() argument
222 error = spi_sync(hw->spi, &m); __write_reg()
226 dev_dbg(hw->dev, "wrote reg %d, data %x, status %x\n", __write_reg()
238 static int __rmw_reg(struct tps6524x *hw, int reg, int mask, int val) __rmw_reg() argument
242 ret = __read_reg(hw, reg); __rmw_reg()
249 ret = __write_reg(hw, reg, ret); __rmw_reg()
254 static int rmw_protect(struct tps6524x *hw, int reg, int mask, int val) rmw_protect() argument
258 mutex_lock(&hw->lock); rmw_protect()
260 ret = __write_reg(hw, REG_WRITE_ENABLE, 1); rmw_protect()
262 dev_err(hw->dev, "failed to set write enable\n"); rmw_protect()
266 ret = __rmw_reg(hw, reg, mask, val); rmw_protect()
268 dev_err(hw->dev, "failed to rmw register %d\n", reg); rmw_protect()
270 ret = __write_reg(hw, REG_WRITE_ENABLE, 0); rmw_protect()
272 dev_err(hw->dev, "failed to clear write enable\n"); rmw_protect()
277 mutex_unlock(&hw->lock); rmw_protect()
282 static int read_field(struct tps6524x *hw, const struct field *field) read_field() argument
286 tmp = read_reg(hw, field->reg); read_field()
293 static int write_field(struct tps6524x *hw, const struct field *field, write_field() argument
299 return rmw_protect(hw, field->reg, write_field()
460 struct tps6524x *hw; set_voltage_sel() local
462 hw = rdev_get_drvdata(rdev); set_voltage_sel()
468 return write_field(hw, &info->voltage, selector); set_voltage_sel()
474 struct tps6524x *hw; get_voltage_sel() local
477 hw = rdev_get_drvdata(rdev); get_voltage_sel()
483 ret = read_field(hw, &info->voltage); get_voltage_sel()
496 struct tps6524x *hw; set_current_limit() local
499 hw = rdev_get_drvdata(rdev); set_current_limit()
508 return write_field(hw, &info->ilimsel, i); set_current_limit()
517 struct tps6524x *hw; get_current_limit() local
520 hw = rdev_get_drvdata(rdev); get_current_limit()
526 ret = read_field(hw, &info->ilimsel); get_current_limit()
538 struct tps6524x *hw; enable_supply() local
540 hw = rdev_get_drvdata(rdev); enable_supply()
543 return write_field(hw, &info->enable, 1); enable_supply()
549 struct tps6524x *hw; disable_supply() local
551 hw = rdev_get_drvdata(rdev); disable_supply()
554 return write_field(hw, &info->enable, 0); disable_supply()
560 struct tps6524x *hw; is_supply_enabled() local
562 hw = rdev_get_drvdata(rdev); is_supply_enabled()
565 return read_field(hw, &info->enable); is_supply_enabled()
582 struct tps6524x *hw; pmic_probe() local
595 hw = devm_kzalloc(&spi->dev, sizeof(struct tps6524x), GFP_KERNEL); pmic_probe()
596 if (!hw) pmic_probe()
599 spi_set_drvdata(spi, hw); pmic_probe()
601 memset(hw, 0, sizeof(struct tps6524x)); pmic_probe()
602 hw->dev = dev; pmic_probe()
603 hw->spi = spi_dev_get(spi); pmic_probe()
604 mutex_init(&hw->lock); pmic_probe()
607 hw->desc[i].name = info->name; pmic_probe()
608 hw->desc[i].id = i; pmic_probe()
609 hw->desc[i].n_voltages = info->n_voltages; pmic_probe()
610 hw->desc[i].volt_table = info->voltages; pmic_probe()
611 hw->desc[i].ops = &regulator_ops; pmic_probe()
612 hw->desc[i].type = REGULATOR_VOLTAGE; pmic_probe()
613 hw->desc[i].owner = THIS_MODULE; pmic_probe()
617 config.driver_data = hw; pmic_probe()
619 hw->rdev[i] = devm_regulator_register(dev, &hw->desc[i], pmic_probe()
621 if (IS_ERR(hw->rdev[i])) pmic_probe()
622 return PTR_ERR(hw->rdev[i]); pmic_probe()
/linux-4.4.14/drivers/clk/pxa/
H A Dclk-pxa.c30 struct clk_hw hw; member in struct:pxa_clk
37 #define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
39 static unsigned long cken_recalc_rate(struct clk_hw *hw, cken_recalc_rate() argument
42 struct pxa_clk *pclk = to_pxa_clk(hw); cken_recalc_rate()
49 __clk_hw_set_clk(&fix->hw, hw); cken_recalc_rate()
50 return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate); cken_recalc_rate()
57 static u8 cken_get_parent(struct clk_hw *hw) cken_get_parent() argument
59 struct pxa_clk *pclk = to_pxa_clk(hw); cken_get_parent()
95 &pxa_clk->hw, &cken_mux_ops, clk_pxa_cken_init()
96 &pxa_clk->hw, &cken_rate_ops, clk_pxa_cken_init()
97 &pxa_clk->gate.hw, &clk_gate_ops, clk_pxa_cken_init()

Completed in 4723 milliseconds

1234567891011>>