38 csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)  in csio_t5_set_mem_win()  argument
59 	csio_wr_reg32(hw, mem_win_base | BIR_V(0) |  in csio_t5_set_mem_win()
62 	csio_rd_reg32(hw,  in csio_t5_set_mem_win()
72 csio_t5_pcie_intr_handler(struct csio_hw *hw)  in csio_t5_pcie_intr_handler()  argument
136 	fat = csio_handle_intr_status(hw,  in csio_t5_pcie_intr_handler()
139 	      csio_handle_intr_status(hw,  in csio_t5_pcie_intr_handler()
142 	      csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);  in csio_t5_pcie_intr_handler()
144 		csio_hw_fatal_err(hw);  in csio_t5_pcie_intr_handler()
155 csio_t5_flash_cfg_addr(struct csio_hw *hw)  in csio_t5_flash_cfg_addr()  argument
173 csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,  in csio_t5_mc_read()  argument
186 	if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)  in csio_t5_mc_read()
188 	csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);  in csio_t5_mc_read()
189 	csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);  in csio_t5_mc_read()
190 	csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);  in csio_t5_mc_read()
191 	csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F |  BIST_CMD_GAP_V(1),  in csio_t5_mc_read()
193 	i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,  in csio_t5_mc_read()
201 		*data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));  in csio_t5_mc_read()
203 		*ecc = csio_rd_reg64(hw, MC_DATA(16));  in csio_t5_mc_read()
221 csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,  in csio_t5_edc_read()  argument
242 	if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)  in csio_t5_edc_read()
244 	csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);  in csio_t5_edc_read()
245 	csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);  in csio_t5_edc_read()
246 	csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);  in csio_t5_edc_read()
247 	csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F |  BIST_CMD_GAP_V(1),  in csio_t5_edc_read()
249 	i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,  in csio_t5_edc_read()
257 		*data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));  in csio_t5_edc_read()
259 		*ecc = csio_rd_reg64(hw, EDC_DATA(16));  in csio_t5_edc_read()
282 csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,  in csio_t5_memory_rw()  argument
301 	edc_size  = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));  in csio_t5_memory_rw()
305 		mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,  in csio_t5_memory_rw()
322 	mem_reg = csio_rd_reg32(hw,  in csio_t5_memory_rw()
329 	win_pf = PFNUM_V(hw->pfn);  in csio_t5_memory_rw()
331 	csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",  in csio_t5_memory_rw()
333 	csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",  in csio_t5_memory_rw()
335 	csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n",  in csio_t5_memory_rw()
337 	csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",  in csio_t5_memory_rw()
346 		csio_wr_reg32(hw, pos | win_pf,  in csio_t5_memory_rw()
348 		csio_rd_reg32(hw,  in csio_t5_memory_rw()
353 				*buf++ = csio_rd_reg32(hw, mem_base + offset);  in csio_t5_memory_rw()
355 				csio_wr_reg32(hw, *buf++, mem_base + offset);  in csio_t5_memory_rw()
372 csio_t5_dfs_create_ext_mem(struct csio_hw *hw)  in csio_t5_dfs_create_ext_mem()  argument
375 	int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);  in csio_t5_dfs_create_ext_mem()
378 		size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);  in csio_t5_dfs_create_ext_mem()
379 		csio_add_debugfs_mem(hw, "mc0", MEM_MC0,  in csio_t5_dfs_create_ext_mem()
383 		size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);  in csio_t5_dfs_create_ext_mem()
384 		csio_add_debugfs_mem(hw, "mc1", MEM_MC1,  in csio_t5_dfs_create_ext_mem()