Lines Matching refs:hw
87 struct atl2_hw *hw = &adapter->hw; in atl2_sw_init() local
91 hw->vendor_id = pdev->vendor; in atl2_sw_init()
92 hw->device_id = pdev->device; in atl2_sw_init()
93 hw->subsystem_vendor_id = pdev->subsystem_vendor; in atl2_sw_init()
94 hw->subsystem_id = pdev->subsystem_device; in atl2_sw_init()
95 hw->revision_id = pdev->revision; in atl2_sw_init()
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); in atl2_sw_init()
104 hw->phy_configured = false; in atl2_sw_init()
105 hw->preamble_len = 7; in atl2_sw_init()
106 hw->ipgt = 0x60; in atl2_sw_init()
107 hw->min_ifg = 0x50; in atl2_sw_init()
108 hw->ipgr1 = 0x40; in atl2_sw_init()
109 hw->ipgr2 = 0x60; in atl2_sw_init()
110 hw->retry_buf = 2; in atl2_sw_init()
111 hw->max_retry = 0xf; in atl2_sw_init()
112 hw->lcol = 0x37; in atl2_sw_init()
113 hw->jam_ipg = 7; in atl2_sw_init()
114 hw->fc_rxd_hi = 0; in atl2_sw_init()
115 hw->fc_rxd_lo = 0; in atl2_sw_init()
116 hw->max_frame_size = adapter->netdev->mtu; in atl2_sw_init()
137 struct atl2_hw *hw = &adapter->hw; in atl2_set_multi() local
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); in atl2_set_multi()
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); in atl2_set_multi()
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); in atl2_set_multi()
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); in atl2_set_multi()
161 hash_value = atl2_hash_mc_addr(hw, ha->addr); in atl2_set_multi()
162 atl2_hash_set(hw, hash_value); in atl2_set_multi()
187 struct atl2_hw *hw = &adapter->hw; in atl2_configure() local
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); in atl2_configure()
194 value = (((u32)hw->mac_addr[2]) << 24) | in atl2_configure()
195 (((u32)hw->mac_addr[3]) << 16) | in atl2_configure()
196 (((u32)hw->mac_addr[4]) << 8) | in atl2_configure()
197 (((u32)hw->mac_addr[5])); in atl2_configure()
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); in atl2_configure()
199 value = (((u32)hw->mac_addr[0]) << 8) | in atl2_configure()
200 (((u32)hw->mac_addr[1])); in atl2_configure()
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); in atl2_configure()
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, in atl2_configure()
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, in atl2_configure()
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, in atl2_configure()
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, in atl2_configure()
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); in atl2_configure()
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); in atl2_configure()
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); in atl2_configure()
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << in atl2_configure()
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << in atl2_configure()
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << in atl2_configure()
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << in atl2_configure()
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); in atl2_configure()
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | in atl2_configure()
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << in atl2_configure()
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << in atl2_configure()
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); in atl2_configure()
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); in atl2_configure()
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); in atl2_configure()
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); in atl2_configure()
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + in atl2_configure()
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); in atl2_configure()
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); in atl2_configure()
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); in atl2_configure()
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); in atl2_configure()
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); in atl2_configure()
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); in atl2_configure()
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); in atl2_configure()
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR); in atl2_configure()
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); in atl2_configure()
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); in atl2_configure()
348 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); in atl2_irq_enable()
349 ATL2_WRITE_FLUSH(&adapter->hw); in atl2_irq_enable()
358 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); in atl2_irq_disable()
359 ATL2_WRITE_FLUSH(&adapter->hw); in atl2_irq_disable()
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); in atl2_vlan_mode()
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); in atl2_vlan_mode()
479 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); in atl2_intr_rx()
573 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); in atl2_check_for_link()
574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); in atl2_check_for_link()
594 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); in atl2_clear_phy_int()
606 struct atl2_hw *hw = &adapter->hw; in atl2_intr() local
609 status = ATL2_READ_REG(hw, REG_ISR); in atl2_intr()
618 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); in atl2_intr()
623 ATL2_WRITE_REG(hw, REG_ISR, 0); in atl2_intr()
624 ATL2_WRITE_REG(hw, REG_IMR, 0); in atl2_intr()
625 ATL2_WRITE_FLUSH(hw); in atl2_intr()
633 ATL2_WRITE_REG(hw, REG_ISR, 0); in atl2_intr()
634 ATL2_WRITE_REG(hw, REG_IMR, 0); in atl2_intr()
635 ATL2_WRITE_FLUSH(hw); in atl2_intr()
655 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); in atl2_intr()
717 err = atl2_init_hw(&adapter->hw); in atl2_open()
742 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); in atl2_open()
743 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, in atl2_open()
754 atl2_reset_hw(&adapter->hw); in atl2_open()
770 atl2_reset_hw(&adapter->hw); in atl2_down()
908 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, in atl2_xmit_frame()
926 struct atl2_hw *hw = &adapter->hw; in atl2_change_mtu() local
932 if (hw->max_frame_size != new_mtu) { in atl2_change_mtu()
934 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + in atl2_change_mtu()
960 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); in atl2_set_mac()
962 atl2_set_mac_addr(&adapter->hw); in atl2_set_mac()
979 if (atl2_read_phy_reg(&adapter->hw, in atl2_mii_ioctl()
990 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, in atl2_mii_ioctl()
1044 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); in atl2_watchdog()
1045 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); in atl2_watchdog()
1063 struct atl2_hw *hw = &adapter->hw; in atl2_phy_config() local
1067 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); in atl2_phy_config()
1068 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | in atl2_phy_config()
1082 err = atl2_init_hw(&adapter->hw); in atl2_up()
1100 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); in atl2_up()
1101 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | in atl2_up()
1131 struct atl2_hw *hw = &adapter->hw; in atl2_setup_mac_ctrl() local
1148 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << in atl2_setup_mac_ctrl()
1162 value |= (((u32)(adapter->hw.retry_buf & in atl2_setup_mac_ctrl()
1165 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); in atl2_setup_mac_ctrl()
1170 struct atl2_hw *hw = &adapter->hw; in atl2_check_link() local
1177 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); in atl2_check_link()
1178 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); in atl2_check_link()
1183 value = ATL2_READ_REG(hw, REG_MAC_CTRL); in atl2_check_link()
1185 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); in atl2_check_link()
1194 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); in atl2_check_link()
1197 switch (hw->MediaType) { in atl2_check_link()
1240 value = ATL2_READ_REG(hw, REG_MAC_CTRL); in atl2_check_link()
1242 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); in atl2_check_link()
1384 adapter->hw.back = adapter; in atl2_probe()
1389 adapter->hw.mem_rang = (u32)mmio_len; in atl2_probe()
1390 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); in atl2_probe()
1391 if (!adapter->hw.hw_addr) { in atl2_probe()
1419 atl2_phy_init(&adapter->hw); in atl2_probe()
1424 if (atl2_reset_hw(&adapter->hw)) { in atl2_probe()
1430 atl2_read_mac_addr(&adapter->hw); in atl2_probe()
1431 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); in atl2_probe()
1465 iounmap(adapter->hw.hw_addr); in atl2_probe()
1503 atl2_force_ps(&adapter->hw); in atl2_remove()
1505 iounmap(adapter->hw.hw_addr); in atl2_remove()
1517 struct atl2_hw *hw = &adapter->hw; in atl2_suspend() local
1539 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); in atl2_suspend()
1540 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); in atl2_suspend()
1547 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); in atl2_suspend()
1562 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); in atl2_suspend()
1569 ctrl |= (((u32)adapter->hw.preamble_len & in atl2_suspend()
1571 ctrl |= (((u32)(adapter->hw.retry_buf & in atl2_suspend()
1579 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); in atl2_suspend()
1582 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); in atl2_suspend()
1584 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); in atl2_suspend()
1585 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); in atl2_suspend()
1587 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); in atl2_suspend()
1596 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); in atl2_suspend()
1597 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); in atl2_suspend()
1600 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); in atl2_suspend()
1602 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); in atl2_suspend()
1603 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); in atl2_suspend()
1605 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); in atl2_suspend()
1607 hw->phy_configured = false; /* re-init PHY when resume */ in atl2_suspend()
1616 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); in atl2_suspend()
1619 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); in atl2_suspend()
1621 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); in atl2_suspend()
1622 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); in atl2_suspend()
1624 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); in atl2_suspend()
1626 atl2_force_ps(hw); in atl2_suspend()
1627 hw->phy_configured = false; /* re-init PHY when resume */ in atl2_suspend()
1661 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ in atl2_resume()
1666 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); in atl2_resume()
1674 atl2_reset_hw(&adapter->hw); in atl2_resume()
1730 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) in atl2_read_pci_cfg() argument
1732 struct atl2_adapter *adapter = hw->back; in atl2_read_pci_cfg()
1736 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) in atl2_write_pci_cfg() argument
1738 struct atl2_adapter *adapter = hw->back; in atl2_write_pci_cfg()
1746 struct atl2_hw *hw = &adapter->hw; in atl2_get_settings() local
1757 ecmd->advertising |= hw->autoneg_advertised; in atl2_get_settings()
1782 struct atl2_hw *hw = &adapter->hw; in atl2_set_settings() local
1794 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; in atl2_set_settings()
1795 hw->autoneg_advertised = MY_ADV_MASK; in atl2_set_settings()
1798 hw->MediaType = MEDIA_TYPE_100M_FULL; in atl2_set_settings()
1799 hw->autoneg_advertised = ADVERTISE_100_FULL; in atl2_set_settings()
1802 hw->MediaType = MEDIA_TYPE_100M_HALF; in atl2_set_settings()
1803 hw->autoneg_advertised = ADVERTISE_100_HALF; in atl2_set_settings()
1806 hw->MediaType = MEDIA_TYPE_10M_FULL; in atl2_set_settings()
1807 hw->autoneg_advertised = ADVERTISE_10_FULL; in atl2_set_settings()
1810 hw->MediaType = MEDIA_TYPE_10M_HALF; in atl2_set_settings()
1811 hw->autoneg_advertised = ADVERTISE_10_HALF; in atl2_set_settings()
1816 ecmd->advertising = hw->autoneg_advertised | in atl2_set_settings()
1828 atl2_reset_hw(&adapter->hw); in atl2_set_settings()
1856 struct atl2_hw *hw = &adapter->hw; in atl2_get_regs() local
1862 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; in atl2_get_regs()
1864 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); in atl2_get_regs()
1865 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); in atl2_get_regs()
1866 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); in atl2_get_regs()
1867 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); in atl2_get_regs()
1868 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); in atl2_get_regs()
1869 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); in atl2_get_regs()
1870 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); in atl2_get_regs()
1871 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); in atl2_get_regs()
1872 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); in atl2_get_regs()
1873 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); in atl2_get_regs()
1874 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); in atl2_get_regs()
1875 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); in atl2_get_regs()
1876 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); in atl2_get_regs()
1877 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); in atl2_get_regs()
1878 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); in atl2_get_regs()
1879 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); in atl2_get_regs()
1880 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); in atl2_get_regs()
1881 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); in atl2_get_regs()
1882 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); in atl2_get_regs()
1883 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); in atl2_get_regs()
1884 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); in atl2_get_regs()
1885 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); in atl2_get_regs()
1886 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); in atl2_get_regs()
1887 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); in atl2_get_regs()
1888 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); in atl2_get_regs()
1889 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); in atl2_get_regs()
1890 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); in atl2_get_regs()
1891 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); in atl2_get_regs()
1892 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); in atl2_get_regs()
1893 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); in atl2_get_regs()
1894 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); in atl2_get_regs()
1895 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); in atl2_get_regs()
1896 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); in atl2_get_regs()
1897 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); in atl2_get_regs()
1898 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); in atl2_get_regs()
1899 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); in atl2_get_regs()
1900 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); in atl2_get_regs()
1901 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); in atl2_get_regs()
1902 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); in atl2_get_regs()
1904 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); in atl2_get_regs()
1906 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); in atl2_get_regs()
1914 if (!atl2_check_eeprom_exist(&adapter->hw)) in atl2_get_eeprom_len()
1924 struct atl2_hw *hw = &adapter->hw; in atl2_get_eeprom() local
1933 if (atl2_check_eeprom_exist(hw)) in atl2_get_eeprom()
1936 eeprom->magic = hw->vendor_id | (hw->device_id << 16); in atl2_get_eeprom()
1947 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { in atl2_get_eeprom()
1965 struct atl2_hw *hw = &adapter->hw; in atl2_set_eeprom() local
1974 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) in atl2_set_eeprom()
1990 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { in atl2_set_eeprom()
2001 if (!atl2_read_eeprom(hw, last_dword * 4, in atl2_set_eeprom()
2012 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { in atl2_set_eeprom()
2112 static s32 atl2_reset_hw(struct atl2_hw *hw) in atl2_reset_hw() argument
2119 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); in atl2_reset_hw()
2125 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); in atl2_reset_hw()
2140 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); in atl2_reset_hw()
2146 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); in atl2_reset_hw()
2173 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) in atl2_spi_read() argument
2178 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); in atl2_spi_read()
2179 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); in atl2_spi_read()
2194 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); in atl2_spi_read()
2198 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); in atl2_spi_read()
2202 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); in atl2_spi_read()
2210 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); in atl2_spi_read()
2219 static int get_permanent_address(struct atl2_hw *hw) in get_permanent_address() argument
2227 if (is_valid_ether_addr(hw->perm_mac_addr)) in get_permanent_address()
2233 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ in get_permanent_address()
2240 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { in get_permanent_address()
2265 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); in get_permanent_address()
2278 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { in get_permanent_address()
2300 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); in get_permanent_address()
2304 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); in get_permanent_address()
2305 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); in get_permanent_address()
2310 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); in get_permanent_address()
2322 static s32 atl2_read_mac_addr(struct atl2_hw *hw) in atl2_read_mac_addr() argument
2324 if (get_permanent_address(hw)) { in atl2_read_mac_addr()
2327 hw->perm_mac_addr[0] = 0x00; in atl2_read_mac_addr()
2328 hw->perm_mac_addr[1] = 0x13; in atl2_read_mac_addr()
2329 hw->perm_mac_addr[2] = 0x74; in atl2_read_mac_addr()
2330 hw->perm_mac_addr[3] = 0x00; in atl2_read_mac_addr()
2331 hw->perm_mac_addr[4] = 0x5c; in atl2_read_mac_addr()
2332 hw->perm_mac_addr[5] = 0x38; in atl2_read_mac_addr()
2335 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); in atl2_read_mac_addr()
2353 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) in atl2_hash_mc_addr() argument
2373 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) in atl2_hash_set() argument
2389 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); in atl2_hash_set()
2393 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); in atl2_hash_set()
2399 static void atl2_init_pcie(struct atl2_hw *hw) in atl2_init_pcie() argument
2403 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); in atl2_init_pcie()
2406 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); in atl2_init_pcie()
2409 static void atl2_init_flash_opcode(struct atl2_hw *hw) in atl2_init_flash_opcode() argument
2411 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) in atl2_init_flash_opcode()
2412 hw->flash_vendor = 0; /* ATMEL */ in atl2_init_flash_opcode()
2415 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, in atl2_init_flash_opcode()
2416 flash_table[hw->flash_vendor].cmdPROGRAM); in atl2_init_flash_opcode()
2417 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, in atl2_init_flash_opcode()
2418 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); in atl2_init_flash_opcode()
2419 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, in atl2_init_flash_opcode()
2420 flash_table[hw->flash_vendor].cmdCHIP_ERASE); in atl2_init_flash_opcode()
2421 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, in atl2_init_flash_opcode()
2422 flash_table[hw->flash_vendor].cmdRDID); in atl2_init_flash_opcode()
2423 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, in atl2_init_flash_opcode()
2424 flash_table[hw->flash_vendor].cmdWREN); in atl2_init_flash_opcode()
2425 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, in atl2_init_flash_opcode()
2426 flash_table[hw->flash_vendor].cmdRDSR); in atl2_init_flash_opcode()
2427 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, in atl2_init_flash_opcode()
2428 flash_table[hw->flash_vendor].cmdWRSR); in atl2_init_flash_opcode()
2429 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, in atl2_init_flash_opcode()
2430 flash_table[hw->flash_vendor].cmdREAD); in atl2_init_flash_opcode()
2442 static s32 atl2_init_hw(struct atl2_hw *hw) in atl2_init_hw() argument
2446 atl2_init_pcie(hw); in atl2_init_hw()
2450 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); in atl2_init_hw()
2451 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); in atl2_init_hw()
2453 atl2_init_flash_opcode(hw); in atl2_init_hw()
2455 ret_val = atl2_phy_init(hw); in atl2_init_hw()
2467 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, in atl2_get_speed_and_duplex() argument
2474 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); in atl2_get_speed_and_duplex()
2505 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) in atl2_read_phy_reg() argument
2515 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); in atl2_read_phy_reg()
2521 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); in atl2_read_phy_reg()
2540 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) in atl2_write_phy_reg() argument
2550 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); in atl2_write_phy_reg()
2556 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); in atl2_write_phy_reg()
2574 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) in atl2_phy_setup_autoneg_adv() argument
2596 switch (hw->MediaType) { in atl2_phy_setup_autoneg_adv()
2603 hw->autoneg_advertised = in atl2_phy_setup_autoneg_adv()
2611 hw->autoneg_advertised = ADVERTISE_100_FULL; in atl2_phy_setup_autoneg_adv()
2615 hw->autoneg_advertised = ADVERTISE_100_HALF; in atl2_phy_setup_autoneg_adv()
2619 hw->autoneg_advertised = ADVERTISE_10_FULL; in atl2_phy_setup_autoneg_adv()
2623 hw->autoneg_advertised = ADVERTISE_10_HALF; in atl2_phy_setup_autoneg_adv()
2630 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; in atl2_phy_setup_autoneg_adv()
2632 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); in atl2_phy_setup_autoneg_adv()
2647 static s32 atl2_phy_commit(struct atl2_hw *hw) in atl2_phy_commit() argument
2653 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); in atl2_phy_commit()
2660 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); in atl2_phy_commit()
2673 static s32 atl2_phy_init(struct atl2_hw *hw) in atl2_phy_init() argument
2678 if (hw->phy_configured) in atl2_phy_init()
2682 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); in atl2_phy_init()
2683 ATL2_WRITE_FLUSH(hw); in atl2_phy_init()
2687 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); in atl2_phy_init()
2688 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); in atl2_phy_init()
2693 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); in atl2_phy_init()
2699 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); in atl2_phy_init()
2704 ret_val = atl2_phy_setup_autoneg_adv(hw); in atl2_phy_init()
2709 ret_val = atl2_phy_commit(hw); in atl2_phy_init()
2713 hw->phy_configured = true; in atl2_phy_init()
2718 static void atl2_set_mac_addr(struct atl2_hw *hw) in atl2_set_mac_addr() argument
2724 value = (((u32)hw->mac_addr[2]) << 24) | in atl2_set_mac_addr()
2725 (((u32)hw->mac_addr[3]) << 16) | in atl2_set_mac_addr()
2726 (((u32)hw->mac_addr[4]) << 8) | in atl2_set_mac_addr()
2727 (((u32)hw->mac_addr[5])); in atl2_set_mac_addr()
2728 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); in atl2_set_mac_addr()
2730 value = (((u32)hw->mac_addr[0]) << 8) | in atl2_set_mac_addr()
2731 (((u32)hw->mac_addr[1])); in atl2_set_mac_addr()
2732 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); in atl2_set_mac_addr()
2739 static int atl2_check_eeprom_exist(struct atl2_hw *hw) in atl2_check_eeprom_exist() argument
2743 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); in atl2_check_eeprom_exist()
2746 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); in atl2_check_eeprom_exist()
2748 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); in atl2_check_eeprom_exist()
2753 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) in atl2_write_eeprom() argument
2758 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) in atl2_read_eeprom() argument
2766 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); in atl2_read_eeprom()
2768 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); in atl2_read_eeprom()
2772 Control = ATL2_READ_REG(hw, REG_VPD_CAP); in atl2_read_eeprom()
2778 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); in atl2_read_eeprom()
2784 static void atl2_force_ps(struct atl2_hw *hw) in atl2_force_ps() argument
2788 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); in atl2_force_ps()
2789 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); in atl2_force_ps()
2790 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); in atl2_force_ps()
2792 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); in atl2_force_ps()
2793 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); in atl2_force_ps()
2794 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); in atl2_force_ps()
2795 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); in atl2_force_ps()
3025 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; in atl2_check_options()
3026 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > in atl2_check_options()
3059 adapter->hw.flash_vendor = (u8) val; in atl2_check_options()
3062 adapter->hw.flash_vendor = (u8)(opt.def); in atl2_check_options()
3076 adapter->hw.MediaType = (u16) val; in atl2_check_options()
3079 adapter->hw.MediaType = (u16)(opt.def); in atl2_check_options()