Lines Matching refs:hw
151 struct _hfc4s8s_hw *hw; /* pointer to hardware area */ member
274 Read_hfc8_stable(hfc4s8s_hw *hw, int reg) in Read_hfc8_stable() argument
278 ref8 = Read_hfc8(hw, reg); in Read_hfc8_stable()
279 while (((in8 = Read_hfc8(hw, reg)) != ref8)) { in Read_hfc8_stable()
286 Read_hfc16_stable(hfc4s8s_hw *hw, int reg) in Read_hfc16_stable() argument
291 ref16 = Read_hfc16(hw, reg); in Read_hfc16_stable()
292 while (((in16 = Read_hfc16(hw, reg)) != ref16)) { in Read_hfc16_stable()
319 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= in dch_l2l1()
322 schedule_work(&l1->hw->tqueue); in dch_l2l1()
335 Write_hfc8(l1->hw, R_ST_SEL, in dch_l2l1()
337 Write_hfc8(l1->hw, A_ST_WR_STA, in dch_l2l1()
352 Write_hfc8(l1->hw, R_ST_SEL, in dch_l2l1()
354 Write_hfc8(l1->hw, A_ST_WR_STA, in dch_l2l1()
399 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= in bch_l2l1()
402 schedule_work(&l1->hw->tqueue); in bch_l2l1()
418 l1->hw->mr.timer_usg_cnt++; in bch_l2l1()
419 l1->hw->mr. in bch_l2l1()
425 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
429 wait_busy(l1->hw); in bch_l2l1()
430 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ in bch_l2l1()
431 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
432 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ in bch_l2l1()
433 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
434 wait_busy(l1->hw); in bch_l2l1()
436 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
440 wait_busy(l1->hw); in bch_l2l1()
441 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ in bch_l2l1()
442 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
443 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ in bch_l2l1()
444 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
446 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
448 l1->hw->mr.r_ctrl0 |= in bch_l2l1()
450 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
451 l1->hw->mr.r_ctrl0); in bch_l2l1()
465 l1->hw->mr. in bch_l2l1()
471 l1->hw->mr.timer_usg_cnt++; in bch_l2l1()
472 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
476 wait_busy(l1->hw); in bch_l2l1()
477 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ in bch_l2l1()
478 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
479 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ in bch_l2l1()
480 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
481 wait_busy(l1->hw); in bch_l2l1()
483 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
487 wait_busy(l1->hw); in bch_l2l1()
488 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ in bch_l2l1()
489 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
490 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ in bch_l2l1()
491 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
493 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
495 l1->hw->mr.r_ctrl0 |= in bch_l2l1()
497 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
498 l1->hw->mr.r_ctrl0); in bch_l2l1()
514 l1->hw->mr. in bch_l2l1()
520 l1->hw->mr. in bch_l2l1()
526 l1->hw->mr.timer_usg_cnt--; in bch_l2l1()
527 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
531 wait_busy(l1->hw); in bch_l2l1()
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ in bch_l2l1()
533 wait_busy(l1->hw); in bch_l2l1()
534 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
538 wait_busy(l1->hw); in bch_l2l1()
539 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ in bch_l2l1()
540 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
542 l1->hw->mr.r_ctrl0 &= in bch_l2l1()
544 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
545 l1->hw->mr.r_ctrl0); in bch_l2l1()
570 if (l1->hw->mr.timer_usg_cnt) { in bch_l2l1()
571 Write_hfc8(l1->hw, R_IRQMSK_MISC, in bch_l2l1()
574 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); in bch_l2l1()
604 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
605 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); in hfc_l1_timer()
611 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); in hfc_l1_timer()
615 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
616 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); in hfc_l1_timer()
621 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
622 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); in hfc_l1_timer()
643 Write_hfc8(l1p->hw, R_FIFO, in rx_d_frame()
645 wait_busy(l1p->hw); in rx_d_frame()
647 f1 = Read_hfc8_stable(l1p->hw, A_F1); in rx_d_frame()
648 f2 = Read_hfc8(l1p->hw, A_F2); in rx_d_frame()
658 z1 = Read_hfc16_stable(l1p->hw, A_Z1); in rx_d_frame()
659 z2 = Read_hfc16(l1p->hw, A_Z2); in rx_d_frame()
669 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); in rx_d_frame()
670 wait_busy(l1p->hw); in rx_d_frame()
680 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); in rx_d_frame()
681 wait_busy(l1p->hw); in rx_d_frame()
685 SetRegAddr(l1p->hw, A_FIFO_DATA0); in rx_d_frame()
688 fRead_hfc32(l1p->hw); in rx_d_frame()
693 fRead_hfc8(l1p->hw); in rx_d_frame()
695 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); in rx_d_frame()
696 wait_busy(l1p->hw); in rx_d_frame()
703 SetRegAddr(l1p->hw, A_FIFO_DATA0); in rx_d_frame()
706 *((unsigned long *) cp) = fRead_hfc32(l1p->hw); in rx_d_frame()
712 *cp++ = fRead_hfc8(l1p->hw); in rx_d_frame()
714 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ in rx_d_frame()
715 wait_busy(l1p->hw); in rx_d_frame()
749 Write_hfc8(l1->hw, R_FIFO, in rx_b_frame()
751 wait_busy(l1->hw); in rx_b_frame()
754 f1 = Read_hfc8_stable(l1->hw, A_F1); in rx_b_frame()
755 f2 = Read_hfc8(l1->hw, A_F2); in rx_b_frame()
759 z1 = Read_hfc16_stable(l1->hw, A_Z1); in rx_b_frame()
760 z2 = Read_hfc16(l1->hw, A_Z2); in rx_b_frame()
794 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in rx_b_frame()
795 wait_busy(l1->hw); in rx_b_frame()
798 SetRegAddr(l1->hw, A_FIFO_DATA0); in rx_b_frame()
802 fRead_hfc32(l1->hw); in rx_b_frame()
808 *(bch->rx_ptr++) = fRead_hfc8(l1->hw); in rx_b_frame()
812 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); in rx_b_frame()
813 wait_busy(l1->hw); in rx_b_frame()
849 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); in tx_d_frame()
850 wait_busy(l1p->hw); in tx_d_frame()
852 f1 = Read_hfc8(l1p->hw, A_F1); in tx_d_frame()
853 f2 = Read_hfc8_stable(l1p->hw, A_F2); in tx_d_frame()
868 SetRegAddr(l1p->hw, A_FIFO_DATA0); in tx_d_frame()
871 SetRegAddr(l1p->hw, A_FIFO_DATA0); in tx_d_frame()
872 fWrite_hfc32(l1p->hw, *(unsigned long *) cp); in tx_d_frame()
878 fWrite_hfc8(l1p->hw, *cp++); in tx_d_frame()
881 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ in tx_d_frame()
882 wait_busy(l1p->hw); in tx_d_frame()
904 Write_hfc8(l1->hw, R_FIFO, in tx_b_frame()
906 wait_busy(l1->hw); in tx_b_frame()
910 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; in tx_b_frame()
912 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); in tx_b_frame()
922 l1->hw->mr.fifo_slow_timer_service[l1-> in tx_b_frame()
932 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= in tx_b_frame()
935 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= in tx_b_frame()
938 max = Read_hfc16_stable(l1->hw, A_Z2); in tx_b_frame()
939 max -= Read_hfc16(l1->hw, A_Z1); in tx_b_frame()
953 SetRegAddr(l1->hw, A_FIFO_DATA0); in tx_b_frame()
955 fWrite_hfc32(l1->hw, *(unsigned long *) cp); in tx_b_frame()
961 fWrite_hfc8(l1->hw, *cp++); in tx_b_frame()
966 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); in tx_b_frame()
974 Write_hfc8(l1->hw, R_FIFO, in tx_b_frame()
977 wait_busy(l1->hw); in tx_b_frame()
991 hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue); in hfc4s8s_bh() local
999 l1p = hw->l1; in hfc4s8s_bh()
1001 if ((b & hw->mr.r_irq_statech)) { in hfc4s8s_bh()
1003 hw->mr.r_irq_statech &= ~b; in hfc4s8s_bh()
1008 Write_hfc8(l1p->hw, R_ST_SEL, in hfc4s8s_bh()
1011 Read_hfc8(l1p->hw, in hfc4s8s_bh()
1037 Write_hfc8(hw, A_ST_WR_STA, in hfc4s8s_bh()
1050 Write_hfc8(l1p->hw, R_ST_SEL, in hfc4s8s_bh()
1053 Read_hfc8(l1p->hw, in hfc4s8s_bh()
1094 l1p->hw->cardnum, in hfc4s8s_bh()
1106 fifo_stat = hw->mr.r_irq_fifo_blx; in hfc4s8s_bh()
1107 l1p = hw->l1; in hfc4s8s_bh()
1108 while (idx < hw->driver_data.max_st_ports) { in hfc4s8s_bh()
1110 if (hw->mr.timer_irq) { in hfc4s8s_bh()
1111 *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx]; in hfc4s8s_bh()
1112 if (hw->fifo_sched_cnt <= 0) { in hfc4s8s_bh()
1114 hw->mr.fifo_slow_timer_service[l1p-> in hfc4s8s_bh()
1166 if (hw->fifo_sched_cnt <= 0) in hfc4s8s_bh()
1167 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE)); in hfc4s8s_bh()
1168 hw->mr.timer_irq = 0; /* clear requested timer irq */ in hfc4s8s_bh()
1177 hfc4s8s_hw *hw = dev_id; in hfc4s8s_interrupt() local
1183 if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) in hfc4s8s_interrupt()
1187 old_ioreg = GetRegAddr(hw); in hfc4s8s_interrupt()
1190 hw->mr.r_irq_statech |= in hfc4s8s_interrupt()
1191 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg); in hfc4s8s_interrupt()
1193 (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) in hfc4s8s_interrupt()
1194 && !hw->mr.r_irq_statech) { in hfc4s8s_interrupt()
1195 SetRegAddr(hw, old_ioreg); in hfc4s8s_interrupt()
1200 if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) { in hfc4s8s_interrupt()
1201 hw->mr.timer_irq = 1; in hfc4s8s_interrupt()
1202 hw->fifo_sched_cnt--; in hfc4s8s_interrupt()
1206 if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) { in hfc4s8s_interrupt()
1207 hw->mr.r_irq_oview |= ovr; in hfc4s8s_interrupt()
1209 ovp = hw->mr.r_irq_fifo_blx; in hfc4s8s_interrupt()
1212 *ovp |= Read_hfc8(hw, idx); in hfc4s8s_interrupt()
1221 schedule_work(&hw->tqueue); in hfc4s8s_interrupt()
1223 SetRegAddr(hw, old_ioreg); in hfc4s8s_interrupt()
1231 chipreset(hfc4s8s_hw *hw) in chipreset() argument
1235 spin_lock_irqsave(&hw->lock, flags); in chipreset()
1236 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */ in chipreset()
1237 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */ in chipreset()
1238 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */ in chipreset()
1239 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */ in chipreset()
1240 hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */ in chipreset()
1241 spin_unlock_irqrestore(&hw->lock, flags); in chipreset()
1244 Write_hfc8(hw, R_CIRM, 0); /* disable reset */ in chipreset()
1245 wait_busy(hw); in chipreset()
1247 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */ in chipreset()
1248 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */ in chipreset()
1249 if (hw->driver_data.clock_mode == 1) in chipreset()
1250 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */ in chipreset()
1251 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */ in chipreset()
1253 memset(&hw->mr, 0, sizeof(hw->mr)); in chipreset()
1260 hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode) in hfc_hardware_enable() argument
1268 hw->nt_mode = nt_mode; in hfc_hardware_enable()
1271 hw->mr.r_irq_ctrl = M_FIFO_IRQ; in hfc_hardware_enable()
1272 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); in hfc_hardware_enable()
1273 hw->mr.r_irqmsk_statchg = 0; in hfc_hardware_enable()
1274 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); in hfc_hardware_enable()
1275 Write_hfc8(hw, R_PWM_MD, 0x80); in hfc_hardware_enable()
1276 Write_hfc8(hw, R_PWM1, 26); in hfc_hardware_enable()
1278 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); in hfc_hardware_enable()
1281 for (i = 0; i < hw->driver_data.max_st_ports; i++) { in hfc_hardware_enable()
1282 hw->mr.r_irqmsk_statchg |= (1 << i); in hfc_hardware_enable()
1283 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); in hfc_hardware_enable()
1284 Write_hfc8(hw, R_ST_SEL, i); in hfc_hardware_enable()
1285 Write_hfc8(hw, A_ST_CLK_DLY, in hfc_hardware_enable()
1287 hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE); in hfc_hardware_enable()
1288 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); in hfc_hardware_enable()
1289 Write_hfc8(hw, A_ST_CTRL2, 3); in hfc_hardware_enable()
1290 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */ in hfc_hardware_enable()
1292 hw->l1[i].enabled = 1; in hfc_hardware_enable()
1293 hw->l1[i].nt_mode = nt_mode; in hfc_hardware_enable()
1297 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */ in hfc_hardware_enable()
1298 wait_busy(hw); in hfc_hardware_enable()
1299 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ in hfc_hardware_enable()
1300 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ in hfc_hardware_enable()
1301 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ in hfc_hardware_enable()
1302 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ in hfc_hardware_enable()
1303 wait_busy(hw); in hfc_hardware_enable()
1306 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */ in hfc_hardware_enable()
1307 wait_busy(hw); in hfc_hardware_enable()
1308 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ in hfc_hardware_enable()
1309 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ in hfc_hardware_enable()
1310 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ in hfc_hardware_enable()
1311 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ in hfc_hardware_enable()
1312 wait_busy(hw); in hfc_hardware_enable()
1315 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */ in hfc_hardware_enable()
1316 wait_busy(hw); in hfc_hardware_enable()
1317 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ in hfc_hardware_enable()
1318 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ in hfc_hardware_enable()
1319 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ in hfc_hardware_enable()
1320 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ in hfc_hardware_enable()
1321 wait_busy(hw); in hfc_hardware_enable()
1324 sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i); in hfc_hardware_enable()
1327 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name, in hfc_hardware_enable()
1330 hw->l1[i].enabled = 0; in hfc_hardware_enable()
1331 hw->mr.r_irqmsk_statchg &= ~(1 << i); in hfc_hardware_enable()
1332 Write_hfc8(hw, R_SCI_MSK, in hfc_hardware_enable()
1333 hw->mr.r_irqmsk_statchg); in hfc_hardware_enable()
1340 spin_lock_irqsave(&hw->lock, flags); in hfc_hardware_enable()
1341 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN; in hfc_hardware_enable()
1342 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); in hfc_hardware_enable()
1343 spin_unlock_irqrestore(&hw->lock, flags); in hfc_hardware_enable()
1346 spin_lock_irqsave(&hw->lock, flags); in hfc_hardware_enable()
1347 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN; in hfc_hardware_enable()
1348 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); in hfc_hardware_enable()
1349 spin_unlock_irqrestore(&hw->lock, flags); in hfc_hardware_enable()
1351 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) { in hfc_hardware_enable()
1352 hw->l1[i].enabled = 0; in hfc_hardware_enable()
1353 hisax_unregister(&hw->l1[i].d_if); in hfc_hardware_enable()
1354 del_timer(&hw->l1[i].l1_timer); in hfc_hardware_enable()
1355 skb_queue_purge(&hw->l1[i].d_tx_queue); in hfc_hardware_enable()
1356 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); in hfc_hardware_enable()
1357 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); in hfc_hardware_enable()
1359 chipreset(hw); in hfc_hardware_enable()
1367 release_pci_ports(hfc4s8s_hw *hw) in release_pci_ports() argument
1369 pci_write_config_word(hw->pdev, PCI_COMMAND, 0); in release_pci_ports()
1370 if (hw->iobase) in release_pci_ports()
1371 release_region(hw->iobase, 8); in release_pci_ports()
1378 enable_pci_ports(hfc4s8s_hw *hw) in enable_pci_ports() argument
1380 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); in enable_pci_ports()
1388 setup_instance(hfc4s8s_hw *hw) in setup_instance() argument
1396 l1p = hw->l1 + i; in setup_instance()
1398 l1p->hw = hw; in setup_instance()
1404 l1p->d_if.ifc.priv = hw->l1 + i; in setup_instance()
1410 l1p->b_ch[0].l1p = hw->l1 + i; in setup_instance()
1418 l1p->b_ch[1].l1p = hw->l1 + i; in setup_instance()
1424 enable_pci_ports(hw); in setup_instance()
1425 chipreset(hw); in setup_instance()
1427 i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT; in setup_instance()
1428 if (i != hw->driver_data.chip_id) { in setup_instance()
1431 i, hw->driver_data.chip_id); in setup_instance()
1435 i = Read_hfc8(hw, R_CHIP_RV) & 0xf; in setup_instance()
1442 INIT_WORK(&hw->tqueue, hfc4s8s_bh); in setup_instance()
1445 (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) { in setup_instance()
1448 hw->irq); in setup_instance()
1453 hw->iobase, hw->irq); in setup_instance()
1455 hfc_hardware_enable(hw, 1, 0); in setup_instance()
1460 hw->irq = 0; in setup_instance()
1461 release_pci_ports(hw); in setup_instance()
1462 kfree(hw); in setup_instance()
1474 hfc4s8s_hw *hw; in hfc4s8s_probe() local
1476 if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) { in hfc4s8s_probe()
1481 hw->pdev = pdev; in hfc4s8s_probe()
1487 hw->cardnum = card_cnt; in hfc4s8s_probe()
1488 sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum); in hfc4s8s_probe()
1490 driver_data->device_name, hw->card_name, pci_name(pdev)); in hfc4s8s_probe()
1492 spin_lock_init(&hw->lock); in hfc4s8s_probe()
1494 hw->driver_data = *driver_data; in hfc4s8s_probe()
1495 hw->irq = pdev->irq; in hfc4s8s_probe()
1496 hw->iobase = pci_resource_start(pdev, 0); in hfc4s8s_probe()
1498 if (!request_region(hw->iobase, 8, hw->card_name)) { in hfc4s8s_probe()
1501 hw->iobase); in hfc4s8s_probe()
1505 pci_set_drvdata(pdev, hw); in hfc4s8s_probe()
1506 err = setup_instance(hw); in hfc4s8s_probe()
1512 kfree(hw); in hfc4s8s_probe()
1522 hfc4s8s_hw *hw = pci_get_drvdata(pdev); in hfc4s8s_remove() local
1524 printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum); in hfc4s8s_remove()
1525 hfc_hardware_enable(hw, 0, 0); in hfc4s8s_remove()
1527 if (hw->irq) in hfc4s8s_remove()
1528 free_irq(hw->irq, hw); in hfc4s8s_remove()
1529 hw->irq = 0; in hfc4s8s_remove()
1530 release_pci_ports(hw); in hfc4s8s_remove()
1534 kfree(hw); in hfc4s8s_remove()