1/*
2 * Clock tree for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/syscore_ops.h>
17
18#include "prima2.h"
19#include "clk-common.c"
20
21static struct clk_dmn clk_mmc01 = {
22	.regofs = SIRFSOC_CLKC_MMC_CFG,
23	.enable_bit = 59,
24	.hw = {
25		.init = &clk_mmc01_init,
26	},
27};
28
29static struct clk_dmn clk_mmc23 = {
30	.regofs = SIRFSOC_CLKC_MMC_CFG,
31	.enable_bit = 60,
32	.hw = {
33		.init = &clk_mmc23_init,
34	},
35};
36
37static struct clk_dmn clk_mmc45 = {
38	.regofs = SIRFSOC_CLKC_MMC_CFG,
39	.enable_bit = 61,
40	.hw = {
41		.init = &clk_mmc45_init,
42	},
43};
44
45static struct clk_init_data clk_nand_init = {
46	.name = "nand",
47	.ops = &ios_ops,
48	.parent_names = std_clk_io_parents,
49	.num_parents = ARRAY_SIZE(std_clk_io_parents),
50};
51
52static struct clk_std clk_nand = {
53	.enable_bit = 34,
54	.hw = {
55		.init = &clk_nand_init,
56	},
57};
58
59enum prima2_clk_index {
60	/* 0    1     2      3      4      5      6       7         8      9 */
61	rtc,    osc,   pll1,  pll2,  pll3,  mem,   sys,   security, dsp,   gps,
62	mf,     io,    cpu,   uart0, uart1, uart2, tsc,   i2c0,     i2c1,  spi0,
63	spi1,   pwmc,  efuse, pulse, dmac0, dmac1, nand,  audio,    usp0,  usp1,
64	usp2,   vip,   gfx,   mm,    lcd,   vpp,   mmc01, mmc23,    mmc45, usbpll,
65	usb0,  usb1,   cphif, maxclk,
66};
67
68static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
69	NULL, /* dummy */
70	NULL,
71	&clk_pll1.hw,
72	&clk_pll2.hw,
73	&clk_pll3.hw,
74	&clk_mem.hw,
75	&clk_sys.hw,
76	&clk_security.hw,
77	&clk_dsp.hw,
78	&clk_gps.hw,
79	&clk_mf.hw,
80	&clk_io.hw,
81	&clk_cpu.hw,
82	&clk_uart0.hw,
83	&clk_uart1.hw,
84	&clk_uart2.hw,
85	&clk_tsc.hw,
86	&clk_i2c0.hw,
87	&clk_i2c1.hw,
88	&clk_spi0.hw,
89	&clk_spi1.hw,
90	&clk_pwmc.hw,
91	&clk_efuse.hw,
92	&clk_pulse.hw,
93	&clk_dmac0.hw,
94	&clk_dmac1.hw,
95	&clk_nand.hw,
96	&clk_audio.hw,
97	&clk_usp0.hw,
98	&clk_usp1.hw,
99	&clk_usp2.hw,
100	&clk_vip.hw,
101	&clk_gfx.hw,
102	&clk_mm.hw,
103	&clk_lcd.hw,
104	&clk_vpp.hw,
105	&clk_mmc01.hw,
106	&clk_mmc23.hw,
107	&clk_mmc45.hw,
108	&usb_pll_clk_hw,
109	&clk_usb0.hw,
110	&clk_usb1.hw,
111	&clk_cphif.hw,
112};
113
114static struct clk *prima2_clks[maxclk];
115
116static void __init prima2_clk_init(struct device_node *np)
117{
118	struct device_node *rscnp;
119	int i;
120
121	rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
122	sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
123	if (!sirfsoc_rsc_vbase)
124		panic("unable to map rsc registers\n");
125	of_node_put(rscnp);
126
127	sirfsoc_clk_vbase = of_iomap(np, 0);
128	if (!sirfsoc_clk_vbase)
129		panic("unable to map clkc registers\n");
130
131	/* These are always available (RTC and 26MHz OSC)*/
132	prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
133		CLK_IS_ROOT, 32768);
134	prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
135		CLK_IS_ROOT, 26000000);
136
137	for (i = pll1; i < maxclk; i++) {
138		prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
139		BUG_ON(!prima2_clks[i]);
140	}
141	clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
142	clk_register_clkdev(prima2_clks[io],  NULL, "io");
143	clk_register_clkdev(prima2_clks[mem],  NULL, "mem");
144	clk_register_clkdev(prima2_clks[mem],  NULL, "osc");
145
146	clk_data.clks = prima2_clks;
147	clk_data.clk_num = maxclk;
148
149	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
150}
151CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);
152