Lines Matching refs:hw
472 int intelfbhw_active_pipe(const struct intelfb_hwstate *hw) in intelfbhw_active_pipe() argument
477 if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) { in intelfbhw_active_pipe()
478 pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_active_pipe()
483 if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) { in intelfbhw_active_pipe()
484 pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_active_pipe()
517 struct intelfb_hwstate *hw, int flag) in intelfbhw_read_hw_state() argument
525 if (!hw || !dinfo) in intelfbhw_read_hw_state()
529 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()
530 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()
531 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()
532 hw->dpll_a = INREG(DPLL_A); in intelfbhw_read_hw_state()
533 hw->dpll_b = INREG(DPLL_B); in intelfbhw_read_hw_state()
534 hw->fpa0 = INREG(FPA0); in intelfbhw_read_hw_state()
535 hw->fpa1 = INREG(FPA1); in intelfbhw_read_hw_state()
536 hw->fpb0 = INREG(FPB0); in intelfbhw_read_hw_state()
537 hw->fpb1 = INREG(FPB1); in intelfbhw_read_hw_state()
545 hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); in intelfbhw_read_hw_state()
546 hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); in intelfbhw_read_hw_state()
553 hw->htotal_a = INREG(HTOTAL_A); in intelfbhw_read_hw_state()
554 hw->hblank_a = INREG(HBLANK_A); in intelfbhw_read_hw_state()
555 hw->hsync_a = INREG(HSYNC_A); in intelfbhw_read_hw_state()
556 hw->vtotal_a = INREG(VTOTAL_A); in intelfbhw_read_hw_state()
557 hw->vblank_a = INREG(VBLANK_A); in intelfbhw_read_hw_state()
558 hw->vsync_a = INREG(VSYNC_A); in intelfbhw_read_hw_state()
559 hw->src_size_a = INREG(SRC_SIZE_A); in intelfbhw_read_hw_state()
560 hw->bclrpat_a = INREG(BCLRPAT_A); in intelfbhw_read_hw_state()
561 hw->htotal_b = INREG(HTOTAL_B); in intelfbhw_read_hw_state()
562 hw->hblank_b = INREG(HBLANK_B); in intelfbhw_read_hw_state()
563 hw->hsync_b = INREG(HSYNC_B); in intelfbhw_read_hw_state()
564 hw->vtotal_b = INREG(VTOTAL_B); in intelfbhw_read_hw_state()
565 hw->vblank_b = INREG(VBLANK_B); in intelfbhw_read_hw_state()
566 hw->vsync_b = INREG(VSYNC_B); in intelfbhw_read_hw_state()
567 hw->src_size_b = INREG(SRC_SIZE_B); in intelfbhw_read_hw_state()
568 hw->bclrpat_b = INREG(BCLRPAT_B); in intelfbhw_read_hw_state()
573 hw->adpa = INREG(ADPA); in intelfbhw_read_hw_state()
574 hw->dvoa = INREG(DVOA); in intelfbhw_read_hw_state()
575 hw->dvob = INREG(DVOB); in intelfbhw_read_hw_state()
576 hw->dvoc = INREG(DVOC); in intelfbhw_read_hw_state()
577 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); in intelfbhw_read_hw_state()
578 hw->dvob_srcdim = INREG(DVOB_SRCDIM); in intelfbhw_read_hw_state()
579 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); in intelfbhw_read_hw_state()
580 hw->lvds = INREG(LVDS); in intelfbhw_read_hw_state()
585 hw->pipe_a_conf = INREG(PIPEACONF); in intelfbhw_read_hw_state()
586 hw->pipe_b_conf = INREG(PIPEBCONF); in intelfbhw_read_hw_state()
587 hw->disp_arb = INREG(DISPARB); in intelfbhw_read_hw_state()
592 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); in intelfbhw_read_hw_state()
593 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); in intelfbhw_read_hw_state()
594 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); in intelfbhw_read_hw_state()
595 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); in intelfbhw_read_hw_state()
601 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); in intelfbhw_read_hw_state()
602 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); in intelfbhw_read_hw_state()
608 hw->cursor_size = INREG(CURSOR_SIZE); in intelfbhw_read_hw_state()
613 hw->disp_a_ctrl = INREG(DSPACNTR); in intelfbhw_read_hw_state()
614 hw->disp_b_ctrl = INREG(DSPBCNTR); in intelfbhw_read_hw_state()
615 hw->disp_a_base = INREG(DSPABASE); in intelfbhw_read_hw_state()
616 hw->disp_b_base = INREG(DSPBBASE); in intelfbhw_read_hw_state()
617 hw->disp_a_stride = INREG(DSPASTRIDE); in intelfbhw_read_hw_state()
618 hw->disp_b_stride = INREG(DSPBSTRIDE); in intelfbhw_read_hw_state()
623 hw->vgacntrl = INREG(VGACNTRL); in intelfbhw_read_hw_state()
628 hw->add_id = INREG(ADD_ID); in intelfbhw_read_hw_state()
634 hw->swf0x[i] = INREG(SWF00 + (i << 2)); in intelfbhw_read_hw_state()
635 hw->swf1x[i] = INREG(SWF10 + (i << 2)); in intelfbhw_read_hw_state()
637 hw->swf3x[i] = INREG(SWF30 + (i << 2)); in intelfbhw_read_hw_state()
641 hw->fence[i] = INREG(FENCE + (i << 2)); in intelfbhw_read_hw_state()
643 hw->instpm = INREG(INSTPM); in intelfbhw_read_hw_state()
644 hw->mem_mode = INREG(MEM_MODE); in intelfbhw_read_hw_state()
645 hw->fw_blc_0 = INREG(FW_BLC_0); in intelfbhw_read_hw_state()
646 hw->fw_blc_1 = INREG(FW_BLC_1); in intelfbhw_read_hw_state()
648 hw->hwstam = INREG16(HWSTAM); in intelfbhw_read_hw_state()
649 hw->ier = INREG16(IER); in intelfbhw_read_hw_state()
650 hw->iir = INREG16(IIR); in intelfbhw_read_hw_state()
651 hw->imr = INREG16(IMR); in intelfbhw_read_hw_state()
711 struct intelfb_hwstate *hw) in intelfbhw_print_hw_state() argument
718 if (!hw) in intelfbhw_print_hw_state()
722 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); in intelfbhw_print_hw_state()
723 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); in intelfbhw_print_hw_state()
724 printk(" VGAPD: 0x%08x\n", hw->vga_pd); in intelfbhw_print_hw_state()
725 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
726 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
727 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
729 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); in intelfbhw_print_hw_state()
736 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
737 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
738 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
740 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); in intelfbhw_print_hw_state()
746 printk(" DPLL_A: 0x%08x\n", hw->dpll_a); in intelfbhw_print_hw_state()
747 printk(" DPLL_B: 0x%08x\n", hw->dpll_b); in intelfbhw_print_hw_state()
748 printk(" FPA0: 0x%08x\n", hw->fpa0); in intelfbhw_print_hw_state()
749 printk(" FPA1: 0x%08x\n", hw->fpa1); in intelfbhw_print_hw_state()
750 printk(" FPB0: 0x%08x\n", hw->fpb0); in intelfbhw_print_hw_state()
751 printk(" FPB1: 0x%08x\n", hw->fpb1); in intelfbhw_print_hw_state()
753 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
754 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
755 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
757 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); in intelfbhw_print_hw_state()
764 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
765 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
766 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
768 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); in intelfbhw_print_hw_state()
778 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]); in intelfbhw_print_hw_state()
781 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]); in intelfbhw_print_hw_state()
784 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); in intelfbhw_print_hw_state()
785 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); in intelfbhw_print_hw_state()
786 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); in intelfbhw_print_hw_state()
787 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); in intelfbhw_print_hw_state()
788 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); in intelfbhw_print_hw_state()
789 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); in intelfbhw_print_hw_state()
790 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); in intelfbhw_print_hw_state()
791 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); in intelfbhw_print_hw_state()
792 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); in intelfbhw_print_hw_state()
793 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); in intelfbhw_print_hw_state()
794 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); in intelfbhw_print_hw_state()
795 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); in intelfbhw_print_hw_state()
796 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); in intelfbhw_print_hw_state()
797 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); in intelfbhw_print_hw_state()
798 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); in intelfbhw_print_hw_state()
799 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); in intelfbhw_print_hw_state()
801 printk(" ADPA: 0x%08x\n", hw->adpa); in intelfbhw_print_hw_state()
802 printk(" DVOA: 0x%08x\n", hw->dvoa); in intelfbhw_print_hw_state()
803 printk(" DVOB: 0x%08x\n", hw->dvob); in intelfbhw_print_hw_state()
804 printk(" DVOC: 0x%08x\n", hw->dvoc); in intelfbhw_print_hw_state()
805 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); in intelfbhw_print_hw_state()
806 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); in intelfbhw_print_hw_state()
807 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); in intelfbhw_print_hw_state()
808 printk(" LVDS: 0x%08x\n", hw->lvds); in intelfbhw_print_hw_state()
810 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); in intelfbhw_print_hw_state()
811 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); in intelfbhw_print_hw_state()
812 printk(" DISPARB: 0x%08x\n", hw->disp_arb); in intelfbhw_print_hw_state()
814 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); in intelfbhw_print_hw_state()
815 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); in intelfbhw_print_hw_state()
816 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); in intelfbhw_print_hw_state()
817 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); in intelfbhw_print_hw_state()
821 printk("0x%08x", hw->cursor_a_palette[i]); in intelfbhw_print_hw_state()
828 printk("0x%08x", hw->cursor_b_palette[i]); in intelfbhw_print_hw_state()
834 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); in intelfbhw_print_hw_state()
836 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); in intelfbhw_print_hw_state()
837 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); in intelfbhw_print_hw_state()
838 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); in intelfbhw_print_hw_state()
839 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); in intelfbhw_print_hw_state()
840 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); in intelfbhw_print_hw_state()
841 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); in intelfbhw_print_hw_state()
843 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); in intelfbhw_print_hw_state()
844 printk(" ADD_ID: 0x%08x\n", hw->add_id); in intelfbhw_print_hw_state()
848 hw->swf0x[i]); in intelfbhw_print_hw_state()
852 hw->swf1x[i]); in intelfbhw_print_hw_state()
856 hw->swf3x[i]); in intelfbhw_print_hw_state()
860 hw->fence[i]); in intelfbhw_print_hw_state()
862 printk(" INSTPM 0x%08x\n", hw->instpm); in intelfbhw_print_hw_state()
863 printk(" MEM_MODE 0x%08x\n", hw->mem_mode); in intelfbhw_print_hw_state()
864 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); in intelfbhw_print_hw_state()
865 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); in intelfbhw_print_hw_state()
867 printk(" HWSTAM 0x%04x\n", hw->hwstam); in intelfbhw_print_hw_state()
868 printk(" IER 0x%04x\n", hw->ier); in intelfbhw_print_hw_state()
869 printk(" IIR 0x%04x\n", hw->iir); in intelfbhw_print_hw_state()
870 printk(" IMR 0x%04x\n", hw->imr); in intelfbhw_print_hw_state()
1044 struct intelfb_hwstate *hw, in intelfbhw_mode_to_hw() argument
1047 int pipe = intelfbhw_active_pipe(hw); in intelfbhw_mode_to_hw()
1059 hw->vgacntrl |= VGA_DISABLE; in intelfbhw_mode_to_hw()
1063 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1064 fp0 = &hw->fpb0; in intelfbhw_mode_to_hw()
1065 fp1 = &hw->fpb1; in intelfbhw_mode_to_hw()
1066 hs = &hw->hsync_b; in intelfbhw_mode_to_hw()
1067 hb = &hw->hblank_b; in intelfbhw_mode_to_hw()
1068 ht = &hw->htotal_b; in intelfbhw_mode_to_hw()
1069 vs = &hw->vsync_b; in intelfbhw_mode_to_hw()
1070 vb = &hw->vblank_b; in intelfbhw_mode_to_hw()
1071 vt = &hw->vtotal_b; in intelfbhw_mode_to_hw()
1072 ss = &hw->src_size_b; in intelfbhw_mode_to_hw()
1073 pipe_conf = &hw->pipe_b_conf; in intelfbhw_mode_to_hw()
1075 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
1076 fp0 = &hw->fpa0; in intelfbhw_mode_to_hw()
1077 fp1 = &hw->fpa1; in intelfbhw_mode_to_hw()
1078 hs = &hw->hsync_a; in intelfbhw_mode_to_hw()
1079 hb = &hw->hblank_a; in intelfbhw_mode_to_hw()
1080 ht = &hw->htotal_a; in intelfbhw_mode_to_hw()
1081 vs = &hw->vsync_a; in intelfbhw_mode_to_hw()
1082 vb = &hw->vblank_a; in intelfbhw_mode_to_hw()
1083 vt = &hw->vtotal_a; in intelfbhw_mode_to_hw()
1084 ss = &hw->src_size_a; in intelfbhw_mode_to_hw()
1085 pipe_conf = &hw->pipe_a_conf; in intelfbhw_mode_to_hw()
1089 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; in intelfbhw_mode_to_hw()
1096 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | in intelfbhw_mode_to_hw()
1098 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | in intelfbhw_mode_to_hw()
1102 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); in intelfbhw_mode_to_hw()
1103 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); in intelfbhw_mode_to_hw()
1106 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; in intelfbhw_mode_to_hw()
1107 hw->adpa |= ADPA_DPMS_D0; in intelfbhw_mode_to_hw()
1109 hw->adpa |= ADPA_DAC_ENABLE; in intelfbhw_mode_to_hw()
1151 hw->dvob &= ~PORT_ENABLE; in intelfbhw_mode_to_hw()
1152 hw->dvoc &= ~PORT_ENABLE; in intelfbhw_mode_to_hw()
1155 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; in intelfbhw_mode_to_hw()
1156 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; in intelfbhw_mode_to_hw()
1157 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; in intelfbhw_mode_to_hw()
1160 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; in intelfbhw_mode_to_hw()
1163 hw->disp_a_ctrl |= DISPPLANE_15_16BPP; in intelfbhw_mode_to_hw()
1166 hw->disp_a_ctrl |= DISPPLANE_16BPP; in intelfbhw_mode_to_hw()
1169 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; in intelfbhw_mode_to_hw()
1172 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_mode_to_hw()
1173 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_mode_to_hw()
1251 hw->disp_a_stride = dinfo->pitch; in intelfbhw_mode_to_hw()
1252 DBG_MSG("pitch is %d\n", hw->disp_a_stride); in intelfbhw_mode_to_hw()
1254 hw->disp_a_base = hw->disp_a_stride * var->yoffset + in intelfbhw_mode_to_hw()
1257 hw->disp_a_base += dinfo->fb.offset << 12; in intelfbhw_mode_to_hw()
1262 if (hw->disp_a_stride % stride_alignment != 0) { in intelfbhw_mode_to_hw()
1264 hw->disp_a_stride, stride_alignment); in intelfbhw_mode_to_hw()
1281 const struct intelfb_hwstate *hw, int blank) in intelfbhw_program_mode() argument
1303 dinfo->pipe = intelfbhw_active_pipe(hw); in intelfbhw_program_mode()
1306 dpll = &hw->dpll_b; in intelfbhw_program_mode()
1307 fp0 = &hw->fpb0; in intelfbhw_program_mode()
1308 fp1 = &hw->fpb1; in intelfbhw_program_mode()
1309 pipe_conf = &hw->pipe_b_conf; in intelfbhw_program_mode()
1310 hs = &hw->hsync_b; in intelfbhw_program_mode()
1311 hb = &hw->hblank_b; in intelfbhw_program_mode()
1312 ht = &hw->htotal_b; in intelfbhw_program_mode()
1313 vs = &hw->vsync_b; in intelfbhw_program_mode()
1314 vb = &hw->vblank_b; in intelfbhw_program_mode()
1315 vt = &hw->vtotal_b; in intelfbhw_program_mode()
1316 ss = &hw->src_size_b; in intelfbhw_program_mode()
1330 dpll = &hw->dpll_a; in intelfbhw_program_mode()
1331 fp0 = &hw->fpa0; in intelfbhw_program_mode()
1332 fp1 = &hw->fpa1; in intelfbhw_program_mode()
1333 pipe_conf = &hw->pipe_a_conf; in intelfbhw_program_mode()
1334 hs = &hw->hsync_a; in intelfbhw_program_mode()
1335 hb = &hw->hblank_a; in intelfbhw_program_mode()
1336 ht = &hw->htotal_a; in intelfbhw_program_mode()
1337 vs = &hw->vsync_a; in intelfbhw_program_mode()
1338 vb = &hw->vblank_a; in intelfbhw_program_mode()
1339 vt = &hw->vtotal_a; in intelfbhw_program_mode()
1340 ss = &hw->src_size_a; in intelfbhw_program_mode()
1413 OUTREG(DVOB, hw->dvob); in intelfbhw_program_mode()
1414 OUTREG(DVOC, hw->dvoc); in intelfbhw_program_mode()
1421 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); in intelfbhw_program_mode()
1464 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); in intelfbhw_program_mode()
1469 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); in intelfbhw_program_mode()
1470 OUTREG(DSPASTRIDE, hw->disp_a_stride); in intelfbhw_program_mode()
1471 OUTREG(DSPABASE, hw->disp_a_base); in intelfbhw_program_mode()
1478 OUTREG(DSPABASE, hw->disp_a_base); in intelfbhw_program_mode()