Lines Matching refs:hw
38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) in ixgbe_device_supports_autoneg_fc() argument
80 switch (hw->phy.media_type) { in ixgbe_device_supports_autoneg_fc()
82 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_device_supports_autoneg_fc()
95 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
119 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw) in ixgbe_setup_fc() argument
130 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { in ixgbe_setup_fc()
131 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); in ixgbe_setup_fc()
139 if (hw->fc.requested_mode == ixgbe_fc_default) in ixgbe_setup_fc()
140 hw->fc.requested_mode = ixgbe_fc_full; in ixgbe_setup_fc()
147 switch (hw->phy.media_type) { in ixgbe_setup_fc()
150 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); in ixgbe_setup_fc()
156 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc()
160 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc()
177 switch (hw->fc.requested_mode) { in ixgbe_setup_fc()
181 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc()
184 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc()
194 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc()
197 } else if (hw->phy.media_type == ixgbe_media_type_copper) { in ixgbe_setup_fc()
215 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc()
218 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc()
222 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_setup_fc()
226 if (hw->mac.type != ixgbe_mac_X540) { in ixgbe_setup_fc()
231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc()
232 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); in ixgbe_setup_fc()
235 if (hw->fc.strict_ieee) in ixgbe_setup_fc()
238 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc()
239 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); in ixgbe_setup_fc()
247 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc()
252 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); in ixgbe_setup_fc()
256 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && in ixgbe_setup_fc()
257 ixgbe_device_supports_autoneg_fc(hw)) { in ixgbe_setup_fc()
258 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc()
262 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); in ixgbe_setup_fc()
275 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) in ixgbe_start_hw_generic() argument
281 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
284 hw->phy.ops.identify(hw); in ixgbe_start_hw_generic()
287 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
290 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
293 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_start_hw_generic()
295 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
296 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_generic()
299 ret_val = ixgbe_setup_fc(hw); in ixgbe_start_hw_generic()
304 hw->adapter_stopped = false; in ixgbe_start_hw_generic()
319 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) in ixgbe_start_hw_gen2() argument
324 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
325 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
326 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
328 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_gen2()
332 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
335 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); in ixgbe_start_hw_gen2()
337 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); in ixgbe_start_hw_gen2()
340 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_start_hw_gen2()
343 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_gen2()
346 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
362 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) in ixgbe_init_hw_generic() argument
367 status = hw->mac.ops.reset_hw(hw); in ixgbe_init_hw_generic()
371 status = hw->mac.ops.start_hw(hw); in ixgbe_init_hw_generic()
384 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) in ixgbe_clear_hw_cntrs_generic() argument
388 IXGBE_READ_REG(hw, IXGBE_CRCERRS); in ixgbe_clear_hw_cntrs_generic()
389 IXGBE_READ_REG(hw, IXGBE_ILLERRC); in ixgbe_clear_hw_cntrs_generic()
390 IXGBE_READ_REG(hw, IXGBE_ERRBC); in ixgbe_clear_hw_cntrs_generic()
391 IXGBE_READ_REG(hw, IXGBE_MSPDC); in ixgbe_clear_hw_cntrs_generic()
393 IXGBE_READ_REG(hw, IXGBE_MPC(i)); in ixgbe_clear_hw_cntrs_generic()
395 IXGBE_READ_REG(hw, IXGBE_MLFC); in ixgbe_clear_hw_cntrs_generic()
396 IXGBE_READ_REG(hw, IXGBE_MRFC); in ixgbe_clear_hw_cntrs_generic()
397 IXGBE_READ_REG(hw, IXGBE_RLEC); in ixgbe_clear_hw_cntrs_generic()
398 IXGBE_READ_REG(hw, IXGBE_LXONTXC); in ixgbe_clear_hw_cntrs_generic()
399 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); in ixgbe_clear_hw_cntrs_generic()
400 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
401 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); in ixgbe_clear_hw_cntrs_generic()
402 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); in ixgbe_clear_hw_cntrs_generic()
404 IXGBE_READ_REG(hw, IXGBE_LXONRXC); in ixgbe_clear_hw_cntrs_generic()
405 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); in ixgbe_clear_hw_cntrs_generic()
409 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); in ixgbe_clear_hw_cntrs_generic()
410 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); in ixgbe_clear_hw_cntrs_generic()
411 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
412 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
413 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
415 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); in ixgbe_clear_hw_cntrs_generic()
416 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); in ixgbe_clear_hw_cntrs_generic()
419 if (hw->mac.type >= ixgbe_mac_82599EB) in ixgbe_clear_hw_cntrs_generic()
421 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); in ixgbe_clear_hw_cntrs_generic()
422 IXGBE_READ_REG(hw, IXGBE_PRC64); in ixgbe_clear_hw_cntrs_generic()
423 IXGBE_READ_REG(hw, IXGBE_PRC127); in ixgbe_clear_hw_cntrs_generic()
424 IXGBE_READ_REG(hw, IXGBE_PRC255); in ixgbe_clear_hw_cntrs_generic()
425 IXGBE_READ_REG(hw, IXGBE_PRC511); in ixgbe_clear_hw_cntrs_generic()
426 IXGBE_READ_REG(hw, IXGBE_PRC1023); in ixgbe_clear_hw_cntrs_generic()
427 IXGBE_READ_REG(hw, IXGBE_PRC1522); in ixgbe_clear_hw_cntrs_generic()
428 IXGBE_READ_REG(hw, IXGBE_GPRC); in ixgbe_clear_hw_cntrs_generic()
429 IXGBE_READ_REG(hw, IXGBE_BPRC); in ixgbe_clear_hw_cntrs_generic()
430 IXGBE_READ_REG(hw, IXGBE_MPRC); in ixgbe_clear_hw_cntrs_generic()
431 IXGBE_READ_REG(hw, IXGBE_GPTC); in ixgbe_clear_hw_cntrs_generic()
432 IXGBE_READ_REG(hw, IXGBE_GORCL); in ixgbe_clear_hw_cntrs_generic()
433 IXGBE_READ_REG(hw, IXGBE_GORCH); in ixgbe_clear_hw_cntrs_generic()
434 IXGBE_READ_REG(hw, IXGBE_GOTCL); in ixgbe_clear_hw_cntrs_generic()
435 IXGBE_READ_REG(hw, IXGBE_GOTCH); in ixgbe_clear_hw_cntrs_generic()
436 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_clear_hw_cntrs_generic()
438 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); in ixgbe_clear_hw_cntrs_generic()
439 IXGBE_READ_REG(hw, IXGBE_RUC); in ixgbe_clear_hw_cntrs_generic()
440 IXGBE_READ_REG(hw, IXGBE_RFC); in ixgbe_clear_hw_cntrs_generic()
441 IXGBE_READ_REG(hw, IXGBE_ROC); in ixgbe_clear_hw_cntrs_generic()
442 IXGBE_READ_REG(hw, IXGBE_RJC); in ixgbe_clear_hw_cntrs_generic()
443 IXGBE_READ_REG(hw, IXGBE_MNGPRC); in ixgbe_clear_hw_cntrs_generic()
444 IXGBE_READ_REG(hw, IXGBE_MNGPDC); in ixgbe_clear_hw_cntrs_generic()
445 IXGBE_READ_REG(hw, IXGBE_MNGPTC); in ixgbe_clear_hw_cntrs_generic()
446 IXGBE_READ_REG(hw, IXGBE_TORL); in ixgbe_clear_hw_cntrs_generic()
447 IXGBE_READ_REG(hw, IXGBE_TORH); in ixgbe_clear_hw_cntrs_generic()
448 IXGBE_READ_REG(hw, IXGBE_TPR); in ixgbe_clear_hw_cntrs_generic()
449 IXGBE_READ_REG(hw, IXGBE_TPT); in ixgbe_clear_hw_cntrs_generic()
450 IXGBE_READ_REG(hw, IXGBE_PTC64); in ixgbe_clear_hw_cntrs_generic()
451 IXGBE_READ_REG(hw, IXGBE_PTC127); in ixgbe_clear_hw_cntrs_generic()
452 IXGBE_READ_REG(hw, IXGBE_PTC255); in ixgbe_clear_hw_cntrs_generic()
453 IXGBE_READ_REG(hw, IXGBE_PTC511); in ixgbe_clear_hw_cntrs_generic()
454 IXGBE_READ_REG(hw, IXGBE_PTC1023); in ixgbe_clear_hw_cntrs_generic()
455 IXGBE_READ_REG(hw, IXGBE_PTC1522); in ixgbe_clear_hw_cntrs_generic()
456 IXGBE_READ_REG(hw, IXGBE_MPTC); in ixgbe_clear_hw_cntrs_generic()
457 IXGBE_READ_REG(hw, IXGBE_BPTC); in ixgbe_clear_hw_cntrs_generic()
459 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); in ixgbe_clear_hw_cntrs_generic()
460 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); in ixgbe_clear_hw_cntrs_generic()
461 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
462 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); in ixgbe_clear_hw_cntrs_generic()
463 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); in ixgbe_clear_hw_cntrs_generic()
464 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); in ixgbe_clear_hw_cntrs_generic()
465 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); in ixgbe_clear_hw_cntrs_generic()
466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); in ixgbe_clear_hw_cntrs_generic()
468 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); in ixgbe_clear_hw_cntrs_generic()
469 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); in ixgbe_clear_hw_cntrs_generic()
473 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { in ixgbe_clear_hw_cntrs_generic()
474 if (hw->phy.id == 0) in ixgbe_clear_hw_cntrs_generic()
475 hw->phy.ops.identify(hw); in ixgbe_clear_hw_cntrs_generic()
476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
477 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
479 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
493 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, in ixgbe_read_pba_string_generic() argument
503 hw_dbg(hw, "PBA string buffer was null\n"); in ixgbe_read_pba_string_generic()
507 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_string_generic()
509 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
513 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); in ixgbe_read_pba_string_generic()
515 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
525 hw_dbg(hw, "NVM PBA number is not stored as string\n"); in ixgbe_read_pba_string_generic()
529 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
559 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); in ixgbe_read_pba_string_generic()
561 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
566 hw_dbg(hw, "NVM PBA number section invalid length\n"); in ixgbe_read_pba_string_generic()
572 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
581 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); in ixgbe_read_pba_string_generic()
583 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
603 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) in ixgbe_get_mac_addr_generic() argument
609 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); in ixgbe_get_mac_addr_generic()
610 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); in ixgbe_get_mac_addr_generic()
657 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) in ixgbe_get_bus_info_generic() argument
661 hw->bus.type = ixgbe_bus_type_pci_express; in ixgbe_get_bus_info_generic()
664 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); in ixgbe_get_bus_info_generic()
666 hw->bus.width = ixgbe_convert_bus_width(link_status); in ixgbe_get_bus_info_generic()
667 hw->bus.speed = ixgbe_convert_bus_speed(link_status); in ixgbe_get_bus_info_generic()
669 hw->mac.ops.set_lan_id(hw); in ixgbe_get_bus_info_generic()
681 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) in ixgbe_set_lan_id_multi_port_pcie() argument
683 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie()
686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_set_lan_id_multi_port_pcie()
691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); in ixgbe_set_lan_id_multi_port_pcie()
705 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) in ixgbe_stop_adapter_generic() argument
714 hw->adapter_stopped = true; in ixgbe_stop_adapter_generic()
717 hw->mac.ops.disable_rx(hw); in ixgbe_stop_adapter_generic()
720 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
723 IXGBE_READ_REG(hw, IXGBE_EICR); in ixgbe_stop_adapter_generic()
726 for (i = 0; i < hw->mac.max_tx_queues; i++) in ixgbe_stop_adapter_generic()
727 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
730 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_stop_adapter_generic()
731 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); in ixgbe_stop_adapter_generic()
734 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
738 IXGBE_WRITE_FLUSH(hw); in ixgbe_stop_adapter_generic()
745 return ixgbe_disable_pcie_master(hw); in ixgbe_stop_adapter_generic()
753 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_on_generic() argument
755 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_on_generic()
760 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_on_generic()
761 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_on_generic()
771 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_off_generic() argument
773 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_off_generic()
778 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_off_generic()
779 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_off_generic()
791 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) in ixgbe_init_eeprom_params_generic() argument
793 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_eeprom_params_generic()
809 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_init_eeprom_params_generic()
827 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", in ixgbe_init_eeprom_params_generic()
843 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang_generic() argument
849 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
854 if (offset + words > hw->eeprom.word_size) in ixgbe_write_eeprom_buffer_bit_bang_generic()
861 if ((hw->eeprom.word_page_size == 0) && in ixgbe_write_eeprom_buffer_bit_bang_generic()
863 ixgbe_detect_eeprom_page_size_generic(hw, offset); in ixgbe_write_eeprom_buffer_bit_bang_generic()
873 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_write_eeprom_buffer_bit_bang_generic()
893 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang() argument
903 status = ixgbe_acquire_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
907 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_write_eeprom_buffer_bit_bang()
908 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
913 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
916 ixgbe_shift_out_eeprom_bits(hw, in ixgbe_write_eeprom_buffer_bit_bang()
920 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
925 if ((hw->eeprom.address_bits == 8) && in ixgbe_write_eeprom_buffer_bit_bang()
930 ixgbe_shift_out_eeprom_bits(hw, write_opcode, in ixgbe_write_eeprom_buffer_bit_bang()
932 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_write_eeprom_buffer_bit_bang()
933 hw->eeprom.address_bits); in ixgbe_write_eeprom_buffer_bit_bang()
935 page_size = hw->eeprom.word_page_size; in ixgbe_write_eeprom_buffer_bit_bang()
941 ixgbe_shift_out_eeprom_bits(hw, word, 16); in ixgbe_write_eeprom_buffer_bit_bang()
952 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
956 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
970 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eeprom_generic() argument
972 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
974 if (offset >= hw->eeprom.word_size) in ixgbe_write_eeprom_generic()
977 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); in ixgbe_write_eeprom_generic()
989 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang_generic() argument
995 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1000 if (offset + words > hw->eeprom.word_size) in ixgbe_read_eeprom_buffer_bit_bang_generic()
1012 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_read_eeprom_buffer_bit_bang_generic()
1031 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang() argument
1040 status = ixgbe_acquire_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1044 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_read_eeprom_buffer_bit_bang()
1045 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1050 ixgbe_standby_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1054 if ((hw->eeprom.address_bits == 8) && in ixgbe_read_eeprom_buffer_bit_bang()
1059 ixgbe_shift_out_eeprom_bits(hw, read_opcode, in ixgbe_read_eeprom_buffer_bit_bang()
1061 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_read_eeprom_buffer_bit_bang()
1062 hw->eeprom.address_bits); in ixgbe_read_eeprom_buffer_bit_bang()
1065 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); in ixgbe_read_eeprom_buffer_bit_bang()
1070 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1083 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_bit_bang_generic() argument
1086 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_bit_bang_generic()
1088 if (offset >= hw->eeprom.word_size) in ixgbe_read_eeprom_bit_bang_generic()
1091 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_read_eeprom_bit_bang_generic()
1103 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eerd_buffer_generic() argument
1110 hw->eeprom.ops.init_params(hw); in ixgbe_read_eerd_buffer_generic()
1115 if (offset >= hw->eeprom.word_size) in ixgbe_read_eerd_buffer_generic()
1122 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); in ixgbe_read_eerd_buffer_generic()
1123 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); in ixgbe_read_eerd_buffer_generic()
1126 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> in ixgbe_read_eerd_buffer_generic()
1129 hw_dbg(hw, "Eeprom read timed out\n"); in ixgbe_read_eerd_buffer_generic()
1146 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, in ixgbe_detect_eeprom_page_size_generic() argument
1156 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; in ixgbe_detect_eeprom_page_size_generic()
1157 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, in ixgbe_detect_eeprom_page_size_generic()
1159 hw->eeprom.word_page_size = 0; in ixgbe_detect_eeprom_page_size_generic()
1163 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_detect_eeprom_page_size_generic()
1171 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; in ixgbe_detect_eeprom_page_size_generic()
1173 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", in ixgbe_detect_eeprom_page_size_generic()
1174 hw->eeprom.word_page_size); in ixgbe_detect_eeprom_page_size_generic()
1186 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) in ixgbe_read_eerd_generic() argument
1188 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); in ixgbe_read_eerd_generic()
1200 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eewr_buffer_generic() argument
1207 hw->eeprom.ops.init_params(hw); in ixgbe_write_eewr_buffer_generic()
1212 if (offset >= hw->eeprom.word_size) in ixgbe_write_eewr_buffer_generic()
1220 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1222 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1226 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); in ixgbe_write_eewr_buffer_generic()
1228 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1230 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1246 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eewr_generic() argument
1248 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); in ixgbe_write_eewr_generic()
1259 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) in ixgbe_poll_eerd_eewr_done() argument
1266 reg = IXGBE_READ_REG(hw, IXGBE_EERD); in ixgbe_poll_eerd_eewr_done()
1268 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); in ixgbe_poll_eerd_eewr_done()
1285 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) in ixgbe_acquire_eeprom() argument
1290 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) in ixgbe_acquire_eeprom()
1293 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1297 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1300 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1309 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1310 hw_dbg(hw, "Could not acquire EEPROM grant\n"); in ixgbe_acquire_eeprom()
1312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_acquire_eeprom()
1319 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1320 IXGBE_WRITE_FLUSH(hw); in ixgbe_acquire_eeprom()
1331 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_get_eeprom_semaphore() argument
1343 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1350 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1356 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1363 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1365 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); in ixgbe_get_eeprom_semaphore()
1372 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1376 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_get_eeprom_semaphore()
1381 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1392 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1393 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1406 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_release_eeprom_semaphore() argument
1410 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_release_eeprom_semaphore()
1414 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_release_eeprom_semaphore()
1415 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom_semaphore()
1422 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) in ixgbe_ready_eeprom() argument
1434 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, in ixgbe_ready_eeprom()
1436 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); in ixgbe_ready_eeprom()
1441 ixgbe_standby_eeprom(hw); in ixgbe_ready_eeprom()
1449 hw_dbg(hw, "SPI EEPROM Status error\n"); in ixgbe_ready_eeprom()
1460 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) in ixgbe_standby_eeprom() argument
1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_standby_eeprom()
1468 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1469 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1472 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1473 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1483 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, in ixgbe_shift_out_eeprom_bits() argument
1490 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_out_eeprom_bits()
1511 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1512 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1516 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1517 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1528 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1529 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1536 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) in ixgbe_shift_in_eeprom_bits() argument
1549 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1555 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1557 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1563 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1574 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_raise_eeprom_clk() argument
1581 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_raise_eeprom_clk()
1582 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_eeprom_clk()
1591 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_lower_eeprom_clk() argument
1598 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_lower_eeprom_clk()
1599 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_eeprom_clk()
1607 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) in ixgbe_release_eeprom() argument
1611 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_release_eeprom()
1616 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1617 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom()
1623 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1625 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_release_eeprom()
1631 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_release_eeprom()
1632 hw->eeprom.semaphore_delay * 2000); in ixgbe_release_eeprom()
1639 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_calc_eeprom_checksum_generic() argument
1650 if (hw->eeprom.ops.read(hw, i, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1651 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1659 if (hw->eeprom.ops.read(hw, i, &pointer)) { in ixgbe_calc_eeprom_checksum_generic()
1660 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1668 if (hw->eeprom.ops.read(hw, pointer, &length)) { in ixgbe_calc_eeprom_checksum_generic()
1669 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1677 if (hw->eeprom.ops.read(hw, j, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1678 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1698 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, in ixgbe_validate_eeprom_checksum_generic() argument
1710 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_validate_eeprom_checksum_generic()
1712 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1716 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_generic()
1722 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); in ixgbe_validate_eeprom_checksum_generic()
1724 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1745 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_update_eeprom_checksum_generic() argument
1755 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_update_eeprom_checksum_generic()
1757 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_update_eeprom_checksum_generic()
1761 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_update_eeprom_checksum_generic()
1767 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); in ixgbe_update_eeprom_checksum_generic()
1782 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_generic() argument
1786 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_rar_generic()
1790 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_set_rar_generic()
1795 hw->mac.ops.set_vmdq(hw, index, vmdq); in ixgbe_set_rar_generic()
1810 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_set_rar_generic()
1817 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); in ixgbe_set_rar_generic()
1818 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_set_rar_generic()
1830 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_clear_rar_generic() argument
1833 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_rar_generic()
1837 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_clear_rar_generic()
1846 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_clear_rar_generic()
1849 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); in ixgbe_clear_rar_generic()
1850 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_clear_rar_generic()
1853 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_clear_rar_generic()
1866 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) in ixgbe_init_rx_addrs_generic() argument
1869 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_init_rx_addrs_generic()
1876 if (!is_valid_ether_addr(hw->mac.addr)) { in ixgbe_init_rx_addrs_generic()
1878 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1880 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1883 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); in ixgbe_init_rx_addrs_generic()
1884 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1886 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
1889 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_init_rx_addrs_generic()
1891 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_init_rx_addrs_generic()
1893 hw->addr_ctrl.rar_used_count = 1; in ixgbe_init_rx_addrs_generic()
1896 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); in ixgbe_init_rx_addrs_generic()
1898 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); in ixgbe_init_rx_addrs_generic()
1899 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); in ixgbe_init_rx_addrs_generic()
1903 hw->addr_ctrl.mta_in_use = 0; in ixgbe_init_rx_addrs_generic()
1904 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_init_rx_addrs_generic()
1906 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_init_rx_addrs_generic()
1907 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_init_rx_addrs_generic()
1908 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); in ixgbe_init_rx_addrs_generic()
1910 if (hw->mac.ops.init_uta_tables) in ixgbe_init_rx_addrs_generic()
1911 hw->mac.ops.init_uta_tables(hw); in ixgbe_init_rx_addrs_generic()
1928 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_mta_vector() argument
1932 switch (hw->mac.mc_filter_type) { in ixgbe_mta_vector()
1946 hw_dbg(hw, "MC filter type param set incorrectly\n"); in ixgbe_mta_vector()
1962 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_set_mta() argument
1968 hw->addr_ctrl.mta_in_use++; in ixgbe_set_mta()
1970 vector = ixgbe_mta_vector(hw, mc_addr); in ixgbe_set_mta()
1971 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); in ixgbe_set_mta()
1984 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); in ixgbe_set_mta()
1997 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, in ixgbe_update_mc_addr_list_generic() argument
2007 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); in ixgbe_update_mc_addr_list_generic()
2008 hw->addr_ctrl.mta_in_use = 0; in ixgbe_update_mc_addr_list_generic()
2011 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_update_mc_addr_list_generic()
2012 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in ixgbe_update_mc_addr_list_generic()
2016 hw_dbg(hw, " Adding the multicast addresses:\n"); in ixgbe_update_mc_addr_list_generic()
2017 ixgbe_set_mta(hw, ha->addr); in ixgbe_update_mc_addr_list_generic()
2021 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_update_mc_addr_list_generic()
2022 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, in ixgbe_update_mc_addr_list_generic()
2023 hw->mac.mta_shadow[i]); in ixgbe_update_mc_addr_list_generic()
2025 if (hw->addr_ctrl.mta_in_use > 0) in ixgbe_update_mc_addr_list_generic()
2026 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, in ixgbe_update_mc_addr_list_generic()
2027 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); in ixgbe_update_mc_addr_list_generic()
2029 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); in ixgbe_update_mc_addr_list_generic()
2039 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) in ixgbe_enable_mc_generic() argument
2041 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_enable_mc_generic()
2044 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | in ixgbe_enable_mc_generic()
2045 hw->mac.mc_filter_type); in ixgbe_enable_mc_generic()
2056 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) in ixgbe_disable_mc_generic() argument
2058 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_disable_mc_generic()
2061 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_disable_mc_generic()
2072 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) in ixgbe_fc_enable_generic() argument
2080 if (!hw->fc.pause_time) in ixgbe_fc_enable_generic()
2085 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2086 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2087 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_generic()
2088 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2089 hw_dbg(hw, "Invalid water mark configuration\n"); in ixgbe_fc_enable_generic()
2096 ixgbe_fc_autoneg(hw); in ixgbe_fc_enable_generic()
2099 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); in ixgbe_fc_enable_generic()
2102 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); in ixgbe_fc_enable_generic()
2115 switch (hw->fc.current_mode) { in ixgbe_fc_enable_generic()
2146 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_fc_enable_generic()
2152 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); in ixgbe_fc_enable_generic()
2153 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); in ixgbe_fc_enable_generic()
2157 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2158 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2159 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_generic()
2160 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); in ixgbe_fc_enable_generic()
2161 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
2163 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); in ixgbe_fc_enable_generic()
2171 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; in ixgbe_fc_enable_generic()
2174 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); in ixgbe_fc_enable_generic()
2178 reg = hw->fc.pause_time * 0x00010001; in ixgbe_fc_enable_generic()
2180 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_generic()
2182 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_generic()
2200 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, in ixgbe_negotiate_fc() argument
2214 if (hw->fc.requested_mode == ixgbe_fc_full) { in ixgbe_negotiate_fc()
2215 hw->fc.current_mode = ixgbe_fc_full; in ixgbe_negotiate_fc()
2216 hw_dbg(hw, "Flow Control = FULL.\n"); in ixgbe_negotiate_fc()
2218 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2219 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); in ixgbe_negotiate_fc()
2223 hw->fc.current_mode = ixgbe_fc_tx_pause; in ixgbe_negotiate_fc()
2224 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2227 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2228 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2230 hw->fc.current_mode = ixgbe_fc_none; in ixgbe_negotiate_fc()
2231 hw_dbg(hw, "Flow Control = NONE.\n"); in ixgbe_negotiate_fc()
2242 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_fiber() argument
2253 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); in ixgbe_fc_autoneg_fiber()
2258 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_fc_autoneg_fiber()
2259 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); in ixgbe_fc_autoneg_fiber()
2261 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, in ixgbe_fc_autoneg_fiber()
2276 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_backplane() argument
2286 links = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_fc_autoneg_backplane()
2290 if (hw->mac.type == ixgbe_mac_82599EB) { in ixgbe_fc_autoneg_backplane()
2291 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); in ixgbe_fc_autoneg_backplane()
2299 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_fc_autoneg_backplane()
2300 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_fc_autoneg_backplane()
2302 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, in ixgbe_fc_autoneg_backplane()
2315 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_copper() argument
2320 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_fc_autoneg_copper()
2323 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, in ixgbe_fc_autoneg_copper()
2327 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, in ixgbe_fc_autoneg_copper()
2340 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) in ixgbe_fc_autoneg() argument
2355 if (hw->fc.disable_fc_autoneg) in ixgbe_fc_autoneg()
2358 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_fc_autoneg()
2362 switch (hw->phy.media_type) { in ixgbe_fc_autoneg()
2366 ret_val = ixgbe_fc_autoneg_fiber(hw); in ixgbe_fc_autoneg()
2371 ret_val = ixgbe_fc_autoneg_backplane(hw); in ixgbe_fc_autoneg()
2376 if (ixgbe_device_supports_autoneg_fc(hw)) in ixgbe_fc_autoneg()
2377 ret_val = ixgbe_fc_autoneg_copper(hw); in ixgbe_fc_autoneg()
2386 hw->fc.fc_was_autonegged = true; in ixgbe_fc_autoneg()
2388 hw->fc.fc_was_autonegged = false; in ixgbe_fc_autoneg()
2389 hw->fc.current_mode = hw->fc.requested_mode; in ixgbe_fc_autoneg()
2403 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) in ixgbe_pcie_timeout_poll() argument
2408 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); in ixgbe_pcie_timeout_poll()
2449 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) in ixgbe_disable_pcie_master() argument
2455 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); in ixgbe_disable_pcie_master()
2458 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || in ixgbe_disable_pcie_master()
2459 ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_master()
2465 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) in ixgbe_disable_pcie_master()
2477 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); in ixgbe_disable_pcie_master()
2478 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_disable_pcie_master()
2480 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_disable_pcie_master()
2487 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_disable_pcie_master()
2490 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_disable_pcie_master()
2491 if (ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_master()
2497 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); in ixgbe_disable_pcie_master()
2509 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_acquire_swfw_sync() argument
2522 if (ixgbe_get_eeprom_semaphore(hw)) in ixgbe_acquire_swfw_sync()
2525 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_acquire_swfw_sync()
2528 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_acquire_swfw_sync()
2529 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2533 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2540 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); in ixgbe_acquire_swfw_sync()
2554 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_release_swfw_sync() argument
2559 ixgbe_get_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2561 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_release_swfw_sync()
2563 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_release_swfw_sync()
2565 ixgbe_release_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2577 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_generic() argument
2580 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_generic()
2591 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) in prot_autoc_write_generic() argument
2593 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); in prot_autoc_write_generic()
2604 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_buff_generic() argument
2610 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_disable_rx_buff_generic()
2612 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_disable_rx_buff_generic()
2614 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); in ixgbe_disable_rx_buff_generic()
2624 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); in ixgbe_disable_rx_buff_generic()
2636 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_buff_generic() argument
2640 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_enable_rx_buff_generic()
2642 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_enable_rx_buff_generic()
2643 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_rx_buff_generic()
2655 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
2658 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_generic()
2660 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_generic()
2670 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_start_generic() argument
2674 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_blink_led_start_generic()
2675 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_start_generic()
2683 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_blink_led_start_generic()
2686 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_start_generic()
2693 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_start_generic()
2697 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2704 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_start_generic()
2705 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2715 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_stop_generic() argument
2718 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_stop_generic()
2722 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_stop_generic()
2729 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_stop_generic()
2736 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_stop_generic()
2737 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_stop_generic()
2751 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, in ixgbe_get_san_mac_addr_offset() argument
2760 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, in ixgbe_get_san_mac_addr_offset()
2763 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_offset()
2779 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_get_san_mac_addr_generic() argument
2789 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_get_san_mac_addr_generic()
2795 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
2797 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_get_san_mac_addr_generic()
2800 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, in ixgbe_get_san_mac_addr_generic()
2803 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_generic()
2829 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) in ixgbe_get_pcie_msix_count_generic() argument
2835 switch (hw->mac.type) { in ixgbe_get_pcie_msix_count_generic()
2851 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); in ixgbe_get_pcie_msix_count_generic()
2852 if (ixgbe_removed(hw->hw_addr)) in ixgbe_get_pcie_msix_count_generic()
2871 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_generic() argument
2874 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_generic()
2878 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_clear_vmdq_generic()
2882 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
2883 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
2885 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_vmdq_generic()
2893 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_clear_vmdq_generic()
2897 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_clear_vmdq_generic()
2902 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); in ixgbe_clear_vmdq_generic()
2905 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); in ixgbe_clear_vmdq_generic()
2910 hw->mac.ops.clear_rar(hw, rar); in ixgbe_clear_vmdq_generic()
2920 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_generic() argument
2923 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_generic()
2927 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_set_vmdq_generic()
2932 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_set_vmdq_generic()
2934 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); in ixgbe_set_vmdq_generic()
2936 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_set_vmdq_generic()
2938 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); in ixgbe_set_vmdq_generic()
2953 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac_generic() argument
2955 u32 rar = hw->mac.san_mac_rar_index; in ixgbe_set_vmdq_san_mac_generic()
2958 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); in ixgbe_set_vmdq_san_mac_generic()
2959 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
2961 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
2962 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); in ixgbe_set_vmdq_san_mac_generic()
2972 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) in ixgbe_init_uta_tables_generic() argument
2977 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); in ixgbe_init_uta_tables_generic()
2990 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) in ixgbe_find_vlvf_slot() argument
3005 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); in ixgbe_find_vlvf_slot()
3021 hw_dbg(hw, "No space in VLVF.\n"); in ixgbe_find_vlvf_slot()
3038 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vfta_generic() argument
3067 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); in ixgbe_set_vfta_generic()
3089 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); in ixgbe_set_vfta_generic()
3093 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); in ixgbe_set_vfta_generic()
3100 bits = IXGBE_READ_REG(hw, in ixgbe_set_vfta_generic()
3103 IXGBE_WRITE_REG(hw, in ixgbe_set_vfta_generic()
3107 bits = IXGBE_READ_REG(hw, in ixgbe_set_vfta_generic()
3110 IXGBE_WRITE_REG(hw, in ixgbe_set_vfta_generic()
3117 bits = IXGBE_READ_REG(hw, in ixgbe_set_vfta_generic()
3120 IXGBE_WRITE_REG(hw, in ixgbe_set_vfta_generic()
3123 bits |= IXGBE_READ_REG(hw, in ixgbe_set_vfta_generic()
3126 bits = IXGBE_READ_REG(hw, in ixgbe_set_vfta_generic()
3129 IXGBE_WRITE_REG(hw, in ixgbe_set_vfta_generic()
3132 bits |= IXGBE_READ_REG(hw, in ixgbe_set_vfta_generic()
3153 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), in ixgbe_set_vfta_generic()
3162 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); in ixgbe_set_vfta_generic()
3167 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); in ixgbe_set_vfta_generic()
3178 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) in ixgbe_clear_vfta_generic() argument
3182 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_generic()
3183 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_generic()
3186 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); in ixgbe_clear_vfta_generic()
3187 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); in ixgbe_clear_vfta_generic()
3188 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); in ixgbe_clear_vfta_generic()
3203 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_mac_link_generic() argument
3210 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3212 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3215 hw_dbg(hw, "LINKS changed from %08X to %08X\n", in ixgbe_check_mac_link_generic()
3228 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3239 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3249 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3272 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, in ixgbe_get_wwn_prefix_generic() argument
3284 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) in ixgbe_get_wwn_prefix_generic()
3293 if (hw->eeprom.ops.read(hw, offset, &caps)) in ixgbe_get_wwn_prefix_generic()
3300 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) in ixgbe_get_wwn_prefix_generic()
3301 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3304 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) in ixgbe_get_wwn_prefix_generic()
3310 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3321 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) in ixgbe_set_mac_anti_spoofing() argument
3328 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_mac_anti_spoofing()
3339 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
3346 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
3353 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); in ixgbe_set_mac_anti_spoofing()
3363 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_vlan_anti_spoofing() argument
3369 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_vlan_anti_spoofing()
3372 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_vlan_anti_spoofing()
3377 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_vlan_anti_spoofing()
3388 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) in ixgbe_get_device_caps_generic() argument
3390 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); in ixgbe_get_device_caps_generic()
3402 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, in ixgbe_set_rxpba_generic() argument
3407 u32 pbsize = hw->mac.rx_pb_size; in ixgbe_set_rxpba_generic()
3429 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3435 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3449 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); in ixgbe_set_rxpba_generic()
3450 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); in ixgbe_set_rxpba_generic()
3455 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3456 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3457 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); in ixgbe_set_rxpba_generic()
3500 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, in ixgbe_host_interface_command() argument
3509 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_host_interface_command()
3514 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); in ixgbe_host_interface_command()
3515 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); in ixgbe_host_interface_command()
3518 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_host_interface_command()
3520 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); in ixgbe_host_interface_command()
3526 hw_dbg(hw, "Buffer length failure, not aligned to dword"); in ixgbe_host_interface_command()
3537 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_host_interface_command()
3541 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); in ixgbe_host_interface_command()
3544 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_host_interface_command()
3552 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { in ixgbe_host_interface_command()
3553 hw_dbg(hw, "Command has failed with no status valid.\n"); in ixgbe_host_interface_command()
3565 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3575 hw_dbg(hw, "Buffer not large enough for reply message.\n"); in ixgbe_host_interface_command()
3584 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3604 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, in ixgbe_set_fw_drv_ver_generic() argument
3611 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)) in ixgbe_set_fw_drv_ver_generic()
3617 fw_cmd.port_num = (u8)hw->bus.func; in ixgbe_set_fw_drv_ver_generic()
3629 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, in ixgbe_set_fw_drv_ver_generic()
3645 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_set_fw_drv_ver_generic()
3657 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) in ixgbe_clear_tx_pending() argument
3666 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) in ixgbe_clear_tx_pending()
3674 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); in ixgbe_clear_tx_pending()
3675 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); in ixgbe_clear_tx_pending()
3678 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3684 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_clear_tx_pending()
3687 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_clear_tx_pending()
3688 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_tx_pending()
3695 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_clear_tx_pending()
3696 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, in ixgbe_clear_tx_pending()
3700 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3704 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); in ixgbe_clear_tx_pending()
3705 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); in ixgbe_clear_tx_pending()
3729 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, in ixgbe_get_ets_data() argument
3734 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); in ixgbe_get_ets_data()
3741 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); in ixgbe_get_ets_data()
3757 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) in ixgbe_get_thermal_sensor_data_generic() argument
3765 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_get_thermal_sensor_data_generic()
3768 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_get_thermal_sensor_data_generic()
3771 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_get_thermal_sensor_data_generic()
3783 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), in ixgbe_get_thermal_sensor_data_generic()
3794 status = hw->phy.ops.read_i2c_byte(hw, in ixgbe_get_thermal_sensor_data_generic()
3813 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) in ixgbe_init_thermal_sensor_thresh_generic() argument
3823 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_init_thermal_sensor_thresh_generic()
3828 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_init_thermal_sensor_thresh_generic()
3831 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_init_thermal_sensor_thresh_generic()
3845 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { in ixgbe_init_thermal_sensor_thresh_generic()
3846 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_init_thermal_sensor_thresh_generic()
3856 hw->phy.ops.write_i2c_byte(hw, in ixgbe_init_thermal_sensor_thresh_generic()
3871 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_generic() argument
3875 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_disable_rx_generic()
3877 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_disable_rx_generic()
3880 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_disable_rx_generic()
3883 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_disable_rx_generic()
3884 hw->mac.set_lben = true; in ixgbe_disable_rx_generic()
3886 hw->mac.set_lben = false; in ixgbe_disable_rx_generic()
3890 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); in ixgbe_disable_rx_generic()
3894 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_generic() argument
3898 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_enable_rx_generic()
3899 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); in ixgbe_enable_rx_generic()
3901 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_enable_rx_generic()
3902 if (hw->mac.set_lben) { in ixgbe_enable_rx_generic()
3905 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_enable_rx_generic()
3907 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_enable_rx_generic()
3908 hw->mac.set_lben = false; in ixgbe_enable_rx_generic()
3916 bool ixgbe_mng_present(struct ixgbe_hw *hw) in ixgbe_mng_present() argument
3920 if (hw->mac.type < ixgbe_mac_82599EB) in ixgbe_mng_present()
3923 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); in ixgbe_mng_present()
3936 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_multispeed_fiber() argument
3948 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); in ixgbe_setup_mac_link_multispeed_fiber()
3962 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
3971 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
3973 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
3980 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
3987 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
3994 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
3995 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4006 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_multispeed_fiber()
4022 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
4031 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4033 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4040 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4047 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4054 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4055 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4061 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
4075 status = ixgbe_setup_mac_link_multispeed_fiber(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4081 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_multispeed_fiber()
4084 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4087 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4099 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_soft_rate_select_speed() argument
4114 hw_dbg(hw, "Invalid fixed module speed\n"); in ixgbe_set_soft_rate_select_speed()
4119 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4123 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4129 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4133 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()