Lines Matching refs:hw
36 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
38 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
42 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw);
43 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
46 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
48 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw);
54 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
57 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
60 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw);
61 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw);
63 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) in rtl92ee_phy_query_bb_reg() argument
65 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_query_bb_reg()
81 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, in rtl92ee_phy_set_bb_reg() argument
84 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_bb_reg()
104 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw, in rtl92ee_phy_query_rf_reg() argument
107 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_query_rf_reg()
117 original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr); in rtl92ee_phy_query_rf_reg()
130 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw, in rtl92ee_phy_set_rf_reg() argument
134 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_rf_reg()
145 original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr); in rtl92ee_phy_set_rf_reg()
150 _rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data); in rtl92ee_phy_set_rf_reg()
159 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw, in _rtl92ee_phy_rf_serial_read() argument
162 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_rf_serial_read()
172 if (RT_CANNOT_IO(hw)) { in _rtl92ee_phy_rf_serial_read()
176 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); in _rtl92ee_phy_rf_serial_read()
180 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); in _rtl92ee_phy_rf_serial_read()
183 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92ee_phy_rf_serial_read()
186 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92ee_phy_rf_serial_read()
189 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, in _rtl92ee_phy_rf_serial_read()
192 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, in _rtl92ee_phy_rf_serial_read()
195 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, in _rtl92ee_phy_rf_serial_read()
198 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, in _rtl92ee_phy_rf_serial_read()
206 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw, in _rtl92ee_phy_rf_serial_write() argument
212 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_rf_serial_write()
216 if (RT_CANNOT_IO(hw)) { in _rtl92ee_phy_rf_serial_write()
223 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92ee_phy_rf_serial_write()
240 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw) in rtl92ee_phy_mac_config() argument
242 return _rtl92ee_phy_config_mac_with_headerfile(hw); in rtl92ee_phy_mac_config()
245 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw) in rtl92ee_phy_bb_config() argument
247 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_bb_config()
253 phy_init_bb_rf_register_def(hw); in rtl92ee_phy_bb_config()
268 rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw); in rtl92ee_phy_bb_config()
271 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl92ee_phy_bb_config()
276 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw) in rtl92ee_phy_rf_config() argument
278 return rtl92ee_phy_rf6052_config(hw); in rtl92ee_phy_rf_config()
281 static bool _check_condition(struct ieee80211_hw *hw, in _check_condition() argument
284 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in _check_condition()
285 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); in _check_condition()
311 static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data, in _rtl92ee_config_rf_reg() argument
317 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); in _rtl92ee_config_rf_reg()
324 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); in _rtl92ee_config_rf_reg()
329 rtl_set_rfreg(hw, rfpath, regaddr, in _rtl92ee_config_rf_reg()
332 getvalue = rtl_get_rfreg(hw, rfpath, addr, in _rtl92ee_config_rf_reg()
343 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); in _rtl92ee_config_rf_reg()
348 rtl_set_rfreg(hw, rfpath, regaddr, in _rtl92ee_config_rf_reg()
351 rtl_set_rfreg(hw, rfpath, 0x18, in _rtl92ee_config_rf_reg()
354 getvalue = rtl_get_rfreg(hw, rfpath, addr, in _rtl92ee_config_rf_reg()
363 static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw, in _rtl92ee_config_rf_radio_a() argument
369 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A, in _rtl92ee_config_rf_radio_a()
373 static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw, in _rtl92ee_config_rf_radio_b() argument
379 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B, in _rtl92ee_config_rf_radio_b()
383 static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw, in _rtl92ee_config_bb_reg() argument
399 rtl_set_bbreg(hw, addr, MASKDWORD , data); in _rtl92ee_config_bb_reg()
404 static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) in _rtl92ee_phy_init_tx_power_by_rate() argument
406 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_init_tx_power_by_rate()
419 static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, in _rtl92ee_phy_set_txpower_by_rate_base() argument
424 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_set_txpower_by_rate_base()
459 static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, in _rtl92ee_phy_get_txpower_by_rate_base() argument
463 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_get_txpower_by_rate_base()
500 static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) in _rtl92ee_phy_store_txpower_by_rate_base() argument
502 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_store_txpower_by_rate_base()
513 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, in _rtl92ee_phy_store_txpower_by_rate_base()
521 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, in _rtl92ee_phy_store_txpower_by_rate_base()
528 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, in _rtl92ee_phy_store_txpower_by_rate_base()
534 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, in _rtl92ee_phy_store_txpower_by_rate_base()
541 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, in _rtl92ee_phy_store_txpower_by_rate_base()
571 static void phy_convert_txpwr_dbm_to_rel_val(struct ieee80211_hw *hw) in phy_convert_txpwr_dbm_to_rel_val() argument
573 struct rtl_priv *rtlpriv = rtl_priv(hw); in phy_convert_txpwr_dbm_to_rel_val()
579 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, in phy_convert_txpwr_dbm_to_rel_val()
591 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, in phy_convert_txpwr_dbm_to_rel_val()
603 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, in phy_convert_txpwr_dbm_to_rel_val()
612 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, in phy_convert_txpwr_dbm_to_rel_val()
622 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, in phy_convert_txpwr_dbm_to_rel_val()
638 static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw) in _rtl92ee_phy_txpower_by_rate_configuration() argument
640 _rtl92ee_phy_store_txpower_by_rate_base(hw); in _rtl92ee_phy_txpower_by_rate_configuration()
641 phy_convert_txpwr_dbm_to_rel_val(hw); in _rtl92ee_phy_txpower_by_rate_configuration()
644 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw) in _rtl92ee_phy_bb8192ee_config_parafile() argument
646 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_bb8192ee_config_parafile()
648 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); in _rtl92ee_phy_bb8192ee_config_parafile()
651 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_PHY_REG); in _rtl92ee_phy_bb8192ee_config_parafile()
657 _rtl92ee_phy_init_tx_power_by_rate(hw); in _rtl92ee_phy_bb8192ee_config_parafile()
661 phy_config_bb_with_pghdrfile(hw, BASEBAND_CONFIG_PHY_REG); in _rtl92ee_phy_bb8192ee_config_parafile()
663 _rtl92ee_phy_txpower_by_rate_configuration(hw); in _rtl92ee_phy_bb8192ee_config_parafile()
668 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_AGC_TAB); in _rtl92ee_phy_bb8192ee_config_parafile()
673 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, in _rtl92ee_phy_bb8192ee_config_parafile()
680 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) in _rtl92ee_phy_config_mac_with_headerfile() argument
682 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_config_mac_with_headerfile()
704 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw, in phy_config_bb_with_hdr_file() argument
710 struct rtl_priv *rtlpriv = rtl_priv(hw); in phy_config_bb_with_hdr_file()
721 _rtl92ee_config_bb_reg(hw, v1, v2); in phy_config_bb_with_hdr_file()
727 if (!_check_condition(hw , array[i])) { in phy_config_bb_with_hdr_file()
744 _rtl92ee_config_bb_reg(hw, v1, in phy_config_bb_with_hdr_file()
762 rtl_set_bbreg(hw, array[i], MASKDWORD, in phy_config_bb_with_hdr_file()
771 if (!_check_condition(hw , array[i])) { in phy_config_bb_with_hdr_file()
790 rtl_set_bbreg(hw, in phy_config_bb_with_hdr_file()
860 static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw, in _rtl92ee_store_tx_power_by_rate() argument
866 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_store_tx_power_by_rate()
888 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw, in phy_config_bb_with_pghdrfile() argument
891 struct rtl_priv *rtlpriv = rtl_priv(hw); in phy_config_bb_with_pghdrfile()
910 _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3, in phy_config_bb_with_pghdrfile()
929 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, in rtl92ee_phy_config_rf_with_headerfile() argument
932 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_config_rf_with_headerfile()
949 _rtl92ee_config_rf_radio_a(hw, v1, v2); in rtl92ee_phy_config_rf_with_headerfile()
956 if (!_check_condition(hw , array[i])) { in rtl92ee_phy_config_rf_with_headerfile()
973 _rtl92ee_config_rf_radio_a(hw, in rtl92ee_phy_config_rf_with_headerfile()
996 _rtl92ee_config_rf_radio_b(hw, v1, v2); in rtl92ee_phy_config_rf_with_headerfile()
1003 if (!_check_condition(hw , array[i])) { in rtl92ee_phy_config_rf_with_headerfile()
1020 _rtl92ee_config_rf_radio_b(hw, in rtl92ee_phy_config_rf_with_headerfile()
1039 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) in rtl92ee_phy_get_hw_reg_originalvalue() argument
1041 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_get_hw_reg_originalvalue()
1045 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); in rtl92ee_phy_get_hw_reg_originalvalue()
1047 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); in rtl92ee_phy_get_hw_reg_originalvalue()
1049 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); in rtl92ee_phy_get_hw_reg_originalvalue()
1051 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); in rtl92ee_phy_get_hw_reg_originalvalue()
1060 rtlphy->framesync = (u8)rtl_get_bbreg(hw, in rtl92ee_phy_get_hw_reg_originalvalue()
1062 rtlphy->framesync_c34 = rtl_get_bbreg(hw, in rtl92ee_phy_get_hw_reg_originalvalue()
1070 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw) in phy_init_bb_rf_register_def() argument
1072 struct rtl_priv *rtlpriv = rtl_priv(hw); in phy_init_bb_rf_register_def()
1099 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) in rtl92ee_phy_get_txpower_level() argument
1101 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_get_txpower_level()
1107 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, in rtl92ee_phy_get_txpower_level()
1110 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > in rtl92ee_phy_get_txpower_level()
1112 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, in rtl92ee_phy_get_txpower_level()
1115 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, in rtl92ee_phy_get_txpower_level()
1117 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, in rtl92ee_phy_get_txpower_level()
1185 static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw, in _rtl92ee_get_txpower_by_rate() argument
1189 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_get_txpower_by_rate()
1252 static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw, in _rtl92ee_get_txpower_index() argument
1256 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_get_txpower_index()
1292 diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G, in _rtl92ee_get_txpower_index()
1303 static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx, in _rtl92ee_set_txpower_index() argument
1306 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_set_txpower_index()
1311 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, in _rtl92ee_set_txpower_index()
1315 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1, in _rtl92ee_set_txpower_index()
1319 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2, in _rtl92ee_set_txpower_index()
1323 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3, in _rtl92ee_set_txpower_index()
1327 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0, in _rtl92ee_set_txpower_index()
1331 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1, in _rtl92ee_set_txpower_index()
1335 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2, in _rtl92ee_set_txpower_index()
1339 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3, in _rtl92ee_set_txpower_index()
1343 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0, in _rtl92ee_set_txpower_index()
1347 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1, in _rtl92ee_set_txpower_index()
1351 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2, in _rtl92ee_set_txpower_index()
1355 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3, in _rtl92ee_set_txpower_index()
1359 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, in _rtl92ee_set_txpower_index()
1363 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, in _rtl92ee_set_txpower_index()
1367 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, in _rtl92ee_set_txpower_index()
1371 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, in _rtl92ee_set_txpower_index()
1375 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, in _rtl92ee_set_txpower_index()
1379 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, in _rtl92ee_set_txpower_index()
1383 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, in _rtl92ee_set_txpower_index()
1387 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, in _rtl92ee_set_txpower_index()
1391 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, in _rtl92ee_set_txpower_index()
1395 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, in _rtl92ee_set_txpower_index()
1399 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, in _rtl92ee_set_txpower_index()
1403 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, in _rtl92ee_set_txpower_index()
1407 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, in _rtl92ee_set_txpower_index()
1411 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, in _rtl92ee_set_txpower_index()
1415 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, in _rtl92ee_set_txpower_index()
1419 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, in _rtl92ee_set_txpower_index()
1430 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1, in _rtl92ee_set_txpower_index()
1434 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2, in _rtl92ee_set_txpower_index()
1438 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3, in _rtl92ee_set_txpower_index()
1442 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, in _rtl92ee_set_txpower_index()
1446 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0, in _rtl92ee_set_txpower_index()
1450 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1, in _rtl92ee_set_txpower_index()
1454 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2, in _rtl92ee_set_txpower_index()
1458 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3, in _rtl92ee_set_txpower_index()
1462 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0, in _rtl92ee_set_txpower_index()
1466 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1, in _rtl92ee_set_txpower_index()
1470 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2, in _rtl92ee_set_txpower_index()
1474 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3, in _rtl92ee_set_txpower_index()
1478 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, in _rtl92ee_set_txpower_index()
1482 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, in _rtl92ee_set_txpower_index()
1486 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, in _rtl92ee_set_txpower_index()
1490 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, in _rtl92ee_set_txpower_index()
1494 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, in _rtl92ee_set_txpower_index()
1498 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, in _rtl92ee_set_txpower_index()
1502 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, in _rtl92ee_set_txpower_index()
1506 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, in _rtl92ee_set_txpower_index()
1510 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, in _rtl92ee_set_txpower_index()
1514 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, in _rtl92ee_set_txpower_index()
1518 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, in _rtl92ee_set_txpower_index()
1522 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, in _rtl92ee_set_txpower_index()
1526 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, in _rtl92ee_set_txpower_index()
1530 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, in _rtl92ee_set_txpower_index()
1534 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, in _rtl92ee_set_txpower_index()
1538 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, in _rtl92ee_set_txpower_index()
1551 static void phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw, in phy_set_txpower_index_by_rate_array() argument
1559 power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i], in phy_set_txpower_index_by_rate_array()
1561 _rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]); in phy_set_txpower_index_by_rate_array()
1565 static void phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw, in phy_set_txpower_index_by_rate_section() argument
1570 struct rtl_priv *rtlpriv = rtl_priv(hw); in phy_set_txpower_index_by_rate_section()
1578 phy_set_txpower_index_by_rate_array(hw, rfpath, in phy_set_txpower_index_by_rate_section()
1586 phy_set_txpower_index_by_rate_array(hw, rfpath, in phy_set_txpower_index_by_rate_section()
1594 phy_set_txpower_index_by_rate_array(hw, rfpath, in phy_set_txpower_index_by_rate_section()
1602 phy_set_txpower_index_by_rate_array(hw, rfpath, in phy_set_txpower_index_by_rate_section()
1610 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) in rtl92ee_phy_set_txpower_level() argument
1612 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); in rtl92ee_phy_set_txpower_level()
1613 struct rtl_phy *rtlphy = &rtl_priv(hw)->phy; in rtl92ee_phy_set_txpower_level()
1620 phy_set_txpower_index_by_rate_section(hw, rfpath, in rtl92ee_phy_set_txpower_level()
1622 phy_set_txpower_index_by_rate_section(hw, rfpath, in rtl92ee_phy_set_txpower_level()
1624 phy_set_txpower_index_by_rate_section(hw, rfpath, in rtl92ee_phy_set_txpower_level()
1629 phy_set_txpower_index_by_rate_section(hw, in rtl92ee_phy_set_txpower_level()
1635 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, in _rtl92ee_phy_txpwr_idx_to_dbm() argument
1658 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) in rtl92ee_phy_scan_operation_backup() argument
1660 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_scan_operation_backup()
1661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in rtl92ee_phy_scan_operation_backup()
1668 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, in rtl92ee_phy_scan_operation_backup()
1674 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, in rtl92ee_phy_scan_operation_backup()
1685 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw) in rtl92ee_phy_set_bw_mode_callback() argument
1687 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_bw_mode_callback()
1688 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in rtl92ee_phy_set_bw_mode_callback()
1690 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in rtl92ee_phy_set_bw_mode_callback()
1727 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1728 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1729 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT, in rtl92ee_phy_set_bw_mode_callback()
1733 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1734 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1735 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, in rtl92ee_phy_set_bw_mode_callback()
1737 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, in rtl92ee_phy_set_bw_mode_callback()
1740 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92ee_phy_set_bw_mode_callback()
1749 rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); in rtl92ee_phy_set_bw_mode_callback()
1754 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw, in rtl92ee_phy_set_bw_mode() argument
1757 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_bw_mode()
1759 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in rtl92ee_phy_set_bw_mode()
1765 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { in rtl92ee_phy_set_bw_mode()
1766 rtl92ee_phy_set_bw_mode_callback(hw); in rtl92ee_phy_set_bw_mode()
1775 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw) in rtl92ee_phy_sw_chnl_callback() argument
1777 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_sw_chnl_callback()
1778 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in rtl92ee_phy_sw_chnl_callback()
1790 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, in rtl92ee_phy_sw_chnl_callback()
1804 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw) in rtl92ee_phy_sw_chnl() argument
1806 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_sw_chnl()
1808 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in rtl92ee_phy_sw_chnl()
1819 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { in rtl92ee_phy_sw_chnl()
1820 rtl92ee_phy_sw_chnl_callback(hw); in rtl92ee_phy_sw_chnl()
1833 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, in _rtl92ee_phy_sw_chnl_step_by_step() argument
1837 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_sw_chnl_step_by_step()
1902 rtl92ee_phy_set_txpower_level(hw, channel); in _rtl92ee_phy_sw_chnl_step_by_step()
1922 rtl_set_rfreg(hw, (enum radio_path)rfpath, in _rtl92ee_phy_sw_chnl_step_by_step()
1965 static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) in _rtl92ee_phy_path_a_iqk() argument
1971 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_iqk()
1972 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_iqk()
1973 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_iqk()
1975 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_iqk()
1976 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1977 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1978 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1980 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); in _rtl92ee_phy_path_a_iqk()
1981 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_a_iqk()
1984 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_a_iqk()
1987 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92ee_phy_path_a_iqk()
1988 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_iqk()
1992 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1993 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1994 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
2006 static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw) in _rtl92ee_phy_path_b_iqk() argument
2012 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
2013 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_iqk()
2014 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
2016 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
2019 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
2020 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
2021 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_iqk()
2022 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
2024 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); in _rtl92ee_phy_path_b_iqk()
2025 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_b_iqk()
2028 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_b_iqk()
2031 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_iqk()
2032 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_iqk()
2036 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2037 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2038 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2050 static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) in _rtl92ee_phy_path_a_rx_iqk() argument
2057 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2059 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2060 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2061 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2062 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_a_rx_iqk()
2065 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2066 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2069 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2072 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_a_rx_iqk()
2073 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2076 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2077 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2078 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2079 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2081 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2082 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2085 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_a_rx_iqk()
2088 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2089 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2094 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2095 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2096 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2104 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2111 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_a_rx_iqk()
2114 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2116 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2118 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2119 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2120 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_a_rx_iqk()
2123 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2124 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2127 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2130 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2133 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2134 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2135 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2136 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2138 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2139 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2142 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_a_rx_iqk()
2144 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2145 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2149 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2150 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_a_rx_iqk()
2154 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2155 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2165 static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) in _rtl92ee_phy_path_b_rx_iqk() argument
2167 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_path_b_rx_iqk()
2173 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2175 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2176 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2177 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2178 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_b_rx_iqk()
2181 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2182 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2184 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2187 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_b_rx_iqk()
2188 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2191 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2192 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2193 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2194 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2196 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2197 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_b_rx_iqk()
2203 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2204 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2209 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2210 reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2211 reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2220 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2226 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_b_rx_iqk()
2229 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2230 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2232 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2233 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2234 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_b_rx_iqk()
2237 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2238 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2241 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2244 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2247 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2248 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2249 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2250 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2252 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2253 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2256 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_b_rx_iqk()
2258 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2259 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2263 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2264 reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2265 reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); in _rtl92ee_phy_path_b_rx_iqk()
2268 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2269 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2281 static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, in _rtl92ee_phy_path_a_fill_iqk_matrix() argument
2292 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2298 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2299 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), in _rtl92ee_phy_path_a_fill_iqk_matrix()
2305 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2307 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2309 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), in _rtl92ee_phy_path_a_fill_iqk_matrix()
2316 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2319 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2322 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2326 static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw, in _rtl92ee_phy_path_b_fill_iqk_matrix() argument
2337 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2343 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2344 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), in _rtl92ee_phy_path_b_fill_iqk_matrix()
2350 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2352 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2354 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), in _rtl92ee_phy_path_b_fill_iqk_matrix()
2361 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2364 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2367 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2371 static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw, in _rtl92ee_phy_save_adda_registers() argument
2378 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); in _rtl92ee_phy_save_adda_registers()
2381 static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw, in _rtl92ee_phy_save_mac_registers() argument
2384 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_save_mac_registers()
2393 static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw, in _rtl92ee_phy_reload_adda_registers() argument
2400 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); in _rtl92ee_phy_reload_adda_registers()
2403 static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw, in _rtl92ee_phy_reload_mac_registers() argument
2406 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_reload_mac_registers()
2414 static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, in _rtl92ee_phy_path_adda_on() argument
2423 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616); in _rtl92ee_phy_path_adda_on()
2425 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl92ee_phy_path_adda_on()
2429 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); in _rtl92ee_phy_path_adda_on()
2432 static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw, in _rtl92ee_phy_mac_setting_calibration() argument
2435 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); in _rtl92ee_phy_mac_setting_calibration()
2438 static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw) in _rtl92ee_phy_path_a_standby() argument
2440 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92ee_phy_path_a_standby()
2441 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); in _rtl92ee_phy_path_a_standby()
2442 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_standby()
2445 static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw, in _rtl92ee_phy_simularity_compare() argument
2520 static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, in _rtl92ee_phy_iq_calibrate() argument
2523 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_iq_calibrate()
2527 u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0); in _rtl92ee_phy_iq_calibrate()
2528 u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0); in _rtl92ee_phy_iq_calibrate()
2547 _rtl92ee_phy_save_adda_registers(hw, adda_reg, in _rtl92ee_phy_iq_calibrate()
2550 _rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg, in _rtl92ee_phy_iq_calibrate()
2552 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg, in _rtl92ee_phy_iq_calibrate()
2557 _rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t); in _rtl92ee_phy_iq_calibrate()
2560 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92ee_phy_iq_calibrate()
2561 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92ee_phy_iq_calibrate()
2562 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92ee_phy_iq_calibrate()
2563 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); in _rtl92ee_phy_iq_calibrate()
2565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2566 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); in _rtl92ee_phy_iq_calibrate()
2567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2568 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2570 _rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg, in _rtl92ee_phy_iq_calibrate()
2574 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2575 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2576 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2579 patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t); in _rtl92ee_phy_iq_calibrate()
2584 result[t][0] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2588 result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, in _rtl92ee_phy_iq_calibrate()
2599 patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t); in _rtl92ee_phy_iq_calibrate()
2604 result[t][2] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2608 result[t][3] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2623 _rtl92ee_phy_path_a_standby(hw); in _rtl92ee_phy_iq_calibrate()
2625 _rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t); in _rtl92ee_phy_iq_calibrate()
2628 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2629 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2630 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2633 pathb_ok = _rtl92ee_phy_path_b_iqk(hw); in _rtl92ee_phy_iq_calibrate()
2637 result[t][4] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2641 result[t][5] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2653 pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t); in _rtl92ee_phy_iq_calibrate()
2657 result[t][6] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2661 result[t][7] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2679 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl92ee_phy_iq_calibrate()
2683 _rtl92ee_phy_reload_adda_registers(hw, adda_reg, in _rtl92ee_phy_iq_calibrate()
2688 _rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg, in _rtl92ee_phy_iq_calibrate()
2691 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg, in _rtl92ee_phy_iq_calibrate()
2696 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2697 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); in _rtl92ee_phy_iq_calibrate()
2699 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2700 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); in _rtl92ee_phy_iq_calibrate()
2704 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2705 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2709 static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) in _rtl92ee_phy_lc_calibrate() argument
2713 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_lc_calibrate()
2723 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl92ee_phy_lc_calibrate()
2726 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl92ee_phy_lc_calibrate()
2729 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2733 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2736 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl92ee_phy_lc_calibrate()
2738 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl92ee_phy_lc_calibrate()
2744 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl92ee_phy_lc_calibrate()
2747 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2754 static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, in _rtl92ee_phy_set_rfpath_switch() argument
2757 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_set_rfpath_switch()
2758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); in _rtl92ee_phy_set_rfpath_switch()
2759 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); in _rtl92ee_phy_set_rfpath_switch()
2768 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92ee_phy_set_rfpath_switch()
2772 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2775 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2778 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl92ee_phy_set_rfpath_switch()
2779 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl92ee_phy_set_rfpath_switch()
2786 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2788 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2791 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl92ee_phy_set_rfpath_switch()
2793 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2795 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2798 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); in _rtl92ee_phy_set_rfpath_switch()
2828 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) in rtl92ee_phy_iq_calibrate() argument
2830 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_iq_calibrate()
2852 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg, in rtl92ee_phy_iq_calibrate()
2874 _rtl92ee_phy_iq_calibrate(hw, result, i, true); in rtl92ee_phy_iq_calibrate()
2876 is12simular = _rtl92ee_phy_simularity_compare(hw, in rtl92ee_phy_iq_calibrate()
2886 is13simular = _rtl92ee_phy_simularity_compare(hw, in rtl92ee_phy_iq_calibrate()
2893 is23simular = _rtl92ee_phy_simularity_compare(hw, in rtl92ee_phy_iq_calibrate()
2937 _rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, in rtl92ee_phy_iq_calibrate()
2941 _rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result, in rtl92ee_phy_iq_calibrate()
2955 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg, in rtl92ee_phy_iq_calibrate()
2959 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw) in rtl92ee_phy_lc_calibrate() argument
2961 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_lc_calibrate()
2976 _rtl92ee_phy_lc_calibrate(hw, false); in rtl92ee_phy_lc_calibrate()
2981 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta) in rtl92ee_phy_ap_calibrate() argument
2985 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) in rtl92ee_phy_set_rfpath_switch() argument
2987 _rtl92ee_phy_set_rfpath_switch(hw, bmain, false); in rtl92ee_phy_set_rfpath_switch()
2990 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) in rtl92ee_phy_set_io_cmd() argument
2992 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_io_cmd()
3023 rtl92ee_phy_set_io(hw); in rtl92ee_phy_set_io_cmd()
3028 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw) in rtl92ee_phy_set_io() argument
3030 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_io()
3039 rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); in rtl92ee_phy_set_io()
3040 rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca); in rtl92ee_phy_set_io()
3042 rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92ee_phy_set_io()
3047 rtl92ee_dm_write_dig(hw, 0x17); in rtl92ee_phy_set_io()
3049 rtl92ee_dm_write_cck_cca_thres(hw, 0x40); in rtl92ee_phy_set_io()
3061 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw) in rtl92ee_phy_set_rf_on() argument
3063 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_phy_set_rf_on()
3073 static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw) in _rtl92ee_phy_set_rf_sleep() argument
3075 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_set_rf_sleep()
3078 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92ee_phy_set_rf_sleep()
3084 static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, in _rtl92ee_phy_set_rf_power_state() argument
3087 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_phy_set_rf_power_state()
3088 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); in _rtl92ee_phy_set_rf_power_state()
3089 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in _rtl92ee_phy_set_rf_power_state()
3090 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); in _rtl92ee_phy_set_rf_power_state()
3106 rtstatus = rtl_ps_enable_nic(hw); in _rtl92ee_phy_set_rf_power_state()
3115 rtl92ee_phy_set_rf_on(hw); in _rtl92ee_phy_set_rf_power_state()
3118 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); in _rtl92ee_phy_set_rf_power_state()
3120 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); in _rtl92ee_phy_set_rf_power_state()
3152 rtl_ps_disable_nic(hw); in _rtl92ee_phy_set_rf_power_state()
3156 rtlpriv->cfg->ops->led_control(hw, in _rtl92ee_phy_set_rf_power_state()
3159 rtlpriv->cfg->ops->led_control(hw, in _rtl92ee_phy_set_rf_power_state()
3195 _rtl92ee_phy_set_rf_sleep(hw); in _rtl92ee_phy_set_rf_power_state()
3208 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, in rtl92ee_phy_set_rf_power_state() argument
3211 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); in rtl92ee_phy_set_rf_power_state()
3217 bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state); in rtl92ee_phy_set_rf_power_state()