Lines Matching refs:hw
108 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
112 static void yukon_init(struct skge_hw *hw, int port);
113 static void genesis_mac_init(struct skge_hw *hw, int port);
126 static inline bool is_genesis(const struct skge_hw *hw) in is_genesis() argument
129 return hw->chip_id == CHIP_ID_GENESIS; in is_genesis()
149 const void __iomem *io = skge->hw->regs; in skge_get_regs()
160 static u32 wol_supported(const struct skge_hw *hw) in wol_supported() argument
162 if (is_genesis(hw)) in wol_supported()
165 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in wol_supported()
173 struct skge_hw *hw = skge->hw; in skge_wol_init() local
177 skge_write16(hw, B0_CTST, CS_RST_CLR); in skge_wol_init()
178 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_wol_init()
181 skge_write8(hw, B0_POWER_CTRL, in skge_wol_init()
185 if (hw->chip_id == CHIP_ID_YUKON_LITE && in skge_wol_init()
186 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in skge_wol_init()
187 u32 reg = skge_read32(hw, B2_GP_IO); in skge_wol_init()
190 skge_write32(hw, B2_GP_IO, reg); in skge_wol_init()
193 skge_write32(hw, SK_REG(port, GPHY_CTRL), in skge_wol_init()
198 skge_write32(hw, SK_REG(port, GPHY_CTRL), in skge_wol_init()
203 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in skge_wol_init()
206 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, in skge_wol_init()
210 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); in skge_wol_init()
211 gm_phy_write(hw, port, PHY_MARV_CTRL, in skge_wol_init()
217 gma_write16(hw, port, GM_GP_CTRL, in skge_wol_init()
222 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), in skge_wol_init()
226 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); in skge_wol_init()
239 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); in skge_wol_init()
242 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_wol_init()
249 wol->supported = wol_supported(skge->hw); in skge_get_wol()
256 struct skge_hw *hw = skge->hw; in skge_set_wol() local
258 if ((wol->wolopts & ~wol_supported(hw)) || in skge_set_wol()
259 !device_can_wakeup(&hw->pdev->dev)) in skge_set_wol()
264 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); in skge_set_wol()
272 static u32 skge_supported_modes(const struct skge_hw *hw) in skge_supported_modes() argument
276 if (hw->copper) { in skge_supported_modes()
286 if (is_genesis(hw)) in skge_supported_modes()
292 else if (hw->chip_id == CHIP_ID_YUKON) in skge_supported_modes()
307 struct skge_hw *hw = skge->hw; in skge_get_settings() local
310 ecmd->supported = skge_supported_modes(hw); in skge_get_settings()
312 if (hw->copper) { in skge_get_settings()
314 ecmd->phy_address = hw->phy_addr; in skge_get_settings()
328 const struct skge_hw *hw = skge->hw; in skge_set_settings() local
329 u32 supported = skge_supported_modes(hw); in skge_set_settings()
399 strlcpy(info->bus_info, pci_name(skge->hw->pdev), in skge_get_drvinfo()
449 if (is_genesis(skge->hw)) in skge_get_ethtool_stats()
464 if (is_genesis(skge->hw)) in skge_get_stats()
599 static inline u32 hwkhz(const struct skge_hw *hw) in hwkhz() argument
601 return is_genesis(hw) ? 53125 : 78125; in hwkhz()
605 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) in skge_clk2usec() argument
607 return (ticks * 1000) / hwkhz(hw); in skge_clk2usec()
611 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) in skge_usecs2clk() argument
613 return hwkhz(hw) * usec / 1000; in skge_usecs2clk()
620 struct skge_hw *hw = skge->hw; in skge_get_coalesce() local
626 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { in skge_get_coalesce()
627 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); in skge_get_coalesce()
628 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_get_coalesce()
644 struct skge_hw *hw = skge->hw; in skge_set_coalesce() local
646 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_set_coalesce()
669 skge_write32(hw, B2_IRQM_MSK, msk); in skge_set_coalesce()
671 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); in skge_set_coalesce()
673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); in skge_set_coalesce()
674 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_set_coalesce()
682 struct skge_hw *hw = skge->hw; in skge_led() local
685 spin_lock_bh(&hw->phy_lock); in skge_led()
686 if (is_genesis(hw)) { in skge_led()
689 if (hw->phy_type == SK_PHY_BCOM) in skge_led()
690 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); in skge_led()
692 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); in skge_led()
693 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); in skge_led()
695 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); in skge_led()
696 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); in skge_led()
697 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); in skge_led()
701 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); in skge_led()
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); in skge_led()
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
705 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
710 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); in skge_led()
711 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); in skge_led()
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
714 if (hw->phy_type == SK_PHY_BCOM) in skge_led()
715 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); in skge_led()
717 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); in skge_led()
718 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); in skge_led()
719 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
726 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
727 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
735 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, in skge_led()
741 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
756 spin_unlock_bh(&hw->phy_lock); in skge_led()
790 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); in skge_get_eeprom_len()
823 struct pci_dev *pdev = skge->hw->pdev; in skge_get_eeprom()
849 struct pci_dev *pdev = skge->hw->pdev; in skge_set_eeprom()
940 map = pci_map_single(skge->hw->pdev, skb->data, bufsize, in skge_rx_setup()
943 if (pci_dma_mapping_error(skge->hw->pdev, map)) in skge_rx_setup()
982 struct skge_hw *hw = skge->hw; in skge_rx_clean() local
991 pci_unmap_single(hw->pdev, in skge_rx_clean()
1050 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), in skge_link_up()
1065 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); in skge_link_down()
1072 static void xm_link_down(struct skge_hw *hw, int port) in xm_link_down() argument
1074 struct net_device *dev = hw->dev[port]; in xm_link_down()
1077 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); in xm_link_down()
1083 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __xm_phy_read() argument
1087 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in __xm_phy_read()
1088 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
1090 if (hw->phy_type == SK_PHY_XMAC) in __xm_phy_read()
1094 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) in __xm_phy_read()
1101 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
1106 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) in xm_phy_read() argument
1109 if (__xm_phy_read(hw, port, reg, &v)) in xm_phy_read()
1110 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); in xm_phy_read()
1114 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in xm_phy_write() argument
1118 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in xm_phy_write()
1120 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
1127 xm_write16(hw, port, XM_PHY_DATA, val); in xm_phy_write()
1129 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
1136 static void genesis_init(struct skge_hw *hw) in genesis_init() argument
1139 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); in genesis_init()
1140 skge_write8(hw, B2_BSC_CTRL, BSC_START); in genesis_init()
1143 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_init()
1146 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); in genesis_init()
1147 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); in genesis_init()
1148 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); in genesis_init()
1149 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); in genesis_init()
1151 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_init()
1152 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_init()
1153 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_init()
1154 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_init()
1157 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); in genesis_init()
1158 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); in genesis_init()
1159 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); in genesis_init()
1160 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); in genesis_init()
1161 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); in genesis_init()
1164 static void genesis_reset(struct skge_hw *hw, int port) in genesis_reset() argument
1169 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in genesis_reset()
1172 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); in genesis_reset()
1173 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); in genesis_reset()
1174 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ in genesis_reset()
1175 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ in genesis_reset()
1176 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ in genesis_reset()
1179 if (hw->phy_type == SK_PHY_BCOM) in genesis_reset()
1180 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); in genesis_reset()
1182 xm_outhash(hw, port, XM_HSM, zero); in genesis_reset()
1185 reg = xm_read32(hw, port, XM_MODE); in genesis_reset()
1186 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); in genesis_reset()
1187 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); in genesis_reset()
1208 static void bcom_check_link(struct skge_hw *hw, int port) in bcom_check_link() argument
1210 struct net_device *dev = hw->dev[port]; in bcom_check_link()
1215 xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
1216 status = xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
1219 xm_link_down(hw, port); in bcom_check_link()
1229 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); in bcom_check_link()
1235 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); in bcom_check_link()
1276 struct skge_hw *hw = skge->hw; in bcom_phy_init() local
1296 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); in bcom_phy_init()
1299 r = xm_read16(hw, port, XM_MMU_CMD); in bcom_phy_init()
1301 xm_write16(hw, port, XM_MMU_CMD, r); in bcom_phy_init()
1310 xm_phy_write(hw, port, in bcom_phy_init()
1320 xm_phy_write(hw, port, in bcom_phy_init()
1329 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); in bcom_phy_init()
1331 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); in bcom_phy_init()
1334 xm_read16(hw, port, XM_ISRC); in bcom_phy_init()
1350 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); in bcom_phy_init()
1357 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); in bcom_phy_init()
1361 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, in bcom_phy_init()
1365 if (hw->dev[port]->mtu > ETH_DATA_LEN) { in bcom_phy_init()
1366 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in bcom_phy_init()
1373 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); in bcom_phy_init()
1374 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); in bcom_phy_init()
1377 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in bcom_phy_init()
1382 struct skge_hw *hw = skge->hw; in xm_phy_init() local
1394 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); in xm_phy_init()
1408 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); in xm_phy_init()
1417 struct skge_hw *hw = skge->hw; in xm_check_link() local
1422 xm_phy_read(hw, port, PHY_XMAC_STAT); in xm_check_link()
1423 status = xm_phy_read(hw, port, PHY_XMAC_STAT); in xm_check_link()
1426 xm_link_down(hw, port); in xm_check_link()
1436 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); in xm_check_link()
1442 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); in xm_check_link()
1491 struct skge_hw *hw = skge->hw; in xm_link_timer() local
1499 spin_lock_irqsave(&hw->phy_lock, flags); in xm_link_timer()
1506 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) in xm_link_timer()
1512 u16 msk = xm_read16(hw, port, XM_IMSK); in xm_link_timer()
1514 xm_write16(hw, port, XM_IMSK, msk); in xm_link_timer()
1515 xm_read16(hw, port, XM_ISRC); in xm_link_timer()
1521 spin_unlock_irqrestore(&hw->phy_lock, flags); in xm_link_timer()
1524 static void genesis_mac_init(struct skge_hw *hw, int port) in genesis_mac_init() argument
1526 struct net_device *dev = hw->dev[port]; in genesis_mac_init()
1528 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; in genesis_mac_init()
1534 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in genesis_mac_init()
1536 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) in genesis_mac_init()
1545 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_mac_init()
1552 if (hw->phy_type != SK_PHY_XMAC) { in genesis_mac_init()
1554 r = skge_read32(hw, B2_GP_IO); in genesis_mac_init()
1560 skge_write32(hw, B2_GP_IO, r); in genesis_mac_init()
1563 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); in genesis_mac_init()
1567 switch (hw->phy_type) { in genesis_mac_init()
1573 bcom_check_link(hw, port); in genesis_mac_init()
1577 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in genesis_mac_init()
1581 xm_outaddr(hw, port, XM_EXM(i), zero); in genesis_mac_init()
1584 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1587 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1591 xm_write16(hw, port, XM_RX_HI_WM, 1450); in genesis_mac_init()
1606 xm_write16(hw, port, XM_RX_CMD, r); in genesis_mac_init()
1609 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); in genesis_mac_init()
1612 if (hw->ports > 1 && jumbo) in genesis_mac_init()
1613 xm_write16(hw, port, XM_TX_THR, 1020); in genesis_mac_init()
1615 xm_write16(hw, port, XM_TX_THR, 512); in genesis_mac_init()
1631 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); in genesis_mac_init()
1639 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); in genesis_mac_init()
1646 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); in genesis_mac_init()
1649 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_mac_init()
1652 skge_write8(hw, B3_MA_TOINI_RX1, 72); in genesis_mac_init()
1653 skge_write8(hw, B3_MA_TOINI_RX2, 72); in genesis_mac_init()
1654 skge_write8(hw, B3_MA_TOINI_TX1, 72); in genesis_mac_init()
1655 skge_write8(hw, B3_MA_TOINI_TX2, 72); in genesis_mac_init()
1657 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_mac_init()
1658 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_mac_init()
1659 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_mac_init()
1660 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_mac_init()
1663 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1664 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); in genesis_mac_init()
1665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1668 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1669 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); in genesis_mac_init()
1670 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1674 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); in genesis_mac_init()
1677 skge_write16(hw, B3_PA_CTRL, in genesis_mac_init()
1684 struct skge_hw *hw = skge->hw; in genesis_stop() local
1690 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1692 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_stop()
1694 genesis_reset(hw, port); in genesis_stop()
1697 skge_write16(hw, B3_PA_CTRL, in genesis_stop()
1701 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_stop()
1703 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); in genesis_stop()
1704 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) in genesis_stop()
1709 if (hw->phy_type != SK_PHY_XMAC) { in genesis_stop()
1710 u32 reg = skge_read32(hw, B2_GP_IO); in genesis_stop()
1718 skge_write32(hw, B2_GP_IO, reg); in genesis_stop()
1719 skge_read32(hw, B2_GP_IO); in genesis_stop()
1722 xm_write16(hw, port, XM_MMU_CMD, in genesis_stop()
1723 xm_read16(hw, port, XM_MMU_CMD) in genesis_stop()
1726 xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1732 struct skge_hw *hw = skge->hw; in genesis_get_stats() local
1737 xm_write16(hw, port, in genesis_get_stats()
1741 while (xm_read16(hw, port, XM_STAT_CMD) in genesis_get_stats()
1749 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 in genesis_get_stats()
1750 | xm_read32(hw, port, XM_TXO_OK_LO); in genesis_get_stats()
1751 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 in genesis_get_stats()
1752 | xm_read32(hw, port, XM_RXO_OK_LO); in genesis_get_stats()
1755 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); in genesis_get_stats()
1758 static void genesis_mac_intr(struct skge_hw *hw, int port) in genesis_mac_intr() argument
1760 struct net_device *dev = hw->dev[port]; in genesis_mac_intr()
1762 u16 status = xm_read16(hw, port, XM_ISRC); in genesis_mac_intr()
1767 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { in genesis_mac_intr()
1768 xm_link_down(hw, port); in genesis_mac_intr()
1773 xm_write32(hw, port, XM_MODE, XM_MD_FTF); in genesis_mac_intr()
1780 struct skge_hw *hw = skge->hw; in genesis_link_up() local
1785 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1799 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_link_up()
1801 mode = xm_read32(hw, port, XM_MODE); in genesis_link_up()
1815 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); in genesis_link_up()
1818 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); in genesis_link_up()
1827 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); in genesis_link_up()
1830 xm_write32(hw, port, XM_MODE, mode); in genesis_link_up()
1833 msk = xm_read16(hw, port, XM_IMSK); in genesis_link_up()
1835 xm_write16(hw, port, XM_IMSK, msk); in genesis_link_up()
1837 xm_read16(hw, port, XM_ISRC); in genesis_link_up()
1840 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1841 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) in genesis_link_up()
1848 if (hw->phy_type == SK_PHY_BCOM) { in genesis_link_up()
1849 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in genesis_link_up()
1850 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) in genesis_link_up()
1852 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in genesis_link_up()
1856 xm_write16(hw, port, XM_MMU_CMD, in genesis_link_up()
1864 struct skge_hw *hw = skge->hw; in bcom_phy_intr() local
1868 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); in bcom_phy_intr()
1874 hw->dev[port]->name); in bcom_phy_intr()
1880 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); in bcom_phy_intr()
1881 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1883 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1888 bcom_check_link(hw, port); in bcom_phy_intr()
1892 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in gm_phy_write() argument
1896 gma_write16(hw, port, GM_SMI_DATA, val); in gm_phy_write()
1897 gma_write16(hw, port, GM_SMI_CTRL, in gm_phy_write()
1898 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); in gm_phy_write()
1902 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) in gm_phy_write()
1906 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); in gm_phy_write()
1910 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __gm_phy_read() argument
1914 gma_write16(hw, port, GM_SMI_CTRL, in __gm_phy_read()
1915 GM_SMI_CT_PHY_AD(hw->phy_addr) in __gm_phy_read()
1920 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) in __gm_phy_read()
1926 *val = gma_read16(hw, port, GM_SMI_DATA); in __gm_phy_read()
1930 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) in gm_phy_read() argument
1933 if (__gm_phy_read(hw, port, reg, &v)) in gm_phy_read()
1934 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); in gm_phy_read()
1939 static void yukon_init(struct skge_hw *hw, int port) in yukon_init() argument
1941 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_init()
1945 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); in yukon_init()
1953 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); in yukon_init()
1956 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_init()
1961 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
1968 if (hw->copper) { in yukon_init()
2014 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); in yukon_init()
2016 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); in yukon_init()
2017 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
2021 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); in yukon_init()
2023 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_init()
2026 static void yukon_reset(struct skge_hw *hw, int port) in yukon_reset() argument
2028 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ in yukon_reset()
2029 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ in yukon_reset()
2030 gma_write16(hw, port, GM_MC_ADDR_H2, 0); in yukon_reset()
2031 gma_write16(hw, port, GM_MC_ADDR_H3, 0); in yukon_reset()
2032 gma_write16(hw, port, GM_MC_ADDR_H4, 0); in yukon_reset()
2034 gma_write16(hw, port, GM_RX_CTRL, in yukon_reset()
2035 gma_read16(hw, port, GM_RX_CTRL) in yukon_reset()
2040 static int is_yukon_lite_a0(struct skge_hw *hw) in is_yukon_lite_a0() argument
2045 if (hw->chip_id != CHIP_ID_YUKON) in is_yukon_lite_a0()
2048 reg = skge_read32(hw, B2_FAR); in is_yukon_lite_a0()
2049 skge_write8(hw, B2_FAR + 3, 0xff); in is_yukon_lite_a0()
2050 ret = (skge_read8(hw, B2_FAR + 3) != 0); in is_yukon_lite_a0()
2051 skge_write32(hw, B2_FAR, reg); in is_yukon_lite_a0()
2055 static void yukon_mac_init(struct skge_hw *hw, int port) in yukon_mac_init() argument
2057 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_mac_init()
2060 const u8 *addr = hw->dev[port]->dev_addr; in yukon_mac_init()
2063 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
2064 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
2065 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
2067 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
2071 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_mac_init()
2072 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_mac_init()
2075 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
2076 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
2077 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
2080 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
2086 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; in yukon_mac_init()
2089 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); in yukon_mac_init()
2090 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); in yukon_mac_init()
2091 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); in yukon_mac_init()
2095 gma_write16(hw, port, GM_GP_CTRL, in yukon_mac_init()
2096 gma_read16(hw, port, GM_GP_CTRL) | reg); in yukon_mac_init()
2119 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_mac_init()
2132 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_mac_init()
2133 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_init()
2135 yukon_init(hw, port); in yukon_mac_init()
2138 reg = gma_read16(hw, port, GM_PHY_ADDR); in yukon_mac_init()
2139 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); in yukon_mac_init()
2142 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); in yukon_mac_init()
2143 gma_write16(hw, port, GM_PHY_ADDR, reg); in yukon_mac_init()
2146 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in yukon_mac_init()
2149 gma_write16(hw, port, GM_RX_CTRL, in yukon_mac_init()
2153 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); in yukon_mac_init()
2156 gma_write16(hw, port, GM_TX_PARAM, in yukon_mac_init()
2166 if (hw->dev[port]->mtu > ETH_DATA_LEN) in yukon_mac_init()
2169 gma_write16(hw, port, GM_SERIAL_MODE, reg); in yukon_mac_init()
2172 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); in yukon_mac_init()
2174 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); in yukon_mac_init()
2177 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); in yukon_mac_init()
2178 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); in yukon_mac_init()
2179 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); in yukon_mac_init()
2184 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); in yukon_mac_init()
2188 if (is_yukon_lite_a0(hw)) in yukon_mac_init()
2191 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
2192 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); in yukon_mac_init()
2198 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); in yukon_mac_init()
2201 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
2202 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); in yukon_mac_init()
2206 static void yukon_suspend(struct skge_hw *hw, int port) in yukon_suspend() argument
2210 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in yukon_suspend()
2212 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in yukon_suspend()
2214 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
2216 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
2219 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
2221 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
2226 struct skge_hw *hw = skge->hw; in yukon_stop() local
2229 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in yukon_stop()
2230 yukon_reset(hw, port); in yukon_stop()
2232 gma_write16(hw, port, GM_GP_CTRL, in yukon_stop()
2233 gma_read16(hw, port, GM_GP_CTRL) in yukon_stop()
2235 gma_read16(hw, port, GM_GP_CTRL); in yukon_stop()
2237 yukon_suspend(hw, port); in yukon_stop()
2240 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_stop()
2241 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_stop()
2246 struct skge_hw *hw = skge->hw; in yukon_get_stats() local
2250 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 in yukon_get_stats()
2251 | gma_read32(hw, port, GM_TXO_OK_LO); in yukon_get_stats()
2252 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 in yukon_get_stats()
2253 | gma_read32(hw, port, GM_RXO_OK_LO); in yukon_get_stats()
2256 data[i] = gma_read32(hw, port, in yukon_get_stats()
2260 static void yukon_mac_intr(struct skge_hw *hw, int port) in yukon_mac_intr() argument
2262 struct net_device *dev = hw->dev[port]; in yukon_mac_intr()
2264 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_intr()
2271 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in yukon_mac_intr()
2276 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in yukon_mac_intr()
2281 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) in yukon_speed() argument
2295 struct skge_hw *hw = skge->hw; in yukon_link_up() local
2300 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); in yukon_link_up()
2302 reg = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_up()
2308 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_link_up()
2310 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_link_up()
2316 struct skge_hw *hw = skge->hw; in yukon_link_down() local
2320 ctrl = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_down()
2322 gma_write16(hw, port, GM_GP_CTRL, ctrl); in yukon_link_down()
2325 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); in yukon_link_down()
2328 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); in yukon_link_down()
2333 yukon_init(hw, port); in yukon_link_down()
2338 struct skge_hw *hw = skge->hw; in yukon_phy_intr() local
2343 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); in yukon_phy_intr()
2344 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); in yukon_phy_intr()
2350 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) in yukon_phy_intr()
2356 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { in yukon_phy_intr()
2368 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2387 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_phy_intr()
2389 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in yukon_phy_intr()
2395 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2414 struct skge_hw *hw = skge->hw; in skge_phy_reset() local
2416 struct net_device *dev = hw->dev[port]; in skge_phy_reset()
2421 spin_lock_bh(&hw->phy_lock); in skge_phy_reset()
2422 if (is_genesis(hw)) { in skge_phy_reset()
2423 genesis_reset(hw, port); in skge_phy_reset()
2424 genesis_mac_init(hw, port); in skge_phy_reset()
2426 yukon_reset(hw, port); in skge_phy_reset()
2427 yukon_init(hw, port); in skge_phy_reset()
2429 spin_unlock_bh(&hw->phy_lock); in skge_phy_reset()
2439 struct skge_hw *hw = skge->hw; in skge_ioctl() local
2447 data->phy_id = hw->phy_addr; in skge_ioctl()
2452 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2454 if (is_genesis(hw)) in skge_ioctl()
2455 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2457 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2458 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2464 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2465 if (is_genesis(hw)) in skge_ioctl()
2466 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2469 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2471 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2477 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) in skge_ramset() argument
2485 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2486 skge_write32(hw, RB_ADDR(q, RB_START), start); in skge_ramset()
2487 skge_write32(hw, RB_ADDR(q, RB_WP), start); in skge_ramset()
2488 skge_write32(hw, RB_ADDR(q, RB_RP), start); in skge_ramset()
2489 skge_write32(hw, RB_ADDR(q, RB_END), end); in skge_ramset()
2493 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), in skge_ramset()
2495 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), in skge_ramset()
2501 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2504 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2511 struct skge_hw *hw = skge->hw; in skge_qset() local
2516 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) in skge_qset()
2519 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset()
2520 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset()
2521 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset()
2522 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset()
2528 struct skge_hw *hw = skge->hw; in skge_up() local
2548 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); in skge_up()
2555 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n"); in skge_up()
2575 if (hw->ports == 1) { in skge_up()
2576 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, in skge_up()
2577 dev->name, hw); in skge_up()
2580 hw->pdev->irq, err); in skge_up()
2587 spin_lock_bh(&hw->phy_lock); in skge_up()
2588 if (is_genesis(hw)) in skge_up()
2589 genesis_mac_init(hw, port); in skge_up()
2591 yukon_mac_init(hw, port); in skge_up()
2592 spin_unlock_bh(&hw->phy_lock); in skge_up()
2595 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); in skge_up()
2596 ram_addr = hw->ram_offset + 2 * chunk * port; in skge_up()
2598 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); in skge_up()
2602 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); in skge_up()
2607 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2610 spin_lock_irq(&hw->hw_lock); in skge_up()
2611 hw->intr_mask |= portmask[port]; in skge_up()
2612 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_up()
2613 skge_read32(hw, B0_IMSK); in skge_up()
2614 spin_unlock_irq(&hw->hw_lock); in skge_up()
2628 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); in skge_up()
2635 static void skge_rx_stop(struct skge_hw *hw, int port) in skge_rx_stop() argument
2637 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop()
2638 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_rx_stop()
2640 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop()
2646 struct skge_hw *hw = skge->hw; in skge_down() local
2656 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) in skge_down()
2662 spin_lock_irq(&hw->hw_lock); in skge_down()
2663 hw->intr_mask &= ~portmask[port]; in skge_down()
2664 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); in skge_down()
2665 skge_read32(hw, B0_IMSK); in skge_down()
2666 spin_unlock_irq(&hw->hw_lock); in skge_down()
2668 if (hw->ports == 1) in skge_down()
2669 free_irq(hw->pdev->irq, hw); in skge_down()
2671 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); in skge_down()
2672 if (is_genesis(hw)) in skge_down()
2678 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2679 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2684 skge_write8(hw, SK_REG(port, TXA_CTRL), in skge_down()
2688 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); in skge_down()
2689 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); in skge_down()
2692 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2693 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2696 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
2698 skge_rx_stop(hw, port); in skge_down()
2700 if (is_genesis(hw)) { in skge_down()
2701 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2702 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2704 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2705 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2718 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); in skge_down()
2734 struct skge_hw *hw = skge->hw; in skge_xmit_frame() local
2752 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); in skge_xmit_frame()
2753 if (pci_dma_mapping_error(hw->pdev, map)) in skge_xmit_frame()
2769 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) in skge_xmit_frame()
2789 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, in skge_xmit_frame()
2791 if (dma_mapping_error(&hw->pdev->dev, map)) in skge_xmit_frame()
2815 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame()
2833 pci_unmap_single(hw->pdev, in skge_xmit_frame()
2839 pci_unmap_page(hw->pdev, in skge_xmit_frame()
2847 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); in skge_xmit_frame()
2877 skge_tx_unmap(skge->hw->pdev, e, td->control); in skge_tx_clean()
2894 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); in skge_tx_timeout()
2936 struct skge_hw *hw = skge->hw; in genesis_set_multicast() local
2942 mode = xm_read32(hw, port, XM_MODE); in genesis_set_multicast()
2962 xm_write32(hw, port, XM_MODE, mode); in genesis_set_multicast()
2963 xm_outhash(hw, port, XM_HSM, filter); in genesis_set_multicast()
2975 struct skge_hw *hw = skge->hw; in yukon_set_multicast() local
2985 reg = gma_read16(hw, port, GM_RX_CTRL); in yukon_set_multicast()
3005 gma_write16(hw, port, GM_MC_ADDR_H1, in yukon_set_multicast()
3007 gma_write16(hw, port, GM_MC_ADDR_H2, in yukon_set_multicast()
3009 gma_write16(hw, port, GM_MC_ADDR_H3, in yukon_set_multicast()
3011 gma_write16(hw, port, GM_MC_ADDR_H4, in yukon_set_multicast()
3014 gma_write16(hw, port, GM_RX_CTRL, reg); in yukon_set_multicast()
3017 static inline u16 phy_length(const struct skge_hw *hw, u32 status) in phy_length() argument
3019 if (is_genesis(hw)) in phy_length()
3025 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) in bad_phy_status() argument
3027 if (is_genesis(hw)) in bad_phy_status()
3038 if (is_genesis(skge->hw)) in skge_set_multicast()
3067 if (bad_phy_status(skge->hw, status)) in skge_rx_get()
3070 if (phy_length(skge->hw, status) != len) in skge_rx_get()
3078 pci_dma_sync_single_for_cpu(skge->hw->pdev, in skge_rx_get()
3083 pci_dma_sync_single_for_device(skge->hw->pdev, in skge_rx_get()
3106 pci_unmap_single(skge->hw->pdev, in skge_rx_get()
3128 if (is_genesis(skge->hw)) { in skge_rx_get()
3157 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_tx_done()
3165 skge_tx_unmap(skge->hw->pdev, e, control); in skge_tx_done()
3200 struct skge_hw *hw = skge->hw; in skge_poll() local
3207 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll()
3229 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); in skge_poll()
3235 spin_lock_irqsave(&hw->hw_lock, flags); in skge_poll()
3237 hw->intr_mask |= napimask[skge->port]; in skge_poll()
3238 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_poll()
3239 skge_read32(hw, B0_IMSK); in skge_poll()
3240 spin_unlock_irqrestore(&hw->hw_lock, flags); in skge_poll()
3249 static void skge_mac_parity(struct skge_hw *hw, int port) in skge_mac_parity() argument
3251 struct net_device *dev = hw->dev[port]; in skge_mac_parity()
3255 if (is_genesis(hw)) in skge_mac_parity()
3256 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in skge_mac_parity()
3260 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), in skge_mac_parity()
3261 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in skge_mac_parity()
3265 static void skge_mac_intr(struct skge_hw *hw, int port) in skge_mac_intr() argument
3267 if (is_genesis(hw)) in skge_mac_intr()
3268 genesis_mac_intr(hw, port); in skge_mac_intr()
3270 yukon_mac_intr(hw, port); in skge_mac_intr()
3274 static void skge_error_irq(struct skge_hw *hw) in skge_error_irq() argument
3276 struct pci_dev *pdev = hw->pdev; in skge_error_irq()
3277 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
3279 if (is_genesis(hw)) { in skge_error_irq()
3282 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); in skge_error_irq()
3284 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); in skge_error_irq()
3288 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in skge_error_irq()
3293 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); in skge_error_irq()
3298 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); in skge_error_irq()
3302 skge_mac_parity(hw, 0); in skge_error_irq()
3305 skge_mac_parity(hw, 1); in skge_error_irq()
3309 hw->dev[0]->name); in skge_error_irq()
3310 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); in skge_error_irq()
3315 hw->dev[1]->name); in skge_error_irq()
3316 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); in skge_error_irq()
3330 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_error_irq()
3334 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_error_irq()
3337 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
3339 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); in skge_error_irq()
3340 hw->intr_mask &= ~IS_HW_ERR; in skge_error_irq()
3352 struct skge_hw *hw = (struct skge_hw *) arg; in skge_extirq() local
3355 for (port = 0; port < hw->ports; port++) { in skge_extirq()
3356 struct net_device *dev = hw->dev[port]; in skge_extirq()
3361 spin_lock(&hw->phy_lock); in skge_extirq()
3362 if (!is_genesis(hw)) in skge_extirq()
3364 else if (hw->phy_type == SK_PHY_BCOM) in skge_extirq()
3366 spin_unlock(&hw->phy_lock); in skge_extirq()
3370 spin_lock_irq(&hw->hw_lock); in skge_extirq()
3371 hw->intr_mask |= IS_EXT_REG; in skge_extirq()
3372 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_extirq()
3373 skge_read32(hw, B0_IMSK); in skge_extirq()
3374 spin_unlock_irq(&hw->hw_lock); in skge_extirq()
3379 struct skge_hw *hw = dev_id; in skge_intr() local
3383 spin_lock(&hw->hw_lock); in skge_intr()
3385 status = skge_read32(hw, B0_SP_ISRC); in skge_intr()
3390 status &= hw->intr_mask; in skge_intr()
3392 hw->intr_mask &= ~IS_EXT_REG; in skge_intr()
3393 tasklet_schedule(&hw->phy_task); in skge_intr()
3397 struct skge_port *skge = netdev_priv(hw->dev[0]); in skge_intr()
3398 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); in skge_intr()
3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); in skge_intr()
3406 ++hw->dev[0]->stats.rx_over_errors; in skge_intr()
3407 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); in skge_intr()
3412 skge_mac_intr(hw, 0); in skge_intr()
3414 if (hw->dev[1]) { in skge_intr()
3415 struct skge_port *skge = netdev_priv(hw->dev[1]); in skge_intr()
3418 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); in skge_intr()
3423 ++hw->dev[1]->stats.rx_over_errors; in skge_intr()
3424 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); in skge_intr()
3428 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); in skge_intr()
3431 skge_mac_intr(hw, 1); in skge_intr()
3435 skge_error_irq(hw); in skge_intr()
3437 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_intr()
3438 skge_read32(hw, B0_IMSK); in skge_intr()
3439 spin_unlock(&hw->hw_lock); in skge_intr()
3450 skge_intr(dev->irq, skge->hw); in skge_netpoll()
3458 struct skge_hw *hw = skge->hw; in skge_set_mac_address() local
3469 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3470 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3473 spin_lock_bh(&hw->phy_lock); in skge_set_mac_address()
3474 ctrl = gma_read16(hw, port, GM_GP_CTRL); in skge_set_mac_address()
3475 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); in skge_set_mac_address()
3477 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3478 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3480 if (is_genesis(hw)) in skge_set_mac_address()
3481 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in skge_set_mac_address()
3483 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); in skge_set_mac_address()
3484 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); in skge_set_mac_address()
3487 gma_write16(hw, port, GM_GP_CTRL, ctrl); in skge_set_mac_address()
3488 spin_unlock_bh(&hw->phy_lock); in skge_set_mac_address()
3504 static const char *skge_board_name(const struct skge_hw *hw) in skge_board_name() argument
3510 if (skge_chips[i].id == hw->chip_id) in skge_board_name()
3513 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); in skge_board_name()
3522 static int skge_reset(struct skge_hw *hw) in skge_reset() argument
3529 ctst = skge_read16(hw, B0_CTST); in skge_reset()
3532 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_reset()
3533 skge_write8(hw, B0_CTST, CS_RST_CLR); in skge_reset()
3536 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3537 skge_write8(hw, B2_TST_CTRL2, 0); in skge_reset()
3539 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); in skge_reset()
3540 pci_write_config_word(hw->pdev, PCI_STATUS, in skge_reset()
3542 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3543 skge_write8(hw, B0_CTST, CS_MRST_CLR); in skge_reset()
3546 skge_write16(hw, B0_CTST, in skge_reset()
3549 hw->chip_id = skge_read8(hw, B2_CHIP_ID); in skge_reset()
3550 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; in skge_reset()
3551 pmd_type = skge_read8(hw, B2_PMD_TYP); in skge_reset()
3552 hw->copper = (pmd_type == 'T' || pmd_type == '1'); in skge_reset()
3554 switch (hw->chip_id) { in skge_reset()
3557 switch (hw->phy_type) { in skge_reset()
3559 hw->phy_addr = PHY_ADDR_XMAC; in skge_reset()
3562 hw->phy_addr = PHY_ADDR_BCOM; in skge_reset()
3565 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", in skge_reset()
3566 hw->phy_type); in skge_reset()
3571 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); in skge_reset()
3578 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') in skge_reset()
3579 hw->copper = 1; in skge_reset()
3581 hw->phy_addr = PHY_ADDR_MARV; in skge_reset()
3585 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", in skge_reset()
3586 hw->chip_id); in skge_reset()
3590 mac_cfg = skge_read8(hw, B2_MAC_CFG); in skge_reset()
3591 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; in skge_reset()
3592 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; in skge_reset()
3595 t8 = skge_read8(hw, B2_E_0); in skge_reset()
3596 if (is_genesis(hw)) { in skge_reset()
3599 hw->ram_size = 0x100000; in skge_reset()
3600 hw->ram_offset = 0x80000; in skge_reset()
3602 hw->ram_size = t8 * 512; in skge_reset()
3604 hw->ram_size = 0x20000; in skge_reset()
3606 hw->ram_size = t8 * 4096; in skge_reset()
3608 hw->intr_mask = IS_HW_ERR; in skge_reset()
3611 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) in skge_reset()
3612 hw->intr_mask |= IS_EXT_REG; in skge_reset()
3614 if (is_genesis(hw)) in skge_reset()
3615 genesis_init(hw); in skge_reset()
3618 skge_write8(hw, B0_POWER_CTRL, in skge_reset()
3622 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && in skge_reset()
3623 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { in skge_reset()
3624 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); in skge_reset()
3625 hw->intr_mask &= ~IS_HW_ERR; in skge_reset()
3629 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3630 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); in skge_reset()
3632 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); in skge_reset()
3633 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3636 for (i = 0; i < hw->ports; i++) { in skge_reset()
3637 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); in skge_reset()
3638 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_reset()
3643 skge_write8(hw, B2_TI_CTRL, TIM_STOP); in skge_reset()
3644 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); in skge_reset()
3645 skge_write8(hw, B0_LED, LED_STAT_ON); in skge_reset()
3648 for (i = 0; i < hw->ports; i++) in skge_reset()
3649 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); in skge_reset()
3652 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); in skge_reset()
3654 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); in skge_reset()
3655 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); in skge_reset()
3656 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); in skge_reset()
3657 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); in skge_reset()
3658 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); in skge_reset()
3659 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); in skge_reset()
3660 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); in skge_reset()
3661 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); in skge_reset()
3662 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); in skge_reset()
3663 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); in skge_reset()
3664 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); in skge_reset()
3665 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); in skge_reset()
3667 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); in skge_reset()
3672 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); in skge_reset()
3673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); in skge_reset()
3674 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_reset()
3677 skge_write32(hw, B0_IMSK, 0); in skge_reset()
3679 for (i = 0; i < hw->ports; i++) { in skge_reset()
3680 if (is_genesis(hw)) in skge_reset()
3681 genesis_reset(hw, i); in skge_reset()
3683 yukon_reset(hw, i); in skge_reset()
3698 const struct skge_hw *hw = skge->hw; in skge_debug_show() local
3704 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), in skge_debug_show()
3705 skge_read32(hw, B0_IMSK)); in skge_debug_show()
3845 static struct net_device *skge_devinit(struct skge_hw *hw, int port, in skge_devinit() argument
3854 SET_NETDEV_DEV(dev, &hw->pdev->dev); in skge_devinit()
3858 dev->irq = hw->pdev->irq; in skge_devinit()
3866 skge->hw = hw; in skge_devinit()
3877 skge->advertising = skge_supported_modes(hw); in skge_devinit()
3879 if (device_can_wakeup(&hw->pdev->dev)) { in skge_devinit()
3880 skge->wol = wol_supported(hw) & WAKE_MAGIC; in skge_devinit()
3881 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); in skge_devinit()
3884 hw->dev[port] = dev; in skge_devinit()
3889 if (is_genesis(hw)) in skge_devinit()
3898 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); in skge_devinit()
3915 struct skge_hw *hw; in skge_probe() local
3958 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") in skge_probe()
3960 if (!hw) in skge_probe()
3963 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); in skge_probe()
3965 hw->pdev = pdev; in skge_probe()
3966 spin_lock_init(&hw->hw_lock); in skge_probe()
3967 spin_lock_init(&hw->phy_lock); in skge_probe()
3968 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw); in skge_probe()
3970 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); in skge_probe()
3971 if (!hw->regs) { in skge_probe()
3976 err = skge_reset(hw); in skge_probe()
3983 skge_board_name(hw), hw->chip_rev); in skge_probe()
3985 dev = skge_devinit(hw, 0, using_dac); in skge_probe()
4003 if (hw->ports > 1) { in skge_probe()
4004 dev1 = skge_devinit(hw, 1, using_dac); in skge_probe()
4017 hw->irq_name, hw); in skge_probe()
4026 pci_set_drvdata(pdev, hw); in skge_probe()
4039 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_probe()
4041 iounmap(hw->regs); in skge_probe()
4043 kfree(hw); in skge_probe()
4054 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_remove() local
4057 if (!hw) in skge_remove()
4060 dev1 = hw->dev[1]; in skge_remove()
4063 dev0 = hw->dev[0]; in skge_remove()
4066 tasklet_kill(&hw->phy_task); in skge_remove()
4068 spin_lock_irq(&hw->hw_lock); in skge_remove()
4069 hw->intr_mask = 0; in skge_remove()
4071 if (hw->ports > 1) { in skge_remove()
4072 skge_write32(hw, B0_IMSK, 0); in skge_remove()
4073 skge_read32(hw, B0_IMSK); in skge_remove()
4074 free_irq(pdev->irq, hw); in skge_remove()
4076 spin_unlock_irq(&hw->hw_lock); in skge_remove()
4078 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_remove()
4079 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_remove()
4081 if (hw->ports > 1) in skge_remove()
4082 free_irq(pdev->irq, hw); in skge_remove()
4089 iounmap(hw->regs); in skge_remove()
4090 kfree(hw); in skge_remove()
4097 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_suspend() local
4100 if (!hw) in skge_suspend()
4103 for (i = 0; i < hw->ports; i++) { in skge_suspend()
4104 struct net_device *dev = hw->dev[i]; in skge_suspend()
4114 skge_write32(hw, B0_IMSK, 0); in skge_suspend()
4122 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_resume() local
4125 if (!hw) in skge_resume()
4128 err = skge_reset(hw); in skge_resume()
4132 for (i = 0; i < hw->ports; i++) { in skge_resume()
4133 struct net_device *dev = hw->dev[i]; in skge_resume()
4159 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_shutdown() local
4162 if (!hw) in skge_shutdown()
4165 for (i = 0; i < hw->ports; i++) { in skge_shutdown()
4166 struct net_device *dev = hw->dev[i]; in skge_shutdown()