94 	minfo->hw.DACclk[0] = m;  in DAC1064_setpclk()
95 	minfo->hw.DACclk[1] = n;  in DAC1064_setpclk()
96 	minfo->hw.DACclk[2] = p;  in DAC1064_setpclk()
103 	struct matrox_hw_state *hw = &minfo->hw;  in DAC1064_setmclk()  local
109 		hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);  in DAC1064_setmclk()
110 		hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);  in DAC1064_setmclk()
111 		hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);  in DAC1064_setmclk()
114 	mx = hw->MXoptionReg | 0x00000004;  in DAC1064_setmclk()
142 		outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);  in DAC1064_setmclk()
143 		outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);  in DAC1064_setmclk()
144 		outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);  in DAC1064_setmclk()
160 	hw->MXoptionReg = mx;  in DAC1064_setmclk()
168 	struct matrox_hw_state *hw = &minfo->hw;  in g450_set_plls()  local
172 	c2_ctl = hw->crtc2.ctl & ~0x4007;	/* Clear PLL + enable for CRTC2 */  in g450_set_plls()
174 	hw->DACreg[POS1064_XPWRCTRL] &= ~0x02;	/* Stop VIDEO PLL */  in g450_set_plls()
179 		hw->DACreg[POS1064_XPWRCTRL] &= ~0x10;	/* Powerdown CRTC2 */  in g450_set_plls()
193 		hw->DACreg[POS1064_XPWRCTRL] |= 0x02;  in g450_set_plls()
195 		outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);  in g450_set_plls()
199 	hw->DACreg[POS1064_XPIXCLKCTRL] &= ~M1064_XPIXCLKCTRL_PLL_UP;  in g450_set_plls()
201 		hw->DACreg[POS1064_XPIXCLKCTRL] |= M1064_XPIXCLKCTRL_PLL_UP;  in g450_set_plls()
203 		outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);  in g450_set_plls()
206 	if (c2_ctl != hw->crtc2.ctl) {  in g450_set_plls()
207 		hw->crtc2.ctl = c2_ctl;  in g450_set_plls()
217 			hw->DACreg[POS1064_XPANMODE] = 0x00;	/* 0-50 */  in g450_set_plls()
219 			hw->DACreg[POS1064_XPANMODE] = 0x08;	/* 34-62 */  in g450_set_plls()
221 			hw->DACreg[POS1064_XPANMODE] = 0x10;	/* 42-78 */  in g450_set_plls()
223 			hw->DACreg[POS1064_XPANMODE] = 0x18;	/* 62-92 */  in g450_set_plls()
225 			hw->DACreg[POS1064_XPANMODE] = 0x20;	/* 74-108 */  in g450_set_plls()
227 			hw->DACreg[POS1064_XPANMODE] = 0x28;	/* 94-122 */  in g450_set_plls()
229 			hw->DACreg[POS1064_XPANMODE] = 0x30;	/* 108-132 */  in g450_set_plls()
231 			hw->DACreg[POS1064_XPANMODE] = 0x38;	/* 120-168 */  in g450_set_plls()
236 			hw->DACreg[POS1064_XPANMODE] = 0x00;	/* 0-54 */  in g450_set_plls()
238 			hw->DACreg[POS1064_XPANMODE] = 0x08;	/* 38-70 */  in g450_set_plls()
240 			hw->DACreg[POS1064_XPANMODE] = 0x10;	/* 56-96 */  in g450_set_plls()
242 			hw->DACreg[POS1064_XPANMODE] = 0x18;	/* 80-114 */  in g450_set_plls()
244 			hw->DACreg[POS1064_XPANMODE] = 0x20;	/* 102-144 */  in g450_set_plls()
246 			hw->DACreg[POS1064_XPANMODE] = 0x28;	/* 132-166 */  in g450_set_plls()
248 			hw->DACreg[POS1064_XPANMODE] = 0x30;	/* 154-182 */  in g450_set_plls()
250 			hw->DACreg[POS1064_XPANMODE] = 0x38;	/* 170-204 */  in g450_set_plls()
258 	struct matrox_hw_state *hw = &minfo->hw;  in DAC1064_global_init()  local
260 	hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK;  in DAC1064_global_init()
261 	hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN;  in DAC1064_global_init()
262 …hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKC…  in DAC1064_global_init()
265 		hw->DACreg[POS1064_XPWRCTRL] = 0x1F;	/* powerup everything */  in DAC1064_global_init()
266 		hw->DACreg[POS1064_XOUTPUTCONN] = 0x00;	/* disable outputs */  in DAC1064_global_init()
267 		hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;  in DAC1064_global_init()
271 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01;	/* enable output; CRTC1/2 selection is in CRTC2 ctl */  in DAC1064_global_init()
274 				hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN;  in DAC1064_global_init()
279 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04;  in DAC1064_global_init()
283 					hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08;  in DAC1064_global_init()
285 					hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C;  in DAC1064_global_init()
289 				hw->DACreg[POS1064_XPWRCTRL] &= ~0x01;		/* Poweroff DAC2 */  in DAC1064_global_init()
294 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20;  in DAC1064_global_init()
297 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x40;  in DAC1064_global_init()
306 				hw->DACreg[POS1064_XPWRCTRL] &= ~0x04;		/* Poweroff TMDS */  in DAC1064_global_init()
316 …hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKC…  in DAC1064_global_init()
317 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12;  in DAC1064_global_init()
319 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12;  in DAC1064_global_init()
321 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12;  in DAC1064_global_init()
323 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS;  in DAC1064_global_init()
326 			hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;  in DAC1064_global_init()
332 	struct matrox_hw_state *hw = &minfo->hw;  in DAC1064_global_restore()  local
334 	outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);  in DAC1064_global_restore()
335 	outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);  in DAC1064_global_restore()
341 			outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);  in DAC1064_global_restore()
342 			outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);  in DAC1064_global_restore()
343 			outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]);  in DAC1064_global_restore()
350 	struct matrox_hw_state *hw = &minfo->hw;  in DAC1064_init_1()  local
354 	memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs));  in DAC1064_init_1()
358 			hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;  in DAC1064_init_1()
362 …hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;  in DAC1064_init_1()
364 				hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;  in DAC1064_init_1()
367 			hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_24BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;  in DAC1064_init_1()
370 			hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_32BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;  in DAC1064_init_1()
375 	hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;  in DAC1064_init_1()
376 	hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK;  in DAC1064_init_1()
377 …hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XG…  in DAC1064_init_1()
378 	hw->DACreg[POS1064_XCURADDL] = 0;  in DAC1064_init_1()
379 	hw->DACreg[POS1064_XCURADDH] = 0;  in DAC1064_init_1()
387 	struct matrox_hw_state *hw = &minfo->hw;  in DAC1064_init_2()  local
395 			hw->DACpal[i * 3 + 0] = i;  in DAC1064_init_2()
396 			hw->DACpal[i * 3 + 1] = i;  in DAC1064_init_2()
397 			hw->DACpal[i * 3 + 2] = i;  in DAC1064_init_2()
405 				hw->DACpal[i * 3 + 0] = i << 3;  in DAC1064_init_2()
406 				hw->DACpal[i * 3 + 1] = i << 3;  in DAC1064_init_2()
407 				hw->DACpal[i * 3 + 2] = i << 3;  in DAC1064_init_2()
409 				hw->DACpal[(i + 128) * 3 + 0] = i << 3;  in DAC1064_init_2()
410 				hw->DACpal[(i + 128) * 3 + 1] = i << 3;  in DAC1064_init_2()
411 				hw->DACpal[(i + 128) * 3 + 2] = i << 3;  in DAC1064_init_2()
417 				hw->DACpal[i * 3 + 0] = i << 3;  in DAC1064_init_2()
418 				hw->DACpal[i * 3 + 1] = i << 2;  in DAC1064_init_2()
419 				hw->DACpal[i * 3 + 2] = i << 3;  in DAC1064_init_2()
423 		memset(hw->DACpal, 0, 768);  in DAC1064_init_2()
430 	struct matrox_hw_state *hw = &minfo->hw;  in DAC1064_restore_1()  local
438 	if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) ||  in DAC1064_restore_1()
439 	    (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) ||  in DAC1064_restore_1()
440 	    (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) {  in DAC1064_restore_1()
441 		outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]);  in DAC1064_restore_1()
442 		outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]);  in DAC1064_restore_1()
443 		outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]);  in DAC1064_restore_1()
450 				outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);  in DAC1064_restore_1()
470 		dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);  in DAC1064_restore_2()
475 		dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);  in DAC1064_restore_2()
492 			outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);  in m1064_compute()
537 	struct matrox_hw_state *hw = &minfo->hw;  in MGA1064_init()  local
544 	hw->MiscOutReg = 0xCB;  in MGA1064_init()
546 		hw->MiscOutReg &= ~0x40;  in MGA1064_init()
548 		hw->MiscOutReg &= ~0x80;  in MGA1064_init()
550 		hw->CRTCEXT[3] |= 0x40;  in MGA1064_init()
560 	struct matrox_hw_state *hw = &minfo->hw;  in MGAG100_init()  local
565 	hw->MXoptionReg &= ~0x2000;  in MGAG100_init()
568 	hw->MiscOutReg = 0xEF;  in MGAG100_init()
570 		hw->MiscOutReg &= ~0x40;  in MGAG100_init()
572 		hw->MiscOutReg &= ~0x80;  in MGAG100_init()
574 		hw->CRTCEXT[3] |= 0x40;  in MGAG100_init()
673 	struct matrox_hw_state *hw = &minfo->hw;  in MGA1064_preinit()  local
688 	hw->MXoptionReg &= 0xC0000100;  in MGA1064_preinit()
689 	hw->MXoptionReg |= 0x00094E20;  in MGA1064_preinit()
691 		hw->MXoptionReg &= ~0x00000100;  in MGA1064_preinit()
693 		hw->MXoptionReg &= ~0x40000000;  in MGA1064_preinit()
695 		hw->MXoptionReg |=  0x20000000;  in MGA1064_preinit()
696 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGA1064_preinit()
719 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);  in g450_mclk_init()
721 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);  in g450_mclk_init()
739 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);  in g450_mclk_init()
741 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);  in g450_mclk_init()
748 	minfo->hw.MXoptionReg &= ~0x001F8000;  in g450_memory_init()
749 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);  in g450_memory_init()
752 	minfo->hw.MXoptionReg &= ~0x00207E00;  in g450_memory_init()
753 	minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;  in g450_memory_init()
754 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);  in g450_memory_init()
775 	minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;  in g450_memory_init()
776 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);  in g450_memory_init()
795 	minfo->hw.MXoptionReg &= 0xC0000100;  in g450_preinit()
796 	minfo->hw.MXoptionReg |= 0x00000020;  in g450_preinit()
798 		minfo->hw.MXoptionReg &= ~0x00000100;  in g450_preinit()
800 		minfo->hw.MXoptionReg &= ~0x40000000;  in g450_preinit()
802 		minfo->hw.MXoptionReg |=  0x20000000;  in g450_preinit()
803 	minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;  in g450_preinit()
804 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);  in g450_preinit()
842 	struct matrox_hw_state *hw = &minfo->hw;  in MGAG100_preinit()  local
892 	hw->MXoptionReg &= 0xC0000100;  in MGAG100_preinit()
893 	hw->MXoptionReg |= 0x00000020;  in MGAG100_preinit()
895 		hw->MXoptionReg &= ~0x00000100;  in MGAG100_preinit()
897 		hw->MXoptionReg &= ~0x40000000;  in MGAG100_preinit()
899 		hw->MXoptionReg |=  0x20000000;  in MGAG100_preinit()
900 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGAG100_preinit()
908 		hw->MXoptionReg |= 0x1080;  in MGAG100_preinit()
909 		pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGAG100_preinit()
931 			hw->MXoptionReg &= ~0x1000;  in MGAG100_preinit()
934 		hw->MXoptionReg |= 0x00078020;  in MGAG100_preinit()
941 			hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;  in MGAG100_preinit()
943 			hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;  in MGAG100_preinit()
945 			hw->MXoptionReg |= 0x4000;  in MGAG100_preinit()
953 		hw->MXoptionReg |= 0x00078020;  in MGAG100_preinit()
961 			hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;  in MGAG100_preinit()
963 			hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;  in MGAG100_preinit()
965 			hw->MXoptionReg |= 0x4000;  in MGAG100_preinit()
973 		hw->MXoptionReg |= 0x00040020;  in MGAG100_preinit()
975 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGAG100_preinit()
982 	struct matrox_hw_state *hw = &minfo->hw;  in MGAG100_reset()  local
1001 				hw->MXoptionReg |= 0x40;	/* FIXME... */  in MGAG100_reset()
1002 				pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGAG100_reset()
1009 		hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);  in MGAG100_reset()
1010 		hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);  in MGAG100_reset()
1011 		hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);  in MGAG100_reset()
1040 	struct matrox_hw_state *hw = &minfo->hw;  in MGA1064_restore()  local
1048 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGA1064_restore()
1058 		mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);  in MGA1064_restore()
1067 	struct matrox_hw_state *hw = &minfo->hw;  in MGAG100_restore()  local
1075 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);  in MGAG100_restore()
1081 		mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]);  in MGAG100_restore()
1084 		mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);  in MGAG100_restore()