Lines Matching refs:hw
257 static s32 atl1_reset_hw(struct atl1_hw *hw) in atl1_reset_hw() argument
259 struct pci_dev *pdev = hw->back->pdev; in atl1_reset_hw()
260 struct atl1_adapter *adapter = hw->back; in atl1_reset_hw()
279 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); in atl1_reset_hw()
280 ioread32(hw->hw_addr + REG_MASTER_CTRL); in atl1_reset_hw()
282 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); in atl1_reset_hw()
283 ioread16(hw->hw_addr + REG_PHY_ENABLE); in atl1_reset_hw()
290 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); in atl1_reset_hw()
313 static int atl1_check_eeprom_exist(struct atl1_hw *hw) in atl1_check_eeprom_exist() argument
316 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_check_eeprom_exist()
319 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_check_eeprom_exist()
322 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); in atl1_check_eeprom_exist()
326 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) in atl1_read_eeprom() argument
335 iowrite32(0, hw->hw_addr + REG_VPD_DATA); in atl1_read_eeprom()
337 iowrite32(control, hw->hw_addr + REG_VPD_CAP); in atl1_read_eeprom()
338 ioread32(hw->hw_addr + REG_VPD_CAP); in atl1_read_eeprom()
342 control = ioread32(hw->hw_addr + REG_VPD_CAP); in atl1_read_eeprom()
347 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); in atl1_read_eeprom()
359 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) in atl1_read_phy_reg() argument
367 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); in atl1_read_phy_reg()
368 ioread32(hw->hw_addr + REG_MDIO_CTRL); in atl1_read_phy_reg()
372 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); in atl1_read_phy_reg()
389 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) in atl1_spi_read() argument
394 iowrite32(0, hw->hw_addr + REG_SPI_DATA); in atl1_spi_read()
395 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); in atl1_spi_read()
410 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
413 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
414 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
418 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
426 *buf = ioread32(hw->hw_addr + REG_SPI_DATA); in atl1_spi_read()
435 static int atl1_get_permanent_address(struct atl1_hw *hw) in atl1_get_permanent_address() argument
443 if (is_valid_ether_addr(hw->perm_mac_addr)) in atl1_get_permanent_address()
449 if (!atl1_check_eeprom_exist(hw)) { in atl1_get_permanent_address()
455 if (atl1_read_eeprom(hw, i + 0x100, &control)) { in atl1_get_permanent_address()
476 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); in atl1_get_permanent_address()
487 if (atl1_spi_read(hw, i + 0x1f000, &control)) { in atl1_get_permanent_address()
509 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); in atl1_get_permanent_address()
519 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); in atl1_get_permanent_address()
520 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); in atl1_get_permanent_address()
524 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); in atl1_get_permanent_address()
535 static s32 atl1_read_mac_addr(struct atl1_hw *hw) in atl1_read_mac_addr() argument
540 if (atl1_get_permanent_address(hw)) { in atl1_read_mac_addr()
541 eth_random_addr(hw->perm_mac_addr); in atl1_read_mac_addr()
546 hw->mac_addr[i] = hw->perm_mac_addr[i]; in atl1_read_mac_addr()
562 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) in atl1_hash_mc_addr() argument
579 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) in atl1_hash_set() argument
595 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); in atl1_hash_set()
597 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); in atl1_hash_set()
606 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) in atl1_write_phy_reg() argument
615 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); in atl1_write_phy_reg()
616 ioread32(hw->hw_addr + REG_MDIO_CTRL); in atl1_write_phy_reg()
620 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); in atl1_write_phy_reg()
637 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) in atl1_phy_leave_power_saving() argument
640 ret = atl1_write_phy_reg(hw, 29, 0x0029); in atl1_phy_leave_power_saving()
643 return atl1_write_phy_reg(hw, 30, 0); in atl1_phy_leave_power_saving()
652 static s32 atl1_phy_reset(struct atl1_hw *hw) in atl1_phy_reset() argument
654 struct pci_dev *pdev = hw->back->pdev; in atl1_phy_reset()
655 struct atl1_adapter *adapter = hw->back; in atl1_phy_reset()
659 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_phy_reset()
660 hw->media_type == MEDIA_TYPE_1000M_FULL) in atl1_phy_reset()
663 switch (hw->media_type) { in atl1_phy_reset()
683 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); in atl1_phy_reset()
693 val = ioread32(hw->hw_addr + REG_MDIO_CTRL); in atl1_phy_reset()
712 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) in atl1_phy_setup_autoneg_adv() argument
736 switch (hw->media_type) { in atl1_phy_setup_autoneg_adv()
769 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; in atl1_phy_setup_autoneg_adv()
770 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; in atl1_phy_setup_autoneg_adv()
772 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); in atl1_phy_setup_autoneg_adv()
776 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); in atl1_phy_setup_autoneg_adv()
789 static s32 atl1_setup_link(struct atl1_hw *hw) in atl1_setup_link() argument
791 struct pci_dev *pdev = hw->back->pdev; in atl1_setup_link()
792 struct atl1_adapter *adapter = hw->back; in atl1_setup_link()
801 ret_val = atl1_phy_setup_autoneg_adv(hw); in atl1_setup_link()
809 ret_val = atl1_phy_reset(hw); in atl1_setup_link()
815 hw->phy_configured = true; in atl1_setup_link()
819 static void atl1_init_flash_opcode(struct atl1_hw *hw) in atl1_init_flash_opcode() argument
821 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) in atl1_init_flash_opcode()
823 hw->flash_vendor = 0; in atl1_init_flash_opcode()
826 iowrite8(flash_table[hw->flash_vendor].cmd_program, in atl1_init_flash_opcode()
827 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); in atl1_init_flash_opcode()
828 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, in atl1_init_flash_opcode()
829 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); in atl1_init_flash_opcode()
830 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, in atl1_init_flash_opcode()
831 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); in atl1_init_flash_opcode()
832 iowrite8(flash_table[hw->flash_vendor].cmd_rdid, in atl1_init_flash_opcode()
833 hw->hw_addr + REG_SPI_FLASH_OP_RDID); in atl1_init_flash_opcode()
834 iowrite8(flash_table[hw->flash_vendor].cmd_wren, in atl1_init_flash_opcode()
835 hw->hw_addr + REG_SPI_FLASH_OP_WREN); in atl1_init_flash_opcode()
836 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, in atl1_init_flash_opcode()
837 hw->hw_addr + REG_SPI_FLASH_OP_RDSR); in atl1_init_flash_opcode()
838 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, in atl1_init_flash_opcode()
839 hw->hw_addr + REG_SPI_FLASH_OP_WRSR); in atl1_init_flash_opcode()
840 iowrite8(flash_table[hw->flash_vendor].cmd_read, in atl1_init_flash_opcode()
841 hw->hw_addr + REG_SPI_FLASH_OP_READ); in atl1_init_flash_opcode()
852 static s32 atl1_init_hw(struct atl1_hw *hw) in atl1_init_hw() argument
857 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); in atl1_init_hw()
859 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); in atl1_init_hw()
861 atl1_init_flash_opcode(hw); in atl1_init_hw()
863 if (!hw->phy_configured) { in atl1_init_hw()
865 ret_val = atl1_write_phy_reg(hw, 18, 0xC00); in atl1_init_hw()
869 ret_val = atl1_phy_leave_power_saving(hw); in atl1_init_hw()
873 ret_val = atl1_setup_link(hw); in atl1_init_hw()
884 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) in atl1_get_speed_and_duplex() argument
886 struct pci_dev *pdev = hw->back->pdev; in atl1_get_speed_and_duplex()
887 struct atl1_adapter *adapter = hw->back; in atl1_get_speed_and_duplex()
892 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); in atl1_get_speed_and_duplex()
922 static void atl1_set_mac_addr(struct atl1_hw *hw) in atl1_set_mac_addr() argument
930 value = (((u32) hw->mac_addr[2]) << 24) | in atl1_set_mac_addr()
931 (((u32) hw->mac_addr[3]) << 16) | in atl1_set_mac_addr()
932 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); in atl1_set_mac_addr()
933 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); in atl1_set_mac_addr()
935 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); in atl1_set_mac_addr()
936 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); in atl1_set_mac_addr()
949 struct atl1_hw *hw = &adapter->hw; in atl1_sw_init() local
952 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in atl1_sw_init()
953 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; in atl1_sw_init()
957 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; in atl1_sw_init()
962 hw->phy_configured = false; in atl1_sw_init()
963 hw->preamble_len = 7; in atl1_sw_init()
964 hw->ipgt = 0x60; in atl1_sw_init()
965 hw->min_ifg = 0x50; in atl1_sw_init()
966 hw->ipgr1 = 0x40; in atl1_sw_init()
967 hw->ipgr2 = 0x60; in atl1_sw_init()
968 hw->max_retry = 0xf; in atl1_sw_init()
969 hw->lcol = 0x37; in atl1_sw_init()
970 hw->jam_ipg = 7; in atl1_sw_init()
971 hw->rfd_burst = 8; in atl1_sw_init()
972 hw->rrd_burst = 8; in atl1_sw_init()
973 hw->rfd_fetch_gap = 1; in atl1_sw_init()
974 hw->rx_jumbo_th = adapter->rx_buffer_len / 8; in atl1_sw_init()
975 hw->rx_jumbo_lkah = 1; in atl1_sw_init()
976 hw->rrd_ret_timer = 16; in atl1_sw_init()
977 hw->tpd_burst = 4; in atl1_sw_init()
978 hw->tpd_fetch_th = 16; in atl1_sw_init()
979 hw->txf_burst = 0x100; in atl1_sw_init()
980 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; in atl1_sw_init()
981 hw->tpd_fetch_gap = 1; in atl1_sw_init()
982 hw->rcb_value = atl1_rcb_64; in atl1_sw_init()
983 hw->dma_ord = atl1_dma_ord_enh; in atl1_sw_init()
984 hw->dmar_block = atl1_dma_req_256; in atl1_sw_init()
985 hw->dmaw_block = atl1_dma_req_256; in atl1_sw_init()
986 hw->cmb_rrd = 4; in atl1_sw_init()
987 hw->cmb_tpd = 4; in atl1_sw_init()
988 hw->cmb_rx_timer = 1; /* about 2us */ in atl1_sw_init()
989 hw->cmb_tx_timer = 1; /* about 2us */ in atl1_sw_init()
990 hw->smb_timer = 100000; /* about 200ms */ in atl1_sw_init()
1003 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); in mdio_read()
1013 atl1_write_phy_reg(&adapter->hw, reg_num, val); in mdio_write()
1265 struct atl1_hw *hw = &adapter->hw; in atl1_setup_mac_ctrl() local
1281 value |= (((u32) adapter->hw.preamble_len in atl1_setup_mac_ctrl()
1296 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); in atl1_setup_mac_ctrl()
1301 struct atl1_hw *hw = &adapter->hw; in atl1_check_link() local
1308 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); in atl1_check_link()
1309 atl1_read_phy_reg(hw, MII_BMSR, &phy_data); in atl1_check_link()
1323 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); in atl1_check_link()
1327 switch (hw->media_type) { in atl1_check_link()
1378 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && in atl1_check_link()
1379 hw->media_type != MEDIA_TYPE_1000M_FULL) { in atl1_check_link()
1380 switch (hw->media_type) { in atl1_check_link()
1397 atl1_write_phy_reg(hw, MII_BMCR, phy_data); in atl1_check_link()
1424 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); in set_flow_ctrl_old()
1434 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); in set_flow_ctrl_old()
1437 static void set_flow_ctrl_new(struct atl1_hw *hw) in set_flow_ctrl_new() argument
1442 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); in set_flow_ctrl_new()
1451 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); in set_flow_ctrl_new()
1454 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); in set_flow_ctrl_new()
1463 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); in set_flow_ctrl_new()
1474 struct atl1_hw *hw = &adapter->hw; in atl1_configure() local
1478 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); in atl1_configure()
1481 value = (((u32) hw->mac_addr[2]) << 24) | in atl1_configure()
1482 (((u32) hw->mac_addr[3]) << 16) | in atl1_configure()
1483 (((u32) hw->mac_addr[4]) << 8) | in atl1_configure()
1484 (((u32) hw->mac_addr[5])); in atl1_configure()
1485 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); in atl1_configure()
1486 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); in atl1_configure()
1487 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); in atl1_configure()
1493 hw->hw_addr + REG_DESC_BASE_ADDR_HI); in atl1_configure()
1496 hw->hw_addr + REG_DESC_RFD_ADDR_LO); in atl1_configure()
1498 hw->hw_addr + REG_DESC_RRD_ADDR_LO); in atl1_configure()
1500 hw->hw_addr + REG_DESC_TPD_ADDR_LO); in atl1_configure()
1502 hw->hw_addr + REG_DESC_CMB_ADDR_LO); in atl1_configure()
1504 hw->hw_addr + REG_DESC_SMB_ADDR_LO); in atl1_configure()
1510 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); in atl1_configure()
1511 iowrite32(adapter->tpd_ring.count, hw->hw_addr + in atl1_configure()
1515 iowrite32(1, hw->hw_addr + REG_LOAD_PTR); in atl1_configure()
1524 iowrite32(value, hw->hw_addr + REG_MAILBOX); in atl1_configure()
1527 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) in atl1_configure()
1529 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) in atl1_configure()
1531 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) in atl1_configure()
1533 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) in atl1_configure()
1535 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); in atl1_configure()
1538 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | in atl1_configure()
1539 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) in atl1_configure()
1543 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) in atl1_configure()
1545 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); in atl1_configure()
1548 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); in atl1_configure()
1549 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); in atl1_configure()
1552 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); in atl1_configure()
1555 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); in atl1_configure()
1558 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) in atl1_configure()
1560 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) in atl1_configure()
1562 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) in atl1_configure()
1564 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); in atl1_configure()
1567 switch (hw->dev_rev) { in atl1_configure()
1575 set_flow_ctrl_new(hw); in atl1_configure()
1580 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) in atl1_configure()
1582 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) in atl1_configure()
1584 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) in atl1_configure()
1587 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); in atl1_configure()
1590 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) in atl1_configure()
1592 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) in atl1_configure()
1594 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); in atl1_configure()
1597 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) in atl1_configure()
1599 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) in atl1_configure()
1601 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) in atl1_configure()
1604 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); in atl1_configure()
1607 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) in atl1_configure()
1609 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) in atl1_configure()
1612 value |= (u32) hw->dma_ord; in atl1_configure()
1613 if (atl1_rcb_128 == hw->rcb_value) in atl1_configure()
1615 iowrite32(value, hw->hw_addr + REG_DMA_CTRL); in atl1_configure()
1618 value = (hw->cmb_tpd > adapter->tpd_ring.count) ? in atl1_configure()
1619 hw->cmb_tpd : adapter->tpd_ring.count; in atl1_configure()
1621 value |= hw->cmb_rrd; in atl1_configure()
1622 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); in atl1_configure()
1623 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); in atl1_configure()
1624 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); in atl1_configure()
1625 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); in atl1_configure()
1629 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); in atl1_configure()
1631 value = ioread32(adapter->hw.hw_addr + REG_ISR); in atl1_configure()
1638 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); in atl1_configure()
1639 iowrite32(0, adapter->hw.hw_addr + REG_ISR); in atl1_configure()
1652 iowrite32(value, adapter->hw.hw_addr + 0x12FC); in atl1_pcie_patch()
1654 value = ioread32(adapter->hw.hw_addr + 0x1008); in atl1_pcie_patch()
1656 iowrite32(value, adapter->hw.hw_addr + 0x1008); in atl1_pcie_patch()
1669 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); in atl1_via_workaround()
1672 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); in atl1_via_workaround()
1774 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); in atl1_update_mailbox()
2065 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); in atl1_intr_rx()
2516 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); in atl1_intr()
2570 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); in atl1_intr()
2582 struct atl1_hw *hw = &adapter->hw; in atl1_phy_config() local
2587 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); in atl1_phy_config()
2588 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); in atl1_phy_config()
2589 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); in atl1_phy_config()
2607 ret = atl1_reset_hw(&adapter->hw); in atl1_reset()
2610 return atl1_init_hw(&adapter->hw); in atl1_reset()
2671 atl1_reset_hw(&adapter->hw); in atl1_down()
2714 adapter->hw.max_frame_size = max_frame; in atl1_change_mtu()
2715 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; in atl1_change_mtu()
2717 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; in atl1_change_mtu()
2788 struct atl1_hw *hw = &adapter->hw; in atl1_suspend() local
2799 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); in atl1_suspend()
2800 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); in atl1_suspend()
2808 val = atl1_get_speed_and_duplex(hw, &speed, &duplex); in atl1_suspend()
2821 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); in atl1_suspend()
2822 ioread32(hw->hw_addr + REG_WOL_CTRL); in atl1_suspend()
2830 ctrl |= (((u32)adapter->hw.preamble_len & in atl1_suspend()
2835 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); in atl1_suspend()
2836 ioread32(hw->hw_addr + REG_MAC_CTRL); in atl1_suspend()
2839 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); in atl1_suspend()
2841 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); in atl1_suspend()
2842 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); in atl1_suspend()
2845 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); in atl1_suspend()
2846 ioread32(hw->hw_addr + REG_WOL_CTRL); in atl1_suspend()
2847 iowrite32(0, hw->hw_addr + REG_MAC_CTRL); in atl1_suspend()
2848 ioread32(hw->hw_addr + REG_MAC_CTRL); in atl1_suspend()
2849 hw->phy_configured = false; in atl1_suspend()
2855 iowrite32(0, hw->hw_addr + REG_WOL_CTRL); in atl1_suspend()
2856 ioread32(hw->hw_addr + REG_WOL_CTRL); in atl1_suspend()
2857 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); in atl1_suspend()
2859 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); in atl1_suspend()
2860 ioread32(hw->hw_addr + REG_PCIE_PHYMISC); in atl1_suspend()
2861 hw->phy_configured = false; in atl1_suspend()
2872 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); in atl1_resume()
2874 atl1_reset_hw(&adapter->hw); in atl1_resume()
2988 adapter->hw.back = adapter; in atl1_probe()
2991 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); in atl1_probe()
2992 if (!adapter->hw.hw_addr) { in atl1_probe()
2997 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + in atl1_probe()
3042 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); in atl1_probe()
3048 if (atl1_reset_hw(&adapter->hw)) { in atl1_probe()
3054 if (atl1_read_mac_addr(&adapter->hw)) { in atl1_probe()
3058 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); in atl1_probe()
3068 err = atl1_init_hw(&adapter->hw); in atl1_probe()
3095 pci_iounmap(pdev, adapter->hw.hw_addr); in atl1_probe()
3130 if (!ether_addr_equal_unaligned(adapter->hw.mac_addr, in atl1_remove()
3131 adapter->hw.perm_mac_addr)) { in atl1_remove()
3132 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, in atl1_remove()
3134 atl1_set_mac_addr(&adapter->hw); in atl1_remove()
3137 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); in atl1_remove()
3139 pci_iounmap(pdev, adapter->hw.hw_addr); in atl1_remove()
3224 struct atl1_hw *hw = &adapter->hw; in atl1_get_settings() local
3233 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_get_settings()
3234 hw->media_type == MEDIA_TYPE_1000M_FULL) { in atl1_get_settings()
3236 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { in atl1_get_settings()
3253 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); in atl1_get_settings()
3263 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_get_settings()
3264 hw->media_type == MEDIA_TYPE_1000M_FULL) in atl1_get_settings()
3276 struct atl1_hw *hw = &adapter->hw; in atl1_set_settings() local
3279 u16 old_media_type = hw->media_type; in atl1_set_settings()
3289 hw->media_type = MEDIA_TYPE_AUTO_SENSOR; in atl1_set_settings()
3300 hw->media_type = MEDIA_TYPE_1000M_FULL; in atl1_set_settings()
3303 hw->media_type = MEDIA_TYPE_100M_FULL; in atl1_set_settings()
3305 hw->media_type = MEDIA_TYPE_100M_HALF; in atl1_set_settings()
3308 hw->media_type = MEDIA_TYPE_10M_FULL; in atl1_set_settings()
3310 hw->media_type = MEDIA_TYPE_10M_HALF; in atl1_set_settings()
3313 switch (hw->media_type) { in atl1_set_settings()
3332 if (atl1_phy_setup_autoneg_adv(hw)) { in atl1_set_settings()
3339 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_set_settings()
3340 hw->media_type == MEDIA_TYPE_1000M_FULL) in atl1_set_settings()
3343 switch (hw->media_type) { in atl1_set_settings()
3362 atl1_write_phy_reg(hw, MII_BMCR, phy_data); in atl1_set_settings()
3365 hw->media_type = old_media_type; in atl1_set_settings()
3442 struct atl1_hw *hw = &adapter->hw; in atl1_get_regs() local
3479 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); in atl1_get_regs()
3584 struct atl1_hw *hw = &adapter->hw; in atl1_get_pauseparam() local
3586 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_get_pauseparam()
3587 hw->media_type == MEDIA_TYPE_1000M_FULL) { in atl1_get_pauseparam()
3600 struct atl1_hw *hw = &adapter->hw; in atl1_set_pauseparam() local
3602 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_set_pauseparam()
3603 hw->media_type == MEDIA_TYPE_1000M_FULL) { in atl1_set_pauseparam()
3635 struct atl1_hw *hw = &adapter->hw; in atl1_nway_reset() local
3641 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || in atl1_nway_reset()
3642 hw->media_type == MEDIA_TYPE_1000M_FULL) { in atl1_nway_reset()
3645 switch (hw->media_type) { in atl1_nway_reset()
3662 atl1_write_phy_reg(hw, MII_BMCR, phy_data); in atl1_nway_reset()