43 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)  in ixgbe_set_pcie_completion_timeout()  argument
61 	u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);  in ixgbe_set_pcie_completion_timeout()
64 	if (ixgbe_removed(hw->hw_addr))  in ixgbe_set_pcie_completion_timeout()
85 	pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);  in ixgbe_set_pcie_completion_timeout()
87 	ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);  in ixgbe_set_pcie_completion_timeout()
91 	IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);  in ixgbe_set_pcie_completion_timeout()
94 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)  in ixgbe_get_invariants_82598()  argument
96 	struct ixgbe_mac_info *mac = &hw->mac;  in ixgbe_get_invariants_82598()
99 	ixgbe_identify_phy_generic(hw);  in ixgbe_get_invariants_82598()
107 	mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);  in ixgbe_get_invariants_82598()
121 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)  in ixgbe_init_phy_ops_82598()  argument
123 	struct ixgbe_mac_info *mac = &hw->mac;  in ixgbe_init_phy_ops_82598()
124 	struct ixgbe_phy_info *phy = &hw->phy;  in ixgbe_init_phy_ops_82598()
129 	phy->ops.identify(hw);  in ixgbe_init_phy_ops_82598()
132 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {  in ixgbe_init_phy_ops_82598()
138 	switch (hw->phy.type) {  in ixgbe_init_phy_ops_82598()
149 		ret_val = phy->ops.identify_sfp(hw);  in ixgbe_init_phy_ops_82598()
152 		if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)  in ixgbe_init_phy_ops_82598()
156 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,  in ixgbe_init_phy_ops_82598()
178 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)  in ixgbe_start_hw_82598()  argument
186 	ret_val = ixgbe_start_hw_generic(hw);  in ixgbe_start_hw_82598()
190 	for (i = 0; ((i < hw->mac.max_tx_queues) &&  in ixgbe_start_hw_82598()
192 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));  in ixgbe_start_hw_82598()
194 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);  in ixgbe_start_hw_82598()
197 	for (i = 0; ((i < hw->mac.max_rx_queues) &&  in ixgbe_start_hw_82598()
199 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));  in ixgbe_start_hw_82598()
202 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);  in ixgbe_start_hw_82598()
209 	ixgbe_set_pcie_completion_timeout(hw);  in ixgbe_start_hw_82598()
222 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,  in ixgbe_get_link_capabilities_82598()  argument
233 	if (hw->mac.orig_link_settings_stored)  in ixgbe_get_link_capabilities_82598()
234 		autoc = hw->mac.orig_autoc;  in ixgbe_get_link_capabilities_82598()
236 		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_get_link_capabilities_82598()
277 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)  in ixgbe_get_media_type_82598()  argument
280 	switch (hw->phy.type) {  in ixgbe_get_media_type_82598()
290 	switch (hw->device_id) {  in ixgbe_get_media_type_82598()
323 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)  in ixgbe_fc_enable_82598()  argument
334 	if (!hw->fc.pause_time)  in ixgbe_fc_enable_82598()
339 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&  in ixgbe_fc_enable_82598()
340 		    hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
341 			if (!hw->fc.low_water[i] ||  in ixgbe_fc_enable_82598()
342 			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
343 				hw_dbg(hw, "Invalid water mark configuration\n");  in ixgbe_fc_enable_82598()
354 	hw->mac.ops.check_link(hw, &link_speed, &link_up, false);  in ixgbe_fc_enable_82598()
356 		switch (hw->fc.requested_mode) {  in ixgbe_fc_enable_82598()
358 			hw->fc.requested_mode = ixgbe_fc_tx_pause;  in ixgbe_fc_enable_82598()
361 			hw->fc.requested_mode = ixgbe_fc_none;  in ixgbe_fc_enable_82598()
370 	ixgbe_fc_autoneg(hw);  in ixgbe_fc_enable_82598()
373 	fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);  in ixgbe_fc_enable_82598()
376 	rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);  in ixgbe_fc_enable_82598()
389 	switch (hw->fc.current_mode) {  in ixgbe_fc_enable_82598()
420 		hw_dbg(hw, "Flow control param set incorrectly\n");  in ixgbe_fc_enable_82598()
426 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);  in ixgbe_fc_enable_82598()
427 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);  in ixgbe_fc_enable_82598()
431 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&  in ixgbe_fc_enable_82598()
432 		    hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
433 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;  in ixgbe_fc_enable_82598()
434 			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_fc_enable_82598()
435 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);  in ixgbe_fc_enable_82598()
436 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);  in ixgbe_fc_enable_82598()
438 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);  in ixgbe_fc_enable_82598()
439 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);  in ixgbe_fc_enable_82598()
445 	reg = hw->fc.pause_time * 0x00010001;  in ixgbe_fc_enable_82598()
447 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);  in ixgbe_fc_enable_82598()
450 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);  in ixgbe_fc_enable_82598()
462 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,  in ixgbe_start_mac_link_82598()  argument
471 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_start_mac_link_82598()
473 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);  in ixgbe_start_mac_link_82598()
483 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);  in ixgbe_start_mac_link_82598()
490 				hw_dbg(hw, "Autonegotiation did not complete.\n");  in ixgbe_start_mac_link_82598()
508 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)  in ixgbe_validate_link_ready()  argument
513 	if (hw->device_id != IXGBE_DEV_ID_82598AT2)  in ixgbe_validate_link_ready()
518 		hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);  in ixgbe_validate_link_ready()
528 		hw_dbg(hw, "Link was indicated but link is down\n");  in ixgbe_validate_link_ready()
544 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,  in ixgbe_check_mac_link_82598()  argument
558 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_check_mac_link_82598()
559 		hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);  in ixgbe_check_mac_link_82598()
560 		hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);  in ixgbe_check_mac_link_82598()
561 		hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,  in ixgbe_check_mac_link_82598()
573 				hw->phy.ops.read_reg(hw, 0xC79F,  in ixgbe_check_mac_link_82598()
576 				hw->phy.ops.read_reg(hw, 0xC00C,  in ixgbe_check_mac_link_82598()
591 	links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);  in ixgbe_check_mac_link_82598()
601 			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);  in ixgbe_check_mac_link_82598()
615 	if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&  in ixgbe_check_mac_link_82598()
616 	    (ixgbe_validate_link_ready(hw) != 0))  in ixgbe_check_mac_link_82598()
630 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,  in ixgbe_setup_mac_link_82598()  argument
636 	u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_setup_mac_link_82598()
641 	ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);  in ixgbe_setup_mac_link_82598()
656 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);  in ixgbe_setup_mac_link_82598()
663 	return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);  in ixgbe_setup_mac_link_82598()
675 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,  in ixgbe_setup_copper_link_82598()  argument
682 	status = hw->phy.ops.setup_link_speed(hw, speed,  in ixgbe_setup_copper_link_82598()
685 	ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);  in ixgbe_setup_copper_link_82598()
698 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)  in ixgbe_reset_hw_82598()  argument
709 	status = hw->mac.ops.stop_adapter(hw);  in ixgbe_reset_hw_82598()
718 	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);  in ixgbe_reset_hw_82598()
721 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,  in ixgbe_reset_hw_82598()
724 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,  in ixgbe_reset_hw_82598()
727 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,  in ixgbe_reset_hw_82598()
730 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,  in ixgbe_reset_hw_82598()
733 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,  in ixgbe_reset_hw_82598()
736 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,  in ixgbe_reset_hw_82598()
739 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,  in ixgbe_reset_hw_82598()
742 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,  in ixgbe_reset_hw_82598()
747 	if (hw->phy.reset_disable == false) {  in ixgbe_reset_hw_82598()
751 		phy_status = hw->phy.ops.init(hw);  in ixgbe_reset_hw_82598()
757 		hw->phy.ops.reset(hw);  in ixgbe_reset_hw_82598()
765 	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;  in ixgbe_reset_hw_82598()
766 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);  in ixgbe_reset_hw_82598()
767 	IXGBE_WRITE_FLUSH(hw);  in ixgbe_reset_hw_82598()
772 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);  in ixgbe_reset_hw_82598()
778 		hw_dbg(hw, "Reset polling failed to complete.\n");  in ixgbe_reset_hw_82598()
788 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {  in ixgbe_reset_hw_82598()
789 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;  in ixgbe_reset_hw_82598()
793 	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);  in ixgbe_reset_hw_82598()
795 	IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);  in ixgbe_reset_hw_82598()
802 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_reset_hw_82598()
803 	if (hw->mac.orig_link_settings_stored == false) {  in ixgbe_reset_hw_82598()
804 		hw->mac.orig_autoc = autoc;  in ixgbe_reset_hw_82598()
805 		hw->mac.orig_link_settings_stored = true;  in ixgbe_reset_hw_82598()
806 	} else if (autoc != hw->mac.orig_autoc) {  in ixgbe_reset_hw_82598()
807 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);  in ixgbe_reset_hw_82598()
811 	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);  in ixgbe_reset_hw_82598()
817 	hw->mac.ops.init_rx_addrs(hw);  in ixgbe_reset_hw_82598()
831 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)  in ixgbe_set_vmdq_82598()  argument
834 	u32 rar_entries = hw->mac.num_rar_entries;  in ixgbe_set_vmdq_82598()
838 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);  in ixgbe_set_vmdq_82598()
842 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));  in ixgbe_set_vmdq_82598()
845 	IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);  in ixgbe_set_vmdq_82598()
855 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)  in ixgbe_clear_vmdq_82598()  argument
858 	u32 rar_entries = hw->mac.num_rar_entries;  in ixgbe_clear_vmdq_82598()
863 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);  in ixgbe_clear_vmdq_82598()
867 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));  in ixgbe_clear_vmdq_82598()
870 		IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);  in ixgbe_clear_vmdq_82598()
885 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,  in ixgbe_set_vfta_82598()  argument
904 	bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));  in ixgbe_set_vfta_82598()
907 	IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);  in ixgbe_set_vfta_82598()
912 	bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));  in ixgbe_set_vfta_82598()
919 	IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);  in ixgbe_set_vfta_82598()
930 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)  in ixgbe_clear_vfta_82598()  argument
935 	for (offset = 0; offset < hw->mac.vft_size; offset++)  in ixgbe_clear_vfta_82598()
936 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);  in ixgbe_clear_vfta_82598()
939 		for (offset = 0; offset < hw->mac.vft_size; offset++)  in ixgbe_clear_vfta_82598()
940 			IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),  in ixgbe_clear_vfta_82598()
954 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)  in ixgbe_read_analog_reg8_82598()  argument
958 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,  in ixgbe_read_analog_reg8_82598()
960 	IXGBE_WRITE_FLUSH(hw);  in ixgbe_read_analog_reg8_82598()
962 	atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);  in ixgbe_read_analog_reg8_82598()
976 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)  in ixgbe_write_analog_reg8_82598()  argument
981 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);  in ixgbe_write_analog_reg8_82598()
982 	IXGBE_WRITE_FLUSH(hw);  in ixgbe_write_analog_reg8_82598()
997 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,  in ixgbe_read_i2c_phy_82598()  argument
1007 	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)  in ixgbe_read_i2c_phy_82598()
1012 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)  in ixgbe_read_i2c_phy_82598()
1015 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_read_i2c_phy_82598()
1023 		hw->phy.ops.write_reg_mdi(hw,  in ixgbe_read_i2c_phy_82598()
1030 			hw->phy.ops.read_reg_mdi(hw,  in ixgbe_read_i2c_phy_82598()
1041 			hw_dbg(hw, "EEPROM read did not pass.\n");  in ixgbe_read_i2c_phy_82598()
1047 		hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,  in ixgbe_read_i2c_phy_82598()
1056 	hw->mac.ops.release_swfw_sync(hw, gssr);  in ixgbe_read_i2c_phy_82598()
1068 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,  in ixgbe_read_i2c_eeprom_82598()  argument
1071 	return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,  in ixgbe_read_i2c_eeprom_82598()
1083 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,  in ixgbe_read_i2c_sff8472_82598()  argument
1086 	return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,  in ixgbe_read_i2c_sff8472_82598()
1098 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)  in ixgbe_set_lan_id_multi_port_pcie_82598()  argument
1100 	struct ixgbe_bus_info *bus = &hw->bus;  in ixgbe_set_lan_id_multi_port_pcie_82598()
1104 	ixgbe_set_lan_id_multi_port_pcie(hw);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1107 	hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1110 		hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1129 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,  in ixgbe_set_rxpba_82598()  argument
1144 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);  in ixgbe_set_rxpba_82598()
1152 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);  in ixgbe_set_rxpba_82598()
1158 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);  in ixgbe_set_rxpba_82598()