Lines Matching refs:hw
282 struct inf_hw *hw = dev_id; in diva_irq() local
285 spin_lock(&hw->lock); in diva_irq()
286 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); in diva_irq()
288 spin_unlock(&hw->lock); in diva_irq()
291 hw->irqcnt++; in diva_irq()
292 mISDNipac_irq(&hw->ipac, irqloops); in diva_irq()
293 spin_unlock(&hw->lock); in diva_irq()
300 struct inf_hw *hw = dev_id; in diva20x_irq() local
303 spin_lock(&hw->lock); in diva20x_irq()
304 val = readb(hw->cfg.p); in diva20x_irq()
306 spin_unlock(&hw->lock); in diva20x_irq()
309 hw->irqcnt++; in diva20x_irq()
310 mISDNipac_irq(&hw->ipac, irqloops); in diva20x_irq()
311 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */ in diva20x_irq()
312 spin_unlock(&hw->lock); in diva20x_irq()
319 struct inf_hw *hw = dev_id; in tiger_irq() local
322 spin_lock(&hw->lock); in tiger_irq()
323 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); in tiger_irq()
325 spin_unlock(&hw->lock); in tiger_irq()
328 hw->irqcnt++; in tiger_irq()
329 mISDNipac_irq(&hw->ipac, irqloops); in tiger_irq()
330 spin_unlock(&hw->lock); in tiger_irq()
337 struct inf_hw *hw = dev_id; in elsa_irq() local
340 spin_lock(&hw->lock); in elsa_irq()
341 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); in elsa_irq()
343 spin_unlock(&hw->lock); in elsa_irq()
346 hw->irqcnt++; in elsa_irq()
347 mISDNipac_irq(&hw->ipac, irqloops); in elsa_irq()
348 spin_unlock(&hw->lock); in elsa_irq()
355 struct inf_hw *hw = dev_id; in niccy_irq() local
358 spin_lock(&hw->lock); in niccy_irq()
359 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
361 spin_unlock(&hw->lock); in niccy_irq()
364 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
365 hw->irqcnt++; in niccy_irq()
366 mISDNipac_irq(&hw->ipac, irqloops); in niccy_irq()
367 spin_unlock(&hw->lock); in niccy_irq()
374 struct inf_hw *hw = dev_id; in gazel_irq() local
377 spin_lock(&hw->lock); in gazel_irq()
378 ret = mISDNipac_irq(&hw->ipac, irqloops); in gazel_irq()
379 spin_unlock(&hw->lock); in gazel_irq()
386 struct inf_hw *hw = dev_id; in ipac_irq() local
389 spin_lock(&hw->lock); in ipac_irq()
390 val = hw->ipac.read_reg(hw, IPAC_ISTA); in ipac_irq()
392 spin_unlock(&hw->lock); in ipac_irq()
395 hw->irqcnt++; in ipac_irq()
396 mISDNipac_irq(&hw->ipac, irqloops); in ipac_irq()
397 spin_unlock(&hw->lock); in ipac_irq()
402 enable_hwirq(struct inf_hw *hw) in enable_hwirq() argument
407 switch (hw->ci->typ) { in enable_hwirq()
410 writel(PITA_INT0_ENABLE, hw->cfg.p); in enable_hwirq()
414 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in enable_hwirq()
417 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
420 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
423 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
425 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
428 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
430 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
434 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
438 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
446 disable_hwirq(struct inf_hw *hw) in disable_hwirq() argument
451 switch (hw->ci->typ) { in disable_hwirq()
454 writel(0, hw->cfg.p); in disable_hwirq()
458 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in disable_hwirq()
461 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
464 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
467 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
469 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
472 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
474 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
478 outb(0, (u32)hw->cfg.start + GAZEL_INCSR); in disable_hwirq()
486 ipac_chip_reset(struct inf_hw *hw) in ipac_chip_reset() argument
488 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20); in ipac_chip_reset()
490 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00); in ipac_chip_reset()
492 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf); in ipac_chip_reset()
493 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0); in ipac_chip_reset()
497 reset_inf(struct inf_hw *hw) in reset_inf() argument
503 pr_notice("%s: resetting card\n", hw->name); in reset_inf()
504 switch (hw->ci->typ) { in reset_inf()
507 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
509 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
512 outb(9, (u32)hw->cfg.start + 0x69); in reset_inf()
514 (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
518 hw->cfg.p + PITA_MISC_REG); in reset_inf()
520 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG); in reset_inf()
525 hw->cfg.p + PITA_MISC_REG); in reset_inf()
528 hw->cfg.p + PITA_MISC_REG); in reset_inf()
533 ipac_chip_reset(hw); in reset_inf()
534 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
535 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
536 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12); in reset_inf()
540 ipac_chip_reset(hw); in reset_inf()
541 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00); in reset_inf()
542 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c); in reset_inf()
543 hw->ipac.write_reg(hw, IPAC_ATX, 0xff); in reset_inf()
548 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
550 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
552 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
554 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
558 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
563 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
565 hw->ipac.isac.adf2 = 0x87; in reset_inf()
566 hw->ipac.hscx[0].slot = 0x1f; in reset_inf()
567 hw->ipac.hscx[1].slot = 0x23; in reset_inf()
570 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
572 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
575 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
577 ipac_chip_reset(hw); in reset_inf()
578 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
579 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
580 hw->ipac.conf = 0x01; /* IOM off */ in reset_inf()
585 enable_hwirq(hw); in reset_inf()
589 inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg) in inf_ctrl() argument
595 reset_inf(hw); in inf_ctrl()
599 hw->name, __func__, cmd, arg); in inf_ctrl()
607 init_irq(struct inf_hw *hw) in init_irq() argument
612 if (!hw->ci->irqfunc) in init_irq()
614 ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw); in init_irq()
616 pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq); in init_irq()
620 spin_lock_irqsave(&hw->lock, flags); in init_irq()
621 reset_inf(hw); in init_irq()
622 ret = hw->ipac.init(&hw->ipac); in init_irq()
624 spin_unlock_irqrestore(&hw->lock, flags); in init_irq()
626 hw->name, ret); in init_irq()
629 spin_unlock_irqrestore(&hw->lock, flags); in init_irq()
632 pr_notice("%s: IRQ %d count %d\n", hw->name, in init_irq()
633 hw->irq, hw->irqcnt); in init_irq()
634 if (!hw->irqcnt) { in init_irq()
636 hw->name, hw->irq, 3 - cnt); in init_irq()
640 free_irq(hw->irq, hw); in init_irq()
645 release_io(struct inf_hw *hw) in release_io() argument
647 if (hw->cfg.mode) { in release_io()
648 if (hw->cfg.p) { in release_io()
649 release_mem_region(hw->cfg.start, hw->cfg.size); in release_io()
650 iounmap(hw->cfg.p); in release_io()
652 release_region(hw->cfg.start, hw->cfg.size); in release_io()
653 hw->cfg.mode = AM_NONE; in release_io()
655 if (hw->addr.mode) { in release_io()
656 if (hw->addr.p) { in release_io()
657 release_mem_region(hw->addr.start, hw->addr.size); in release_io()
658 iounmap(hw->addr.p); in release_io()
660 release_region(hw->addr.start, hw->addr.size); in release_io()
661 hw->addr.mode = AM_NONE; in release_io()
666 setup_io(struct inf_hw *hw) in setup_io() argument
670 if (hw->ci->cfg_mode) { in setup_io()
671 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar); in setup_io()
672 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar); in setup_io()
673 if (hw->ci->cfg_mode == AM_MEMIO) { in setup_io()
674 if (!request_mem_region(hw->cfg.start, hw->cfg.size, in setup_io()
675 hw->name)) in setup_io()
678 if (!request_region(hw->cfg.start, hw->cfg.size, in setup_io()
679 hw->name)) in setup_io()
684 "already in use\n", hw->name, in setup_io()
685 (ulong)hw->cfg.start, (ulong)hw->cfg.size); in setup_io()
688 if (hw->ci->cfg_mode == AM_MEMIO) in setup_io()
689 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size); in setup_io()
690 hw->cfg.mode = hw->ci->cfg_mode; in setup_io()
693 hw->name, (ulong)hw->cfg.start, in setup_io()
694 (ulong)hw->cfg.size, hw->ci->cfg_mode); in setup_io()
697 if (hw->ci->addr_mode) { in setup_io()
698 hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar); in setup_io()
699 hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar); in setup_io()
700 if (hw->ci->addr_mode == AM_MEMIO) { in setup_io()
701 if (!request_mem_region(hw->addr.start, hw->addr.size, in setup_io()
702 hw->name)) in setup_io()
705 if (!request_region(hw->addr.start, hw->addr.size, in setup_io()
706 hw->name)) in setup_io()
711 "already in use\n", hw->name, in setup_io()
712 (ulong)hw->addr.start, (ulong)hw->addr.size); in setup_io()
715 if (hw->ci->addr_mode == AM_MEMIO) in setup_io()
716 hw->addr.p = ioremap(hw->addr.start, hw->addr.size); in setup_io()
717 hw->addr.mode = hw->ci->addr_mode; in setup_io()
720 hw->name, (ulong)hw->addr.start, in setup_io()
721 (ulong)hw->addr.size, hw->ci->addr_mode); in setup_io()
725 switch (hw->ci->typ) { in setup_io()
728 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
729 hw->isac.mode = hw->cfg.mode; in setup_io()
730 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE; in setup_io()
731 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT; in setup_io()
732 hw->hscx.mode = hw->cfg.mode; in setup_io()
733 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; in setup_io()
734 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; in setup_io()
737 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
738 hw->ipac.isac.off = 0x80; in setup_io()
739 hw->isac.mode = hw->addr.mode; in setup_io()
740 hw->isac.a.p = hw->addr.p; in setup_io()
741 hw->hscx.mode = hw->addr.mode; in setup_io()
742 hw->hscx.a.p = hw->addr.p; in setup_io()
745 hw->ipac.type = IPAC_TYPE_IPACX; in setup_io()
746 hw->isac.mode = hw->addr.mode; in setup_io()
747 hw->isac.a.p = hw->addr.p; in setup_io()
748 hw->hscx.mode = hw->addr.mode; in setup_io()
749 hw->hscx.a.p = hw->addr.p; in setup_io()
753 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
754 hw->ipac.isac.off = 0x80; in setup_io()
755 hw->isac.mode = hw->cfg.mode; in setup_io()
756 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
757 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
758 hw->hscx.mode = hw->cfg.mode; in setup_io()
759 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
760 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
761 outb(0xff, (ulong)hw->cfg.start); in setup_io()
763 outb(0x00, (ulong)hw->cfg.start); in setup_io()
765 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL); in setup_io()
769 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
770 hw->ipac.isac.off = 0x80; in setup_io()
771 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
772 hw->isac.a.io.port = (u32)hw->addr.start + 1; in setup_io()
773 hw->isac.mode = hw->addr.mode; in setup_io()
774 hw->hscx.a.io.ale = (u32)hw->addr.start; in setup_io()
775 hw->hscx.a.io.port = (u32)hw->addr.start + 1; in setup_io()
776 hw->hscx.mode = hw->addr.mode; in setup_io()
779 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
780 hw->isac.mode = hw->addr.mode; in setup_io()
781 hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE; in setup_io()
782 hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT; in setup_io()
783 hw->hscx.mode = hw->addr.mode; in setup_io()
784 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE; in setup_io()
785 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT; in setup_io()
788 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
789 hw->ipac.isac.off = 0x80; in setup_io()
790 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
791 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
792 hw->isac.mode = hw->addr.mode; in setup_io()
793 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
794 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
795 hw->hscx.mode = hw->addr.mode; in setup_io()
798 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
799 hw->ipac.isac.off = 0x80; in setup_io()
800 hw->isac.a.io.ale = (u32)hw->addr.start + 0x08; in setup_io()
801 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
802 hw->isac.mode = hw->addr.mode; in setup_io()
803 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
804 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
805 hw->hscx.mode = hw->addr.mode; in setup_io()
808 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
809 hw->ipac.isac.off = 0x80; in setup_io()
810 hw->isac.a.io.ale = (u32)hw->addr.start + 0x10; in setup_io()
811 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
812 hw->isac.mode = hw->addr.mode; in setup_io()
813 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
814 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
815 hw->hscx.mode = hw->addr.mode; in setup_io()
818 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
819 hw->ipac.isac.off = 0x80; in setup_io()
820 hw->isac.a.io.ale = (u32)hw->addr.start + 0x20; in setup_io()
821 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
822 hw->isac.mode = hw->addr.mode; in setup_io()
823 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
824 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
825 hw->hscx.mode = hw->addr.mode; in setup_io()
828 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
829 hw->ipac.isac.off = 0x80; in setup_io()
830 hw->isac.mode = hw->addr.mode; in setup_io()
831 hw->isac.a.io.port = (u32)hw->addr.start; in setup_io()
832 hw->hscx.mode = hw->addr.mode; in setup_io()
833 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
836 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
837 hw->ipac.isac.off = 0x80; in setup_io()
838 hw->isac.mode = hw->addr.mode; in setup_io()
839 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
840 hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT; in setup_io()
841 hw->hscx.mode = hw->addr.mode; in setup_io()
842 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
843 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
848 switch (hw->isac.mode) { in setup_io()
850 ASSIGN_FUNC_IPAC(MIO, hw->ipac); in setup_io()
853 ASSIGN_FUNC_IPAC(IND, hw->ipac); in setup_io()
856 ASSIGN_FUNC_IPAC(IO, hw->ipac); in setup_io()