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Searched refs:RREG32 (Results 1 – 109 of 109) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
143 status = RREG32(mmVCE_STATUS); in vce_v2_0_start()
308 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
312 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
316 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
322 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
327 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
[all …]
Duvd_v5_0.c51 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_ring_get_rptr()
65 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
366 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_start()
537 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
620 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v5_0_is_idle()
629 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) in uvd_v5_0_wait_for_idle()
653 RREG32(mmUVD_SEMA_ADDR_LOW)); in uvd_v5_0_print_status()
655 RREG32(mmUVD_SEMA_ADDR_HIGH)); in uvd_v5_0_print_status()
657 RREG32(mmUVD_SEMA_CMD)); in uvd_v5_0_print_status()
[all …]
Duvd_v4_2.c55 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v4_2_ring_get_rptr()
69 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v4_2_ring_get_wptr()
331 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
370 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v4_2_start()
493 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v4_2_ring_test_ring()
619 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
628 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
640 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
667 u32 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_init_cg()
677 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v4_2_is_idle()
[all …]
Duvd_v6_0.c51 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_ring_get_rptr()
65 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v6_0_ring_get_wptr()
365 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start()
420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_start()
537 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v6_0_ring_test_ring()
612 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v6_0_is_idle()
621 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) in uvd_v6_0_wait_for_idle()
645 RREG32(mmUVD_SEMA_ADDR_LOW)); in uvd_v6_0_print_status()
647 RREG32(mmUVD_SEMA_ADDR_HIGH)); in uvd_v6_0_print_status()
649 RREG32(mmUVD_SEMA_CMD)); in uvd_v6_0_print_status()
[all …]
Dgmc_v7_0.c92 tmp = RREG32(mmSRBM_STATUS) & 0x1F00; in gmc_v7_0_mc_wait_for_idle()
110 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
129 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
225 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
229 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_load_microcode()
253 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
259 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
341 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
345 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
364 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v7_0_mc_init()
[all …]
Dgmc_v8_0.c137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK | in gmc_v8_0_mc_wait_for_idle()
160 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
179 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
266 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_mc_load_microcode()
270 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_load_microcode()
294 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_mc_load_microcode()
300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_mc_load_microcode()
382 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v8_0_mc_program()
386 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v8_0_mc_program()
405 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v8_0_mc_init()
[all …]
Dvce_v3_0.c67 return RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
69 return RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
84 return RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
86 return RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
154 status = RREG32(mmVCE_STATUS); in vce_v3_0_start()
452 return !(RREG32(mmSRBM_STATUS2) & mask); in vce_v3_0_is_idle()
473 if (!(RREG32(mmSRBM_STATUS2) & mask)) in vce_v3_0_wait_for_idle()
508 RREG32(mmVCE_STATUS)); in vce_v3_0_print_status()
510 RREG32(mmVCE_VCPU_CNTL)); in vce_v3_0_print_status()
512 RREG32(mmVCE_VCPU_CACHE_OFFSET0)); in vce_v3_0_print_status()
[all …]
Dcik_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts()
116 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cik_ih_irq_init()
202 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
345 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
361 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; in cik_ih_wait_for_idle()
375 RREG32(mmSRBM_STATUS)); in cik_ih_print_status()
377 RREG32(mmSRBM_STATUS2)); in cik_ih_print_status()
[all …]
Dcz_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
116 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
204 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
323 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
339 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
353 RREG32(mmSRBM_STATUS)); in cz_ih_print_status()
[all …]
Diceland_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
116 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
204 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
323 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
339 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
353 RREG32(mmSRBM_STATUS)); in iceland_ih_print_status()
[all …]
Dvi.c86 (void)RREG32(mmPCIE_INDEX); in vi_pcie_rreg()
87 r = RREG32(mmPCIE_DATA); in vi_pcie_rreg()
98 (void)RREG32(mmPCIE_INDEX); in vi_pcie_wreg()
100 (void)RREG32(mmPCIE_DATA); in vi_pcie_wreg()
111 r = RREG32(mmSMC_IND_DATA_0); in vi_smc_rreg()
137 r = RREG32(mmMP0PUB_IND_DATA); in cz_smc_rreg()
159 r = RREG32(mmUVD_CTX_DATA); in vi_uvd_ctx_rreg()
181 r = RREG32(mmDIDT_IND_DATA); in vi_didt_rreg()
345 bus_cntl = RREG32(mmBUS_CNTL); in vi_read_disabled_bios()
347 d1vga_control = RREG32(mmD1VGA_CONTROL); in vi_read_disabled_bios()
[all …]
Dtonga_ih.c60 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts()
77 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts()
112 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in tonga_ih_irq_init()
151 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); in tonga_ih_irq_init()
215 tmp = RREG32(mmIH_RB_CNTL); in tonga_ih_get_wptr()
346 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_is_idle()
362 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_wait_for_idle()
376 RREG32(mmSRBM_STATUS)); in tonga_ih_print_status()
378 RREG32(mmSRBM_STATUS2)); in tonga_ih_print_status()
380 RREG32(mmINTERRUPT_CNTL)); in tonga_ih_print_status()
[all …]
Dgfx_v7_0.c1922 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_disabled()
1928 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_disabled()
2170 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); in gfx_v7_0_gpu_init()
2171 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_init()
2178 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_init()
2182 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_init()
2279 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_gpu_init()
2287 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_gpu_init()
2291 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_gpu_init()
2295 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_gpu_init()
[all …]
Damdgpu_i2c.c50 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in amdgpu_i2c_pre_xfer()
70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in amdgpu_i2c_pre_xfer()
72 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in amdgpu_i2c_pre_xfer()
76 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in amdgpu_i2c_post_xfer()
[all …]
Dcik.c79 (void)RREG32(mmPCIE_INDEX); in cik_pcie_rreg()
80 r = RREG32(mmPCIE_DATA); in cik_pcie_rreg()
91 (void)RREG32(mmPCIE_INDEX); in cik_pcie_wreg()
93 (void)RREG32(mmPCIE_DATA); in cik_pcie_wreg()
104 r = RREG32(mmSMC_IND_DATA_0); in cik_smc_rreg()
126 r = RREG32(mmUVD_CTX_DATA); in cik_uvd_ctx_rreg()
148 r = RREG32(mmDIDT_IND_DATA); in cik_didt_rreg()
879 tmp = RREG32(mmCONFIG_CNTL); in cik_vga_set_state()
896 bus_cntl = RREG32(mmBUS_CNTL); in cik_read_disabled_bios()
898 d1vga_control = RREG32(mmD1VGA_CONTROL); in cik_read_disabled_bios()
[all …]
Dcik_sdma.c173 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; in cik_sdma_ring_get_wptr()
340 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
380 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in cik_sdma_enable()
892 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
897 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
910 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
915 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
920 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
925 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
1039 u32 tmp = RREG32(mmSRBM_STATUS2); in cik_sdma_is_idle()
[all …]
Dgfx_v8_0.c647 tmp = RREG32(scratch); in gfx_v8_0_ring_test_ring()
703 tmp = RREG32(scratch); in gfx_v8_0_ring_test_ib()
1134 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); in gfx_v8_0_gpu_early_init()
1135 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1142 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v8_0_gpu_early_init()
1146 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v8_0_gpu_early_init()
2766 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v8_0_get_rb_disabled()
2769 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v8_0_get_rb_disabled()
2895 tmp = RREG32(mmGRBM_CNTL); in gfx_v8_0_gpu_init()
2975 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v8_0_wait_for_rlc_serdes()
[all …]
Dsdma_v2_4.c203 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; in sdma_v2_4_ring_get_wptr()
381 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
384 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
423 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
466 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
497 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
1055 u32 tmp = RREG32(mmSRBM_STATUS2); in sdma_v2_4_is_idle()
1071 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | in sdma_v2_4_wait_for_idle()
1088 RREG32(mmSRBM_STATUS2)); in sdma_v2_4_print_status()
1091 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); in sdma_v2_4_print_status()
[all …]
Dsdma_v3_0.c306 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; in sdma_v3_0_ring_get_wptr()
492 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
495 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
529 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
559 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
603 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
630 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
645 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
1215 u32 tmp = RREG32(mmSRBM_STATUS2); in sdma_v3_0_is_idle()
1231 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | in sdma_v3_0_wait_for_idle()
[all …]
Ddce_v10_0.c175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v10_0_audio_endpt_rreg()
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v10_0_is_in_vblank()
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_is_counter_moving()
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_is_counter_moving()
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v10_0_vblank_wait()
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
298 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
307 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
308 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
351 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & in dce_v10_0_hpd_sense()
[all …]
Ddce_v11_0.c165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v11_0_audio_endpt_rreg()
184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v11_0_is_in_vblank()
195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_is_counter_moving()
196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_is_counter_moving()
219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v11_0_vblank_wait()
245 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v11_0_vblank_get_counter()
288 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
297 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
298 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
341 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & in dce_v11_0_hpd_sense()
[all …]
Dkv_smc.c41 if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0) in amdgpu_kv_notify_message_to_smu()
45 tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK; in amdgpu_kv_notify_message_to_smu()
102 *value = RREG32(mmSMC_IND_DATA_0); in amdgpu_kv_read_smc_sram_dword()
143 original_data = RREG32(mmSMC_IND_DATA_0); in amdgpu_kv_copy_bytes_to_smc()
197 original_data = RREG32(mmSMC_IND_DATA_0); in amdgpu_kv_copy_bytes_to_smc()
Ddce_v8_0.c124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v8_0_audio_endpt_rreg()
143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v8_0_is_in_vblank()
154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_is_counter_moving()
155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_is_counter_moving()
178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v8_0_vblank_wait()
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v8_0_vblank_get_counter()
247 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v8_0_page_flip()
256 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
257 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
278 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) in dce_v8_0_hpd_sense()
[all …]
Damdgpu_amdkfd_gfx_v8.c195 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
320 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
325 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
326 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
343 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
363 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
391 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_destroy()
396 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_destroy()
419 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in get_atc_vmid_pasid_mapping_valid()
429 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in get_atc_vmid_pasid_mapping_pasid()
Dci_dpm.c186 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff); in ci_get_memory_module_index()
204 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING); in ci_copy_and_switch_arb_sets()
205 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2); in ci_copy_and_switch_arb_sets()
206 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >> in ci_copy_and_switch_arb_sets()
210 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1); in ci_copy_and_switch_arb_sets()
211 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1); in ci_copy_and_switch_arb_sets()
212 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >> in ci_copy_and_switch_arb_sets()
236 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F; in ci_copy_and_switch_arb_sets()
705 data = RREG32(config_regs->offset); in ci_program_pt_config_registers()
1791 *parameter = RREG32(mmSMC_MSG_ARG_0); in amdgpu_ci_send_msg_to_smc_return_parameter()
[all …]
Damdgpu_amdkfd_gfx_v7.c233 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
408 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
413 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
414 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
431 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
452 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
480 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_destroy()
485 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_destroy()
591 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in get_atc_vmid_pasid_mapping_valid()
601 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in get_atc_vmid_pasid_mapping_pasid()
Dci_smc.c91 original_data = RREG32(mmSMC_IND_DATA_0); in amdgpu_ci_copy_bytes_to_smc()
180 tmp = RREG32(mmSMC_RESP_0); in amdgpu_ci_send_msg_to_smc()
185 tmp = RREG32(mmSMC_RESP_0); in amdgpu_ci_send_msg_to_smc()
260 *value = RREG32(mmSMC_IND_DATA_0); in amdgpu_ci_read_smc_sram_dword()
Diceland_smc.c50 val = RREG32(mmSMC_IND_ACCESS_CNTL); in iceland_set_smc_sram_address()
101 orig_data = RREG32(mmSMC_IND_DATA_0); in iceland_copy_bytes_to_smc()
178 val = RREG32(mmSMC_RESP_0); in wait_smu_response()
316 val = RREG32(mmSMC_IND_ACCESS_CNTL); in iceland_smu_upload_firmware_image()
327 val = RREG32(mmSMC_IND_ACCESS_CNTL); in iceland_smu_upload_firmware_image()
347 *value = RREG32(mmSMC_IND_DATA_0);
Dcz_smc.c40 return RREG32(mmSMU_MP1_SRBM2P_ARG_0); in cz_get_argument()
57 tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0), in cz_send_msg_to_smc_async()
83 tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0), in cz_send_msg_to_smc()
138 *value = RREG32(mmMP0PUB_IND_DATA_0); in cz_read_smc_sram_dword()
206 if (fw_mask == (RREG32(mmMP0PUB_IND_DATA) & fw_mask)) in cz_smu_check_fw_load_finish()
214 fw_mask, RREG32(mmMP0PUB_IND_DATA)); in cz_smu_check_fw_load_finish()
279 tmp = RREG32(mmCP_MEC_CNTL); in cz_load_mec_firmware()
284 tmp = RREG32(mmCP_CPC_IC_BASE_CNTL); in cz_load_mec_firmware()
Dfiji_smc.c49 val = RREG32(mmSMC_IND_ACCESS_CNTL); in fiji_set_smc_sram_address()
97 orig_data = RREG32(mmSMC_IND_DATA_0); in fiji_copy_bytes_to_smc()
142 val = RREG32(mmSMC_RESP_0); in wait_smu_response()
297 val = RREG32(mmSMC_IND_ACCESS_CNTL); in fiji_smu_upload_firmware_image()
306 val = RREG32(mmSMC_IND_ACCESS_CNTL); in fiji_smu_upload_firmware_image()
326 *value = RREG32(mmSMC_IND_DATA_0);
Dtonga_smc.c49 val = RREG32(mmSMC_IND_ACCESS_CNTL); in tonga_set_smc_sram_address()
97 orig_data = RREG32(mmSMC_IND_DATA_0); in tonga_copy_bytes_to_smc()
142 val = RREG32(mmSMC_RESP_0); in wait_smu_response()
297 val = RREG32(mmSMC_IND_ACCESS_CNTL); in tonga_smu_upload_firmware_image()
306 val = RREG32(mmSMC_IND_ACCESS_CNTL); in tonga_smu_upload_firmware_image()
326 *value = RREG32(mmSMC_IND_DATA_0);
Datombios_encoders.c43 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); in amdgpu_atombios_encoder_get_backlight_level_from_reg()
57 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); in amdgpu_atombios_encoder_set_backlight_level_to_reg()
1675 bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); in amdgpu_atombios_encoder_dac_detect()
1720 bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); in amdgpu_atombios_encoder_dig_detect()
1768 bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); in amdgpu_atombios_encoder_set_bios_scratch_regs()
1769 bios_3_scratch = RREG32(mmBIOS_SCRATCH_3); in amdgpu_atombios_encoder_set_bios_scratch_regs()
1770 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); in amdgpu_atombios_encoder_set_bios_scratch_regs()
Damdgpu_device.c318 tmp = RREG32(reg); in amdgpu_program_register_sequence()
628 reg = RREG32(mmCONFIG_MEMSIZE); in amdgpu_card_posted()
803 r = RREG32(reg); in cail_reg_read()
1962 value = RREG32(*pos >> 2); in amdgpu_debugfs_regs_read()
Dkv_dpm.c127 u32 v = RREG32(mmDOUT_SCRATCH3); in sumo_take_smu_control()
437 data = RREG32(config_regs->offset); in kv_program_pt_config_registers()
3194 RREG32(mmSMC_MESSAGE_0)); in kv_dpm_print_status()
3196 RREG32(mmSMC_RESP_0)); in kv_dpm_print_status()
3198 RREG32(mmSMC_MSG_ARG_0)); in kv_dpm_print_status()
3200 RREG32(mmSMC_IND_INDEX_0)); in kv_dpm_print_status()
3202 RREG32(mmSMC_IND_DATA_0)); in kv_dpm_print_status()
3204 RREG32(mmSMC_IND_ACCESS_CNTL)); in kv_dpm_print_status()
Damdgpu_atombios.c1521 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); in amdgpu_atombios_scratch_regs_lock()
1538 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); in amdgpu_atombios_scratch_regs_init()
1539 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); in amdgpu_atombios_scratch_regs_init()
1559 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i); in amdgpu_atombios_scratch_regs_save()
Damdgpu_cgs.c289 return RREG32(offset); in amdgpu_cgs_read_register()
Damdgpu.h2141 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) macro
2160 uint32_t tmp_ = RREG32(reg); \
Damdgpu_ttm.c1139 value = RREG32(mmMM_DATA); in amdgpu_ttm_vram_read()
/linux-4.4.14/drivers/gpu/drm/radeon/
Dradeon_bios.c256 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
257 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in ni_read_disabled_bios()
258 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in ni_read_disabled_bios()
259 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in ni_read_disabled_bios()
260 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
302 viph_control = RREG32(RADEON_VIPH_CONTROL); in r700_read_disabled_bios()
303 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
304 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in r700_read_disabled_bios()
305 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in r700_read_disabled_bios()
306 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in r700_read_disabled_bios()
[all …]
Dradeon_legacy_encoders.c57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
279 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
353 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_backlight_get_brightness()
[all …]
Dvce_v2_0.c43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
57 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
62 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
77 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
130 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
[all …]
Dradeon_i2c.c129 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
135 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
138 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
142 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
145 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
149 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
151 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
153 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
155 temp = RREG32(rec->mask_data_reg); in pre_xfer()
168 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in post_xfer()
[all …]
Dvce_v1_0.c63 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
65 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
80 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
82 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
107 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
111 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
120 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
124 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
[all …]
Drs600.c58 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
68 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
69 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
116 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
131 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
147 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
225 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
234 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
320 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
[all …]
Drv730_dpm.c203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
205 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
207 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
209 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
211 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
214 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
216 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
218 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
220 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
222 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
Dr600.c121 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
143 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
177 *val = RREG32(reg); in r600_get_allowed_info_register()
346 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
791 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
805 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
809 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
813 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
817 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
822 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
[all …]
Devergreen.c48 r = RREG32(EVERGREEN_CG_IND_DATA); in eg_cg_rreg()
70 r = RREG32(EVERGREEN_PIF_PHY0_DATA); in eg_pif_phy0_rreg()
92 r = RREG32(EVERGREEN_PIF_PHY1_DATA); in eg_pif_phy1_rreg()
1099 *val = RREG32(reg); in evergreen_get_allowed_info_register()
1151 if (RREG32(status_reg) & DCLK_STATUS) in sumo_set_uvd_clock()
1164 u32 cg_scratch = RREG32(CG_SCRATCH1); in sumo_set_uvd_clocks()
1345 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1355 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1356 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1379 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
[all …]
Drs400.c153 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
157 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
244 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
259 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
273 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
287 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
312 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info()
314 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info()
327 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info()
330 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info()
[all …]
Dr100.c74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
[all …]
Dsi.c1290 *val = RREG32(reg); in si_get_allowed_info_register()
1313 tmp = RREG32(CG_CLKPIN_CNTL_2); in si_get_xclk()
1317 tmp = RREG32(CG_CLKPIN_CNTL); in si_get_xclk()
1330 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> in si_get_temp()
1593 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in si_mc_load_microcode()
1597 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in si_mc_load_microcode()
1630 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in si_mc_load_microcode()
1635 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in si_mc_load_microcode()
1950 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
1972 u32 tmp = RREG32(MC_SHARED_CHMAP); in si_get_number_of_dram_channels()
[all …]
Dcik.c170 *val = RREG32(reg); in cik_get_allowed_info_register()
187 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
249 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
250 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
261 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
263 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1910 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1914 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in ci_mc_load_microcode()
1933 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1956 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
[all …]
Dr420.c99 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); in r420_pipes_init()
135 tmp = RREG32(R300_DST_PIPE_CONFIG); in r420_pipes_init()
139 RREG32(R300_RB2D_DSTCACHE_MODE) | in r420_pipes_init()
149 tmp = RREG32(RV530_GB_PIPE_SELECT2); in r420_pipes_init()
168 r = RREG32(R_0001FC_MC_IND_DATA); in r420_mc_rreg()
282 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
314 RREG32(R_000E40_RBBM_STATUS), in r420_resume()
315 RREG32(R_0007C0_CP_STAT)); in r420_resume()
405 RREG32(R_000E40_RBBM_STATUS), in r420_init()
406 RREG32(R_0007C0_CP_STAT)); in r420_init()
[all …]
Dni.c49 r = RREG32(TN_SMC_IND_DATA_0); in tn_smc_rreg()
668 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; in ni_mc_load_microcode()
669 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ni_mc_load_microcode()
673 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in ni_mc_load_microcode()
698 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) in ni_mc_load_microcode()
878 *val = RREG32(reg); in cayman_get_allowed_info_register()
1024 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in cayman_gpu_init()
1025 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in cayman_gpu_init()
1102 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in cayman_gpu_init()
1122 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in cayman_gpu_init()
[all …]
Dsi_smc.c86 original_data = RREG32(SMC_IND_DATA_0); in si_copy_bytes_to_smc()
126 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
127 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
128 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
129 RREG32(CB_CGTT_SCLK_CTRL); in si_reset_smc()
183 tmp = RREG32(SMC_RESP_0); in si_send_msg_to_smc()
188 tmp = RREG32(SMC_RESP_0); in si_send_msg_to_smc()
291 *value = RREG32(SMC_IND_DATA_0); in si_read_smc_sram_dword()
Drv740_dpm.c290 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
292 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
294 RREG32(CG_SPLL_FUNC_CNTL_3); in rv740_read_clock_registers()
296 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv740_read_clock_registers()
298 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv740_read_clock_registers()
301 RREG32(MPLL_AD_FUNC_CNTL); in rv740_read_clock_registers()
303 RREG32(MPLL_AD_FUNC_CNTL_2); in rv740_read_clock_registers()
305 RREG32(MPLL_DQ_FUNC_CNTL); in rv740_read_clock_registers()
307 RREG32(MPLL_DQ_FUNC_CNTL_2); in rv740_read_clock_registers()
309 RREG32(MCLK_PWRMGT_CNTL); in rv740_read_clock_registers()
[all …]
Dr520.c82 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); in r520_gpu_init()
83 tmp = RREG32(R300_DST_PIPE_CONFIG); in r520_gpu_init()
204 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r520_startup()
233 RREG32(R_000E40_RBBM_STATUS), in r520_resume()
234 RREG32(R_0007C0_CP_STAT)); in r520_resume()
279 RREG32(R_000E40_RBBM_STATUS), in r520_init()
280 RREG32(R_0007C0_CP_STAT)); in r520_init()
Dkv_smc.c38 if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0) in kv_notify_message_to_smu()
42 tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK; in kv_notify_message_to_smu()
98 *value = RREG32(SMC_IND_DATA_0); in kv_read_smc_sram_dword()
139 original_data = RREG32(SMC_IND_DATA_0); in kv_copy_bytes_to_smc()
193 original_data= RREG32(SMC_IND_DATA_0); in kv_copy_bytes_to_smc()
Drv515.c149 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); in rv515_vga_render_disable()
162 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); in rv515_gpu_init()
163 tmp = RREG32(R300_DST_PIPE_CONFIG); in rv515_gpu_init()
217 r = RREG32(MC_IND_DATA); in rv515_mc_rreg()
243 tmp = RREG32(GB_PIPE_SELECT); in rv515_debugfs_pipes_info()
245 tmp = RREG32(SU_REG_DEST); in rv515_debugfs_pipes_info()
247 tmp = RREG32(GB_TILE_CONFIG); in rv515_debugfs_pipes_info()
249 tmp = RREG32(DST_PIPE_CONFIG); in rv515_debugfs_pipes_info()
261 tmp = RREG32(0x2140); in rv515_debugfs_ga_info()
264 tmp = RREG32(0x425C); in rv515_debugfs_ga_info()
[all …]
Dradeon_dp_auxch.c99 tmp = RREG32(chan->rec.mask_clk_reg); in radeon_dp_aux_transfer_native()
104 tmp = RREG32(AUX_CONTROL + aux_offset[instance]); in radeon_dp_aux_transfer_native()
153 tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); in radeon_dp_aux_transfer_native()
182 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); in radeon_dp_aux_transfer_native()
186 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); in radeon_dp_aux_transfer_native()
Dtrinity_smc.c37 if (RREG32(SMC_RESP_0) != 0) in trinity_notify_message_to_smu()
41 v = RREG32(SMC_RESP_0); in trinity_notify_message_to_smu()
118 if ((RREG32(SMC_INT_REQ) & 0xffff) == 1) in trinity_acquire_mutex()
Drv770.c793 u32 tmp = RREG32(CG_CLKPIN_CNTL); in rv770_get_xclk()
807 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
829 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
845 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
852 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> in rv770_get_temp()
1019 tmp = RREG32(HDP_DEBUG1); in rv770_mc_program()
1103 RREG32(GRBM_SOFT_RESET); in rv770_cp_load_microcode()
1139 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_set_clk_bypass_mode()
1145 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS) in rv770_set_clk_bypass_mode()
1153 tmp = RREG32(MPLL_CNTL_MODE); in rv770_set_clk_bypass_mode()
[all …]
Dsumo_smc.c42 if (RREG32(GFX_INT_STATUS) & INT_DONE) in sumo_send_msg_to_smu()
51 if (RREG32(GFX_INT_REQ) & INT_REQ) in sumo_send_msg_to_smu()
57 if (RREG32(GFX_INT_STATUS) & INT_ACK) in sumo_send_msg_to_smu()
63 if (RREG32(GFX_INT_STATUS) & INT_DONE) in sumo_send_msg_to_smu()
Drv770_smc.c335 original_data = RREG32(SMC_SRAM_DATA); in rv770_copy_bytes_to_smc()
416 tmp = RREG32(SMC_IO); in rv770_is_smc_running()
436 tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK; in rv770_send_msg_to_smc()
443 tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK; in rv770_send_msg_to_smc()
459 if (RREG32(SMC_IO) & SMC_STOP_MODE) in rv770_wait_for_smc_inactive()
612 *value = RREG32(SMC_SRAM_DATA); in rv770_read_smc_sram_dword()
Dni_dpm.c1086 tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK; in ni_stop_smc()
1183 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in ni_read_clock_registers()
1184 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in ni_read_clock_registers()
1185 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in ni_read_clock_registers()
1186 ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); in ni_read_clock_registers()
1187 ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); in ni_read_clock_registers()
1188 ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in ni_read_clock_registers()
1189 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ni_read_clock_registers()
1190 ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2); in ni_read_clock_registers()
1191 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ni_read_clock_registers()
[all …]
Dbtc_dpm.c1344 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; in btc_enable_bif_dynamic_pcie_gen2()
1363 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; in btc_enable_bif_dynamic_pcie_gen2()
1447 tmp = RREG32(sequence[i]); in btc_program_mgcg_hw_sequence()
1744 if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1) in btc_stop_smc()
1759 arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); in btc_read_arb_registers()
1760 arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); in btc_read_arb_registers()
1761 arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE); in btc_read_arb_registers()
1762 arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME); in btc_read_arb_registers()
1926 tmp = RREG32(MC_PMG_CMD_EMRS); in btc_set_mc_special_registers()
1939 tmp = RREG32(MC_PMG_CMD_MRS); in btc_set_mc_special_registers()
[all …]
Dr300.c62 r = RREG32(RADEON_PCIE_DATA); in rv370_pcie_rreg()
337 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { in r300_errata()
349 tmp = RREG32(RADEON_MC_STATUS); in r300_mc_wait_for_idle()
394 tmp = RREG32(R300_DST_PIPE_CONFIG); in r300_gpu_init()
419 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
424 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
428 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
439 RREG32(R_0000F0_RBBM_SOFT_RESET); in r300_asic_reset()
443 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
451 RREG32(R_0000F0_RBBM_SOFT_RESET); in r300_asic_reset()
[all …]
Dradeon_display.c178 dac2_cntl = RREG32(RADEON_DAC_CNTL2); in legacy_crtc_load_lut()
1872 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1874 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + in radeon_get_crtc_scanoutpos()
1879 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1881 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + in radeon_get_crtc_scanoutpos()
1886 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1888 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + in radeon_get_crtc_scanoutpos()
1893 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1895 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + in radeon_get_crtc_scanoutpos()
1900 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
[all …]
Dci_smc.c88 original_data = RREG32(SMC_IND_DATA_0); in ci_copy_bytes_to_smc()
177 tmp = RREG32(SMC_RESP_0); in ci_send_msg_to_smc()
182 tmp = RREG32(SMC_RESP_0); in ci_send_msg_to_smc()
276 *value = RREG32(SMC_IND_DATA_0); in ci_read_smc_sram_dword()
Duvd_v1_0.c42 return RREG32(UVD_RBC_RB_RPTR); in uvd_v1_0_get_rptr()
56 return RREG32(UVD_RBC_RB_WPTR); in uvd_v1_0_get_wptr()
331 status = RREG32(UVD_STATUS); in uvd_v1_0_start()
369 ring->wptr = RREG32(UVD_RBC_RB_RPTR); in uvd_v1_0_start()
437 tmp = RREG32(UVD_CONTEXT_ID); in uvd_v1_0_ring_test()
Devergreen_hdmi.c41 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); in dce4_audio_enable()
249 value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; in dce4_hdmi_audio_set_dto()
275 value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; in dce4_dp_audio_set_dto()
293 unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & in dce4_dp_audio_set_dto()
324 val = RREG32(HDMI_CONTROL + offset); in dce4_hdmi_set_color_depth()
466 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); in evergreen_dp_enable()
Drv770_dpm.c139 RREG32(GB_TILING_CONFIG); in rv770_gfx_clock_gating_enable()
171 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) in rv770_restore_cgcg()
173 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) in rv770_restore_cgcg()
207 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) in rv770_dpm_enabled()
730 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; in rv770_calculate_memory_refresh_rate()
732 tmp = RREG32(MC_SEQ_MISC0) & 3; in rv770_calculate_memory_refresh_rate()
880 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in rv770_enable_display_gap()
1306 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); in rv770_get_memory_module_index()
1344 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in rv770_program_display_gap()
1522 RREG32(CG_SPLL_FUNC_CNTL); in rv770_read_clock_registers()
[all …]
Dsi_dpm.c2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; in si_calculate_cac_wintime()
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; in si_initialize_smc_cac_tables()
2752 data = RREG32(config_regs->offset << 2); in si_program_cac_config_registers()
3223 tmp = RREG32(MC_SEQ_MISC0); in si_is_special_1gb_platform()
3229 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; in si_is_special_1gb_platform()
3231 tmp = RREG32(MC_ARB_RAMCFG); in si_is_special_1gb_platform()
3584 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
3585 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
3586 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in si_read_clock_registers()
3587 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); in si_read_clock_registers()
[all …]
Dsumo_dpm.c97 RREG32(GB_ADDR_CONFIG); in sumo_gfx_clockgating_enable()
109 local0 = RREG32(CG_CGTT_LOCAL_0); in sumo_mg_clockgating_enable()
110 local1 = RREG32(CG_CGTT_LOCAL_1); in sumo_mg_clockgating_enable()
281 RREG32(GB_ADDR_CONFIG); in sumo_gfx_powergating_enable()
500 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); in sumo_set_ds_dividers()
514 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); in sumo_set_ss_dividers()
524 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL); in sumo_set_vid()
540 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); in sumo_set_allos_gnb_slow()
553 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS; in sumo_program_power_level()
602 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) in sumo_dpm_enabled()
[all …]
Dni_dma.c66 rptr = RREG32(reg); in cayman_dma_get_rptr()
90 return (RREG32(reg) & 0x3fffc) >> 2; in cayman_dma_get_wptr()
166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
239 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
Dradeon_device.c192 tmp = RREG32(reg); in radeon_program_register_sequence()
657 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | in radeon_card_posted()
658 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_card_posted()
660 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | in radeon_card_posted()
661 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_card_posted()
664 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | in radeon_card_posted()
665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_card_posted()
670 reg = RREG32(AVIVO_D1CRTC_CONTROL) | in radeon_card_posted()
671 RREG32(AVIVO_D2CRTC_CONTROL); in radeon_card_posted()
676 reg = RREG32(RADEON_CRTC_GEN_CNTL) | in radeon_card_posted()
[all …]
Dr600_hdmi.c64 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); in r600_audio_status()
100 value = RREG32(R600_AUDIO_STATUS_BITS); in r600_audio_status()
145 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); in r600_audio_enable()
270 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; in r600_hdmi_is_audio_buffer_filled()
448 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); in r600_hdmi_update_audio_settings()
Dradeon_legacy_tv.c282 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); in radeon_wait_pll_lock()
294 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); in radeon_wait_pll_lock()
312 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); in radeon_legacy_tv_write_fifo()
332 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
338 return RREG32(RADEON_TV_HOST_READ_DATA);
620 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); in radeon_legacy_tv_mode_set()
662 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; in radeon_legacy_tv_mode_set()
761 tmp = RREG32(RADEON_TV_DAC_CNTL); in radeon_legacy_tv_mode_set()
Dcik_sdma.c76 rptr = RREG32(reg); in cik_sdma_get_rptr()
100 return (RREG32(reg) & 0x3fffc) >> 2; in cik_sdma_get_wptr()
122 (void)RREG32(reg); in cik_sdma_set_wptr()
264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
278 (void)RREG32(SRBM_SOFT_RESET); in cik_sdma_gfx_stop()
281 (void)RREG32(SRBM_SOFT_RESET); in cik_sdma_gfx_stop()
314 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
346 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); in cik_sdma_enable()
Dr600_dma.c59 rptr = RREG32(DMA_RB_RPTR); in r600_dma_get_rptr()
75 return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2; in r600_dma_get_wptr()
101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop()
160 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume()
Dradeon_legacy_crtc.c64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & in radeon_legacy_rmx_mode_set()
67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & in radeon_legacy_rmx_mode_set()
538 gen_cntl_val = RREG32(gen_cntl_reg); in radeon_crtc_do_set_base()
655 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; in radeon_set_crtc_timing()
675 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); in radeon_set_crtc_timing()
688 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; in radeon_set_crtc_timing()
706 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); in radeon_set_crtc_timing()
712 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); in radeon_set_crtc_timing()
Dradeon_combios.c1107 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()
1114 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); in radeon_legacy_get_lvds_info_from_regs()
1115 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); in radeon_legacy_get_lvds_info_from_regs()
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()
1131 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; in radeon_legacy_get_lvds_info_from_regs()
1139 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; in radeon_legacy_get_lvds_info_from_regs()
2917 val = RREG32(reg); in radeon_combios_external_tmds_setup()
2971 val = RREG32(reg); in radeon_combios_external_tmds_setup()
3038 tmp = RREG32(addr); in combios_parse_mmio_table()
3048 tmp = RREG32(addr); in combios_parse_mmio_table()
[all …]
Dcypress_dpm.c60 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; in cypress_enable_bif_dynamic_pcie_gen2()
107 RREG32(GB_ADDR_CONFIG);
148 RREG32(GB_ADDR_CONFIG); in cypress_gfx_clock_gating_enable()
506 mc_seq_misc7 = RREG32(MC_SEQ_MISC7); in cypress_populate_mclk_value()
717 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) in cypress_convert_power_level_to_smc()
718 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in cypress_convert_power_level_to_smc()
720 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; in cypress_convert_power_level_to_smc()
928 u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME); in cypress_program_memory_timing_parameters()
1038 RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_retrieve_ac_timing_for_one_entry()
1109 if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value) in cypress_wait_for_mc_sequencer()
[all …]
Dci_dpm.c587 data = RREG32(config_regs->offset << 2); in ci_program_pt_config_registers()
1663 *parameter = RREG32(SMC_MSG_ARG_0); in ci_send_msg_to_smc_return_parameter()
1856 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1857 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1858 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1859 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1860 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1861 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1862 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1863 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
[all …]
Dradeon_cursor.c37 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
44 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
51 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); in radeon_lock_cursor()
Dradeon_clocks.c478 if ((RREG32(RADEON_CONFIG_CNTL) & in radeon_legacy_set_clock_gating()
617 if (RREG32(RADEON_MEM_CNTL) & in radeon_legacy_set_clock_gating()
670 ((RREG32(RADEON_CONFIG_CNTL) & in radeon_legacy_set_clock_gating()
675 ((RREG32(RADEON_CONFIG_CNTL) & in radeon_legacy_set_clock_gating()
693 ((RREG32(RADEON_CONFIG_CNTL) & in radeon_legacy_set_clock_gating()
705 ((RREG32(RADEON_CONFIG_CNTL) & in radeon_legacy_set_clock_gating()
Drs690.c158 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs690_mc_init()
227 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; in rs690_line_buffer_adjust()
657 r = RREG32(R_00007C_MC_DATA); in rs690_mc_rreg()
729 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs690_startup()
763 RREG32(R_000E40_RBBM_STATUS), in rs690_resume()
764 RREG32(R_0007C0_CP_STAT)); in rs690_resume()
839 RREG32(R_000E40_RBBM_STATUS), in rs690_init()
840 RREG32(R_0007C0_CP_STAT)); in rs690_init()
Ddce3_1_afmt.c154 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; in dce3_2_audio_set_dto()
161 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; in dce3_2_audio_set_dto()
Dradeon_agp.c165 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; in radeon_agp_init()
253 WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); in radeon_agp_init()
Dradeon_dp_mst.c35 reg = RREG32(NI_DIG_BE_CNTL + primary->offset); in radeon_dp_mst_set_be_cntl()
54 temp = RREG32(NI_DIG_FE_CNTL + offset); in radeon_dp_mst_set_be_cntl()
76 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); in radeon_dp_mst_set_stream_attrib()
92 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); in radeon_dp_mst_set_stream_attrib()
167 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); in radeon_dp_mst_set_vcp_size()
Dr600_dpm.c251 if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1) in r600_gfx_clockgating_enable()
259 RREG32(GRBM_PWR_CNTL); in r600_gfx_clockgating_enable()
294 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) in r600_dynamicpm_enabled()
329 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
535 tmp = RREG32(VID_UPPER_GPIO_CNTL); in r600_voltage_control_program_voltages()
545 gpio = RREG32(GPIOPAD_MASK); in r600_voltage_control_deactivate_static_control()
549 gpio = RREG32(GPIOPAD_EN); in r600_voltage_control_deactivate_static_control()
553 gpio = RREG32(GPIOPAD_A); in r600_voltage_control_deactivate_static_control()
625 tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK; in r600_power_level_get_current_index()
634 tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK; in r600_power_level_get_target_index()
Ddce6_afmt.c40 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); in dce6_endpoint_rreg()
304 unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & in dce6_dp_audio_set_dto()
Dtrinity_dpm.c370 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; in trinity_gfx_powergating_initialize()
450 RREG32(GB_ADDR_CONFIG); in trinity_gfx_clockgating_enable()
511 RREG32(GB_ADDR_CONFIG); in trinity_gfx_powergating_enable()
772 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN) in trinity_wait_for_dpm_enabled()
777 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0) in trinity_wait_for_dpm_enabled()
782 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0) in trinity_wait_for_dpm_enabled()
817 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0) in trinity_wait_for_level_0()
938 u32 tmp = RREG32(CG_MISC_REG); in trinity_setup_uvd_clocks()
2035 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >> in trinity_dpm_debugfs_print_current_performance_level()
2056 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >> in trinity_dpm_get_current_sclk()
Datombios_crtc.c234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); in atombios_blank_crtc()
397 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); in atombios_disable_ss()
402 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); in atombios_disable_ss()
413 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); in atombios_disable_ss()
418 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); in atombios_disable_ss()
1429 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); in dce4_crtc_do_set_base()
1629 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); in avivo_crtc_do_set_base()
1691 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); in radeon_legacy_atom_fixup()
1696 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); in radeon_legacy_atom_fixup()
1699 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); in radeon_legacy_atom_fixup()
[all …]
Drs780_dpm.c211 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
985 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; in rs780_dpm_debugfs_print_current_performance_level()
986 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1007 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; in rs780_dpm_get_current_sclk()
1008 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
Dradeon_ring.c299 ptr = RREG32(ring->rptr_save_reg); in radeon_ring_backup()
483 rptr_next = RREG32(ring->rptr_save_reg); in radeon_debugfs_ring_info()
Datombios_encoders.c43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); in radeon_atom_get_backlight_level_from_reg()
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); in radeon_atom_get_backlight_level_from_reg()
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); in radeon_atom_set_backlight_level_to_reg()
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); in radeon_atom_set_backlight_level_to_reg()
1552 temp = RREG32(reg); in atombios_yuv_setup()
1627 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); in radeon_atom_encoder_dpms_avivo()
2066 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); in atombios_apply_encoder_quirks()
2387 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); in radeon_atom_dac_detect()
2389 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); in radeon_atom_dac_detect()
2436 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); in radeon_atom_dig_detect()
Dradeon_atombios.c4069 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); in radeon_atom_initialize_bios_scratch_regs()
4070 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); in radeon_atom_initialize_bios_scratch_regs()
4072 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); in radeon_atom_initialize_bios_scratch_regs()
4073 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); in radeon_atom_initialize_bios_scratch_regs()
4107 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); in radeon_save_bios_scratch_regs()
4131 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); in radeon_atom_output_lock()
4133 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); in radeon_atom_output_lock()
4163 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); in radeon_atombios_connected_scratch_regs()
4164 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); in radeon_atombios_connected_scratch_regs()
4165 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); in radeon_atombios_connected_scratch_regs()
[all …]
Drv6xx_dpm.c788 tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; in calculate_memory_refresh_rate()
790 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3); in calculate_memory_refresh_rate()
1183 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); in rv6xx_program_display_gap()
2035 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> in rv6xx_dpm_debugfs_print_current_performance_level()
2060 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> in rv6xx_dpm_get_current_sclk()
2083 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> in rv6xx_dpm_get_current_mclk()
Dradeon_kfd.c794 reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4); in get_atc_vmid_pasid_mapping_valid()
804 reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4); in get_atc_vmid_pasid_mapping_pasid()
Dradeon_fence.c95 seq = RREG32(drv->scratch_reg); in radeon_fence_read()
Dradeon_uvd.c989 if ((RREG32(cg_upll_func_cntl) & mask) == mask) in radeon_uvd_send_upll_ctlreq()
Dradeon_audio.c119 return RREG32(reg); in radeon_audio_rreg()
Dradeon_ttm.c1073 value = RREG32(RADEON_MM_DATA); in radeon_ttm_vram_read()
Dradeon.h2526 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) macro
2557 uint32_t tmp_ = RREG32(reg); \
Dkv_dpm.c304 data = RREG32(config_regs->offset << 2); in kv_program_pt_config_registers()
/linux-4.4.14/drivers/gpu/drm/cirrus/
Dcirrus_drv.h40 #define RREG32(reg) ioread32(((void __iomem *)cdev->rmmio) + (reg)) macro
/linux-4.4.14/drivers/gpu/drm/mgag200/
Dmgag200_drv.h46 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) macro
Dmgag200_main.c186 mdev->unique_rev_id = RREG32(0x1e24); in mgag200_device_init()
Dmgag200_mode.c77 status = RREG32(MGAREG_Status); in mga_wait_vsync()
82 status = RREG32(MGAREG_Status); in mga_wait_vsync()
1123 u32 mem_ctl = RREG32(MGAREG_MEMCTL); in mga_crtc_mode_set()