55 	return RREG32(mmUVD_RBC_RB_RPTR);  in uvd_v4_2_ring_get_rptr()
69 	return RREG32(mmUVD_RBC_RB_WPTR);  in uvd_v4_2_ring_get_wptr()
331 			status = RREG32(mmUVD_STATUS);  in uvd_v4_2_start()
370 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);  in uvd_v4_2_start()
493 		tmp = RREG32(mmUVD_CONTEXT_ID);  in uvd_v4_2_ring_test_ring()
619 		orig = data = RREG32(mmUVD_CGC_CTRL);  in uvd_v4_2_enable_mgcg()
628 		orig = data = RREG32(mmUVD_CGC_CTRL);  in uvd_v4_2_enable_mgcg()
640 	tmp = RREG32(mmUVD_CGC_CTRL);  in uvd_v4_2_set_dcm()
667 		u32 tmp = RREG32(mmUVD_CGC_CTRL);  in uvd_v4_2_init_cg()
677 	return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);  in uvd_v4_2_is_idle()
686 		if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))  in uvd_v4_2_wait_for_idle()
710 		 RREG32(mmUVD_SEMA_ADDR_LOW));  in uvd_v4_2_print_status()
712 		 RREG32(mmUVD_SEMA_ADDR_HIGH));  in uvd_v4_2_print_status()
714 		 RREG32(mmUVD_SEMA_CMD));  in uvd_v4_2_print_status()
716 		 RREG32(mmUVD_GPCOM_VCPU_CMD));  in uvd_v4_2_print_status()
718 		 RREG32(mmUVD_GPCOM_VCPU_DATA0));  in uvd_v4_2_print_status()
720 		 RREG32(mmUVD_GPCOM_VCPU_DATA1));  in uvd_v4_2_print_status()
722 		 RREG32(mmUVD_ENGINE_CNTL));  in uvd_v4_2_print_status()
724 		 RREG32(mmUVD_UDEC_ADDR_CONFIG));  in uvd_v4_2_print_status()
726 		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));  in uvd_v4_2_print_status()
728 		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));  in uvd_v4_2_print_status()
730 		 RREG32(mmUVD_SEMA_CNTL));  in uvd_v4_2_print_status()
732 		 RREG32(mmUVD_LMI_EXT40_ADDR));  in uvd_v4_2_print_status()
734 		 RREG32(mmUVD_CTX_INDEX));  in uvd_v4_2_print_status()
736 		 RREG32(mmUVD_CTX_DATA));  in uvd_v4_2_print_status()
738 		 RREG32(mmUVD_CGC_GATE));  in uvd_v4_2_print_status()
740 		 RREG32(mmUVD_CGC_CTRL));  in uvd_v4_2_print_status()
742 		 RREG32(mmUVD_LMI_CTRL2));  in uvd_v4_2_print_status()
744 		 RREG32(mmUVD_MASTINT_EN));  in uvd_v4_2_print_status()
746 		 RREG32(mmUVD_LMI_ADDR_EXT));  in uvd_v4_2_print_status()
748 		 RREG32(mmUVD_LMI_CTRL));  in uvd_v4_2_print_status()
750 		 RREG32(mmUVD_LMI_SWAP_CNTL));  in uvd_v4_2_print_status()
752 		 RREG32(mmUVD_MP_SWAP_CNTL));  in uvd_v4_2_print_status()
754 		 RREG32(mmUVD_MPC_SET_MUXA0));  in uvd_v4_2_print_status()
756 		 RREG32(mmUVD_MPC_SET_MUXA1));  in uvd_v4_2_print_status()
758 		 RREG32(mmUVD_MPC_SET_MUXB0));  in uvd_v4_2_print_status()
760 		 RREG32(mmUVD_MPC_SET_MUXB1));  in uvd_v4_2_print_status()
762 		 RREG32(mmUVD_MPC_SET_MUX));  in uvd_v4_2_print_status()
764 		 RREG32(mmUVD_MPC_SET_ALU));  in uvd_v4_2_print_status()
766 		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));  in uvd_v4_2_print_status()
768 		 RREG32(mmUVD_VCPU_CACHE_SIZE0));  in uvd_v4_2_print_status()
770 		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));  in uvd_v4_2_print_status()
772 		 RREG32(mmUVD_VCPU_CACHE_SIZE1));  in uvd_v4_2_print_status()
774 		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));  in uvd_v4_2_print_status()
776 		 RREG32(mmUVD_VCPU_CACHE_SIZE2));  in uvd_v4_2_print_status()
778 		 RREG32(mmUVD_VCPU_CNTL));  in uvd_v4_2_print_status()
780 		 RREG32(mmUVD_SOFT_RESET));  in uvd_v4_2_print_status()
782 		 RREG32(mmUVD_RBC_IB_BASE));  in uvd_v4_2_print_status()
784 		 RREG32(mmUVD_RBC_IB_SIZE));  in uvd_v4_2_print_status()
786 		 RREG32(mmUVD_RBC_RB_BASE));  in uvd_v4_2_print_status()
788 		 RREG32(mmUVD_RBC_RB_RPTR));  in uvd_v4_2_print_status()
790 		 RREG32(mmUVD_RBC_RB_WPTR));  in uvd_v4_2_print_status()
792 		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));  in uvd_v4_2_print_status()
794 		 RREG32(mmUVD_RBC_RB_CNTL));  in uvd_v4_2_print_status()
796 		 RREG32(mmUVD_STATUS));  in uvd_v4_2_print_status()
798 		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));  in uvd_v4_2_print_status()
800 		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));  in uvd_v4_2_print_status()
802 		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));  in uvd_v4_2_print_status()
804 		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));  in uvd_v4_2_print_status()
806 		 RREG32(mmUVD_CONTEXT_ID));  in uvd_v4_2_print_status()