124 	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);  in dce_v8_0_audio_endpt_rreg()
143 	if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &  in dce_v8_0_is_in_vblank()
154 	pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);  in dce_v8_0_is_counter_moving()
155 	pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);  in dce_v8_0_is_counter_moving()
178 	if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))  in dce_v8_0_vblank_wait()
204 		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);  in dce_v8_0_vblank_get_counter()
247 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v8_0_page_flip()
256 	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);  in dce_v8_0_crtc_get_scanoutpos()
257 	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);  in dce_v8_0_crtc_get_scanoutpos()
278 		if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)  in dce_v8_0_hpd_sense()
282 		if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)  in dce_v8_0_hpd_sense()
286 		if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)  in dce_v8_0_hpd_sense()
290 		if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)  in dce_v8_0_hpd_sense()
294 		if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)  in dce_v8_0_hpd_sense()
298 		if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)  in dce_v8_0_hpd_sense()
324 		tmp = RREG32(mmDC_HPD1_INT_CONTROL);  in dce_v8_0_hpd_set_polarity()
332 		tmp = RREG32(mmDC_HPD2_INT_CONTROL);  in dce_v8_0_hpd_set_polarity()
340 		tmp = RREG32(mmDC_HPD3_INT_CONTROL);  in dce_v8_0_hpd_set_polarity()
348 		tmp = RREG32(mmDC_HPD4_INT_CONTROL);  in dce_v8_0_hpd_set_polarity()
356 		tmp = RREG32(mmDC_HPD5_INT_CONTROL);  in dce_v8_0_hpd_set_polarity()
364 		tmp = RREG32(mmDC_HPD6_INT_CONTROL);  in dce_v8_0_hpd_set_polarity()
485 		if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {  in dce_v8_0_is_display_hung()
486 			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);  in dce_v8_0_is_display_hung()
494 				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);  in dce_v8_0_is_display_hung()
513 	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);  in dce_v8_0_stop_mc_access()
514 	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);  in dce_v8_0_stop_mc_access()
517 	tmp = RREG32(mmVGA_RENDER_CONTROL);  in dce_v8_0_stop_mc_access()
523 		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),  in dce_v8_0_stop_mc_access()
531 			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);  in dce_v8_0_stop_mc_access()
546 			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);  in dce_v8_0_stop_mc_access()
551 			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);  in dce_v8_0_stop_mc_access()
559 			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);  in dce_v8_0_stop_mc_access()
590 			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);  in dce_v8_0_resume_mc_access()
595 			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);  in dce_v8_0_resume_mc_access()
600 			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);  in dce_v8_0_resume_mc_access()
606 				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);  in dce_v8_0_resume_mc_access()
611 			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);  in dce_v8_0_resume_mc_access()
641 	tmp = RREG32(mmVGA_HDP_CONTROL);  in dce_v8_0_set_vga_render_state()
649 	tmp = RREG32(mmVGA_RENDER_CONTROL);  in dce_v8_0_set_vga_render_state()
785 		if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &  in dce_v8_0_line_buffer_adjust()
818 	u32 tmp = RREG32(mmMC_SHARED_CHMAP);  in cik_get_number_of_dram_channels()
1283 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1292 	tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1762 	val = RREG32(mmHDMI_CONTROL + offset);  in dce_v8_0_afmt_setmode()
1957 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;  in dce_v8_0_vga_enable()
2177 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_crtc_do_set_base()
2388 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v8_0_lock_cursor()
3051 		tmp = RREG32(mmSRBM_SOFT_RESET);  in dce_v8_0_soft_reset()
3055 		tmp = RREG32(mmSRBM_SOFT_RESET);  in dce_v8_0_soft_reset()
3061 		tmp = RREG32(mmSRBM_SOFT_RESET);  in dce_v8_0_soft_reset()
3107 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);  in dce_v8_0_set_crtc_vblank_interrupt_state()
3112 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);  in dce_v8_0_set_crtc_vblank_interrupt_state()
3158 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);  in dce_v8_0_set_crtc_vline_interrupt_state()
3163 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);  in dce_v8_0_set_crtc_vline_interrupt_state()
3205 		dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);  in dce_v8_0_set_hpd_interrupt_state()
3210 		dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);  in dce_v8_0_set_hpd_interrupt_state()
3274 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);  in dce_v8_0_crtc_irq()
3319 	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);  in dce_v8_0_set_pageflip_interrupt_state()
3347 	if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &  in dce_v8_0_pageflip_irq()
3396 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v8_0_hpd_irq()
3401 		tmp = RREG32(int_control);  in dce_v8_0_hpd_irq()