793 	u32 tmp = RREG32(CG_CLKPIN_CNTL);  in rv770_get_xclk()
807 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rv770_page_flip()
829 		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)  in rv770_page_flip()
845 	return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &  in rv770_page_flip_pending()
852 	u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>  in rv770_get_temp()
1019 	tmp = RREG32(HDP_DEBUG1);  in rv770_mc_program()
1103 	RREG32(GRBM_SOFT_RESET);  in rv770_cp_load_microcode()
1139 	tmp = RREG32(CG_SPLL_FUNC_CNTL_2);  in rv770_set_clk_bypass_mode()
1145 		if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)  in rv770_set_clk_bypass_mode()
1153 	tmp = RREG32(MPLL_CNTL_MODE);  in rv770_set_clk_bypass_mode()
1297 	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);  in rv770_gpu_init()
1299 	shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);  in rv770_gpu_init()
1313 	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;  in rv770_gpu_init()
1335 	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;  in rv770_gpu_init()
1400 	ta_aux_cntl = RREG32(TA_CNTL_AUX);  in rv770_gpu_init()
1403 	sx_debug_1 = RREG32(SX_DEBUG_1);  in rv770_gpu_init()
1407 	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);  in rv770_gpu_init()
1421 	db_debug3 = RREG32(DB_DEBUG3);  in rv770_gpu_init()
1437 		db_debug4 = RREG32(DB_DEBUG4);  in rv770_gpu_init()
1477 	sq_config = RREG32(SQ_CONFIG);  in rv770_gpu_init()
1590 	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);  in rv770_gpu_init()
1646 	tmp = RREG32(MC_ARB_RAMCFG);  in rv770_mc_init()
1654 	tmp = RREG32(MC_SHARED_CHMAP);  in rv770_mc_init()
1675 	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);  in rv770_mc_init()
1676 	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);  in rv770_mc_init()
2018 		tmp = RREG32(0x541c);  in rv770_pcie_gen2_enable()