Lines Matching refs:RREG32
1290 *val = RREG32(reg); in si_get_allowed_info_register()
1313 tmp = RREG32(CG_CLKPIN_CNTL_2); in si_get_xclk()
1317 tmp = RREG32(CG_CLKPIN_CNTL); in si_get_xclk()
1330 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> in si_get_temp()
1593 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in si_mc_load_microcode()
1597 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in si_mc_load_microcode()
1630 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in si_mc_load_microcode()
1635 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in si_mc_load_microcode()
1950 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
1972 u32 tmp = RREG32(MC_SHARED_CHMAP); in si_get_number_of_dram_channels()
2385 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2394 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2979 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in si_get_cu_enabled()
2984 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); in si_get_cu_enabled()
3003 data = RREG32(SPI_STATIC_THREAD_MGMT_3); in si_setup_spi()
3026 data = RREG32(CC_RB_BACKEND_DISABLE); in si_get_rb_disabled()
3031 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); in si_get_rb_disabled()
3205 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in si_gpu_init()
3206 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in si_gpu_init()
3310 sx_debug_1 = RREG32(SX_DEBUG_1); in si_gpu_init()
3344 tmp = RREG32(HDP_MISC_CNTL); in si_gpu_init()
3348 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in si_gpu_init()
3777 tmp = RREG32(GRBM_STATUS); in si_gpu_check_soft_reset()
3794 tmp = RREG32(GRBM_STATUS2); in si_gpu_check_soft_reset()
3799 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3804 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3809 tmp = RREG32(SRBM_STATUS2); in si_gpu_check_soft_reset()
3817 tmp = RREG32(SRBM_STATUS); in si_gpu_check_soft_reset()
3839 tmp = RREG32(VM_L2_STATUS); in si_gpu_check_soft_reset()
3865 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); in si_gpu_soft_reset()
3867 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); in si_gpu_soft_reset()
3881 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3887 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3948 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3952 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3958 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3962 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3966 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3972 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3988 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3992 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3997 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS) in si_set_clk_bypass_mode()
4002 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4006 tmp = RREG32(MPLL_CNTL_MODE); in si_set_clk_bypass_mode()
4015 tmp = RREG32(SPLL_CNTL_MODE); in si_spll_powerdown()
4019 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4023 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4027 tmp = RREG32(SPLL_CNTL_MODE); in si_spll_powerdown()
4048 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4052 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4078 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in si_gpu_pci_config_reset()
4205 tmp = RREG32(MC_ARB_RAMCFG); in si_mc_init()
4213 tmp = RREG32(MC_SHARED_CHMAP); in si_mc_init()
4249 tmp = RREG32(CONFIG_MEMSIZE); in si_mc_init()
4375 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in si_pcie_gart_disable()
5120 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) in si_wait_for_rlc_serdes()
5126 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) in si_wait_for_rlc_serdes()
5135 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt()
5147 tmp = RREG32(DB_DEPTH_INFO); in si_enable_gui_idle_interrupt()
5151 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) in si_enable_gui_idle_interrupt()
5163 tmp = RREG32(UVD_CGC_CTRL); in si_set_uvd_dcm()
5186 u32 tmp = RREG32(UVD_CGC_CTRL); in si_init_uvd_internal_cg()
5196 orig = data = RREG32(RLC_CNTL); in si_halt_rlc()
5212 tmp = RREG32(RLC_CNTL); in si_update_rlc()
5221 orig = data = RREG32(DMA_PG); in si_enable_dma_pg()
5250 tmp = RREG32(RLC_PG_CNTL); in si_enable_gfx_cgpg()
5254 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_enable_gfx_cgpg()
5258 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_enable_gfx_cgpg()
5262 tmp = RREG32(DB_RENDER_CONTROL); in si_enable_gfx_cgpg()
5272 tmp = RREG32(RLC_PG_CNTL); in si_init_gfx_cgpg()
5278 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_init_gfx_cgpg()
5292 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in si_get_cu_active_bitmap()
5293 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); in si_get_cu_active_bitmap()
5336 tmp = RREG32(RLC_MAX_PG_CU); in si_init_ao_cu_mask()
5347 orig = data = RREG32(RLC_CGCG_CGLS_CTRL); in si_enable_cgcg()
5370 RREG32(CB_CGTT_SCLK_CTRL); in si_enable_cgcg()
5371 RREG32(CB_CGTT_SCLK_CTRL); in si_enable_cgcg()
5372 RREG32(CB_CGTT_SCLK_CTRL); in si_enable_cgcg()
5373 RREG32(CB_CGTT_SCLK_CTRL); in si_enable_cgcg()
5388 orig = data = RREG32(CGTS_SM_CTRL_REG); in si_enable_mgcg()
5394 orig = data = RREG32(CP_MEM_SLP_CNTL); in si_enable_mgcg()
5400 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in si_enable_mgcg()
5413 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in si_enable_mgcg()
5418 data = RREG32(CP_MEM_SLP_CNTL); in si_enable_mgcg()
5423 orig = data = RREG32(CGTS_SM_CTRL_REG); in si_enable_mgcg()
5448 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg()
5460 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg()
5490 orig = data = RREG32(mc_cg_registers[i]); in si_enable_mc_ls()
5507 orig = data = RREG32(mc_cg_registers[i]); in si_enable_mc_mgcg()
5529 orig = data = RREG32(DMA_POWER_CNTL + offset); in si_enable_dma_mgcg()
5541 orig = data = RREG32(DMA_POWER_CNTL + offset); in si_enable_dma_mgcg()
5546 orig = data = RREG32(DMA_CLK_CTRL + offset); in si_enable_dma_mgcg()
5577 orig = data = RREG32(HDP_HOST_PATH_CNTL); in si_enable_hdp_mgcg()
5593 orig = data = RREG32(HDP_MEM_POWER_LS); in si_enable_hdp_ls()
5796 u32 tmp = RREG32(GRBM_SOFT_RESET); in si_rlc_reset()
5829 tmp = RREG32(MC_SEQ_MISC0); in si_lbpw_supported()
5839 tmp = RREG32(RLC_LB_CNTL); in si_enable_lbpw()
5909 u32 ih_cntl = RREG32(IH_CNTL); in si_enable_interrupts()
5910 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts()
5921 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts()
5922 u32 ih_cntl = RREG32(IH_CNTL); in si_disable_interrupts()
5939 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5944 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5946 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5979 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5981 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5983 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5985 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5987 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5989 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
6018 interrupt_cntl = RREG32(INTERRUPT_CNTL); in si_irq_init()
6087 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6091 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6092 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6093 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6094 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6095 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6096 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6099 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6100 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6102 thermal_int = RREG32(CG_THERMAL_INT) & in si_irq_set()
6240 RREG32(SRBM_STATUS); in si_irq_set()
6252 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); in si_irq_ack()
6253 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in si_irq_ack()
6254 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in si_irq_ack()
6255 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in si_irq_ack()
6256 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in si_irq_ack()
6257 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in si_irq_ack()
6258 …rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSE… in si_irq_ack()
6259 …rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSE… in si_irq_ack()
6261 …rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSE… in si_irq_ack()
6262 …rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSE… in si_irq_ack()
6265 …rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSE… in si_irq_ack()
6266 …rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSE… in si_irq_ack()
6313 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6318 tmp = RREG32(DC_HPD2_INT_CONTROL); in si_irq_ack()
6323 tmp = RREG32(DC_HPD3_INT_CONTROL); in si_irq_ack()
6328 tmp = RREG32(DC_HPD4_INT_CONTROL); in si_irq_ack()
6333 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6338 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6344 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6349 tmp = RREG32(DC_HPD2_INT_CONTROL); in si_irq_ack()
6354 tmp = RREG32(DC_HPD3_INT_CONTROL); in si_irq_ack()
6359 tmp = RREG32(DC_HPD4_INT_CONTROL); in si_irq_ack()
6364 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6369 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6403 wptr = RREG32(IH_RB_WPTR); in si_get_ih_wptr()
6414 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr()
6775 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in si_irq_process()
6784 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in si_irq_process()
6785 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in si_irq_process()
7316 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | in si_get_gpu_clock_counter()
7317 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in si_get_gpu_clock_counter()
7718 orig = data = RREG32(THM_CLK_CNTL); in si_program_aspm()
7724 orig = data = RREG32(MISC_CLK_CNTL); in si_program_aspm()
7730 orig = data = RREG32(CG_CLKPIN_CNTL); in si_program_aspm()
7735 orig = data = RREG32(CG_CLKPIN_CNTL_2); in si_program_aspm()
7740 orig = data = RREG32(MPLL_BYPASSCLK_SEL); in si_program_aspm()
7746 orig = data = RREG32(SPLL_CNTL_MODE); in si_program_aspm()