97 		RREG32(GB_ADDR_CONFIG);  in sumo_gfx_clockgating_enable()
109 	local0 = RREG32(CG_CGTT_LOCAL_0);  in sumo_mg_clockgating_enable()
110 	local1 = RREG32(CG_CGTT_LOCAL_1);  in sumo_mg_clockgating_enable()
281 		RREG32(GB_ADDR_CONFIG);  in sumo_gfx_powergating_enable()
500 		u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);  in sumo_set_ds_dividers()
514 		u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);  in sumo_set_ss_dividers()
524 	u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);  in sumo_set_vid()
540 	cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);  in sumo_set_allos_gnb_slow()
553 	u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;  in sumo_program_power_level()
602 	if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)  in sumo_dpm_enabled()
632 		if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)  in sumo_set_forced_mode_enabled()
643 		if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)  in sumo_wait_for_level_0()
648 		if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)  in sumo_wait_for_level_0()
741 	u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);  in sumo_program_wl()
803 	u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);  in sumo_program_bootup_state()
878 	u32 v = RREG32(DOUT_SCRATCH3);  in sumo_take_smu_control()
892 		u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);  in sumo_enable_sclk_ds()
893 		u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);  in sumo_enable_sclk_ds()
930 	u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);  in sumo_program_ttp()
943 	u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);  in sumo_program_ttt()
972 	u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);  in sumo_program_dc_hto()
1743 	u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;  in sumo_dpm_init()
1820 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>  in sumo_dpm_debugfs_print_current_performance_level()
1847 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>  in sumo_dpm_get_current_sclk()