256 	bus_cntl = RREG32(R600_BUS_CNTL);  in ni_read_disabled_bios()
257 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in ni_read_disabled_bios()
258 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in ni_read_disabled_bios()
259 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in ni_read_disabled_bios()
260 	rom_cntl = RREG32(R600_ROM_CNTL);  in ni_read_disabled_bios()
302 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in r700_read_disabled_bios()
303 	bus_cntl = RREG32(R600_BUS_CNTL);  in r700_read_disabled_bios()
304 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in r700_read_disabled_bios()
305 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in r700_read_disabled_bios()
306 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in r700_read_disabled_bios()
307 	rom_cntl = RREG32(R600_ROM_CNTL);  in r700_read_disabled_bios()
324 		cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);  in r700_read_disabled_bios()
333 			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);  in r700_read_disabled_bios()
348 			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);  in r700_read_disabled_bios()
375 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in r600_read_disabled_bios()
376 	bus_cntl = RREG32(R600_BUS_CNTL);  in r600_read_disabled_bios()
377 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in r600_read_disabled_bios()
378 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in r600_read_disabled_bios()
379 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in r600_read_disabled_bios()
380 	rom_cntl = RREG32(R600_ROM_CNTL);  in r600_read_disabled_bios()
381 	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);  in r600_read_disabled_bios()
382 	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
383 	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
384 	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
385 	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
386 	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);  in r600_read_disabled_bios()
449 	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);  in avivo_read_disabled_bios()
450 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in avivo_read_disabled_bios()
451 	bus_cntl = RREG32(RV370_BUS_CNTL);  in avivo_read_disabled_bios()
452 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in avivo_read_disabled_bios()
453 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in avivo_read_disabled_bios()
454 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in avivo_read_disabled_bios()
455 	gpiopad_a = RREG32(RADEON_GPIOPAD_A);  in avivo_read_disabled_bios()
456 	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);  in avivo_read_disabled_bios()
457 	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);  in avivo_read_disabled_bios()
508 	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);  in legacy_read_disabled_bios()
509 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in legacy_read_disabled_bios()
511 		bus_cntl = RREG32(RV370_BUS_CNTL);  in legacy_read_disabled_bios()
513 		bus_cntl = RREG32(RADEON_BUS_CNTL);  in legacy_read_disabled_bios()
514 	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);  in legacy_read_disabled_bios()
516 	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);  in legacy_read_disabled_bios()
520 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);  in legacy_read_disabled_bios()
524 		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);  in legacy_read_disabled_bios()