60 				bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;  in cypress_enable_bif_dynamic_pcie_gen2()
107 		RREG32(GB_ADDR_CONFIG);
148 		RREG32(GB_ADDR_CONFIG);  in cypress_gfx_clock_gating_enable()
506 		mc_seq_misc7 = RREG32(MC_SEQ_MISC7);  in cypress_populate_mclk_value()
717 			    ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))  in cypress_convert_power_level_to_smc()
718 				dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;  in cypress_convert_power_level_to_smc()
720 				dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;  in cypress_convert_power_level_to_smc()
928 	u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);  in cypress_program_memory_timing_parameters()
1038 			RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);  in cypress_retrieve_ac_timing_for_one_entry()
1109 			if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)  in cypress_wait_for_mc_sequencer()
1124 	if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)  in cypress_force_mc_use_s1()
1153 		if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)  in cypress_force_mc_use_s1()
1172 		value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);  in cypress_copy_ac_timing_from_s1_to_s0()
1211 		if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))  in cypress_force_mc_use_s0()
1576 	u32 tmp = RREG32(GENERAL_PWRMGT);  in cypress_get_mvdd_configuration()
1730 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);  in cypress_enable_display_gap()
1747 	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);  in cypress_program_display_gap()
1760 	tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);  in cypress_program_display_gap()