1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/seq_file.h> 29#include <linux/slab.h> 30#include <drm/drmP.h> 31#include <drm/radeon_drm.h> 32#include "radeon_reg.h" 33#include "radeon.h" 34#include "radeon_asic.h" 35#include "r100d.h" 36#include "rs100d.h" 37#include "rv200d.h" 38#include "rv250d.h" 39#include "atom.h" 40 41#include <linux/firmware.h> 42#include <linux/module.h> 43 44#include "r100_reg_safe.h" 45#include "rn50_reg_safe.h" 46 47/* Firmware Names */ 48#define FIRMWARE_R100 "radeon/R100_cp.bin" 49#define FIRMWARE_R200 "radeon/R200_cp.bin" 50#define FIRMWARE_R300 "radeon/R300_cp.bin" 51#define FIRMWARE_R420 "radeon/R420_cp.bin" 52#define FIRMWARE_RS690 "radeon/RS690_cp.bin" 53#define FIRMWARE_RS600 "radeon/RS600_cp.bin" 54#define FIRMWARE_R520 "radeon/R520_cp.bin" 55 56MODULE_FIRMWARE(FIRMWARE_R100); 57MODULE_FIRMWARE(FIRMWARE_R200); 58MODULE_FIRMWARE(FIRMWARE_R300); 59MODULE_FIRMWARE(FIRMWARE_R420); 60MODULE_FIRMWARE(FIRMWARE_RS690); 61MODULE_FIRMWARE(FIRMWARE_RS600); 62MODULE_FIRMWARE(FIRMWARE_R520); 63 64#include "r100_track.h" 65 66/* This files gather functions specifics to: 67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 68 * and others in some cases. 69 */ 70 71static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 72{ 73 if (crtc == 0) { 74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 75 return true; 76 else 77 return false; 78 } else { 79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 80 return true; 81 else 82 return false; 83 } 84} 85 86static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 87{ 88 u32 vline1, vline2; 89 90 if (crtc == 0) { 91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 93 } else { 94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 96 } 97 if (vline1 != vline2) 98 return true; 99 else 100 return false; 101} 102 103/** 104 * r100_wait_for_vblank - vblank wait asic callback. 105 * 106 * @rdev: radeon_device pointer 107 * @crtc: crtc to wait for vblank on 108 * 109 * Wait for vblank on the requested crtc (r1xx-r4xx). 110 */ 111void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 112{ 113 unsigned i = 0; 114 115 if (crtc >= rdev->num_crtc) 116 return; 117 118 if (crtc == 0) { 119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 120 return; 121 } else { 122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 123 return; 124 } 125 126 /* depending on when we hit vblank, we may be close to active; if so, 127 * wait for another frame. 128 */ 129 while (r100_is_in_vblank(rdev, crtc)) { 130 if (i++ % 100 == 0) { 131 if (!r100_is_counter_moving(rdev, crtc)) 132 break; 133 } 134 } 135 136 while (!r100_is_in_vblank(rdev, crtc)) { 137 if (i++ % 100 == 0) { 138 if (!r100_is_counter_moving(rdev, crtc)) 139 break; 140 } 141 } 142} 143 144/** 145 * r100_page_flip - pageflip callback. 146 * 147 * @rdev: radeon_device pointer 148 * @crtc_id: crtc to cleanup pageflip on 149 * @crtc_base: new address of the crtc (GPU MC address) 150 * 151 * Does the actual pageflip (r1xx-r4xx). 152 * During vblank we take the crtc lock and wait for the update_pending 153 * bit to go high, when it does, we release the lock, and allow the 154 * double buffered update to take place. 155 */ 156void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 157{ 158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 160 int i; 161 162 /* Lock the graphics update lock */ 163 /* update the scanout addresses */ 164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 165 166 /* Wait for update_pending to go high. */ 167 for (i = 0; i < rdev->usec_timeout; i++) { 168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 169 break; 170 udelay(1); 171 } 172 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 173 174 /* Unlock the lock, so double-buffering can take place inside vblank */ 175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 177 178} 179 180/** 181 * r100_page_flip_pending - check if page flip is still pending 182 * 183 * @rdev: radeon_device pointer 184 * @crtc_id: crtc to check 185 * 186 * Check if the last pagefilp is still pending (r1xx-r4xx). 187 * Returns the current update pending status. 188 */ 189bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 190{ 191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 192 193 /* Return current update_pending status: */ 194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 195 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 196} 197 198/** 199 * r100_pm_get_dynpm_state - look up dynpm power state callback. 200 * 201 * @rdev: radeon_device pointer 202 * 203 * Look up the optimal power state based on the 204 * current state of the GPU (r1xx-r5xx). 205 * Used for dynpm only. 206 */ 207void r100_pm_get_dynpm_state(struct radeon_device *rdev) 208{ 209 int i; 210 rdev->pm.dynpm_can_upclock = true; 211 rdev->pm.dynpm_can_downclock = true; 212 213 switch (rdev->pm.dynpm_planned_action) { 214 case DYNPM_ACTION_MINIMUM: 215 rdev->pm.requested_power_state_index = 0; 216 rdev->pm.dynpm_can_downclock = false; 217 break; 218 case DYNPM_ACTION_DOWNCLOCK: 219 if (rdev->pm.current_power_state_index == 0) { 220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 221 rdev->pm.dynpm_can_downclock = false; 222 } else { 223 if (rdev->pm.active_crtc_count > 1) { 224 for (i = 0; i < rdev->pm.num_power_states; i++) { 225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 226 continue; 227 else if (i >= rdev->pm.current_power_state_index) { 228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 229 break; 230 } else { 231 rdev->pm.requested_power_state_index = i; 232 break; 233 } 234 } 235 } else 236 rdev->pm.requested_power_state_index = 237 rdev->pm.current_power_state_index - 1; 238 } 239 /* don't use the power state if crtcs are active and no display flag is set */ 240 if ((rdev->pm.active_crtc_count > 0) && 241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 242 RADEON_PM_MODE_NO_DISPLAY)) { 243 rdev->pm.requested_power_state_index++; 244 } 245 break; 246 case DYNPM_ACTION_UPCLOCK: 247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 249 rdev->pm.dynpm_can_upclock = false; 250 } else { 251 if (rdev->pm.active_crtc_count > 1) { 252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 254 continue; 255 else if (i <= rdev->pm.current_power_state_index) { 256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 257 break; 258 } else { 259 rdev->pm.requested_power_state_index = i; 260 break; 261 } 262 } 263 } else 264 rdev->pm.requested_power_state_index = 265 rdev->pm.current_power_state_index + 1; 266 } 267 break; 268 case DYNPM_ACTION_DEFAULT: 269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 270 rdev->pm.dynpm_can_upclock = false; 271 break; 272 case DYNPM_ACTION_NONE: 273 default: 274 DRM_ERROR("Requested mode for not defined action\n"); 275 return; 276 } 277 /* only one clock mode per power state */ 278 rdev->pm.requested_clock_mode_index = 0; 279 280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 281 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 282 clock_info[rdev->pm.requested_clock_mode_index].sclk, 283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 284 clock_info[rdev->pm.requested_clock_mode_index].mclk, 285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 286 pcie_lanes); 287} 288 289/** 290 * r100_pm_init_profile - Initialize power profiles callback. 291 * 292 * @rdev: radeon_device pointer 293 * 294 * Initialize the power states used in profile mode 295 * (r1xx-r3xx). 296 * Used for profile mode only. 297 */ 298void r100_pm_init_profile(struct radeon_device *rdev) 299{ 300 /* default */ 301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 305 /* low sh */ 306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 310 /* mid sh */ 311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 315 /* high sh */ 316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 320 /* low mh */ 321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 325 /* mid mh */ 326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 330 /* high mh */ 331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 335} 336 337/** 338 * r100_pm_misc - set additional pm hw parameters callback. 339 * 340 * @rdev: radeon_device pointer 341 * 342 * Set non-clock parameters associated with a power state 343 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 344 */ 345void r100_pm_misc(struct radeon_device *rdev) 346{ 347 int requested_index = rdev->pm.requested_power_state_index; 348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 349 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 351 352 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 353 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 354 tmp = RREG32(voltage->gpio.reg); 355 if (voltage->active_high) 356 tmp |= voltage->gpio.mask; 357 else 358 tmp &= ~(voltage->gpio.mask); 359 WREG32(voltage->gpio.reg, tmp); 360 if (voltage->delay) 361 udelay(voltage->delay); 362 } else { 363 tmp = RREG32(voltage->gpio.reg); 364 if (voltage->active_high) 365 tmp &= ~voltage->gpio.mask; 366 else 367 tmp |= voltage->gpio.mask; 368 WREG32(voltage->gpio.reg, tmp); 369 if (voltage->delay) 370 udelay(voltage->delay); 371 } 372 } 373 374 sclk_cntl = RREG32_PLL(SCLK_CNTL); 375 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 377 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 378 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 380 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 381 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 382 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 383 else 384 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 385 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 386 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 387 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 388 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 389 } else 390 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 391 392 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 393 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 394 if (voltage->delay) { 395 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 396 switch (voltage->delay) { 397 case 33: 398 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 399 break; 400 case 66: 401 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 402 break; 403 case 99: 404 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 405 break; 406 case 132: 407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 408 break; 409 } 410 } else 411 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 412 } else 413 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 414 415 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 416 sclk_cntl &= ~FORCE_HDP; 417 else 418 sclk_cntl |= FORCE_HDP; 419 420 WREG32_PLL(SCLK_CNTL, sclk_cntl); 421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 423 424 /* set pcie lanes */ 425 if ((rdev->flags & RADEON_IS_PCIE) && 426 !(rdev->flags & RADEON_IS_IGP) && 427 rdev->asic->pm.set_pcie_lanes && 428 (ps->pcie_lanes != 429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 430 radeon_set_pcie_lanes(rdev, 431 ps->pcie_lanes); 432 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 433 } 434} 435 436/** 437 * r100_pm_prepare - pre-power state change callback. 438 * 439 * @rdev: radeon_device pointer 440 * 441 * Prepare for a power state change (r1xx-r4xx). 442 */ 443void r100_pm_prepare(struct radeon_device *rdev) 444{ 445 struct drm_device *ddev = rdev->ddev; 446 struct drm_crtc *crtc; 447 struct radeon_crtc *radeon_crtc; 448 u32 tmp; 449 450 /* disable any active CRTCs */ 451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 452 radeon_crtc = to_radeon_crtc(crtc); 453 if (radeon_crtc->enabled) { 454 if (radeon_crtc->crtc_id) { 455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 456 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 458 } else { 459 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 460 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 461 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 462 } 463 } 464 } 465} 466 467/** 468 * r100_pm_finish - post-power state change callback. 469 * 470 * @rdev: radeon_device pointer 471 * 472 * Clean up after a power state change (r1xx-r4xx). 473 */ 474void r100_pm_finish(struct radeon_device *rdev) 475{ 476 struct drm_device *ddev = rdev->ddev; 477 struct drm_crtc *crtc; 478 struct radeon_crtc *radeon_crtc; 479 u32 tmp; 480 481 /* enable any active CRTCs */ 482 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 483 radeon_crtc = to_radeon_crtc(crtc); 484 if (radeon_crtc->enabled) { 485 if (radeon_crtc->crtc_id) { 486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 487 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 489 } else { 490 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 491 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 492 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 493 } 494 } 495 } 496} 497 498/** 499 * r100_gui_idle - gui idle callback. 500 * 501 * @rdev: radeon_device pointer 502 * 503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 504 * Returns true if idle, false if not. 505 */ 506bool r100_gui_idle(struct radeon_device *rdev) 507{ 508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 509 return false; 510 else 511 return true; 512} 513 514/* hpd for digital panel detect/disconnect */ 515/** 516 * r100_hpd_sense - hpd sense callback. 517 * 518 * @rdev: radeon_device pointer 519 * @hpd: hpd (hotplug detect) pin 520 * 521 * Checks if a digital monitor is connected (r1xx-r4xx). 522 * Returns true if connected, false if not connected. 523 */ 524bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 525{ 526 bool connected = false; 527 528 switch (hpd) { 529 case RADEON_HPD_1: 530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 531 connected = true; 532 break; 533 case RADEON_HPD_2: 534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 535 connected = true; 536 break; 537 default: 538 break; 539 } 540 return connected; 541} 542 543/** 544 * r100_hpd_set_polarity - hpd set polarity callback. 545 * 546 * @rdev: radeon_device pointer 547 * @hpd: hpd (hotplug detect) pin 548 * 549 * Set the polarity of the hpd pin (r1xx-r4xx). 550 */ 551void r100_hpd_set_polarity(struct radeon_device *rdev, 552 enum radeon_hpd_id hpd) 553{ 554 u32 tmp; 555 bool connected = r100_hpd_sense(rdev, hpd); 556 557 switch (hpd) { 558 case RADEON_HPD_1: 559 tmp = RREG32(RADEON_FP_GEN_CNTL); 560 if (connected) 561 tmp &= ~RADEON_FP_DETECT_INT_POL; 562 else 563 tmp |= RADEON_FP_DETECT_INT_POL; 564 WREG32(RADEON_FP_GEN_CNTL, tmp); 565 break; 566 case RADEON_HPD_2: 567 tmp = RREG32(RADEON_FP2_GEN_CNTL); 568 if (connected) 569 tmp &= ~RADEON_FP2_DETECT_INT_POL; 570 else 571 tmp |= RADEON_FP2_DETECT_INT_POL; 572 WREG32(RADEON_FP2_GEN_CNTL, tmp); 573 break; 574 default: 575 break; 576 } 577} 578 579/** 580 * r100_hpd_init - hpd setup callback. 581 * 582 * @rdev: radeon_device pointer 583 * 584 * Setup the hpd pins used by the card (r1xx-r4xx). 585 * Set the polarity, and enable the hpd interrupts. 586 */ 587void r100_hpd_init(struct radeon_device *rdev) 588{ 589 struct drm_device *dev = rdev->ddev; 590 struct drm_connector *connector; 591 unsigned enable = 0; 592 593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 594 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 595 enable |= 1 << radeon_connector->hpd.hpd; 596 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 597 } 598 radeon_irq_kms_enable_hpd(rdev, enable); 599} 600 601/** 602 * r100_hpd_fini - hpd tear down callback. 603 * 604 * @rdev: radeon_device pointer 605 * 606 * Tear down the hpd pins used by the card (r1xx-r4xx). 607 * Disable the hpd interrupts. 608 */ 609void r100_hpd_fini(struct radeon_device *rdev) 610{ 611 struct drm_device *dev = rdev->ddev; 612 struct drm_connector *connector; 613 unsigned disable = 0; 614 615 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 616 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 617 disable |= 1 << radeon_connector->hpd.hpd; 618 } 619 radeon_irq_kms_disable_hpd(rdev, disable); 620} 621 622/* 623 * PCI GART 624 */ 625void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 626{ 627 /* TODO: can we do somethings here ? */ 628 /* It seems hw only cache one entry so we should discard this 629 * entry otherwise if first GPU GART read hit this entry it 630 * could end up in wrong address. */ 631} 632 633int r100_pci_gart_init(struct radeon_device *rdev) 634{ 635 int r; 636 637 if (rdev->gart.ptr) { 638 WARN(1, "R100 PCI GART already initialized\n"); 639 return 0; 640 } 641 /* Initialize common gart structure */ 642 r = radeon_gart_init(rdev); 643 if (r) 644 return r; 645 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 646 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 647 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 648 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 649 return radeon_gart_table_ram_alloc(rdev); 650} 651 652int r100_pci_gart_enable(struct radeon_device *rdev) 653{ 654 uint32_t tmp; 655 656 /* discard memory request outside of configured range */ 657 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 658 WREG32(RADEON_AIC_CNTL, tmp); 659 /* set address range for PCI address translate */ 660 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 661 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 662 /* set PCI GART page-table base address */ 663 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 664 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 665 WREG32(RADEON_AIC_CNTL, tmp); 666 r100_pci_gart_tlb_flush(rdev); 667 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 668 (unsigned)(rdev->mc.gtt_size >> 20), 669 (unsigned long long)rdev->gart.table_addr); 670 rdev->gart.ready = true; 671 return 0; 672} 673 674void r100_pci_gart_disable(struct radeon_device *rdev) 675{ 676 uint32_t tmp; 677 678 /* discard memory request outside of configured range */ 679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 680 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 681 WREG32(RADEON_AIC_LO_ADDR, 0); 682 WREG32(RADEON_AIC_HI_ADDR, 0); 683} 684 685uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 686{ 687 return addr; 688} 689 690void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 691 uint64_t entry) 692{ 693 u32 *gtt = rdev->gart.ptr; 694 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 695} 696 697void r100_pci_gart_fini(struct radeon_device *rdev) 698{ 699 radeon_gart_fini(rdev); 700 r100_pci_gart_disable(rdev); 701 radeon_gart_table_ram_free(rdev); 702} 703 704int r100_irq_set(struct radeon_device *rdev) 705{ 706 uint32_t tmp = 0; 707 708 if (!rdev->irq.installed) { 709 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 710 WREG32(R_000040_GEN_INT_CNTL, 0); 711 return -EINVAL; 712 } 713 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 714 tmp |= RADEON_SW_INT_ENABLE; 715 } 716 if (rdev->irq.crtc_vblank_int[0] || 717 atomic_read(&rdev->irq.pflip[0])) { 718 tmp |= RADEON_CRTC_VBLANK_MASK; 719 } 720 if (rdev->irq.crtc_vblank_int[1] || 721 atomic_read(&rdev->irq.pflip[1])) { 722 tmp |= RADEON_CRTC2_VBLANK_MASK; 723 } 724 if (rdev->irq.hpd[0]) { 725 tmp |= RADEON_FP_DETECT_MASK; 726 } 727 if (rdev->irq.hpd[1]) { 728 tmp |= RADEON_FP2_DETECT_MASK; 729 } 730 WREG32(RADEON_GEN_INT_CNTL, tmp); 731 732 /* read back to post the write */ 733 RREG32(RADEON_GEN_INT_CNTL); 734 735 return 0; 736} 737 738void r100_irq_disable(struct radeon_device *rdev) 739{ 740 u32 tmp; 741 742 WREG32(R_000040_GEN_INT_CNTL, 0); 743 /* Wait and acknowledge irq */ 744 mdelay(1); 745 tmp = RREG32(R_000044_GEN_INT_STATUS); 746 WREG32(R_000044_GEN_INT_STATUS, tmp); 747} 748 749static uint32_t r100_irq_ack(struct radeon_device *rdev) 750{ 751 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 752 uint32_t irq_mask = RADEON_SW_INT_TEST | 753 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 754 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 755 756 if (irqs) { 757 WREG32(RADEON_GEN_INT_STATUS, irqs); 758 } 759 return irqs & irq_mask; 760} 761 762int r100_irq_process(struct radeon_device *rdev) 763{ 764 uint32_t status, msi_rearm; 765 bool queue_hotplug = false; 766 767 status = r100_irq_ack(rdev); 768 if (!status) { 769 return IRQ_NONE; 770 } 771 if (rdev->shutdown) { 772 return IRQ_NONE; 773 } 774 while (status) { 775 /* SW interrupt */ 776 if (status & RADEON_SW_INT_TEST) { 777 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 778 } 779 /* Vertical blank interrupts */ 780 if (status & RADEON_CRTC_VBLANK_STAT) { 781 if (rdev->irq.crtc_vblank_int[0]) { 782 drm_handle_vblank(rdev->ddev, 0); 783 rdev->pm.vblank_sync = true; 784 wake_up(&rdev->irq.vblank_queue); 785 } 786 if (atomic_read(&rdev->irq.pflip[0])) 787 radeon_crtc_handle_vblank(rdev, 0); 788 } 789 if (status & RADEON_CRTC2_VBLANK_STAT) { 790 if (rdev->irq.crtc_vblank_int[1]) { 791 drm_handle_vblank(rdev->ddev, 1); 792 rdev->pm.vblank_sync = true; 793 wake_up(&rdev->irq.vblank_queue); 794 } 795 if (atomic_read(&rdev->irq.pflip[1])) 796 radeon_crtc_handle_vblank(rdev, 1); 797 } 798 if (status & RADEON_FP_DETECT_STAT) { 799 queue_hotplug = true; 800 DRM_DEBUG("HPD1\n"); 801 } 802 if (status & RADEON_FP2_DETECT_STAT) { 803 queue_hotplug = true; 804 DRM_DEBUG("HPD2\n"); 805 } 806 status = r100_irq_ack(rdev); 807 } 808 if (queue_hotplug) 809 schedule_delayed_work(&rdev->hotplug_work, 0); 810 if (rdev->msi_enabled) { 811 switch (rdev->family) { 812 case CHIP_RS400: 813 case CHIP_RS480: 814 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 815 WREG32(RADEON_AIC_CNTL, msi_rearm); 816 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 817 break; 818 default: 819 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 820 break; 821 } 822 } 823 return IRQ_HANDLED; 824} 825 826u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 827{ 828 if (crtc == 0) 829 return RREG32(RADEON_CRTC_CRNT_FRAME); 830 else 831 return RREG32(RADEON_CRTC2_CRNT_FRAME); 832} 833 834/** 835 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 836 * rdev: radeon device structure 837 * ring: ring buffer struct for emitting packets 838 */ 839static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 840{ 841 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 842 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 843 RADEON_HDP_READ_BUFFER_INVALIDATE); 844 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 845 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 846} 847 848/* Who ever call radeon_fence_emit should call ring_lock and ask 849 * for enough space (today caller are ib schedule and buffer move) */ 850void r100_fence_ring_emit(struct radeon_device *rdev, 851 struct radeon_fence *fence) 852{ 853 struct radeon_ring *ring = &rdev->ring[fence->ring]; 854 855 /* We have to make sure that caches are flushed before 856 * CPU might read something from VRAM. */ 857 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 858 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 859 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 860 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 861 /* Wait until IDLE & CLEAN */ 862 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 863 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 864 r100_ring_hdp_flush(rdev, ring); 865 /* Emit fence sequence & fire IRQ */ 866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 867 radeon_ring_write(ring, fence->seq); 868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 869 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 870} 871 872bool r100_semaphore_ring_emit(struct radeon_device *rdev, 873 struct radeon_ring *ring, 874 struct radeon_semaphore *semaphore, 875 bool emit_wait) 876{ 877 /* Unused on older asics, since we don't have semaphores or multiple rings */ 878 BUG(); 879 return false; 880} 881 882struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 883 uint64_t src_offset, 884 uint64_t dst_offset, 885 unsigned num_gpu_pages, 886 struct reservation_object *resv) 887{ 888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 889 struct radeon_fence *fence; 890 uint32_t cur_pages; 891 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 892 uint32_t pitch; 893 uint32_t stride_pixels; 894 unsigned ndw; 895 int num_loops; 896 int r = 0; 897 898 /* radeon limited to 16k stride */ 899 stride_bytes &= 0x3fff; 900 /* radeon pitch is /64 */ 901 pitch = stride_bytes / 64; 902 stride_pixels = stride_bytes / 4; 903 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 904 905 /* Ask for enough room for blit + flush + fence */ 906 ndw = 64 + (10 * num_loops); 907 r = radeon_ring_lock(rdev, ring, ndw); 908 if (r) { 909 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 910 return ERR_PTR(-EINVAL); 911 } 912 while (num_gpu_pages > 0) { 913 cur_pages = num_gpu_pages; 914 if (cur_pages > 8191) { 915 cur_pages = 8191; 916 } 917 num_gpu_pages -= cur_pages; 918 919 /* pages are in Y direction - height 920 page width in X direction - width */ 921 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 922 radeon_ring_write(ring, 923 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 924 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 925 RADEON_GMC_SRC_CLIPPING | 926 RADEON_GMC_DST_CLIPPING | 927 RADEON_GMC_BRUSH_NONE | 928 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 929 RADEON_GMC_SRC_DATATYPE_COLOR | 930 RADEON_ROP3_S | 931 RADEON_DP_SRC_SOURCE_MEMORY | 932 RADEON_GMC_CLR_CMP_CNTL_DIS | 933 RADEON_GMC_WR_MSK_DIS); 934 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 935 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 936 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 937 radeon_ring_write(ring, 0); 938 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 939 radeon_ring_write(ring, num_gpu_pages); 940 radeon_ring_write(ring, num_gpu_pages); 941 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 942 } 943 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 944 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 945 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 946 radeon_ring_write(ring, 947 RADEON_WAIT_2D_IDLECLEAN | 948 RADEON_WAIT_HOST_IDLECLEAN | 949 RADEON_WAIT_DMA_GUI_IDLE); 950 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 951 if (r) { 952 radeon_ring_unlock_undo(rdev, ring); 953 return ERR_PTR(r); 954 } 955 radeon_ring_unlock_commit(rdev, ring, false); 956 return fence; 957} 958 959static int r100_cp_wait_for_idle(struct radeon_device *rdev) 960{ 961 unsigned i; 962 u32 tmp; 963 964 for (i = 0; i < rdev->usec_timeout; i++) { 965 tmp = RREG32(R_000E40_RBBM_STATUS); 966 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 967 return 0; 968 } 969 udelay(1); 970 } 971 return -1; 972} 973 974void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 975{ 976 int r; 977 978 r = radeon_ring_lock(rdev, ring, 2); 979 if (r) { 980 return; 981 } 982 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 983 radeon_ring_write(ring, 984 RADEON_ISYNC_ANY2D_IDLE3D | 985 RADEON_ISYNC_ANY3D_IDLE2D | 986 RADEON_ISYNC_WAIT_IDLEGUI | 987 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 988 radeon_ring_unlock_commit(rdev, ring, false); 989} 990 991 992/* Load the microcode for the CP */ 993static int r100_cp_init_microcode(struct radeon_device *rdev) 994{ 995 const char *fw_name = NULL; 996 int err; 997 998 DRM_DEBUG_KMS("\n"); 999 1000 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1001 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1002 (rdev->family == CHIP_RS200)) { 1003 DRM_INFO("Loading R100 Microcode\n"); 1004 fw_name = FIRMWARE_R100; 1005 } else if ((rdev->family == CHIP_R200) || 1006 (rdev->family == CHIP_RV250) || 1007 (rdev->family == CHIP_RV280) || 1008 (rdev->family == CHIP_RS300)) { 1009 DRM_INFO("Loading R200 Microcode\n"); 1010 fw_name = FIRMWARE_R200; 1011 } else if ((rdev->family == CHIP_R300) || 1012 (rdev->family == CHIP_R350) || 1013 (rdev->family == CHIP_RV350) || 1014 (rdev->family == CHIP_RV380) || 1015 (rdev->family == CHIP_RS400) || 1016 (rdev->family == CHIP_RS480)) { 1017 DRM_INFO("Loading R300 Microcode\n"); 1018 fw_name = FIRMWARE_R300; 1019 } else if ((rdev->family == CHIP_R420) || 1020 (rdev->family == CHIP_R423) || 1021 (rdev->family == CHIP_RV410)) { 1022 DRM_INFO("Loading R400 Microcode\n"); 1023 fw_name = FIRMWARE_R420; 1024 } else if ((rdev->family == CHIP_RS690) || 1025 (rdev->family == CHIP_RS740)) { 1026 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1027 fw_name = FIRMWARE_RS690; 1028 } else if (rdev->family == CHIP_RS600) { 1029 DRM_INFO("Loading RS600 Microcode\n"); 1030 fw_name = FIRMWARE_RS600; 1031 } else if ((rdev->family == CHIP_RV515) || 1032 (rdev->family == CHIP_R520) || 1033 (rdev->family == CHIP_RV530) || 1034 (rdev->family == CHIP_R580) || 1035 (rdev->family == CHIP_RV560) || 1036 (rdev->family == CHIP_RV570)) { 1037 DRM_INFO("Loading R500 Microcode\n"); 1038 fw_name = FIRMWARE_R520; 1039 } 1040 1041 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1042 if (err) { 1043 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 1044 fw_name); 1045 } else if (rdev->me_fw->size % 8) { 1046 printk(KERN_ERR 1047 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1048 rdev->me_fw->size, fw_name); 1049 err = -EINVAL; 1050 release_firmware(rdev->me_fw); 1051 rdev->me_fw = NULL; 1052 } 1053 return err; 1054} 1055 1056u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1057 struct radeon_ring *ring) 1058{ 1059 u32 rptr; 1060 1061 if (rdev->wb.enabled) 1062 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1063 else 1064 rptr = RREG32(RADEON_CP_RB_RPTR); 1065 1066 return rptr; 1067} 1068 1069u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1070 struct radeon_ring *ring) 1071{ 1072 u32 wptr; 1073 1074 wptr = RREG32(RADEON_CP_RB_WPTR); 1075 1076 return wptr; 1077} 1078 1079void r100_gfx_set_wptr(struct radeon_device *rdev, 1080 struct radeon_ring *ring) 1081{ 1082 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1083 (void)RREG32(RADEON_CP_RB_WPTR); 1084} 1085 1086static void r100_cp_load_microcode(struct radeon_device *rdev) 1087{ 1088 const __be32 *fw_data; 1089 int i, size; 1090 1091 if (r100_gui_wait_for_idle(rdev)) { 1092 printk(KERN_WARNING "Failed to wait GUI idle while " 1093 "programming pipes. Bad things might happen.\n"); 1094 } 1095 1096 if (rdev->me_fw) { 1097 size = rdev->me_fw->size / 4; 1098 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1099 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1100 for (i = 0; i < size; i += 2) { 1101 WREG32(RADEON_CP_ME_RAM_DATAH, 1102 be32_to_cpup(&fw_data[i])); 1103 WREG32(RADEON_CP_ME_RAM_DATAL, 1104 be32_to_cpup(&fw_data[i + 1])); 1105 } 1106 } 1107} 1108 1109int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1110{ 1111 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1112 unsigned rb_bufsz; 1113 unsigned rb_blksz; 1114 unsigned max_fetch; 1115 unsigned pre_write_timer; 1116 unsigned pre_write_limit; 1117 unsigned indirect2_start; 1118 unsigned indirect1_start; 1119 uint32_t tmp; 1120 int r; 1121 1122 if (r100_debugfs_cp_init(rdev)) { 1123 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1124 } 1125 if (!rdev->me_fw) { 1126 r = r100_cp_init_microcode(rdev); 1127 if (r) { 1128 DRM_ERROR("Failed to load firmware!\n"); 1129 return r; 1130 } 1131 } 1132 1133 /* Align ring size */ 1134 rb_bufsz = order_base_2(ring_size / 8); 1135 ring_size = (1 << (rb_bufsz + 1)) * 4; 1136 r100_cp_load_microcode(rdev); 1137 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1138 RADEON_CP_PACKET2); 1139 if (r) { 1140 return r; 1141 } 1142 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1143 * the rptr copy in system ram */ 1144 rb_blksz = 9; 1145 /* cp will read 128bytes at a time (4 dwords) */ 1146 max_fetch = 1; 1147 ring->align_mask = 16 - 1; 1148 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1149 pre_write_timer = 64; 1150 /* Force CP_RB_WPTR write if written more than one time before the 1151 * delay expire 1152 */ 1153 pre_write_limit = 0; 1154 /* Setup the cp cache like this (cache size is 96 dwords) : 1155 * RING 0 to 15 1156 * INDIRECT1 16 to 79 1157 * INDIRECT2 80 to 95 1158 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1159 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1160 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1161 * Idea being that most of the gpu cmd will be through indirect1 buffer 1162 * so it gets the bigger cache. 1163 */ 1164 indirect2_start = 80; 1165 indirect1_start = 16; 1166 /* cp setup */ 1167 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1168 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1169 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1170 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1171#ifdef __BIG_ENDIAN 1172 tmp |= RADEON_BUF_SWAP_32BIT; 1173#endif 1174 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1175 1176 /* Set ring address */ 1177 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1178 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1179 /* Force read & write ptr to 0 */ 1180 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1181 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1182 ring->wptr = 0; 1183 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1184 1185 /* set the wb address whether it's enabled or not */ 1186 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1187 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1188 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1189 1190 if (rdev->wb.enabled) 1191 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1192 else { 1193 tmp |= RADEON_RB_NO_UPDATE; 1194 WREG32(R_000770_SCRATCH_UMSK, 0); 1195 } 1196 1197 WREG32(RADEON_CP_RB_CNTL, tmp); 1198 udelay(10); 1199 /* Set cp mode to bus mastering & enable cp*/ 1200 WREG32(RADEON_CP_CSQ_MODE, 1201 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1202 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1203 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1204 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1205 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1206 1207 /* at this point everything should be setup correctly to enable master */ 1208 pci_set_master(rdev->pdev); 1209 1210 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1211 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1212 if (r) { 1213 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1214 return r; 1215 } 1216 ring->ready = true; 1217 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1218 1219 if (!ring->rptr_save_reg /* not resuming from suspend */ 1220 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1221 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1222 if (r) { 1223 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1224 ring->rptr_save_reg = 0; 1225 } 1226 } 1227 return 0; 1228} 1229 1230void r100_cp_fini(struct radeon_device *rdev) 1231{ 1232 if (r100_cp_wait_for_idle(rdev)) { 1233 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1234 } 1235 /* Disable ring */ 1236 r100_cp_disable(rdev); 1237 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1238 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1239 DRM_INFO("radeon: cp finalized\n"); 1240} 1241 1242void r100_cp_disable(struct radeon_device *rdev) 1243{ 1244 /* Disable ring */ 1245 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1246 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1247 WREG32(RADEON_CP_CSQ_MODE, 0); 1248 WREG32(RADEON_CP_CSQ_CNTL, 0); 1249 WREG32(R_000770_SCRATCH_UMSK, 0); 1250 if (r100_gui_wait_for_idle(rdev)) { 1251 printk(KERN_WARNING "Failed to wait GUI idle while " 1252 "programming pipes. Bad things might happen.\n"); 1253 } 1254} 1255 1256/* 1257 * CS functions 1258 */ 1259int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1260 struct radeon_cs_packet *pkt, 1261 unsigned idx, 1262 unsigned reg) 1263{ 1264 int r; 1265 u32 tile_flags = 0; 1266 u32 tmp; 1267 struct radeon_bo_list *reloc; 1268 u32 value; 1269 1270 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1271 if (r) { 1272 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1273 idx, reg); 1274 radeon_cs_dump_packet(p, pkt); 1275 return r; 1276 } 1277 1278 value = radeon_get_ib_value(p, idx); 1279 tmp = value & 0x003fffff; 1280 tmp += (((u32)reloc->gpu_offset) >> 10); 1281 1282 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1284 tile_flags |= RADEON_DST_TILE_MACRO; 1285 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1286 if (reg == RADEON_SRC_PITCH_OFFSET) { 1287 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1288 radeon_cs_dump_packet(p, pkt); 1289 return -EINVAL; 1290 } 1291 tile_flags |= RADEON_DST_TILE_MICRO; 1292 } 1293 1294 tmp |= tile_flags; 1295 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1296 } else 1297 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1298 return 0; 1299} 1300 1301int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1302 struct radeon_cs_packet *pkt, 1303 int idx) 1304{ 1305 unsigned c, i; 1306 struct radeon_bo_list *reloc; 1307 struct r100_cs_track *track; 1308 int r = 0; 1309 volatile uint32_t *ib; 1310 u32 idx_value; 1311 1312 ib = p->ib.ptr; 1313 track = (struct r100_cs_track *)p->track; 1314 c = radeon_get_ib_value(p, idx++) & 0x1F; 1315 if (c > 16) { 1316 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1317 pkt->opcode); 1318 radeon_cs_dump_packet(p, pkt); 1319 return -EINVAL; 1320 } 1321 track->num_arrays = c; 1322 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1323 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1324 if (r) { 1325 DRM_ERROR("No reloc for packet3 %d\n", 1326 pkt->opcode); 1327 radeon_cs_dump_packet(p, pkt); 1328 return r; 1329 } 1330 idx_value = radeon_get_ib_value(p, idx); 1331 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1332 1333 track->arrays[i + 0].esize = idx_value >> 8; 1334 track->arrays[i + 0].robj = reloc->robj; 1335 track->arrays[i + 0].esize &= 0x7F; 1336 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1337 if (r) { 1338 DRM_ERROR("No reloc for packet3 %d\n", 1339 pkt->opcode); 1340 radeon_cs_dump_packet(p, pkt); 1341 return r; 1342 } 1343 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1344 track->arrays[i + 1].robj = reloc->robj; 1345 track->arrays[i + 1].esize = idx_value >> 24; 1346 track->arrays[i + 1].esize &= 0x7F; 1347 } 1348 if (c & 1) { 1349 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1350 if (r) { 1351 DRM_ERROR("No reloc for packet3 %d\n", 1352 pkt->opcode); 1353 radeon_cs_dump_packet(p, pkt); 1354 return r; 1355 } 1356 idx_value = radeon_get_ib_value(p, idx); 1357 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1358 track->arrays[i + 0].robj = reloc->robj; 1359 track->arrays[i + 0].esize = idx_value >> 8; 1360 track->arrays[i + 0].esize &= 0x7F; 1361 } 1362 return r; 1363} 1364 1365int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1366 struct radeon_cs_packet *pkt, 1367 const unsigned *auth, unsigned n, 1368 radeon_packet0_check_t check) 1369{ 1370 unsigned reg; 1371 unsigned i, j, m; 1372 unsigned idx; 1373 int r; 1374 1375 idx = pkt->idx + 1; 1376 reg = pkt->reg; 1377 /* Check that register fall into register range 1378 * determined by the number of entry (n) in the 1379 * safe register bitmap. 1380 */ 1381 if (pkt->one_reg_wr) { 1382 if ((reg >> 7) > n) { 1383 return -EINVAL; 1384 } 1385 } else { 1386 if (((reg + (pkt->count << 2)) >> 7) > n) { 1387 return -EINVAL; 1388 } 1389 } 1390 for (i = 0; i <= pkt->count; i++, idx++) { 1391 j = (reg >> 7); 1392 m = 1 << ((reg >> 2) & 31); 1393 if (auth[j] & m) { 1394 r = check(p, pkt, idx, reg); 1395 if (r) { 1396 return r; 1397 } 1398 } 1399 if (pkt->one_reg_wr) { 1400 if (!(auth[j] & m)) { 1401 break; 1402 } 1403 } else { 1404 reg += 4; 1405 } 1406 } 1407 return 0; 1408} 1409 1410/** 1411 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1412 * @parser: parser structure holding parsing context. 1413 * 1414 * Userspace sends a special sequence for VLINE waits. 1415 * PACKET0 - VLINE_START_END + value 1416 * PACKET0 - WAIT_UNTIL +_value 1417 * RELOC (P3) - crtc_id in reloc. 1418 * 1419 * This function parses this and relocates the VLINE START END 1420 * and WAIT UNTIL packets to the correct crtc. 1421 * It also detects a switched off crtc and nulls out the 1422 * wait in that case. 1423 */ 1424int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1425{ 1426 struct drm_crtc *crtc; 1427 struct radeon_crtc *radeon_crtc; 1428 struct radeon_cs_packet p3reloc, waitreloc; 1429 int crtc_id; 1430 int r; 1431 uint32_t header, h_idx, reg; 1432 volatile uint32_t *ib; 1433 1434 ib = p->ib.ptr; 1435 1436 /* parse the wait until */ 1437 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1438 if (r) 1439 return r; 1440 1441 /* check its a wait until and only 1 count */ 1442 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1443 waitreloc.count != 0) { 1444 DRM_ERROR("vline wait had illegal wait until segment\n"); 1445 return -EINVAL; 1446 } 1447 1448 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1449 DRM_ERROR("vline wait had illegal wait until\n"); 1450 return -EINVAL; 1451 } 1452 1453 /* jump over the NOP */ 1454 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1455 if (r) 1456 return r; 1457 1458 h_idx = p->idx - 2; 1459 p->idx += waitreloc.count + 2; 1460 p->idx += p3reloc.count + 2; 1461 1462 header = radeon_get_ib_value(p, h_idx); 1463 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1464 reg = R100_CP_PACKET0_GET_REG(header); 1465 crtc = drm_crtc_find(p->rdev->ddev, crtc_id); 1466 if (!crtc) { 1467 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1468 return -ENOENT; 1469 } 1470 radeon_crtc = to_radeon_crtc(crtc); 1471 crtc_id = radeon_crtc->crtc_id; 1472 1473 if (!crtc->enabled) { 1474 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1475 ib[h_idx + 2] = PACKET2(0); 1476 ib[h_idx + 3] = PACKET2(0); 1477 } else if (crtc_id == 1) { 1478 switch (reg) { 1479 case AVIVO_D1MODE_VLINE_START_END: 1480 header &= ~R300_CP_PACKET0_REG_MASK; 1481 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1482 break; 1483 case RADEON_CRTC_GUI_TRIG_VLINE: 1484 header &= ~R300_CP_PACKET0_REG_MASK; 1485 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1486 break; 1487 default: 1488 DRM_ERROR("unknown crtc reloc\n"); 1489 return -EINVAL; 1490 } 1491 ib[h_idx] = header; 1492 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1493 } 1494 1495 return 0; 1496} 1497 1498static int r100_get_vtx_size(uint32_t vtx_fmt) 1499{ 1500 int vtx_size; 1501 vtx_size = 2; 1502 /* ordered according to bits in spec */ 1503 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1504 vtx_size++; 1505 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1506 vtx_size += 3; 1507 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1508 vtx_size++; 1509 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1510 vtx_size++; 1511 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1512 vtx_size += 3; 1513 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1514 vtx_size++; 1515 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1516 vtx_size++; 1517 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1518 vtx_size += 2; 1519 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1520 vtx_size += 2; 1521 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1522 vtx_size++; 1523 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1524 vtx_size += 2; 1525 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1526 vtx_size++; 1527 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1528 vtx_size += 2; 1529 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1530 vtx_size++; 1531 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1532 vtx_size++; 1533 /* blend weight */ 1534 if (vtx_fmt & (0x7 << 15)) 1535 vtx_size += (vtx_fmt >> 15) & 0x7; 1536 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1537 vtx_size += 3; 1538 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1539 vtx_size += 2; 1540 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1541 vtx_size++; 1542 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1543 vtx_size++; 1544 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1545 vtx_size++; 1546 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1547 vtx_size++; 1548 return vtx_size; 1549} 1550 1551static int r100_packet0_check(struct radeon_cs_parser *p, 1552 struct radeon_cs_packet *pkt, 1553 unsigned idx, unsigned reg) 1554{ 1555 struct radeon_bo_list *reloc; 1556 struct r100_cs_track *track; 1557 volatile uint32_t *ib; 1558 uint32_t tmp; 1559 int r; 1560 int i, face; 1561 u32 tile_flags = 0; 1562 u32 idx_value; 1563 1564 ib = p->ib.ptr; 1565 track = (struct r100_cs_track *)p->track; 1566 1567 idx_value = radeon_get_ib_value(p, idx); 1568 1569 switch (reg) { 1570 case RADEON_CRTC_GUI_TRIG_VLINE: 1571 r = r100_cs_packet_parse_vline(p); 1572 if (r) { 1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1574 idx, reg); 1575 radeon_cs_dump_packet(p, pkt); 1576 return r; 1577 } 1578 break; 1579 /* FIXME: only allow PACKET3 blit? easier to check for out of 1580 * range access */ 1581 case RADEON_DST_PITCH_OFFSET: 1582 case RADEON_SRC_PITCH_OFFSET: 1583 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1584 if (r) 1585 return r; 1586 break; 1587 case RADEON_RB3D_DEPTHOFFSET: 1588 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1589 if (r) { 1590 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1591 idx, reg); 1592 radeon_cs_dump_packet(p, pkt); 1593 return r; 1594 } 1595 track->zb.robj = reloc->robj; 1596 track->zb.offset = idx_value; 1597 track->zb_dirty = true; 1598 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1599 break; 1600 case RADEON_RB3D_COLOROFFSET: 1601 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1602 if (r) { 1603 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1604 idx, reg); 1605 radeon_cs_dump_packet(p, pkt); 1606 return r; 1607 } 1608 track->cb[0].robj = reloc->robj; 1609 track->cb[0].offset = idx_value; 1610 track->cb_dirty = true; 1611 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1612 break; 1613 case RADEON_PP_TXOFFSET_0: 1614 case RADEON_PP_TXOFFSET_1: 1615 case RADEON_PP_TXOFFSET_2: 1616 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1617 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1618 if (r) { 1619 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1620 idx, reg); 1621 radeon_cs_dump_packet(p, pkt); 1622 return r; 1623 } 1624 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1626 tile_flags |= RADEON_TXO_MACRO_TILE; 1627 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1628 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1629 1630 tmp = idx_value & ~(0x7 << 2); 1631 tmp |= tile_flags; 1632 ib[idx] = tmp + ((u32)reloc->gpu_offset); 1633 } else 1634 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1635 track->textures[i].robj = reloc->robj; 1636 track->tex_dirty = true; 1637 break; 1638 case RADEON_PP_CUBIC_OFFSET_T0_0: 1639 case RADEON_PP_CUBIC_OFFSET_T0_1: 1640 case RADEON_PP_CUBIC_OFFSET_T0_2: 1641 case RADEON_PP_CUBIC_OFFSET_T0_3: 1642 case RADEON_PP_CUBIC_OFFSET_T0_4: 1643 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1644 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1645 if (r) { 1646 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1647 idx, reg); 1648 radeon_cs_dump_packet(p, pkt); 1649 return r; 1650 } 1651 track->textures[0].cube_info[i].offset = idx_value; 1652 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1653 track->textures[0].cube_info[i].robj = reloc->robj; 1654 track->tex_dirty = true; 1655 break; 1656 case RADEON_PP_CUBIC_OFFSET_T1_0: 1657 case RADEON_PP_CUBIC_OFFSET_T1_1: 1658 case RADEON_PP_CUBIC_OFFSET_T1_2: 1659 case RADEON_PP_CUBIC_OFFSET_T1_3: 1660 case RADEON_PP_CUBIC_OFFSET_T1_4: 1661 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1662 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1663 if (r) { 1664 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1665 idx, reg); 1666 radeon_cs_dump_packet(p, pkt); 1667 return r; 1668 } 1669 track->textures[1].cube_info[i].offset = idx_value; 1670 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1671 track->textures[1].cube_info[i].robj = reloc->robj; 1672 track->tex_dirty = true; 1673 break; 1674 case RADEON_PP_CUBIC_OFFSET_T2_0: 1675 case RADEON_PP_CUBIC_OFFSET_T2_1: 1676 case RADEON_PP_CUBIC_OFFSET_T2_2: 1677 case RADEON_PP_CUBIC_OFFSET_T2_3: 1678 case RADEON_PP_CUBIC_OFFSET_T2_4: 1679 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1680 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1681 if (r) { 1682 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1683 idx, reg); 1684 radeon_cs_dump_packet(p, pkt); 1685 return r; 1686 } 1687 track->textures[2].cube_info[i].offset = idx_value; 1688 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1689 track->textures[2].cube_info[i].robj = reloc->robj; 1690 track->tex_dirty = true; 1691 break; 1692 case RADEON_RE_WIDTH_HEIGHT: 1693 track->maxy = ((idx_value >> 16) & 0x7FF); 1694 track->cb_dirty = true; 1695 track->zb_dirty = true; 1696 break; 1697 case RADEON_RB3D_COLORPITCH: 1698 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1699 if (r) { 1700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1701 idx, reg); 1702 radeon_cs_dump_packet(p, pkt); 1703 return r; 1704 } 1705 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1707 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1708 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1709 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1710 1711 tmp = idx_value & ~(0x7 << 16); 1712 tmp |= tile_flags; 1713 ib[idx] = tmp; 1714 } else 1715 ib[idx] = idx_value; 1716 1717 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1718 track->cb_dirty = true; 1719 break; 1720 case RADEON_RB3D_DEPTHPITCH: 1721 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1722 track->zb_dirty = true; 1723 break; 1724 case RADEON_RB3D_CNTL: 1725 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1726 case 7: 1727 case 8: 1728 case 9: 1729 case 11: 1730 case 12: 1731 track->cb[0].cpp = 1; 1732 break; 1733 case 3: 1734 case 4: 1735 case 15: 1736 track->cb[0].cpp = 2; 1737 break; 1738 case 6: 1739 track->cb[0].cpp = 4; 1740 break; 1741 default: 1742 DRM_ERROR("Invalid color buffer format (%d) !\n", 1743 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1744 return -EINVAL; 1745 } 1746 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1747 track->cb_dirty = true; 1748 track->zb_dirty = true; 1749 break; 1750 case RADEON_RB3D_ZSTENCILCNTL: 1751 switch (idx_value & 0xf) { 1752 case 0: 1753 track->zb.cpp = 2; 1754 break; 1755 case 2: 1756 case 3: 1757 case 4: 1758 case 5: 1759 case 9: 1760 case 11: 1761 track->zb.cpp = 4; 1762 break; 1763 default: 1764 break; 1765 } 1766 track->zb_dirty = true; 1767 break; 1768 case RADEON_RB3D_ZPASS_ADDR: 1769 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1770 if (r) { 1771 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1772 idx, reg); 1773 radeon_cs_dump_packet(p, pkt); 1774 return r; 1775 } 1776 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1777 break; 1778 case RADEON_PP_CNTL: 1779 { 1780 uint32_t temp = idx_value >> 4; 1781 for (i = 0; i < track->num_texture; i++) 1782 track->textures[i].enabled = !!(temp & (1 << i)); 1783 track->tex_dirty = true; 1784 } 1785 break; 1786 case RADEON_SE_VF_CNTL: 1787 track->vap_vf_cntl = idx_value; 1788 break; 1789 case RADEON_SE_VTX_FMT: 1790 track->vtx_size = r100_get_vtx_size(idx_value); 1791 break; 1792 case RADEON_PP_TEX_SIZE_0: 1793 case RADEON_PP_TEX_SIZE_1: 1794 case RADEON_PP_TEX_SIZE_2: 1795 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1796 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1797 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1798 track->tex_dirty = true; 1799 break; 1800 case RADEON_PP_TEX_PITCH_0: 1801 case RADEON_PP_TEX_PITCH_1: 1802 case RADEON_PP_TEX_PITCH_2: 1803 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1804 track->textures[i].pitch = idx_value + 32; 1805 track->tex_dirty = true; 1806 break; 1807 case RADEON_PP_TXFILTER_0: 1808 case RADEON_PP_TXFILTER_1: 1809 case RADEON_PP_TXFILTER_2: 1810 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1812 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1813 tmp = (idx_value >> 23) & 0x7; 1814 if (tmp == 2 || tmp == 6) 1815 track->textures[i].roundup_w = false; 1816 tmp = (idx_value >> 27) & 0x7; 1817 if (tmp == 2 || tmp == 6) 1818 track->textures[i].roundup_h = false; 1819 track->tex_dirty = true; 1820 break; 1821 case RADEON_PP_TXFORMAT_0: 1822 case RADEON_PP_TXFORMAT_1: 1823 case RADEON_PP_TXFORMAT_2: 1824 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1825 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1826 track->textures[i].use_pitch = 1; 1827 } else { 1828 track->textures[i].use_pitch = 0; 1829 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1830 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1831 } 1832 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1833 track->textures[i].tex_coord_type = 2; 1834 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1835 case RADEON_TXFORMAT_I8: 1836 case RADEON_TXFORMAT_RGB332: 1837 case RADEON_TXFORMAT_Y8: 1838 track->textures[i].cpp = 1; 1839 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1840 break; 1841 case RADEON_TXFORMAT_AI88: 1842 case RADEON_TXFORMAT_ARGB1555: 1843 case RADEON_TXFORMAT_RGB565: 1844 case RADEON_TXFORMAT_ARGB4444: 1845 case RADEON_TXFORMAT_VYUY422: 1846 case RADEON_TXFORMAT_YVYU422: 1847 case RADEON_TXFORMAT_SHADOW16: 1848 case RADEON_TXFORMAT_LDUDV655: 1849 case RADEON_TXFORMAT_DUDV88: 1850 track->textures[i].cpp = 2; 1851 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1852 break; 1853 case RADEON_TXFORMAT_ARGB8888: 1854 case RADEON_TXFORMAT_RGBA8888: 1855 case RADEON_TXFORMAT_SHADOW32: 1856 case RADEON_TXFORMAT_LDUDUV8888: 1857 track->textures[i].cpp = 4; 1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1859 break; 1860 case RADEON_TXFORMAT_DXT1: 1861 track->textures[i].cpp = 1; 1862 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1863 break; 1864 case RADEON_TXFORMAT_DXT23: 1865 case RADEON_TXFORMAT_DXT45: 1866 track->textures[i].cpp = 1; 1867 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1868 break; 1869 } 1870 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1871 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1872 track->tex_dirty = true; 1873 break; 1874 case RADEON_PP_CUBIC_FACES_0: 1875 case RADEON_PP_CUBIC_FACES_1: 1876 case RADEON_PP_CUBIC_FACES_2: 1877 tmp = idx_value; 1878 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1879 for (face = 0; face < 4; face++) { 1880 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1881 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1882 } 1883 track->tex_dirty = true; 1884 break; 1885 default: 1886 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1887 reg, idx); 1888 return -EINVAL; 1889 } 1890 return 0; 1891} 1892 1893int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1894 struct radeon_cs_packet *pkt, 1895 struct radeon_bo *robj) 1896{ 1897 unsigned idx; 1898 u32 value; 1899 idx = pkt->idx + 1; 1900 value = radeon_get_ib_value(p, idx + 2); 1901 if ((value + 1) > radeon_bo_size(robj)) { 1902 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1903 "(need %u have %lu) !\n", 1904 value + 1, 1905 radeon_bo_size(robj)); 1906 return -EINVAL; 1907 } 1908 return 0; 1909} 1910 1911static int r100_packet3_check(struct radeon_cs_parser *p, 1912 struct radeon_cs_packet *pkt) 1913{ 1914 struct radeon_bo_list *reloc; 1915 struct r100_cs_track *track; 1916 unsigned idx; 1917 volatile uint32_t *ib; 1918 int r; 1919 1920 ib = p->ib.ptr; 1921 idx = pkt->idx + 1; 1922 track = (struct r100_cs_track *)p->track; 1923 switch (pkt->opcode) { 1924 case PACKET3_3D_LOAD_VBPNTR: 1925 r = r100_packet3_load_vbpntr(p, pkt, idx); 1926 if (r) 1927 return r; 1928 break; 1929 case PACKET3_INDX_BUFFER: 1930 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1931 if (r) { 1932 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1933 radeon_cs_dump_packet(p, pkt); 1934 return r; 1935 } 1936 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1937 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1938 if (r) { 1939 return r; 1940 } 1941 break; 1942 case 0x23: 1943 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1944 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1945 if (r) { 1946 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1947 radeon_cs_dump_packet(p, pkt); 1948 return r; 1949 } 1950 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1951 track->num_arrays = 1; 1952 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1953 1954 track->arrays[0].robj = reloc->robj; 1955 track->arrays[0].esize = track->vtx_size; 1956 1957 track->max_indx = radeon_get_ib_value(p, idx+1); 1958 1959 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1960 track->immd_dwords = pkt->count - 1; 1961 r = r100_cs_track_check(p->rdev, track); 1962 if (r) 1963 return r; 1964 break; 1965 case PACKET3_3D_DRAW_IMMD: 1966 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1967 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1968 return -EINVAL; 1969 } 1970 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1972 track->immd_dwords = pkt->count - 1; 1973 r = r100_cs_track_check(p->rdev, track); 1974 if (r) 1975 return r; 1976 break; 1977 /* triggers drawing using in-packet vertex data */ 1978 case PACKET3_3D_DRAW_IMMD_2: 1979 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1980 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1981 return -EINVAL; 1982 } 1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1984 track->immd_dwords = pkt->count; 1985 r = r100_cs_track_check(p->rdev, track); 1986 if (r) 1987 return r; 1988 break; 1989 /* triggers drawing using in-packet vertex data */ 1990 case PACKET3_3D_DRAW_VBUF_2: 1991 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1992 r = r100_cs_track_check(p->rdev, track); 1993 if (r) 1994 return r; 1995 break; 1996 /* triggers drawing of vertex buffers setup elsewhere */ 1997 case PACKET3_3D_DRAW_INDX_2: 1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1999 r = r100_cs_track_check(p->rdev, track); 2000 if (r) 2001 return r; 2002 break; 2003 /* triggers drawing using indices to vertex buffer */ 2004 case PACKET3_3D_DRAW_VBUF: 2005 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2006 r = r100_cs_track_check(p->rdev, track); 2007 if (r) 2008 return r; 2009 break; 2010 /* triggers drawing of vertex buffers setup elsewhere */ 2011 case PACKET3_3D_DRAW_INDX: 2012 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2013 r = r100_cs_track_check(p->rdev, track); 2014 if (r) 2015 return r; 2016 break; 2017 /* triggers drawing using indices to vertex buffer */ 2018 case PACKET3_3D_CLEAR_HIZ: 2019 case PACKET3_3D_CLEAR_ZMASK: 2020 if (p->rdev->hyperz_filp != p->filp) 2021 return -EINVAL; 2022 break; 2023 case PACKET3_NOP: 2024 break; 2025 default: 2026 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2027 return -EINVAL; 2028 } 2029 return 0; 2030} 2031 2032int r100_cs_parse(struct radeon_cs_parser *p) 2033{ 2034 struct radeon_cs_packet pkt; 2035 struct r100_cs_track *track; 2036 int r; 2037 2038 track = kzalloc(sizeof(*track), GFP_KERNEL); 2039 if (!track) 2040 return -ENOMEM; 2041 r100_cs_track_clear(p->rdev, track); 2042 p->track = track; 2043 do { 2044 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2045 if (r) { 2046 return r; 2047 } 2048 p->idx += pkt.count + 2; 2049 switch (pkt.type) { 2050 case RADEON_PACKET_TYPE0: 2051 if (p->rdev->family >= CHIP_R200) 2052 r = r100_cs_parse_packet0(p, &pkt, 2053 p->rdev->config.r100.reg_safe_bm, 2054 p->rdev->config.r100.reg_safe_bm_size, 2055 &r200_packet0_check); 2056 else 2057 r = r100_cs_parse_packet0(p, &pkt, 2058 p->rdev->config.r100.reg_safe_bm, 2059 p->rdev->config.r100.reg_safe_bm_size, 2060 &r100_packet0_check); 2061 break; 2062 case RADEON_PACKET_TYPE2: 2063 break; 2064 case RADEON_PACKET_TYPE3: 2065 r = r100_packet3_check(p, &pkt); 2066 break; 2067 default: 2068 DRM_ERROR("Unknown packet type %d !\n", 2069 pkt.type); 2070 return -EINVAL; 2071 } 2072 if (r) 2073 return r; 2074 } while (p->idx < p->chunk_ib->length_dw); 2075 return 0; 2076} 2077 2078static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2079{ 2080 DRM_ERROR("pitch %d\n", t->pitch); 2081 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2082 DRM_ERROR("width %d\n", t->width); 2083 DRM_ERROR("width_11 %d\n", t->width_11); 2084 DRM_ERROR("height %d\n", t->height); 2085 DRM_ERROR("height_11 %d\n", t->height_11); 2086 DRM_ERROR("num levels %d\n", t->num_levels); 2087 DRM_ERROR("depth %d\n", t->txdepth); 2088 DRM_ERROR("bpp %d\n", t->cpp); 2089 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2090 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2091 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2092 DRM_ERROR("compress format %d\n", t->compress_format); 2093} 2094 2095static int r100_track_compress_size(int compress_format, int w, int h) 2096{ 2097 int block_width, block_height, block_bytes; 2098 int wblocks, hblocks; 2099 int min_wblocks; 2100 int sz; 2101 2102 block_width = 4; 2103 block_height = 4; 2104 2105 switch (compress_format) { 2106 case R100_TRACK_COMP_DXT1: 2107 block_bytes = 8; 2108 min_wblocks = 4; 2109 break; 2110 default: 2111 case R100_TRACK_COMP_DXT35: 2112 block_bytes = 16; 2113 min_wblocks = 2; 2114 break; 2115 } 2116 2117 hblocks = (h + block_height - 1) / block_height; 2118 wblocks = (w + block_width - 1) / block_width; 2119 if (wblocks < min_wblocks) 2120 wblocks = min_wblocks; 2121 sz = wblocks * hblocks * block_bytes; 2122 return sz; 2123} 2124 2125static int r100_cs_track_cube(struct radeon_device *rdev, 2126 struct r100_cs_track *track, unsigned idx) 2127{ 2128 unsigned face, w, h; 2129 struct radeon_bo *cube_robj; 2130 unsigned long size; 2131 unsigned compress_format = track->textures[idx].compress_format; 2132 2133 for (face = 0; face < 5; face++) { 2134 cube_robj = track->textures[idx].cube_info[face].robj; 2135 w = track->textures[idx].cube_info[face].width; 2136 h = track->textures[idx].cube_info[face].height; 2137 2138 if (compress_format) { 2139 size = r100_track_compress_size(compress_format, w, h); 2140 } else 2141 size = w * h; 2142 size *= track->textures[idx].cpp; 2143 2144 size += track->textures[idx].cube_info[face].offset; 2145 2146 if (size > radeon_bo_size(cube_robj)) { 2147 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2148 size, radeon_bo_size(cube_robj)); 2149 r100_cs_track_texture_print(&track->textures[idx]); 2150 return -1; 2151 } 2152 } 2153 return 0; 2154} 2155 2156static int r100_cs_track_texture_check(struct radeon_device *rdev, 2157 struct r100_cs_track *track) 2158{ 2159 struct radeon_bo *robj; 2160 unsigned long size; 2161 unsigned u, i, w, h, d; 2162 int ret; 2163 2164 for (u = 0; u < track->num_texture; u++) { 2165 if (!track->textures[u].enabled) 2166 continue; 2167 if (track->textures[u].lookup_disable) 2168 continue; 2169 robj = track->textures[u].robj; 2170 if (robj == NULL) { 2171 DRM_ERROR("No texture bound to unit %u\n", u); 2172 return -EINVAL; 2173 } 2174 size = 0; 2175 for (i = 0; i <= track->textures[u].num_levels; i++) { 2176 if (track->textures[u].use_pitch) { 2177 if (rdev->family < CHIP_R300) 2178 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2179 else 2180 w = track->textures[u].pitch / (1 << i); 2181 } else { 2182 w = track->textures[u].width; 2183 if (rdev->family >= CHIP_RV515) 2184 w |= track->textures[u].width_11; 2185 w = w / (1 << i); 2186 if (track->textures[u].roundup_w) 2187 w = roundup_pow_of_two(w); 2188 } 2189 h = track->textures[u].height; 2190 if (rdev->family >= CHIP_RV515) 2191 h |= track->textures[u].height_11; 2192 h = h / (1 << i); 2193 if (track->textures[u].roundup_h) 2194 h = roundup_pow_of_two(h); 2195 if (track->textures[u].tex_coord_type == 1) { 2196 d = (1 << track->textures[u].txdepth) / (1 << i); 2197 if (!d) 2198 d = 1; 2199 } else { 2200 d = 1; 2201 } 2202 if (track->textures[u].compress_format) { 2203 2204 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2205 /* compressed textures are block based */ 2206 } else 2207 size += w * h * d; 2208 } 2209 size *= track->textures[u].cpp; 2210 2211 switch (track->textures[u].tex_coord_type) { 2212 case 0: 2213 case 1: 2214 break; 2215 case 2: 2216 if (track->separate_cube) { 2217 ret = r100_cs_track_cube(rdev, track, u); 2218 if (ret) 2219 return ret; 2220 } else 2221 size *= 6; 2222 break; 2223 default: 2224 DRM_ERROR("Invalid texture coordinate type %u for unit " 2225 "%u\n", track->textures[u].tex_coord_type, u); 2226 return -EINVAL; 2227 } 2228 if (size > radeon_bo_size(robj)) { 2229 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2230 "%lu\n", u, size, radeon_bo_size(robj)); 2231 r100_cs_track_texture_print(&track->textures[u]); 2232 return -EINVAL; 2233 } 2234 } 2235 return 0; 2236} 2237 2238int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2239{ 2240 unsigned i; 2241 unsigned long size; 2242 unsigned prim_walk; 2243 unsigned nverts; 2244 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2245 2246 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2247 !track->blend_read_enable) 2248 num_cb = 0; 2249 2250 for (i = 0; i < num_cb; i++) { 2251 if (track->cb[i].robj == NULL) { 2252 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2253 return -EINVAL; 2254 } 2255 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2256 size += track->cb[i].offset; 2257 if (size > radeon_bo_size(track->cb[i].robj)) { 2258 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2259 "(need %lu have %lu) !\n", i, size, 2260 radeon_bo_size(track->cb[i].robj)); 2261 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2262 i, track->cb[i].pitch, track->cb[i].cpp, 2263 track->cb[i].offset, track->maxy); 2264 return -EINVAL; 2265 } 2266 } 2267 track->cb_dirty = false; 2268 2269 if (track->zb_dirty && track->z_enabled) { 2270 if (track->zb.robj == NULL) { 2271 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2272 return -EINVAL; 2273 } 2274 size = track->zb.pitch * track->zb.cpp * track->maxy; 2275 size += track->zb.offset; 2276 if (size > radeon_bo_size(track->zb.robj)) { 2277 DRM_ERROR("[drm] Buffer too small for z buffer " 2278 "(need %lu have %lu) !\n", size, 2279 radeon_bo_size(track->zb.robj)); 2280 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2281 track->zb.pitch, track->zb.cpp, 2282 track->zb.offset, track->maxy); 2283 return -EINVAL; 2284 } 2285 } 2286 track->zb_dirty = false; 2287 2288 if (track->aa_dirty && track->aaresolve) { 2289 if (track->aa.robj == NULL) { 2290 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2291 return -EINVAL; 2292 } 2293 /* I believe the format comes from colorbuffer0. */ 2294 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2295 size += track->aa.offset; 2296 if (size > radeon_bo_size(track->aa.robj)) { 2297 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2298 "(need %lu have %lu) !\n", i, size, 2299 radeon_bo_size(track->aa.robj)); 2300 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2301 i, track->aa.pitch, track->cb[0].cpp, 2302 track->aa.offset, track->maxy); 2303 return -EINVAL; 2304 } 2305 } 2306 track->aa_dirty = false; 2307 2308 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2309 if (track->vap_vf_cntl & (1 << 14)) { 2310 nverts = track->vap_alt_nverts; 2311 } else { 2312 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2313 } 2314 switch (prim_walk) { 2315 case 1: 2316 for (i = 0; i < track->num_arrays; i++) { 2317 size = track->arrays[i].esize * track->max_indx * 4; 2318 if (track->arrays[i].robj == NULL) { 2319 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2320 "bound\n", prim_walk, i); 2321 return -EINVAL; 2322 } 2323 if (size > radeon_bo_size(track->arrays[i].robj)) { 2324 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2325 "need %lu dwords have %lu dwords\n", 2326 prim_walk, i, size >> 2, 2327 radeon_bo_size(track->arrays[i].robj) 2328 >> 2); 2329 DRM_ERROR("Max indices %u\n", track->max_indx); 2330 return -EINVAL; 2331 } 2332 } 2333 break; 2334 case 2: 2335 for (i = 0; i < track->num_arrays; i++) { 2336 size = track->arrays[i].esize * (nverts - 1) * 4; 2337 if (track->arrays[i].robj == NULL) { 2338 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2339 "bound\n", prim_walk, i); 2340 return -EINVAL; 2341 } 2342 if (size > radeon_bo_size(track->arrays[i].robj)) { 2343 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2344 "need %lu dwords have %lu dwords\n", 2345 prim_walk, i, size >> 2, 2346 radeon_bo_size(track->arrays[i].robj) 2347 >> 2); 2348 return -EINVAL; 2349 } 2350 } 2351 break; 2352 case 3: 2353 size = track->vtx_size * nverts; 2354 if (size != track->immd_dwords) { 2355 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2356 track->immd_dwords, size); 2357 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2358 nverts, track->vtx_size); 2359 return -EINVAL; 2360 } 2361 break; 2362 default: 2363 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2364 prim_walk); 2365 return -EINVAL; 2366 } 2367 2368 if (track->tex_dirty) { 2369 track->tex_dirty = false; 2370 return r100_cs_track_texture_check(rdev, track); 2371 } 2372 return 0; 2373} 2374 2375void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2376{ 2377 unsigned i, face; 2378 2379 track->cb_dirty = true; 2380 track->zb_dirty = true; 2381 track->tex_dirty = true; 2382 track->aa_dirty = true; 2383 2384 if (rdev->family < CHIP_R300) { 2385 track->num_cb = 1; 2386 if (rdev->family <= CHIP_RS200) 2387 track->num_texture = 3; 2388 else 2389 track->num_texture = 6; 2390 track->maxy = 2048; 2391 track->separate_cube = 1; 2392 } else { 2393 track->num_cb = 4; 2394 track->num_texture = 16; 2395 track->maxy = 4096; 2396 track->separate_cube = 0; 2397 track->aaresolve = false; 2398 track->aa.robj = NULL; 2399 } 2400 2401 for (i = 0; i < track->num_cb; i++) { 2402 track->cb[i].robj = NULL; 2403 track->cb[i].pitch = 8192; 2404 track->cb[i].cpp = 16; 2405 track->cb[i].offset = 0; 2406 } 2407 track->z_enabled = true; 2408 track->zb.robj = NULL; 2409 track->zb.pitch = 8192; 2410 track->zb.cpp = 4; 2411 track->zb.offset = 0; 2412 track->vtx_size = 0x7F; 2413 track->immd_dwords = 0xFFFFFFFFUL; 2414 track->num_arrays = 11; 2415 track->max_indx = 0x00FFFFFFUL; 2416 for (i = 0; i < track->num_arrays; i++) { 2417 track->arrays[i].robj = NULL; 2418 track->arrays[i].esize = 0x7F; 2419 } 2420 for (i = 0; i < track->num_texture; i++) { 2421 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2422 track->textures[i].pitch = 16536; 2423 track->textures[i].width = 16536; 2424 track->textures[i].height = 16536; 2425 track->textures[i].width_11 = 1 << 11; 2426 track->textures[i].height_11 = 1 << 11; 2427 track->textures[i].num_levels = 12; 2428 if (rdev->family <= CHIP_RS200) { 2429 track->textures[i].tex_coord_type = 0; 2430 track->textures[i].txdepth = 0; 2431 } else { 2432 track->textures[i].txdepth = 16; 2433 track->textures[i].tex_coord_type = 1; 2434 } 2435 track->textures[i].cpp = 64; 2436 track->textures[i].robj = NULL; 2437 /* CS IB emission code makes sure texture unit are disabled */ 2438 track->textures[i].enabled = false; 2439 track->textures[i].lookup_disable = false; 2440 track->textures[i].roundup_w = true; 2441 track->textures[i].roundup_h = true; 2442 if (track->separate_cube) 2443 for (face = 0; face < 5; face++) { 2444 track->textures[i].cube_info[face].robj = NULL; 2445 track->textures[i].cube_info[face].width = 16536; 2446 track->textures[i].cube_info[face].height = 16536; 2447 track->textures[i].cube_info[face].offset = 0; 2448 } 2449 } 2450} 2451 2452/* 2453 * Global GPU functions 2454 */ 2455static void r100_errata(struct radeon_device *rdev) 2456{ 2457 rdev->pll_errata = 0; 2458 2459 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2460 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2461 } 2462 2463 if (rdev->family == CHIP_RV100 || 2464 rdev->family == CHIP_RS100 || 2465 rdev->family == CHIP_RS200) { 2466 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2467 } 2468} 2469 2470static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2471{ 2472 unsigned i; 2473 uint32_t tmp; 2474 2475 for (i = 0; i < rdev->usec_timeout; i++) { 2476 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2477 if (tmp >= n) { 2478 return 0; 2479 } 2480 DRM_UDELAY(1); 2481 } 2482 return -1; 2483} 2484 2485int r100_gui_wait_for_idle(struct radeon_device *rdev) 2486{ 2487 unsigned i; 2488 uint32_t tmp; 2489 2490 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2491 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2492 " Bad things might happen.\n"); 2493 } 2494 for (i = 0; i < rdev->usec_timeout; i++) { 2495 tmp = RREG32(RADEON_RBBM_STATUS); 2496 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2497 return 0; 2498 } 2499 DRM_UDELAY(1); 2500 } 2501 return -1; 2502} 2503 2504int r100_mc_wait_for_idle(struct radeon_device *rdev) 2505{ 2506 unsigned i; 2507 uint32_t tmp; 2508 2509 for (i = 0; i < rdev->usec_timeout; i++) { 2510 /* read MC_STATUS */ 2511 tmp = RREG32(RADEON_MC_STATUS); 2512 if (tmp & RADEON_MC_IDLE) { 2513 return 0; 2514 } 2515 DRM_UDELAY(1); 2516 } 2517 return -1; 2518} 2519 2520bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2521{ 2522 u32 rbbm_status; 2523 2524 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2525 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2526 radeon_ring_lockup_update(rdev, ring); 2527 return false; 2528 } 2529 return radeon_ring_test_lockup(rdev, ring); 2530} 2531 2532/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2533void r100_enable_bm(struct radeon_device *rdev) 2534{ 2535 uint32_t tmp; 2536 /* Enable bus mastering */ 2537 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2538 WREG32(RADEON_BUS_CNTL, tmp); 2539} 2540 2541void r100_bm_disable(struct radeon_device *rdev) 2542{ 2543 u32 tmp; 2544 2545 /* disable bus mastering */ 2546 tmp = RREG32(R_000030_BUS_CNTL); 2547 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2548 mdelay(1); 2549 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2550 mdelay(1); 2551 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2552 tmp = RREG32(RADEON_BUS_CNTL); 2553 mdelay(1); 2554 pci_clear_master(rdev->pdev); 2555 mdelay(1); 2556} 2557 2558int r100_asic_reset(struct radeon_device *rdev) 2559{ 2560 struct r100_mc_save save; 2561 u32 status, tmp; 2562 int ret = 0; 2563 2564 status = RREG32(R_000E40_RBBM_STATUS); 2565 if (!G_000E40_GUI_ACTIVE(status)) { 2566 return 0; 2567 } 2568 r100_mc_stop(rdev, &save); 2569 status = RREG32(R_000E40_RBBM_STATUS); 2570 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2571 /* stop CP */ 2572 WREG32(RADEON_CP_CSQ_CNTL, 0); 2573 tmp = RREG32(RADEON_CP_RB_CNTL); 2574 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2575 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2576 WREG32(RADEON_CP_RB_WPTR, 0); 2577 WREG32(RADEON_CP_RB_CNTL, tmp); 2578 /* save PCI state */ 2579 pci_save_state(rdev->pdev); 2580 /* disable bus mastering */ 2581 r100_bm_disable(rdev); 2582 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2583 S_0000F0_SOFT_RESET_RE(1) | 2584 S_0000F0_SOFT_RESET_PP(1) | 2585 S_0000F0_SOFT_RESET_RB(1)); 2586 RREG32(R_0000F0_RBBM_SOFT_RESET); 2587 mdelay(500); 2588 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2589 mdelay(1); 2590 status = RREG32(R_000E40_RBBM_STATUS); 2591 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2592 /* reset CP */ 2593 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2594 RREG32(R_0000F0_RBBM_SOFT_RESET); 2595 mdelay(500); 2596 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2597 mdelay(1); 2598 status = RREG32(R_000E40_RBBM_STATUS); 2599 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2600 /* restore PCI & busmastering */ 2601 pci_restore_state(rdev->pdev); 2602 r100_enable_bm(rdev); 2603 /* Check if GPU is idle */ 2604 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2605 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2606 dev_err(rdev->dev, "failed to reset GPU\n"); 2607 ret = -1; 2608 } else 2609 dev_info(rdev->dev, "GPU reset succeed\n"); 2610 r100_mc_resume(rdev, &save); 2611 return ret; 2612} 2613 2614void r100_set_common_regs(struct radeon_device *rdev) 2615{ 2616 struct drm_device *dev = rdev->ddev; 2617 bool force_dac2 = false; 2618 u32 tmp; 2619 2620 /* set these so they don't interfere with anything */ 2621 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2622 WREG32(RADEON_SUBPIC_CNTL, 0); 2623 WREG32(RADEON_VIPH_CONTROL, 0); 2624 WREG32(RADEON_I2C_CNTL_1, 0); 2625 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2626 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2627 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2628 2629 /* always set up dac2 on rn50 and some rv100 as lots 2630 * of servers seem to wire it up to a VGA port but 2631 * don't report it in the bios connector 2632 * table. 2633 */ 2634 switch (dev->pdev->device) { 2635 /* RN50 */ 2636 case 0x515e: 2637 case 0x5969: 2638 force_dac2 = true; 2639 break; 2640 /* RV100*/ 2641 case 0x5159: 2642 case 0x515a: 2643 /* DELL triple head servers */ 2644 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2645 ((dev->pdev->subsystem_device == 0x016c) || 2646 (dev->pdev->subsystem_device == 0x016d) || 2647 (dev->pdev->subsystem_device == 0x016e) || 2648 (dev->pdev->subsystem_device == 0x016f) || 2649 (dev->pdev->subsystem_device == 0x0170) || 2650 (dev->pdev->subsystem_device == 0x017d) || 2651 (dev->pdev->subsystem_device == 0x017e) || 2652 (dev->pdev->subsystem_device == 0x0183) || 2653 (dev->pdev->subsystem_device == 0x018a) || 2654 (dev->pdev->subsystem_device == 0x019a))) 2655 force_dac2 = true; 2656 break; 2657 } 2658 2659 if (force_dac2) { 2660 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2661 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2662 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2663 2664 /* For CRT on DAC2, don't turn it on if BIOS didn't 2665 enable it, even it's detected. 2666 */ 2667 2668 /* force it to crtc0 */ 2669 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2670 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2671 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2672 2673 /* set up the TV DAC */ 2674 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2675 RADEON_TV_DAC_STD_MASK | 2676 RADEON_TV_DAC_RDACPD | 2677 RADEON_TV_DAC_GDACPD | 2678 RADEON_TV_DAC_BDACPD | 2679 RADEON_TV_DAC_BGADJ_MASK | 2680 RADEON_TV_DAC_DACADJ_MASK); 2681 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2682 RADEON_TV_DAC_NHOLD | 2683 RADEON_TV_DAC_STD_PS2 | 2684 (0x58 << 16)); 2685 2686 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2687 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2688 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2689 } 2690 2691 /* switch PM block to ACPI mode */ 2692 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2693 tmp &= ~RADEON_PM_MODE_SEL; 2694 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2695 2696} 2697 2698/* 2699 * VRAM info 2700 */ 2701static void r100_vram_get_type(struct radeon_device *rdev) 2702{ 2703 uint32_t tmp; 2704 2705 rdev->mc.vram_is_ddr = false; 2706 if (rdev->flags & RADEON_IS_IGP) 2707 rdev->mc.vram_is_ddr = true; 2708 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2709 rdev->mc.vram_is_ddr = true; 2710 if ((rdev->family == CHIP_RV100) || 2711 (rdev->family == CHIP_RS100) || 2712 (rdev->family == CHIP_RS200)) { 2713 tmp = RREG32(RADEON_MEM_CNTL); 2714 if (tmp & RV100_HALF_MODE) { 2715 rdev->mc.vram_width = 32; 2716 } else { 2717 rdev->mc.vram_width = 64; 2718 } 2719 if (rdev->flags & RADEON_SINGLE_CRTC) { 2720 rdev->mc.vram_width /= 4; 2721 rdev->mc.vram_is_ddr = true; 2722 } 2723 } else if (rdev->family <= CHIP_RV280) { 2724 tmp = RREG32(RADEON_MEM_CNTL); 2725 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2726 rdev->mc.vram_width = 128; 2727 } else { 2728 rdev->mc.vram_width = 64; 2729 } 2730 } else { 2731 /* newer IGPs */ 2732 rdev->mc.vram_width = 128; 2733 } 2734} 2735 2736static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2737{ 2738 u32 aper_size; 2739 u8 byte; 2740 2741 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2742 2743 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2744 * that is has the 2nd generation multifunction PCI interface 2745 */ 2746 if (rdev->family == CHIP_RV280 || 2747 rdev->family >= CHIP_RV350) { 2748 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2749 ~RADEON_HDP_APER_CNTL); 2750 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2751 return aper_size * 2; 2752 } 2753 2754 /* Older cards have all sorts of funny issues to deal with. First 2755 * check if it's a multifunction card by reading the PCI config 2756 * header type... Limit those to one aperture size 2757 */ 2758 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2759 if (byte & 0x80) { 2760 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2761 DRM_INFO("Limiting VRAM to one aperture\n"); 2762 return aper_size; 2763 } 2764 2765 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2766 * have set it up. We don't write this as it's broken on some ASICs but 2767 * we expect the BIOS to have done the right thing (might be too optimistic...) 2768 */ 2769 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2770 return aper_size * 2; 2771 return aper_size; 2772} 2773 2774void r100_vram_init_sizes(struct radeon_device *rdev) 2775{ 2776 u64 config_aper_size; 2777 2778 /* work out accessible VRAM */ 2779 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2780 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2781 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2782 /* FIXME we don't use the second aperture yet when we could use it */ 2783 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2784 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2785 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2786 if (rdev->flags & RADEON_IS_IGP) { 2787 uint32_t tom; 2788 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2789 tom = RREG32(RADEON_NB_TOM); 2790 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2791 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2792 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2793 } else { 2794 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2795 /* Some production boards of m6 will report 0 2796 * if it's 8 MB 2797 */ 2798 if (rdev->mc.real_vram_size == 0) { 2799 rdev->mc.real_vram_size = 8192 * 1024; 2800 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2801 } 2802 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2803 * Novell bug 204882 + along with lots of ubuntu ones 2804 */ 2805 if (rdev->mc.aper_size > config_aper_size) 2806 config_aper_size = rdev->mc.aper_size; 2807 2808 if (config_aper_size > rdev->mc.real_vram_size) 2809 rdev->mc.mc_vram_size = config_aper_size; 2810 else 2811 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2812 } 2813} 2814 2815void r100_vga_set_state(struct radeon_device *rdev, bool state) 2816{ 2817 uint32_t temp; 2818 2819 temp = RREG32(RADEON_CONFIG_CNTL); 2820 if (state == false) { 2821 temp &= ~RADEON_CFG_VGA_RAM_EN; 2822 temp |= RADEON_CFG_VGA_IO_DIS; 2823 } else { 2824 temp &= ~RADEON_CFG_VGA_IO_DIS; 2825 } 2826 WREG32(RADEON_CONFIG_CNTL, temp); 2827} 2828 2829static void r100_mc_init(struct radeon_device *rdev) 2830{ 2831 u64 base; 2832 2833 r100_vram_get_type(rdev); 2834 r100_vram_init_sizes(rdev); 2835 base = rdev->mc.aper_base; 2836 if (rdev->flags & RADEON_IS_IGP) 2837 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2838 radeon_vram_location(rdev, &rdev->mc, base); 2839 rdev->mc.gtt_base_align = 0; 2840 if (!(rdev->flags & RADEON_IS_AGP)) 2841 radeon_gtt_location(rdev, &rdev->mc); 2842 radeon_update_bandwidth_info(rdev); 2843} 2844 2845 2846/* 2847 * Indirect registers accessor 2848 */ 2849void r100_pll_errata_after_index(struct radeon_device *rdev) 2850{ 2851 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2852 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2853 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2854 } 2855} 2856 2857static void r100_pll_errata_after_data(struct radeon_device *rdev) 2858{ 2859 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2860 * or the chip could hang on a subsequent access 2861 */ 2862 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2863 mdelay(5); 2864 } 2865 2866 /* This function is required to workaround a hardware bug in some (all?) 2867 * revisions of the R300. This workaround should be called after every 2868 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2869 * may not be correct. 2870 */ 2871 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2872 uint32_t save, tmp; 2873 2874 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2875 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2876 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2877 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2878 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2879 } 2880} 2881 2882uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2883{ 2884 unsigned long flags; 2885 uint32_t data; 2886 2887 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2888 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2889 r100_pll_errata_after_index(rdev); 2890 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2891 r100_pll_errata_after_data(rdev); 2892 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2893 return data; 2894} 2895 2896void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2897{ 2898 unsigned long flags; 2899 2900 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2901 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2902 r100_pll_errata_after_index(rdev); 2903 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2904 r100_pll_errata_after_data(rdev); 2905 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2906} 2907 2908static void r100_set_safe_registers(struct radeon_device *rdev) 2909{ 2910 if (ASIC_IS_RN50(rdev)) { 2911 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2912 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2913 } else if (rdev->family < CHIP_R200) { 2914 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2915 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2916 } else { 2917 r200_set_safe_registers(rdev); 2918 } 2919} 2920 2921/* 2922 * Debugfs info 2923 */ 2924#if defined(CONFIG_DEBUG_FS) 2925static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2926{ 2927 struct drm_info_node *node = (struct drm_info_node *) m->private; 2928 struct drm_device *dev = node->minor->dev; 2929 struct radeon_device *rdev = dev->dev_private; 2930 uint32_t reg, value; 2931 unsigned i; 2932 2933 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2934 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2935 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2936 for (i = 0; i < 64; i++) { 2937 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2938 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2939 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2940 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2941 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2942 } 2943 return 0; 2944} 2945 2946static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2947{ 2948 struct drm_info_node *node = (struct drm_info_node *) m->private; 2949 struct drm_device *dev = node->minor->dev; 2950 struct radeon_device *rdev = dev->dev_private; 2951 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2952 uint32_t rdp, wdp; 2953 unsigned count, i, j; 2954 2955 radeon_ring_free_size(rdev, ring); 2956 rdp = RREG32(RADEON_CP_RB_RPTR); 2957 wdp = RREG32(RADEON_CP_RB_WPTR); 2958 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2959 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2960 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2961 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2962 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2963 seq_printf(m, "%u dwords in ring\n", count); 2964 if (ring->ready) { 2965 for (j = 0; j <= count; j++) { 2966 i = (rdp + j) & ring->ptr_mask; 2967 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2968 } 2969 } 2970 return 0; 2971} 2972 2973 2974static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2975{ 2976 struct drm_info_node *node = (struct drm_info_node *) m->private; 2977 struct drm_device *dev = node->minor->dev; 2978 struct radeon_device *rdev = dev->dev_private; 2979 uint32_t csq_stat, csq2_stat, tmp; 2980 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2981 unsigned i; 2982 2983 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2984 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2985 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2986 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2987 r_rptr = (csq_stat >> 0) & 0x3ff; 2988 r_wptr = (csq_stat >> 10) & 0x3ff; 2989 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2990 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2991 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2992 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2993 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2994 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2995 seq_printf(m, "Ring rptr %u\n", r_rptr); 2996 seq_printf(m, "Ring wptr %u\n", r_wptr); 2997 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2998 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2999 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3000 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3001 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3002 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3003 seq_printf(m, "Ring fifo:\n"); 3004 for (i = 0; i < 256; i++) { 3005 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3006 tmp = RREG32(RADEON_CP_CSQ_DATA); 3007 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3008 } 3009 seq_printf(m, "Indirect1 fifo:\n"); 3010 for (i = 256; i <= 512; i++) { 3011 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3012 tmp = RREG32(RADEON_CP_CSQ_DATA); 3013 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3014 } 3015 seq_printf(m, "Indirect2 fifo:\n"); 3016 for (i = 640; i < ib1_wptr; i++) { 3017 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3018 tmp = RREG32(RADEON_CP_CSQ_DATA); 3019 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3020 } 3021 return 0; 3022} 3023 3024static int r100_debugfs_mc_info(struct seq_file *m, void *data) 3025{ 3026 struct drm_info_node *node = (struct drm_info_node *) m->private; 3027 struct drm_device *dev = node->minor->dev; 3028 struct radeon_device *rdev = dev->dev_private; 3029 uint32_t tmp; 3030 3031 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3032 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3033 tmp = RREG32(RADEON_MC_FB_LOCATION); 3034 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3035 tmp = RREG32(RADEON_BUS_CNTL); 3036 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3037 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3038 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3039 tmp = RREG32(RADEON_AGP_BASE); 3040 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3041 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3042 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3043 tmp = RREG32(0x01D0); 3044 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3045 tmp = RREG32(RADEON_AIC_LO_ADDR); 3046 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3047 tmp = RREG32(RADEON_AIC_HI_ADDR); 3048 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3049 tmp = RREG32(0x01E4); 3050 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3051 return 0; 3052} 3053 3054static struct drm_info_list r100_debugfs_rbbm_list[] = { 3055 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3056}; 3057 3058static struct drm_info_list r100_debugfs_cp_list[] = { 3059 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3060 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3061}; 3062 3063static struct drm_info_list r100_debugfs_mc_info_list[] = { 3064 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3065}; 3066#endif 3067 3068int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3069{ 3070#if defined(CONFIG_DEBUG_FS) 3071 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3072#else 3073 return 0; 3074#endif 3075} 3076 3077int r100_debugfs_cp_init(struct radeon_device *rdev) 3078{ 3079#if defined(CONFIG_DEBUG_FS) 3080 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3081#else 3082 return 0; 3083#endif 3084} 3085 3086int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3087{ 3088#if defined(CONFIG_DEBUG_FS) 3089 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3090#else 3091 return 0; 3092#endif 3093} 3094 3095int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3096 uint32_t tiling_flags, uint32_t pitch, 3097 uint32_t offset, uint32_t obj_size) 3098{ 3099 int surf_index = reg * 16; 3100 int flags = 0; 3101 3102 if (rdev->family <= CHIP_RS200) { 3103 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3104 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3105 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3106 if (tiling_flags & RADEON_TILING_MACRO) 3107 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3108 /* setting pitch to 0 disables tiling */ 3109 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3110 == 0) 3111 pitch = 0; 3112 } else if (rdev->family <= CHIP_RV280) { 3113 if (tiling_flags & (RADEON_TILING_MACRO)) 3114 flags |= R200_SURF_TILE_COLOR_MACRO; 3115 if (tiling_flags & RADEON_TILING_MICRO) 3116 flags |= R200_SURF_TILE_COLOR_MICRO; 3117 } else { 3118 if (tiling_flags & RADEON_TILING_MACRO) 3119 flags |= R300_SURF_TILE_MACRO; 3120 if (tiling_flags & RADEON_TILING_MICRO) 3121 flags |= R300_SURF_TILE_MICRO; 3122 } 3123 3124 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3125 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3126 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3127 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3128 3129 /* r100/r200 divide by 16 */ 3130 if (rdev->family < CHIP_R300) 3131 flags |= pitch / 16; 3132 else 3133 flags |= pitch / 8; 3134 3135 3136 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3137 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3138 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3139 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3140 return 0; 3141} 3142 3143void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3144{ 3145 int surf_index = reg * 16; 3146 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3147} 3148 3149void r100_bandwidth_update(struct radeon_device *rdev) 3150{ 3151 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3152 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3153 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 3154 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3155 fixed20_12 memtcas_ff[8] = { 3156 dfixed_init(1), 3157 dfixed_init(2), 3158 dfixed_init(3), 3159 dfixed_init(0), 3160 dfixed_init_half(1), 3161 dfixed_init_half(2), 3162 dfixed_init(0), 3163 }; 3164 fixed20_12 memtcas_rs480_ff[8] = { 3165 dfixed_init(0), 3166 dfixed_init(1), 3167 dfixed_init(2), 3168 dfixed_init(3), 3169 dfixed_init(0), 3170 dfixed_init_half(1), 3171 dfixed_init_half(2), 3172 dfixed_init_half(3), 3173 }; 3174 fixed20_12 memtcas2_ff[8] = { 3175 dfixed_init(0), 3176 dfixed_init(1), 3177 dfixed_init(2), 3178 dfixed_init(3), 3179 dfixed_init(4), 3180 dfixed_init(5), 3181 dfixed_init(6), 3182 dfixed_init(7), 3183 }; 3184 fixed20_12 memtrbs[8] = { 3185 dfixed_init(1), 3186 dfixed_init_half(1), 3187 dfixed_init(2), 3188 dfixed_init_half(2), 3189 dfixed_init(3), 3190 dfixed_init_half(3), 3191 dfixed_init(4), 3192 dfixed_init_half(4) 3193 }; 3194 fixed20_12 memtrbs_r4xx[8] = { 3195 dfixed_init(4), 3196 dfixed_init(5), 3197 dfixed_init(6), 3198 dfixed_init(7), 3199 dfixed_init(8), 3200 dfixed_init(9), 3201 dfixed_init(10), 3202 dfixed_init(11) 3203 }; 3204 fixed20_12 min_mem_eff; 3205 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3206 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3207 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 3208 disp_drain_rate2, read_return_rate; 3209 fixed20_12 time_disp1_drop_priority; 3210 int c; 3211 int cur_size = 16; /* in octawords */ 3212 int critical_point = 0, critical_point2; 3213/* uint32_t read_return_rate, time_disp1_drop_priority; */ 3214 int stop_req, max_stop_req; 3215 struct drm_display_mode *mode1 = NULL; 3216 struct drm_display_mode *mode2 = NULL; 3217 uint32_t pixel_bytes1 = 0; 3218 uint32_t pixel_bytes2 = 0; 3219 3220 /* Guess line buffer size to be 8192 pixels */ 3221 u32 lb_size = 8192; 3222 3223 if (!rdev->mode_info.mode_config_initialized) 3224 return; 3225 3226 radeon_update_display_priority(rdev); 3227 3228 if (rdev->mode_info.crtcs[0]->base.enabled) { 3229 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3230 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8; 3231 } 3232 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3233 if (rdev->mode_info.crtcs[1]->base.enabled) { 3234 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3235 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8; 3236 } 3237 } 3238 3239 min_mem_eff.full = dfixed_const_8(0); 3240 /* get modes */ 3241 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3242 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3243 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3244 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3245 /* check crtc enables */ 3246 if (mode2) 3247 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3248 if (mode1) 3249 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3250 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3251 } 3252 3253 /* 3254 * determine is there is enough bw for current mode 3255 */ 3256 sclk_ff = rdev->pm.sclk; 3257 mclk_ff = rdev->pm.mclk; 3258 3259 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3260 temp_ff.full = dfixed_const(temp); 3261 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3262 3263 pix_clk.full = 0; 3264 pix_clk2.full = 0; 3265 peak_disp_bw.full = 0; 3266 if (mode1) { 3267 temp_ff.full = dfixed_const(1000); 3268 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3269 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3270 temp_ff.full = dfixed_const(pixel_bytes1); 3271 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3272 } 3273 if (mode2) { 3274 temp_ff.full = dfixed_const(1000); 3275 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3276 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3277 temp_ff.full = dfixed_const(pixel_bytes2); 3278 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3279 } 3280 3281 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3282 if (peak_disp_bw.full >= mem_bw.full) { 3283 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3284 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3285 } 3286 3287 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3288 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3289 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3290 mem_trcd = ((temp >> 2) & 0x3) + 1; 3291 mem_trp = ((temp & 0x3)) + 1; 3292 mem_tras = ((temp & 0x70) >> 4) + 1; 3293 } else if (rdev->family == CHIP_R300 || 3294 rdev->family == CHIP_R350) { /* r300, r350 */ 3295 mem_trcd = (temp & 0x7) + 1; 3296 mem_trp = ((temp >> 8) & 0x7) + 1; 3297 mem_tras = ((temp >> 11) & 0xf) + 4; 3298 } else if (rdev->family == CHIP_RV350 || 3299 rdev->family <= CHIP_RV380) { 3300 /* rv3x0 */ 3301 mem_trcd = (temp & 0x7) + 3; 3302 mem_trp = ((temp >> 8) & 0x7) + 3; 3303 mem_tras = ((temp >> 11) & 0xf) + 6; 3304 } else if (rdev->family == CHIP_R420 || 3305 rdev->family == CHIP_R423 || 3306 rdev->family == CHIP_RV410) { 3307 /* r4xx */ 3308 mem_trcd = (temp & 0xf) + 3; 3309 if (mem_trcd > 15) 3310 mem_trcd = 15; 3311 mem_trp = ((temp >> 8) & 0xf) + 3; 3312 if (mem_trp > 15) 3313 mem_trp = 15; 3314 mem_tras = ((temp >> 12) & 0x1f) + 6; 3315 if (mem_tras > 31) 3316 mem_tras = 31; 3317 } else { /* RV200, R200 */ 3318 mem_trcd = (temp & 0x7) + 1; 3319 mem_trp = ((temp >> 8) & 0x7) + 1; 3320 mem_tras = ((temp >> 12) & 0xf) + 4; 3321 } 3322 /* convert to FF */ 3323 trcd_ff.full = dfixed_const(mem_trcd); 3324 trp_ff.full = dfixed_const(mem_trp); 3325 tras_ff.full = dfixed_const(mem_tras); 3326 3327 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3328 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3329 data = (temp & (7 << 20)) >> 20; 3330 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3331 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3332 tcas_ff = memtcas_rs480_ff[data]; 3333 else 3334 tcas_ff = memtcas_ff[data]; 3335 } else 3336 tcas_ff = memtcas2_ff[data]; 3337 3338 if (rdev->family == CHIP_RS400 || 3339 rdev->family == CHIP_RS480) { 3340 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3341 data = (temp >> 23) & 0x7; 3342 if (data < 5) 3343 tcas_ff.full += dfixed_const(data); 3344 } 3345 3346 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3347 /* on the R300, Tcas is included in Trbs. 3348 */ 3349 temp = RREG32(RADEON_MEM_CNTL); 3350 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3351 if (data == 1) { 3352 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3353 temp = RREG32(R300_MC_IND_INDEX); 3354 temp &= ~R300_MC_IND_ADDR_MASK; 3355 temp |= R300_MC_READ_CNTL_CD_mcind; 3356 WREG32(R300_MC_IND_INDEX, temp); 3357 temp = RREG32(R300_MC_IND_DATA); 3358 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3359 } else { 3360 temp = RREG32(R300_MC_READ_CNTL_AB); 3361 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3362 } 3363 } else { 3364 temp = RREG32(R300_MC_READ_CNTL_AB); 3365 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3366 } 3367 if (rdev->family == CHIP_RV410 || 3368 rdev->family == CHIP_R420 || 3369 rdev->family == CHIP_R423) 3370 trbs_ff = memtrbs_r4xx[data]; 3371 else 3372 trbs_ff = memtrbs[data]; 3373 tcas_ff.full += trbs_ff.full; 3374 } 3375 3376 sclk_eff_ff.full = sclk_ff.full; 3377 3378 if (rdev->flags & RADEON_IS_AGP) { 3379 fixed20_12 agpmode_ff; 3380 agpmode_ff.full = dfixed_const(radeon_agpmode); 3381 temp_ff.full = dfixed_const_666(16); 3382 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3383 } 3384 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3385 3386 if (ASIC_IS_R300(rdev)) { 3387 sclk_delay_ff.full = dfixed_const(250); 3388 } else { 3389 if ((rdev->family == CHIP_RV100) || 3390 rdev->flags & RADEON_IS_IGP) { 3391 if (rdev->mc.vram_is_ddr) 3392 sclk_delay_ff.full = dfixed_const(41); 3393 else 3394 sclk_delay_ff.full = dfixed_const(33); 3395 } else { 3396 if (rdev->mc.vram_width == 128) 3397 sclk_delay_ff.full = dfixed_const(57); 3398 else 3399 sclk_delay_ff.full = dfixed_const(41); 3400 } 3401 } 3402 3403 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3404 3405 if (rdev->mc.vram_is_ddr) { 3406 if (rdev->mc.vram_width == 32) { 3407 k1.full = dfixed_const(40); 3408 c = 3; 3409 } else { 3410 k1.full = dfixed_const(20); 3411 c = 1; 3412 } 3413 } else { 3414 k1.full = dfixed_const(40); 3415 c = 3; 3416 } 3417 3418 temp_ff.full = dfixed_const(2); 3419 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3420 temp_ff.full = dfixed_const(c); 3421 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3422 temp_ff.full = dfixed_const(4); 3423 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3424 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3425 mc_latency_mclk.full += k1.full; 3426 3427 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3428 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3429 3430 /* 3431 HW cursor time assuming worst case of full size colour cursor. 3432 */ 3433 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3434 temp_ff.full += trcd_ff.full; 3435 if (temp_ff.full < tras_ff.full) 3436 temp_ff.full = tras_ff.full; 3437 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3438 3439 temp_ff.full = dfixed_const(cur_size); 3440 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3441 /* 3442 Find the total latency for the display data. 3443 */ 3444 disp_latency_overhead.full = dfixed_const(8); 3445 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3446 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3447 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3448 3449 if (mc_latency_mclk.full > mc_latency_sclk.full) 3450 disp_latency.full = mc_latency_mclk.full; 3451 else 3452 disp_latency.full = mc_latency_sclk.full; 3453 3454 /* setup Max GRPH_STOP_REQ default value */ 3455 if (ASIC_IS_RV100(rdev)) 3456 max_stop_req = 0x5c; 3457 else 3458 max_stop_req = 0x7c; 3459 3460 if (mode1) { 3461 /* CRTC1 3462 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3463 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3464 */ 3465 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3466 3467 if (stop_req > max_stop_req) 3468 stop_req = max_stop_req; 3469 3470 /* 3471 Find the drain rate of the display buffer. 3472 */ 3473 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3474 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3475 3476 /* 3477 Find the critical point of the display buffer. 3478 */ 3479 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3480 crit_point_ff.full += dfixed_const_half(0); 3481 3482 critical_point = dfixed_trunc(crit_point_ff); 3483 3484 if (rdev->disp_priority == 2) { 3485 critical_point = 0; 3486 } 3487 3488 /* 3489 The critical point should never be above max_stop_req-4. Setting 3490 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3491 */ 3492 if (max_stop_req - critical_point < 4) 3493 critical_point = 0; 3494 3495 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3496 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3497 critical_point = 0x10; 3498 } 3499 3500 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3501 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3502 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3503 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3504 if ((rdev->family == CHIP_R350) && 3505 (stop_req > 0x15)) { 3506 stop_req -= 0x10; 3507 } 3508 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3509 temp |= RADEON_GRPH_BUFFER_SIZE; 3510 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3511 RADEON_GRPH_CRITICAL_AT_SOF | 3512 RADEON_GRPH_STOP_CNTL); 3513 /* 3514 Write the result into the register. 3515 */ 3516 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3517 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3518 3519#if 0 3520 if ((rdev->family == CHIP_RS400) || 3521 (rdev->family == CHIP_RS480)) { 3522 /* attempt to program RS400 disp regs correctly ??? */ 3523 temp = RREG32(RS400_DISP1_REG_CNTL); 3524 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3525 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3526 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3527 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3528 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3529 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3530 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3531 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3532 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3533 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3534 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3535 } 3536#endif 3537 3538 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3539 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3540 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3541 } 3542 3543 if (mode2) { 3544 u32 grph2_cntl; 3545 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3546 3547 if (stop_req > max_stop_req) 3548 stop_req = max_stop_req; 3549 3550 /* 3551 Find the drain rate of the display buffer. 3552 */ 3553 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3554 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3555 3556 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3557 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3558 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3559 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3560 if ((rdev->family == CHIP_R350) && 3561 (stop_req > 0x15)) { 3562 stop_req -= 0x10; 3563 } 3564 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3565 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3566 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3567 RADEON_GRPH_CRITICAL_AT_SOF | 3568 RADEON_GRPH_STOP_CNTL); 3569 3570 if ((rdev->family == CHIP_RS100) || 3571 (rdev->family == CHIP_RS200)) 3572 critical_point2 = 0; 3573 else { 3574 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3575 temp_ff.full = dfixed_const(temp); 3576 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3577 if (sclk_ff.full < temp_ff.full) 3578 temp_ff.full = sclk_ff.full; 3579 3580 read_return_rate.full = temp_ff.full; 3581 3582 if (mode1) { 3583 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3584 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3585 } else { 3586 time_disp1_drop_priority.full = 0; 3587 } 3588 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3589 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3590 crit_point_ff.full += dfixed_const_half(0); 3591 3592 critical_point2 = dfixed_trunc(crit_point_ff); 3593 3594 if (rdev->disp_priority == 2) { 3595 critical_point2 = 0; 3596 } 3597 3598 if (max_stop_req - critical_point2 < 4) 3599 critical_point2 = 0; 3600 3601 } 3602 3603 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3604 /* some R300 cards have problem with this set to 0 */ 3605 critical_point2 = 0x10; 3606 } 3607 3608 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3609 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3610 3611 if ((rdev->family == CHIP_RS400) || 3612 (rdev->family == CHIP_RS480)) { 3613#if 0 3614 /* attempt to program RS400 disp2 regs correctly ??? */ 3615 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3616 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3617 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3618 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3619 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3620 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3621 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3622 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3623 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3624 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3625 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3626 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3627#endif 3628 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3629 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3630 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3631 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3632 } 3633 3634 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3635 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3636 } 3637 3638 /* Save number of lines the linebuffer leads before the scanout */ 3639 if (mode1) 3640 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3641 3642 if (mode2) 3643 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3644} 3645 3646int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3647{ 3648 uint32_t scratch; 3649 uint32_t tmp = 0; 3650 unsigned i; 3651 int r; 3652 3653 r = radeon_scratch_get(rdev, &scratch); 3654 if (r) { 3655 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3656 return r; 3657 } 3658 WREG32(scratch, 0xCAFEDEAD); 3659 r = radeon_ring_lock(rdev, ring, 2); 3660 if (r) { 3661 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3662 radeon_scratch_free(rdev, scratch); 3663 return r; 3664 } 3665 radeon_ring_write(ring, PACKET0(scratch, 0)); 3666 radeon_ring_write(ring, 0xDEADBEEF); 3667 radeon_ring_unlock_commit(rdev, ring, false); 3668 for (i = 0; i < rdev->usec_timeout; i++) { 3669 tmp = RREG32(scratch); 3670 if (tmp == 0xDEADBEEF) { 3671 break; 3672 } 3673 DRM_UDELAY(1); 3674 } 3675 if (i < rdev->usec_timeout) { 3676 DRM_INFO("ring test succeeded in %d usecs\n", i); 3677 } else { 3678 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3679 scratch, tmp); 3680 r = -EINVAL; 3681 } 3682 radeon_scratch_free(rdev, scratch); 3683 return r; 3684} 3685 3686void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3687{ 3688 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3689 3690 if (ring->rptr_save_reg) { 3691 u32 next_rptr = ring->wptr + 2 + 3; 3692 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3693 radeon_ring_write(ring, next_rptr); 3694 } 3695 3696 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3697 radeon_ring_write(ring, ib->gpu_addr); 3698 radeon_ring_write(ring, ib->length_dw); 3699} 3700 3701int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3702{ 3703 struct radeon_ib ib; 3704 uint32_t scratch; 3705 uint32_t tmp = 0; 3706 unsigned i; 3707 int r; 3708 3709 r = radeon_scratch_get(rdev, &scratch); 3710 if (r) { 3711 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3712 return r; 3713 } 3714 WREG32(scratch, 0xCAFEDEAD); 3715 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3716 if (r) { 3717 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3718 goto free_scratch; 3719 } 3720 ib.ptr[0] = PACKET0(scratch, 0); 3721 ib.ptr[1] = 0xDEADBEEF; 3722 ib.ptr[2] = PACKET2(0); 3723 ib.ptr[3] = PACKET2(0); 3724 ib.ptr[4] = PACKET2(0); 3725 ib.ptr[5] = PACKET2(0); 3726 ib.ptr[6] = PACKET2(0); 3727 ib.ptr[7] = PACKET2(0); 3728 ib.length_dw = 8; 3729 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3730 if (r) { 3731 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3732 goto free_ib; 3733 } 3734 r = radeon_fence_wait(ib.fence, false); 3735 if (r) { 3736 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3737 goto free_ib; 3738 } 3739 for (i = 0; i < rdev->usec_timeout; i++) { 3740 tmp = RREG32(scratch); 3741 if (tmp == 0xDEADBEEF) { 3742 break; 3743 } 3744 DRM_UDELAY(1); 3745 } 3746 if (i < rdev->usec_timeout) { 3747 DRM_INFO("ib test succeeded in %u usecs\n", i); 3748 } else { 3749 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3750 scratch, tmp); 3751 r = -EINVAL; 3752 } 3753free_ib: 3754 radeon_ib_free(rdev, &ib); 3755free_scratch: 3756 radeon_scratch_free(rdev, scratch); 3757 return r; 3758} 3759 3760void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3761{ 3762 /* Shutdown CP we shouldn't need to do that but better be safe than 3763 * sorry 3764 */ 3765 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3766 WREG32(R_000740_CP_CSQ_CNTL, 0); 3767 3768 /* Save few CRTC registers */ 3769 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3770 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3771 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3772 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3773 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3774 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3775 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3776 } 3777 3778 /* Disable VGA aperture access */ 3779 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3780 /* Disable cursor, overlay, crtc */ 3781 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3782 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3783 S_000054_CRTC_DISPLAY_DIS(1)); 3784 WREG32(R_000050_CRTC_GEN_CNTL, 3785 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3786 S_000050_CRTC_DISP_REQ_EN_B(1)); 3787 WREG32(R_000420_OV0_SCALE_CNTL, 3788 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3789 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3790 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3791 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3792 S_000360_CUR2_LOCK(1)); 3793 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3794 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3795 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3796 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3797 WREG32(R_000360_CUR2_OFFSET, 3798 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3799 } 3800} 3801 3802void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3803{ 3804 /* Update base address for crtc */ 3805 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3806 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3807 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3808 } 3809 /* Restore CRTC registers */ 3810 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3811 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3812 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3813 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3814 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3815 } 3816} 3817 3818void r100_vga_render_disable(struct radeon_device *rdev) 3819{ 3820 u32 tmp; 3821 3822 tmp = RREG8(R_0003C2_GENMO_WT); 3823 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3824} 3825 3826static void r100_debugfs(struct radeon_device *rdev) 3827{ 3828 int r; 3829 3830 r = r100_debugfs_mc_info_init(rdev); 3831 if (r) 3832 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3833} 3834 3835static void r100_mc_program(struct radeon_device *rdev) 3836{ 3837 struct r100_mc_save save; 3838 3839 /* Stops all mc clients */ 3840 r100_mc_stop(rdev, &save); 3841 if (rdev->flags & RADEON_IS_AGP) { 3842 WREG32(R_00014C_MC_AGP_LOCATION, 3843 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3844 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3845 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3846 if (rdev->family > CHIP_RV200) 3847 WREG32(R_00015C_AGP_BASE_2, 3848 upper_32_bits(rdev->mc.agp_base) & 0xff); 3849 } else { 3850 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3851 WREG32(R_000170_AGP_BASE, 0); 3852 if (rdev->family > CHIP_RV200) 3853 WREG32(R_00015C_AGP_BASE_2, 0); 3854 } 3855 /* Wait for mc idle */ 3856 if (r100_mc_wait_for_idle(rdev)) 3857 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3858 /* Program MC, should be a 32bits limited address space */ 3859 WREG32(R_000148_MC_FB_LOCATION, 3860 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3861 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3862 r100_mc_resume(rdev, &save); 3863} 3864 3865static void r100_clock_startup(struct radeon_device *rdev) 3866{ 3867 u32 tmp; 3868 3869 if (radeon_dynclks != -1 && radeon_dynclks) 3870 radeon_legacy_set_clock_gating(rdev, 1); 3871 /* We need to force on some of the block */ 3872 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3873 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3874 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3875 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3876 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3877} 3878 3879static int r100_startup(struct radeon_device *rdev) 3880{ 3881 int r; 3882 3883 /* set common regs */ 3884 r100_set_common_regs(rdev); 3885 /* program mc */ 3886 r100_mc_program(rdev); 3887 /* Resume clock */ 3888 r100_clock_startup(rdev); 3889 /* Initialize GART (initialize after TTM so we can allocate 3890 * memory through TTM but finalize after TTM) */ 3891 r100_enable_bm(rdev); 3892 if (rdev->flags & RADEON_IS_PCI) { 3893 r = r100_pci_gart_enable(rdev); 3894 if (r) 3895 return r; 3896 } 3897 3898 /* allocate wb buffer */ 3899 r = radeon_wb_init(rdev); 3900 if (r) 3901 return r; 3902 3903 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3904 if (r) { 3905 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3906 return r; 3907 } 3908 3909 /* Enable IRQ */ 3910 if (!rdev->irq.installed) { 3911 r = radeon_irq_kms_init(rdev); 3912 if (r) 3913 return r; 3914 } 3915 3916 r100_irq_set(rdev); 3917 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3918 /* 1M ring buffer */ 3919 r = r100_cp_init(rdev, 1024 * 1024); 3920 if (r) { 3921 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3922 return r; 3923 } 3924 3925 r = radeon_ib_pool_init(rdev); 3926 if (r) { 3927 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3928 return r; 3929 } 3930 3931 return 0; 3932} 3933 3934int r100_resume(struct radeon_device *rdev) 3935{ 3936 int r; 3937 3938 /* Make sur GART are not working */ 3939 if (rdev->flags & RADEON_IS_PCI) 3940 r100_pci_gart_disable(rdev); 3941 /* Resume clock before doing reset */ 3942 r100_clock_startup(rdev); 3943 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3944 if (radeon_asic_reset(rdev)) { 3945 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3946 RREG32(R_000E40_RBBM_STATUS), 3947 RREG32(R_0007C0_CP_STAT)); 3948 } 3949 /* post */ 3950 radeon_combios_asic_init(rdev->ddev); 3951 /* Resume clock after posting */ 3952 r100_clock_startup(rdev); 3953 /* Initialize surface registers */ 3954 radeon_surface_init(rdev); 3955 3956 rdev->accel_working = true; 3957 r = r100_startup(rdev); 3958 if (r) { 3959 rdev->accel_working = false; 3960 } 3961 return r; 3962} 3963 3964int r100_suspend(struct radeon_device *rdev) 3965{ 3966 radeon_pm_suspend(rdev); 3967 r100_cp_disable(rdev); 3968 radeon_wb_disable(rdev); 3969 r100_irq_disable(rdev); 3970 if (rdev->flags & RADEON_IS_PCI) 3971 r100_pci_gart_disable(rdev); 3972 return 0; 3973} 3974 3975void r100_fini(struct radeon_device *rdev) 3976{ 3977 radeon_pm_fini(rdev); 3978 r100_cp_fini(rdev); 3979 radeon_wb_fini(rdev); 3980 radeon_ib_pool_fini(rdev); 3981 radeon_gem_fini(rdev); 3982 if (rdev->flags & RADEON_IS_PCI) 3983 r100_pci_gart_fini(rdev); 3984 radeon_agp_fini(rdev); 3985 radeon_irq_kms_fini(rdev); 3986 radeon_fence_driver_fini(rdev); 3987 radeon_bo_fini(rdev); 3988 radeon_atombios_fini(rdev); 3989 kfree(rdev->bios); 3990 rdev->bios = NULL; 3991} 3992 3993/* 3994 * Due to how kexec works, it can leave the hw fully initialised when it 3995 * boots the new kernel. However doing our init sequence with the CP and 3996 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3997 * do some quick sanity checks and restore sane values to avoid this 3998 * problem. 3999 */ 4000void r100_restore_sanity(struct radeon_device *rdev) 4001{ 4002 u32 tmp; 4003 4004 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4005 if (tmp) { 4006 WREG32(RADEON_CP_CSQ_CNTL, 0); 4007 } 4008 tmp = RREG32(RADEON_CP_RB_CNTL); 4009 if (tmp) { 4010 WREG32(RADEON_CP_RB_CNTL, 0); 4011 } 4012 tmp = RREG32(RADEON_SCRATCH_UMSK); 4013 if (tmp) { 4014 WREG32(RADEON_SCRATCH_UMSK, 0); 4015 } 4016} 4017 4018int r100_init(struct radeon_device *rdev) 4019{ 4020 int r; 4021 4022 /* Register debugfs file specific to this group of asics */ 4023 r100_debugfs(rdev); 4024 /* Disable VGA */ 4025 r100_vga_render_disable(rdev); 4026 /* Initialize scratch registers */ 4027 radeon_scratch_init(rdev); 4028 /* Initialize surface registers */ 4029 radeon_surface_init(rdev); 4030 /* sanity check some register to avoid hangs like after kexec */ 4031 r100_restore_sanity(rdev); 4032 /* TODO: disable VGA need to use VGA request */ 4033 /* BIOS*/ 4034 if (!radeon_get_bios(rdev)) { 4035 if (ASIC_IS_AVIVO(rdev)) 4036 return -EINVAL; 4037 } 4038 if (rdev->is_atom_bios) { 4039 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4040 return -EINVAL; 4041 } else { 4042 r = radeon_combios_init(rdev); 4043 if (r) 4044 return r; 4045 } 4046 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4047 if (radeon_asic_reset(rdev)) { 4048 dev_warn(rdev->dev, 4049 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4050 RREG32(R_000E40_RBBM_STATUS), 4051 RREG32(R_0007C0_CP_STAT)); 4052 } 4053 /* check if cards are posted or not */ 4054 if (radeon_boot_test_post_card(rdev) == false) 4055 return -EINVAL; 4056 /* Set asic errata */ 4057 r100_errata(rdev); 4058 /* Initialize clocks */ 4059 radeon_get_clock_info(rdev->ddev); 4060 /* initialize AGP */ 4061 if (rdev->flags & RADEON_IS_AGP) { 4062 r = radeon_agp_init(rdev); 4063 if (r) { 4064 radeon_agp_disable(rdev); 4065 } 4066 } 4067 /* initialize VRAM */ 4068 r100_mc_init(rdev); 4069 /* Fence driver */ 4070 r = radeon_fence_driver_init(rdev); 4071 if (r) 4072 return r; 4073 /* Memory manager */ 4074 r = radeon_bo_init(rdev); 4075 if (r) 4076 return r; 4077 if (rdev->flags & RADEON_IS_PCI) { 4078 r = r100_pci_gart_init(rdev); 4079 if (r) 4080 return r; 4081 } 4082 r100_set_safe_registers(rdev); 4083 4084 /* Initialize power management */ 4085 radeon_pm_init(rdev); 4086 4087 rdev->accel_working = true; 4088 r = r100_startup(rdev); 4089 if (r) { 4090 /* Somethings want wront with the accel init stop accel */ 4091 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4092 r100_cp_fini(rdev); 4093 radeon_wb_fini(rdev); 4094 radeon_ib_pool_fini(rdev); 4095 radeon_irq_kms_fini(rdev); 4096 if (rdev->flags & RADEON_IS_PCI) 4097 r100_pci_gart_fini(rdev); 4098 rdev->accel_working = false; 4099 } 4100 return 0; 4101} 4102 4103uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 4104{ 4105 unsigned long flags; 4106 uint32_t ret; 4107 4108 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4109 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4110 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4111 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4112 return ret; 4113} 4114 4115void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4116{ 4117 unsigned long flags; 4118 4119 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4120 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4121 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4122 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4123} 4124 4125u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4126{ 4127 if (reg < rdev->rio_mem_size) 4128 return ioread32(rdev->rio_mem + reg); 4129 else { 4130 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4131 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4132 } 4133} 4134 4135void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4136{ 4137 if (reg < rdev->rio_mem_size) 4138 iowrite32(v, rdev->rio_mem + reg); 4139 else { 4140 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4141 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4142 } 4143} 4144