Lines Matching refs:RREG32
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
354 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
363 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_prepare()
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_prepare()
486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_finish()
490 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_finish()
508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) in r100_gui_idle()
530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) in r100_hpd_sense()
534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) in r100_hpd_sense()
559 tmp = RREG32(RADEON_FP_GEN_CNTL); in r100_hpd_set_polarity()
567 tmp = RREG32(RADEON_FP2_GEN_CNTL); in r100_hpd_set_polarity()
657 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_enable()
664 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; in r100_pci_gart_enable()
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_disable()
733 RREG32(RADEON_GEN_INT_CNTL); in r100_irq_set()
745 tmp = RREG32(R_000044_GEN_INT_STATUS); in r100_irq_disable()
751 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); in r100_irq_ack()
814 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; in r100_irq_process()
829 return RREG32(RADEON_CRTC_CRNT_FRAME); in r100_get_vblank_counter()
831 return RREG32(RADEON_CRTC2_CRNT_FRAME); in r100_get_vblank_counter()
965 tmp = RREG32(R_000E40_RBBM_STATUS); in r100_cp_wait_for_idle()
1064 rptr = RREG32(RADEON_CP_RB_RPTR); in r100_gfx_get_rptr()
1074 wptr = RREG32(RADEON_CP_RB_WPTR); in r100_gfx_get_wptr()
1083 (void)RREG32(RADEON_CP_RB_WPTR); in r100_gfx_set_wptr()
2476 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; in r100_rbbm_fifo_wait_for_entry()
2495 tmp = RREG32(RADEON_RBBM_STATUS); in r100_gui_wait_for_idle()
2511 tmp = RREG32(RADEON_MC_STATUS); in r100_mc_wait_for_idle()
2524 rbbm_status = RREG32(R_000E40_RBBM_STATUS); in r100_gpu_is_lockup()
2537 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in r100_enable_bm()
2546 tmp = RREG32(R_000030_BUS_CNTL); in r100_bm_disable()
2552 tmp = RREG32(RADEON_BUS_CNTL); in r100_bm_disable()
2564 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2569 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2573 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2586 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2590 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2594 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2598 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2660 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); in r100_set_common_regs()
2661 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); in r100_set_common_regs()
2662 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); in r100_set_common_regs()
2708 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) in r100_vram_get_type()
2713 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2724 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2741 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_get_accessible_vram()
2769 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) in r100_get_accessible_vram()
2785 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_vram_init_sizes()
2789 tom = RREG32(RADEON_NB_TOM); in r100_vram_init_sizes()
2794 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2819 temp = RREG32(RADEON_CONFIG_CNTL); in r100_vga_set_state()
2837 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in r100_mc_init()
2852 (void)RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_index()
2853 (void)RREG32(RADEON_CRTC_GEN_CNTL); in r100_pll_errata_after_index()
2874 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2877 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_data()
2890 data = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_rreg()
2933 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); in r100_debugfs_rbbm_info()
2934 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); in r100_debugfs_rbbm_info()
2935 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_rbbm_info()
2938 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info()
2940 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); in r100_debugfs_rbbm_info()
2956 rdp = RREG32(RADEON_CP_RB_RPTR); in r100_debugfs_cp_ring_info()
2957 wdp = RREG32(RADEON_CP_RB_WPTR); in r100_debugfs_cp_ring_info()
2959 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_ring_info()
2983 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_csq_fifo()
2984 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); in r100_debugfs_cp_csq_fifo()
2985 csq_stat = RREG32(RADEON_CP_CSQ_STAT); in r100_debugfs_cp_csq_fifo()
2986 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); in r100_debugfs_cp_csq_fifo()
3006 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo()
3012 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo()
3018 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo()
3031 tmp = RREG32(RADEON_CONFIG_MEMSIZE); in r100_debugfs_mc_info()
3033 tmp = RREG32(RADEON_MC_FB_LOCATION); in r100_debugfs_mc_info()
3035 tmp = RREG32(RADEON_BUS_CNTL); in r100_debugfs_mc_info()
3037 tmp = RREG32(RADEON_MC_AGP_LOCATION); in r100_debugfs_mc_info()
3039 tmp = RREG32(RADEON_AGP_BASE); in r100_debugfs_mc_info()
3041 tmp = RREG32(RADEON_HOST_PATH_CNTL); in r100_debugfs_mc_info()
3043 tmp = RREG32(0x01D0); in r100_debugfs_mc_info()
3045 tmp = RREG32(RADEON_AIC_LO_ADDR); in r100_debugfs_mc_info()
3047 tmp = RREG32(RADEON_AIC_HI_ADDR); in r100_debugfs_mc_info()
3049 tmp = RREG32(0x01E4); in r100_debugfs_mc_info()
3242 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); in r100_bandwidth_update()
3288 temp = RREG32(RADEON_MEM_TIMING_CNTL); in r100_bandwidth_update()
3328 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); in r100_bandwidth_update()
3349 temp = RREG32(RADEON_MEM_CNTL); in r100_bandwidth_update()
3353 temp = RREG32(R300_MC_IND_INDEX); in r100_bandwidth_update()
3357 temp = RREG32(R300_MC_IND_DATA); in r100_bandwidth_update()
3360 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3364 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3500 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); in r100_bandwidth_update()
3523 temp = RREG32(RS400_DISP1_REG_CNTL); in r100_bandwidth_update()
3529 temp = RREG32(RS400_DMIF_MEM_CNTL1); in r100_bandwidth_update()
3540 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); in r100_bandwidth_update()
3556 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); in r100_bandwidth_update()
3615 temp = RREG32(RS400_DISP2_REQ_CNTL1); in r100_bandwidth_update()
3621 temp = RREG32(RS400_DISP2_REQ_CNTL2); in r100_bandwidth_update()
3635 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); in r100_bandwidth_update()
3669 tmp = RREG32(scratch); in r100_ring_test()
3740 tmp = RREG32(scratch); in r100_ib_test()
3770 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3771 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3772 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3774 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3775 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3788 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); in r100_mc_stop()
3917 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3946 RREG32(R_000E40_RBBM_STATUS), in r100_resume()
3947 RREG32(R_0007C0_CP_STAT)); in r100_resume()
4004 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()
4008 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4012 tmp = RREG32(RADEON_SCRATCH_UMSK); in r100_restore_sanity()
4050 RREG32(R_000E40_RBBM_STATUS), in r100_init()
4051 RREG32(R_0007C0_CP_STAT)); in r100_init()