203 	u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;  in sdma_v2_4_ring_get_wptr()
381 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in sdma_v2_4_gfx_stop()
384 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);  in sdma_v2_4_gfx_stop()
423 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);  in sdma_v2_4_enable()
466 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in sdma_v2_4_gfx_resume()
497 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);  in sdma_v2_4_gfx_resume()
1055 	u32 tmp = RREG32(mmSRBM_STATUS2);  in sdma_v2_4_is_idle()
1071 		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |  in sdma_v2_4_wait_for_idle()
1088 		 RREG32(mmSRBM_STATUS2));  in sdma_v2_4_print_status()
1091 			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));  in sdma_v2_4_print_status()
1093 			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));  in sdma_v2_4_print_status()
1095 			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));  in sdma_v2_4_print_status()
1097 			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));  in sdma_v2_4_print_status()
1099 			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));  in sdma_v2_4_print_status()
1101 			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));  in sdma_v2_4_print_status()
1103 			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));  in sdma_v2_4_print_status()
1105 			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));  in sdma_v2_4_print_status()
1107 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));  in sdma_v2_4_print_status()
1109 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));  in sdma_v2_4_print_status()
1111 			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));  in sdma_v2_4_print_status()
1113 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));  in sdma_v2_4_print_status()
1119 				 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));  in sdma_v2_4_print_status()
1121 				 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));  in sdma_v2_4_print_status()
1132 	u32 tmp = RREG32(mmSRBM_STATUS2);  in sdma_v2_4_soft_reset()
1136 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in sdma_v2_4_soft_reset()
1143 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in sdma_v2_4_soft_reset()
1152 		tmp = RREG32(mmSRBM_SOFT_RESET);  in sdma_v2_4_soft_reset()
1156 		tmp = RREG32(mmSRBM_SOFT_RESET);  in sdma_v2_4_soft_reset()
1162 		tmp = RREG32(mmSRBM_SOFT_RESET);  in sdma_v2_4_soft_reset()
1184 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);  in sdma_v2_4_set_trap_irq_state()
1189 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);  in sdma_v2_4_set_trap_irq_state()
1200 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);  in sdma_v2_4_set_trap_irq_state()
1205 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);  in sdma_v2_4_set_trap_irq_state()