79 	(void)RREG32(mmPCIE_INDEX);  in cik_pcie_rreg()
80 	r = RREG32(mmPCIE_DATA);  in cik_pcie_rreg()
91 	(void)RREG32(mmPCIE_INDEX);  in cik_pcie_wreg()
93 	(void)RREG32(mmPCIE_DATA);  in cik_pcie_wreg()
104 	r = RREG32(mmSMC_IND_DATA_0);  in cik_smc_rreg()
126 	r = RREG32(mmUVD_CTX_DATA);  in cik_uvd_ctx_rreg()
148 	r = RREG32(mmDIDT_IND_DATA);  in cik_didt_rreg()
879 	tmp = RREG32(mmCONFIG_CNTL);  in cik_vga_set_state()
896 	bus_cntl = RREG32(mmBUS_CNTL);  in cik_read_disabled_bios()
898 		d1vga_control = RREG32(mmD1VGA_CONTROL);  in cik_read_disabled_bios()
899 		d2vga_control = RREG32(mmD2VGA_CONTROL);  in cik_read_disabled_bios()
900 		vga_render_control = RREG32(mmVGA_RENDER_CONTROL);  in cik_read_disabled_bios()
1001 	val = RREG32(reg_offset);  in cik_read_indexed_register()
1023 				 RREG32(reg_offset);  in cik_read_register()
1032 		RREG32(mmGRBM_STATUS));  in cik_print_gpu_status_regs()
1034 		RREG32(mmGRBM_STATUS2));  in cik_print_gpu_status_regs()
1036 		RREG32(mmGRBM_STATUS_SE0));  in cik_print_gpu_status_regs()
1038 		RREG32(mmGRBM_STATUS_SE1));  in cik_print_gpu_status_regs()
1040 		RREG32(mmGRBM_STATUS_SE2));  in cik_print_gpu_status_regs()
1042 		RREG32(mmGRBM_STATUS_SE3));  in cik_print_gpu_status_regs()
1044 		RREG32(mmSRBM_STATUS));  in cik_print_gpu_status_regs()
1046 		RREG32(mmSRBM_STATUS2));  in cik_print_gpu_status_regs()
1048 		RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));  in cik_print_gpu_status_regs()
1050 		 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));  in cik_print_gpu_status_regs()
1051 	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));  in cik_print_gpu_status_regs()
1053 		 RREG32(mmCP_STALLED_STAT1));  in cik_print_gpu_status_regs()
1055 		 RREG32(mmCP_STALLED_STAT2));  in cik_print_gpu_status_regs()
1057 		 RREG32(mmCP_STALLED_STAT3));  in cik_print_gpu_status_regs()
1059 		 RREG32(mmCP_CPF_BUSY_STAT));  in cik_print_gpu_status_regs()
1061 		 RREG32(mmCP_CPF_STALLED_STAT1));  in cik_print_gpu_status_regs()
1062 	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));  in cik_print_gpu_status_regs()
1063 	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));  in cik_print_gpu_status_regs()
1065 		 RREG32(mmCP_CPC_STALLED_STAT1));  in cik_print_gpu_status_regs()
1066 	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));  in cik_print_gpu_status_regs()
1084 	tmp = RREG32(mmGRBM_STATUS);  in amdgpu_cik_gpu_check_soft_reset()
1097 	tmp = RREG32(mmGRBM_STATUS2);  in amdgpu_cik_gpu_check_soft_reset()
1102 	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);  in amdgpu_cik_gpu_check_soft_reset()
1107 	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);  in amdgpu_cik_gpu_check_soft_reset()
1112 	tmp = RREG32(mmSRBM_STATUS2);  in amdgpu_cik_gpu_check_soft_reset()
1120 	tmp = RREG32(mmSRBM_STATUS);  in amdgpu_cik_gpu_check_soft_reset()
1171 		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));  in cik_gpu_soft_reset()
1173 		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));  in cik_gpu_soft_reset()
1188 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_soft_reset()
1194 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in cik_gpu_soft_reset()
1244 		tmp = RREG32(mmGRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1248 		tmp = RREG32(mmGRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1254 		tmp = RREG32(mmGRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1258 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1262 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1268 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1289 	save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);  in kv_save_regs_for_reset()
1290 	save->gmcon_misc = RREG32(mmGMCON_MISC);  in kv_save_regs_for_reset()
1291 	save->gmcon_misc3 = RREG32(mmGMCON_MISC3);  in kv_save_regs_for_reset()
1394 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
1398 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
1426 		if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)  in cik_gpu_pci_config_reset()
1438 	u32 tmp = RREG32(mmBIOS_SCRATCH_3);  in cik_set_bios_scratch_engine_hung()
1892 	return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)  in cik_get_rev_id()