Lines Matching refs:RREG32
62 r = RREG32(RADEON_PCIE_DATA); in rv370_pcie_rreg()
337 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { in r300_errata()
349 tmp = RREG32(RADEON_MC_STATUS); in r300_mc_wait_for_idle()
394 tmp = RREG32(R300_DST_PIPE_CONFIG); in r300_gpu_init()
419 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
424 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
428 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
439 RREG32(R_0000F0_RBBM_SOFT_RESET); in r300_asic_reset()
443 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
451 RREG32(R_0000F0_RBBM_SOFT_RESET); in r300_asic_reset()
455 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
480 tmp = RREG32(RADEON_MEM_CNTL); in r300_mc_init()
491 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in r300_mc_init()
1425 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r300_startup()
1456 RREG32(R_000E40_RBBM_STATUS), in r300_resume()
1457 RREG32(R_0007C0_CP_STAT)); in r300_resume()
1537 RREG32(R_000E40_RBBM_STATUS), in r300_init()
1538 RREG32(R_0007C0_CP_STAT)); in r300_init()