60 		return RREG32(mmVCE_RB_RPTR);  in vce_v2_0_ring_get_rptr()
62 		return RREG32(mmVCE_RB_RPTR2);  in vce_v2_0_ring_get_rptr()
77 		return RREG32(mmVCE_RB_WPTR);  in vce_v2_0_ring_get_wptr()
79 		return RREG32(mmVCE_RB_WPTR2);  in vce_v2_0_ring_get_wptr()
143 			status = RREG32(mmVCE_STATUS);  in vce_v2_0_start()
308 		tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_set_sw_cg()
312 		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
316 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
322 		tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_set_sw_cg()
327 		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
332 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
342 	tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_set_dyn_cg()
352 	orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_set_dyn_cg()
358 	orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v2_0_set_dyn_cg()
395 	tmp = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v2_0_init_cg()
401 	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_init_cg()
406 	tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_init_cg()
455 	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);  in vce_v2_0_is_idle()
464 		if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))  in vce_v2_0_wait_for_idle()
487 		 RREG32(mmVCE_STATUS));  in vce_v2_0_print_status()
489 		 RREG32(mmVCE_VCPU_CNTL));  in vce_v2_0_print_status()
491 		 RREG32(mmVCE_VCPU_CACHE_OFFSET0));  in vce_v2_0_print_status()
493 		 RREG32(mmVCE_VCPU_CACHE_SIZE0));  in vce_v2_0_print_status()
495 		 RREG32(mmVCE_VCPU_CACHE_OFFSET1));  in vce_v2_0_print_status()
497 		 RREG32(mmVCE_VCPU_CACHE_SIZE1));  in vce_v2_0_print_status()
499 		 RREG32(mmVCE_VCPU_CACHE_OFFSET2));  in vce_v2_0_print_status()
501 		 RREG32(mmVCE_VCPU_CACHE_SIZE2));  in vce_v2_0_print_status()
503 		 RREG32(mmVCE_SOFT_RESET));  in vce_v2_0_print_status()
505 		 RREG32(mmVCE_RB_BASE_LO2));  in vce_v2_0_print_status()
507 		 RREG32(mmVCE_RB_BASE_HI2));  in vce_v2_0_print_status()
509 		 RREG32(mmVCE_RB_SIZE2));  in vce_v2_0_print_status()
511 		 RREG32(mmVCE_RB_RPTR2));  in vce_v2_0_print_status()
513 		 RREG32(mmVCE_RB_WPTR2));  in vce_v2_0_print_status()
515 		 RREG32(mmVCE_RB_BASE_LO));  in vce_v2_0_print_status()
517 		 RREG32(mmVCE_RB_BASE_HI));  in vce_v2_0_print_status()
519 		 RREG32(mmVCE_RB_SIZE));  in vce_v2_0_print_status()
521 		 RREG32(mmVCE_RB_RPTR));  in vce_v2_0_print_status()
523 		 RREG32(mmVCE_RB_WPTR));  in vce_v2_0_print_status()
525 		 RREG32(mmVCE_CLOCK_GATING_A));  in vce_v2_0_print_status()
527 		 RREG32(mmVCE_CLOCK_GATING_B));  in vce_v2_0_print_status()
529 		 RREG32(mmVCE_CGTT_CLK_OVERRIDE));  in vce_v2_0_print_status()
531 		 RREG32(mmVCE_UENC_CLOCK_GATING));  in vce_v2_0_print_status()
533 		 RREG32(mmVCE_UENC_REG_CLOCK_GATING));  in vce_v2_0_print_status()
535 		 RREG32(mmVCE_SYS_INT_EN));  in vce_v2_0_print_status()
537 		 RREG32(mmVCE_LMI_CTRL2));  in vce_v2_0_print_status()
539 		 RREG32(mmVCE_LMI_CTRL));  in vce_v2_0_print_status()
541 		 RREG32(mmVCE_LMI_VM_CTRL));  in vce_v2_0_print_status()
543 		 RREG32(mmVCE_LMI_SWAP_CNTL));  in vce_v2_0_print_status()
545 		 RREG32(mmVCE_LMI_SWAP_CNTL1));  in vce_v2_0_print_status()
547 		 RREG32(mmVCE_LMI_CACHE_CTRL));  in vce_v2_0_print_status()