1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <drm/drmP.h> 29#include "radeon.h" 30#include "radeon_asic.h" 31#include "radeon_audio.h" 32#include "atom.h" 33#include "rs690d.h" 34 35int rs690_mc_wait_for_idle(struct radeon_device *rdev) 36{ 37 unsigned i; 38 uint32_t tmp; 39 40 for (i = 0; i < rdev->usec_timeout; i++) { 41 /* read MC_STATUS */ 42 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 43 if (G_000090_MC_SYSTEM_IDLE(tmp)) 44 return 0; 45 udelay(1); 46 } 47 return -1; 48} 49 50static void rs690_gpu_init(struct radeon_device *rdev) 51{ 52 /* FIXME: is this correct ? */ 53 r420_pipes_init(rdev); 54 if (rs690_mc_wait_for_idle(rdev)) { 55 printk(KERN_WARNING "Failed to wait MC idle while " 56 "programming pipes. Bad things might happen.\n"); 57 } 58} 59 60union igp_info { 61 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 62 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 63}; 64 65void rs690_pm_info(struct radeon_device *rdev) 66{ 67 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 68 union igp_info *info; 69 uint16_t data_offset; 70 uint8_t frev, crev; 71 fixed20_12 tmp; 72 73 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 74 &frev, &crev, &data_offset)) { 75 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 76 77 /* Get various system informations from bios */ 78 switch (crev) { 79 case 1: 80 tmp.full = dfixed_const(100); 81 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 82 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 83 if (le16_to_cpu(info->info.usK8MemoryClock)) 84 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 85 else if (rdev->clock.default_mclk) { 86 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 87 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 88 } else 89 rdev->pm.igp_system_mclk.full = dfixed_const(400); 90 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 91 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 92 break; 93 case 2: 94 tmp.full = dfixed_const(100); 95 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 96 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 97 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 98 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 99 else if (rdev->clock.default_mclk) 100 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 101 else 102 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 104 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 105 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 106 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 107 break; 108 default: 109 /* We assume the slower possible clock ie worst case */ 110 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 111 rdev->pm.igp_system_mclk.full = dfixed_const(200); 112 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 113 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 114 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 115 break; 116 } 117 } else { 118 /* We assume the slower possible clock ie worst case */ 119 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 120 rdev->pm.igp_system_mclk.full = dfixed_const(200); 121 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 122 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 123 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 124 } 125 /* Compute various bandwidth */ 126 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 127 tmp.full = dfixed_const(4); 128 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 129 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 130 * = ht_clk * ht_width / 5 131 */ 132 tmp.full = dfixed_const(5); 133 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 134 rdev->pm.igp_ht_link_width); 135 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 136 if (tmp.full < rdev->pm.max_bandwidth.full) { 137 /* HT link is a limiting factor */ 138 rdev->pm.max_bandwidth.full = tmp.full; 139 } 140 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 141 * = (sideport_clk * 14) / 10 142 */ 143 tmp.full = dfixed_const(14); 144 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 145 tmp.full = dfixed_const(10); 146 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 147} 148 149static void rs690_mc_init(struct radeon_device *rdev) 150{ 151 u64 base; 152 uint32_t h_addr, l_addr; 153 unsigned long long k8_addr; 154 155 rs400_gart_adjust_size(rdev); 156 rdev->mc.vram_is_ddr = true; 157 rdev->mc.vram_width = 128; 158 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 159 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 160 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 161 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 162 rdev->mc.visible_vram_size = rdev->mc.aper_size; 163 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 164 base = G_000100_MC_FB_START(base) << 16; 165 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 166 /* Some boards seem to be configured for 128MB of sideport memory, 167 * but really only have 64MB. Just skip the sideport and use 168 * UMA memory. 169 */ 170 if (rdev->mc.igp_sideport_enabled && 171 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) { 172 base += 128 * 1024 * 1024; 173 rdev->mc.real_vram_size -= 128 * 1024 * 1024; 174 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 175 } 176 177 /* Use K8 direct mapping for fast fb access. */ 178 rdev->fastfb_working = false; 179 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL)); 180 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION); 181 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 182#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 183 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 184#endif 185 { 186 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 187 * memory is present. 188 */ 189 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 190 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 191 (unsigned long long)rdev->mc.aper_base, k8_addr); 192 rdev->mc.aper_base = (resource_size_t)k8_addr; 193 rdev->fastfb_working = true; 194 } 195 } 196 197 rs690_pm_info(rdev); 198 radeon_vram_location(rdev, &rdev->mc, base); 199 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 200 radeon_gtt_location(rdev, &rdev->mc); 201 radeon_update_bandwidth_info(rdev); 202} 203 204void rs690_line_buffer_adjust(struct radeon_device *rdev, 205 struct drm_display_mode *mode1, 206 struct drm_display_mode *mode2) 207{ 208 u32 tmp; 209 210 /* Guess line buffer size to be 8192 pixels */ 211 u32 lb_size = 8192; 212 213 /* 214 * Line Buffer Setup 215 * There is a single line buffer shared by both display controllers. 216 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 217 * the display controllers. The paritioning can either be done 218 * manually or via one of four preset allocations specified in bits 1:0: 219 * 0 - line buffer is divided in half and shared between crtc 220 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 221 * 2 - D1 gets the whole buffer 222 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 223 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 224 * allocation mode. In manual allocation mode, D1 always starts at 0, 225 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 226 */ 227 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 228 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 229 /* auto */ 230 if (mode1 && mode2) { 231 if (mode1->hdisplay > mode2->hdisplay) { 232 if (mode1->hdisplay > 2560) 233 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 234 else 235 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 236 } else if (mode2->hdisplay > mode1->hdisplay) { 237 if (mode2->hdisplay > 2560) 238 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 239 else 240 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 241 } else 242 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 243 } else if (mode1) { 244 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 245 } else if (mode2) { 246 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 247 } 248 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 249 250 /* Save number of lines the linebuffer leads before the scanout */ 251 if (mode1) 252 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 253 254 if (mode2) 255 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 256} 257 258struct rs690_watermark { 259 u32 lb_request_fifo_depth; 260 fixed20_12 num_line_pair; 261 fixed20_12 estimated_width; 262 fixed20_12 worst_case_latency; 263 fixed20_12 consumption_rate; 264 fixed20_12 active_time; 265 fixed20_12 dbpp; 266 fixed20_12 priority_mark_max; 267 fixed20_12 priority_mark; 268 fixed20_12 sclk; 269}; 270 271static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 272 struct radeon_crtc *crtc, 273 struct rs690_watermark *wm, 274 bool low) 275{ 276 struct drm_display_mode *mode = &crtc->base.mode; 277 fixed20_12 a, b, c; 278 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 279 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 280 fixed20_12 sclk, core_bandwidth, max_bandwidth; 281 u32 selected_sclk; 282 283 if (!crtc->base.enabled) { 284 /* FIXME: wouldn't it better to set priority mark to maximum */ 285 wm->lb_request_fifo_depth = 4; 286 return; 287 } 288 289 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) && 290 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 291 selected_sclk = radeon_dpm_get_sclk(rdev, low); 292 else 293 selected_sclk = rdev->pm.current_sclk; 294 295 /* sclk in Mhz */ 296 a.full = dfixed_const(100); 297 sclk.full = dfixed_const(selected_sclk); 298 sclk.full = dfixed_div(sclk, a); 299 300 /* core_bandwidth = sclk(Mhz) * 16 */ 301 a.full = dfixed_const(16); 302 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 303 304 if (crtc->vsc.full > dfixed_const(2)) 305 wm->num_line_pair.full = dfixed_const(2); 306 else 307 wm->num_line_pair.full = dfixed_const(1); 308 309 b.full = dfixed_const(mode->crtc_hdisplay); 310 c.full = dfixed_const(256); 311 a.full = dfixed_div(b, c); 312 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 313 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 314 if (a.full < dfixed_const(4)) { 315 wm->lb_request_fifo_depth = 4; 316 } else { 317 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 318 } 319 320 /* Determine consumption rate 321 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 322 * vtaps = number of vertical taps, 323 * vsc = vertical scaling ratio, defined as source/destination 324 * hsc = horizontal scaling ration, defined as source/destination 325 */ 326 a.full = dfixed_const(mode->clock); 327 b.full = dfixed_const(1000); 328 a.full = dfixed_div(a, b); 329 pclk.full = dfixed_div(b, a); 330 if (crtc->rmx_type != RMX_OFF) { 331 b.full = dfixed_const(2); 332 if (crtc->vsc.full > b.full) 333 b.full = crtc->vsc.full; 334 b.full = dfixed_mul(b, crtc->hsc); 335 c.full = dfixed_const(2); 336 b.full = dfixed_div(b, c); 337 consumption_time.full = dfixed_div(pclk, b); 338 } else { 339 consumption_time.full = pclk.full; 340 } 341 a.full = dfixed_const(1); 342 wm->consumption_rate.full = dfixed_div(a, consumption_time); 343 344 345 /* Determine line time 346 * LineTime = total time for one line of displayhtotal 347 * LineTime = total number of horizontal pixels 348 * pclk = pixel clock period(ns) 349 */ 350 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 351 line_time.full = dfixed_mul(a, pclk); 352 353 /* Determine active time 354 * ActiveTime = time of active region of display within one line, 355 * hactive = total number of horizontal active pixels 356 * htotal = total number of horizontal pixels 357 */ 358 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 359 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 360 wm->active_time.full = dfixed_mul(line_time, b); 361 wm->active_time.full = dfixed_div(wm->active_time, a); 362 363 /* Maximun bandwidth is the minimun bandwidth of all component */ 364 max_bandwidth = core_bandwidth; 365 if (rdev->mc.igp_sideport_enabled) { 366 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 367 rdev->pm.sideport_bandwidth.full) 368 max_bandwidth = rdev->pm.sideport_bandwidth; 369 read_delay_latency.full = dfixed_const(370 * 800); 370 a.full = dfixed_const(1000); 371 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a); 372 read_delay_latency.full = dfixed_div(read_delay_latency, b); 373 read_delay_latency.full = dfixed_mul(read_delay_latency, a); 374 } else { 375 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && 376 rdev->pm.k8_bandwidth.full) 377 max_bandwidth = rdev->pm.k8_bandwidth; 378 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full && 379 rdev->pm.ht_bandwidth.full) 380 max_bandwidth = rdev->pm.ht_bandwidth; 381 read_delay_latency.full = dfixed_const(5000); 382 } 383 384 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 385 a.full = dfixed_const(16); 386 sclk.full = dfixed_mul(max_bandwidth, a); 387 a.full = dfixed_const(1000); 388 sclk.full = dfixed_div(a, sclk); 389 /* Determine chunk time 390 * ChunkTime = the time it takes the DCP to send one chunk of data 391 * to the LB which consists of pipeline delay and inter chunk gap 392 * sclk = system clock(ns) 393 */ 394 a.full = dfixed_const(256 * 13); 395 chunk_time.full = dfixed_mul(sclk, a); 396 a.full = dfixed_const(10); 397 chunk_time.full = dfixed_div(chunk_time, a); 398 399 /* Determine the worst case latency 400 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 401 * WorstCaseLatency = worst case time from urgent to when the MC starts 402 * to return data 403 * READ_DELAY_IDLE_MAX = constant of 1us 404 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 405 * which consists of pipeline delay and inter chunk gap 406 */ 407 if (dfixed_trunc(wm->num_line_pair) > 1) { 408 a.full = dfixed_const(3); 409 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 410 wm->worst_case_latency.full += read_delay_latency.full; 411 } else { 412 a.full = dfixed_const(2); 413 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 414 wm->worst_case_latency.full += read_delay_latency.full; 415 } 416 417 /* Determine the tolerable latency 418 * TolerableLatency = Any given request has only 1 line time 419 * for the data to be returned 420 * LBRequestFifoDepth = Number of chunk requests the LB can 421 * put into the request FIFO for a display 422 * LineTime = total time for one line of display 423 * ChunkTime = the time it takes the DCP to send one chunk 424 * of data to the LB which consists of 425 * pipeline delay and inter chunk gap 426 */ 427 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 428 tolerable_latency.full = line_time.full; 429 } else { 430 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 431 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 432 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 433 tolerable_latency.full = line_time.full - tolerable_latency.full; 434 } 435 /* We assume worst case 32bits (4 bytes) */ 436 wm->dbpp.full = dfixed_const(4 * 8); 437 438 /* Determine the maximum priority mark 439 * width = viewport width in pixels 440 */ 441 a.full = dfixed_const(16); 442 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 443 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 444 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 445 446 /* Determine estimated width */ 447 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 448 estimated_width.full = dfixed_div(estimated_width, consumption_time); 449 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 450 wm->priority_mark.full = dfixed_const(10); 451 } else { 452 a.full = dfixed_const(16); 453 wm->priority_mark.full = dfixed_div(estimated_width, a); 454 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 455 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 456 } 457} 458 459static void rs690_compute_mode_priority(struct radeon_device *rdev, 460 struct rs690_watermark *wm0, 461 struct rs690_watermark *wm1, 462 struct drm_display_mode *mode0, 463 struct drm_display_mode *mode1, 464 u32 *d1mode_priority_a_cnt, 465 u32 *d2mode_priority_a_cnt) 466{ 467 fixed20_12 priority_mark02, priority_mark12, fill_rate; 468 fixed20_12 a, b; 469 470 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 471 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 472 473 if (mode0 && mode1) { 474 if (dfixed_trunc(wm0->dbpp) > 64) 475 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 476 else 477 a.full = wm0->num_line_pair.full; 478 if (dfixed_trunc(wm1->dbpp) > 64) 479 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 480 else 481 b.full = wm1->num_line_pair.full; 482 a.full += b.full; 483 fill_rate.full = dfixed_div(wm0->sclk, a); 484 if (wm0->consumption_rate.full > fill_rate.full) { 485 b.full = wm0->consumption_rate.full - fill_rate.full; 486 b.full = dfixed_mul(b, wm0->active_time); 487 a.full = dfixed_mul(wm0->worst_case_latency, 488 wm0->consumption_rate); 489 a.full = a.full + b.full; 490 b.full = dfixed_const(16 * 1000); 491 priority_mark02.full = dfixed_div(a, b); 492 } else { 493 a.full = dfixed_mul(wm0->worst_case_latency, 494 wm0->consumption_rate); 495 b.full = dfixed_const(16 * 1000); 496 priority_mark02.full = dfixed_div(a, b); 497 } 498 if (wm1->consumption_rate.full > fill_rate.full) { 499 b.full = wm1->consumption_rate.full - fill_rate.full; 500 b.full = dfixed_mul(b, wm1->active_time); 501 a.full = dfixed_mul(wm1->worst_case_latency, 502 wm1->consumption_rate); 503 a.full = a.full + b.full; 504 b.full = dfixed_const(16 * 1000); 505 priority_mark12.full = dfixed_div(a, b); 506 } else { 507 a.full = dfixed_mul(wm1->worst_case_latency, 508 wm1->consumption_rate); 509 b.full = dfixed_const(16 * 1000); 510 priority_mark12.full = dfixed_div(a, b); 511 } 512 if (wm0->priority_mark.full > priority_mark02.full) 513 priority_mark02.full = wm0->priority_mark.full; 514 if (wm0->priority_mark_max.full > priority_mark02.full) 515 priority_mark02.full = wm0->priority_mark_max.full; 516 if (wm1->priority_mark.full > priority_mark12.full) 517 priority_mark12.full = wm1->priority_mark.full; 518 if (wm1->priority_mark_max.full > priority_mark12.full) 519 priority_mark12.full = wm1->priority_mark_max.full; 520 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 521 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 522 if (rdev->disp_priority == 2) { 523 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 524 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 525 } 526 } else if (mode0) { 527 if (dfixed_trunc(wm0->dbpp) > 64) 528 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair); 529 else 530 a.full = wm0->num_line_pair.full; 531 fill_rate.full = dfixed_div(wm0->sclk, a); 532 if (wm0->consumption_rate.full > fill_rate.full) { 533 b.full = wm0->consumption_rate.full - fill_rate.full; 534 b.full = dfixed_mul(b, wm0->active_time); 535 a.full = dfixed_mul(wm0->worst_case_latency, 536 wm0->consumption_rate); 537 a.full = a.full + b.full; 538 b.full = dfixed_const(16 * 1000); 539 priority_mark02.full = dfixed_div(a, b); 540 } else { 541 a.full = dfixed_mul(wm0->worst_case_latency, 542 wm0->consumption_rate); 543 b.full = dfixed_const(16 * 1000); 544 priority_mark02.full = dfixed_div(a, b); 545 } 546 if (wm0->priority_mark.full > priority_mark02.full) 547 priority_mark02.full = wm0->priority_mark.full; 548 if (wm0->priority_mark_max.full > priority_mark02.full) 549 priority_mark02.full = wm0->priority_mark_max.full; 550 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 551 if (rdev->disp_priority == 2) 552 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 553 } else if (mode1) { 554 if (dfixed_trunc(wm1->dbpp) > 64) 555 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair); 556 else 557 a.full = wm1->num_line_pair.full; 558 fill_rate.full = dfixed_div(wm1->sclk, a); 559 if (wm1->consumption_rate.full > fill_rate.full) { 560 b.full = wm1->consumption_rate.full - fill_rate.full; 561 b.full = dfixed_mul(b, wm1->active_time); 562 a.full = dfixed_mul(wm1->worst_case_latency, 563 wm1->consumption_rate); 564 a.full = a.full + b.full; 565 b.full = dfixed_const(16 * 1000); 566 priority_mark12.full = dfixed_div(a, b); 567 } else { 568 a.full = dfixed_mul(wm1->worst_case_latency, 569 wm1->consumption_rate); 570 b.full = dfixed_const(16 * 1000); 571 priority_mark12.full = dfixed_div(a, b); 572 } 573 if (wm1->priority_mark.full > priority_mark12.full) 574 priority_mark12.full = wm1->priority_mark.full; 575 if (wm1->priority_mark_max.full > priority_mark12.full) 576 priority_mark12.full = wm1->priority_mark_max.full; 577 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 578 if (rdev->disp_priority == 2) 579 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 580 } 581} 582 583void rs690_bandwidth_update(struct radeon_device *rdev) 584{ 585 struct drm_display_mode *mode0 = NULL; 586 struct drm_display_mode *mode1 = NULL; 587 struct rs690_watermark wm0_high, wm0_low; 588 struct rs690_watermark wm1_high, wm1_low; 589 u32 tmp; 590 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; 591 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; 592 593 if (!rdev->mode_info.mode_config_initialized) 594 return; 595 596 radeon_update_display_priority(rdev); 597 598 if (rdev->mode_info.crtcs[0]->base.enabled) 599 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 600 if (rdev->mode_info.crtcs[1]->base.enabled) 601 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 602 /* 603 * Set display0/1 priority up in the memory controller for 604 * modes if the user specifies HIGH for displaypriority 605 * option. 606 */ 607 if ((rdev->disp_priority == 2) && 608 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 609 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 610 tmp &= C_000104_MC_DISP0R_INIT_LAT; 611 tmp &= C_000104_MC_DISP1R_INIT_LAT; 612 if (mode0) 613 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 614 if (mode1) 615 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 616 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 617 } 618 rs690_line_buffer_adjust(rdev, mode0, mode1); 619 620 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 621 WREG32(R_006C9C_DCP_CONTROL, 0); 622 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 623 WREG32(R_006C9C_DCP_CONTROL, 2); 624 625 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); 626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); 627 628 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); 629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); 630 631 tmp = (wm0_high.lb_request_fifo_depth - 1); 632 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16; 633 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 634 635 rs690_compute_mode_priority(rdev, 636 &wm0_high, &wm1_high, 637 mode0, mode1, 638 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); 639 rs690_compute_mode_priority(rdev, 640 &wm0_low, &wm1_low, 641 mode0, mode1, 642 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); 643 644 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 645 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); 646 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 647 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); 648} 649 650uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 651{ 652 unsigned long flags; 653 uint32_t r; 654 655 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 656 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 657 r = RREG32(R_00007C_MC_DATA); 658 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 659 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 660 return r; 661} 662 663void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 664{ 665 unsigned long flags; 666 667 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 668 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 669 S_000078_MC_IND_WR_EN(1)); 670 WREG32(R_00007C_MC_DATA, v); 671 WREG32(R_000078_MC_INDEX, 0x7F); 672 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 673} 674 675static void rs690_mc_program(struct radeon_device *rdev) 676{ 677 struct rv515_mc_save save; 678 679 /* Stops all mc clients */ 680 rv515_mc_stop(rdev, &save); 681 682 /* Wait for mc idle */ 683 if (rs690_mc_wait_for_idle(rdev)) 684 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 685 /* Program MC, should be a 32bits limited address space */ 686 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 687 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 688 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 689 WREG32(R_000134_HDP_FB_LOCATION, 690 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 691 692 rv515_mc_resume(rdev, &save); 693} 694 695static int rs690_startup(struct radeon_device *rdev) 696{ 697 int r; 698 699 rs690_mc_program(rdev); 700 /* Resume clock */ 701 rv515_clock_startup(rdev); 702 /* Initialize GPU configuration (# pipes, ...) */ 703 rs690_gpu_init(rdev); 704 /* Initialize GART (initialize after TTM so we can allocate 705 * memory through TTM but finalize after TTM) */ 706 r = rs400_gart_enable(rdev); 707 if (r) 708 return r; 709 710 /* allocate wb buffer */ 711 r = radeon_wb_init(rdev); 712 if (r) 713 return r; 714 715 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 716 if (r) { 717 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 718 return r; 719 } 720 721 /* Enable IRQ */ 722 if (!rdev->irq.installed) { 723 r = radeon_irq_kms_init(rdev); 724 if (r) 725 return r; 726 } 727 728 rs600_irq_set(rdev); 729 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 730 /* 1M ring buffer */ 731 r = r100_cp_init(rdev, 1024 * 1024); 732 if (r) { 733 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 734 return r; 735 } 736 737 r = radeon_ib_pool_init(rdev); 738 if (r) { 739 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 740 return r; 741 } 742 743 r = radeon_audio_init(rdev); 744 if (r) { 745 dev_err(rdev->dev, "failed initializing audio\n"); 746 return r; 747 } 748 749 return 0; 750} 751 752int rs690_resume(struct radeon_device *rdev) 753{ 754 int r; 755 756 /* Make sur GART are not working */ 757 rs400_gart_disable(rdev); 758 /* Resume clock before doing reset */ 759 rv515_clock_startup(rdev); 760 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 761 if (radeon_asic_reset(rdev)) { 762 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 763 RREG32(R_000E40_RBBM_STATUS), 764 RREG32(R_0007C0_CP_STAT)); 765 } 766 /* post */ 767 atom_asic_init(rdev->mode_info.atom_context); 768 /* Resume clock after posting */ 769 rv515_clock_startup(rdev); 770 /* Initialize surface registers */ 771 radeon_surface_init(rdev); 772 773 rdev->accel_working = true; 774 r = rs690_startup(rdev); 775 if (r) { 776 rdev->accel_working = false; 777 } 778 return r; 779} 780 781int rs690_suspend(struct radeon_device *rdev) 782{ 783 radeon_pm_suspend(rdev); 784 radeon_audio_fini(rdev); 785 r100_cp_disable(rdev); 786 radeon_wb_disable(rdev); 787 rs600_irq_disable(rdev); 788 rs400_gart_disable(rdev); 789 return 0; 790} 791 792void rs690_fini(struct radeon_device *rdev) 793{ 794 radeon_pm_fini(rdev); 795 radeon_audio_fini(rdev); 796 r100_cp_fini(rdev); 797 radeon_wb_fini(rdev); 798 radeon_ib_pool_fini(rdev); 799 radeon_gem_fini(rdev); 800 rs400_gart_fini(rdev); 801 radeon_irq_kms_fini(rdev); 802 radeon_fence_driver_fini(rdev); 803 radeon_bo_fini(rdev); 804 radeon_atombios_fini(rdev); 805 kfree(rdev->bios); 806 rdev->bios = NULL; 807} 808 809int rs690_init(struct radeon_device *rdev) 810{ 811 int r; 812 813 /* Disable VGA */ 814 rv515_vga_render_disable(rdev); 815 /* Initialize scratch registers */ 816 radeon_scratch_init(rdev); 817 /* Initialize surface registers */ 818 radeon_surface_init(rdev); 819 /* restore some register to sane defaults */ 820 r100_restore_sanity(rdev); 821 /* TODO: disable VGA need to use VGA request */ 822 /* BIOS*/ 823 if (!radeon_get_bios(rdev)) { 824 if (ASIC_IS_AVIVO(rdev)) 825 return -EINVAL; 826 } 827 if (rdev->is_atom_bios) { 828 r = radeon_atombios_init(rdev); 829 if (r) 830 return r; 831 } else { 832 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 833 return -EINVAL; 834 } 835 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 836 if (radeon_asic_reset(rdev)) { 837 dev_warn(rdev->dev, 838 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 839 RREG32(R_000E40_RBBM_STATUS), 840 RREG32(R_0007C0_CP_STAT)); 841 } 842 /* check if cards are posted or not */ 843 if (radeon_boot_test_post_card(rdev) == false) 844 return -EINVAL; 845 846 /* Initialize clocks */ 847 radeon_get_clock_info(rdev->ddev); 848 /* initialize memory controller */ 849 rs690_mc_init(rdev); 850 rv515_debugfs(rdev); 851 /* Fence driver */ 852 r = radeon_fence_driver_init(rdev); 853 if (r) 854 return r; 855 /* Memory manager */ 856 r = radeon_bo_init(rdev); 857 if (r) 858 return r; 859 r = rs400_gart_init(rdev); 860 if (r) 861 return r; 862 rs600_set_safe_registers(rdev); 863 864 /* Initialize power management */ 865 radeon_pm_init(rdev); 866 867 rdev->accel_working = true; 868 r = rs690_startup(rdev); 869 if (r) { 870 /* Somethings want wront with the accel init stop accel */ 871 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 872 r100_cp_fini(rdev); 873 radeon_wb_fini(rdev); 874 radeon_ib_pool_fini(rdev); 875 rs400_gart_fini(rdev); 876 radeon_irq_kms_fini(rdev); 877 rdev->accel_working = false; 878 } 879 return 0; 880} 881