Lines Matching refs:RREG32
170 *val = RREG32(reg); in cik_get_allowed_info_register()
187 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
249 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
250 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
261 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
263 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1910 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1914 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in ci_mc_load_microcode()
1933 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1956 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1961 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
3461 data = RREG32(CC_RB_BACKEND_DISABLE); in cik_get_rb_disabled()
3466 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); in cik_get_rb_disabled()
3558 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init()
3679 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in cik_gpu_init()
3680 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in cik_gpu_init()
3775 tmp = RREG32(SPI_CONFIG_CNTL); in cik_gpu_init()
3783 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff; in cik_gpu_init()
3787 tmp = RREG32(DB_DEBUG3) & ~0x0002021c; in cik_gpu_init()
3791 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000; in cik_gpu_init()
3817 tmp = RREG32(HDP_MISC_CNTL); in cik_gpu_init()
3821 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in cik_gpu_init()
3892 tmp = RREG32(scratch); in cik_ring_test()
4230 tmp = RREG32(scratch); in cik_ib_test()
4536 rptr = RREG32(CP_RB0_RPTR); in cik_gfx_get_rptr()
4546 wptr = RREG32(CP_RB0_WPTR); in cik_gfx_get_wptr()
4555 (void)RREG32(CP_RB0_WPTR); in cik_gfx_set_wptr()
4568 rptr = RREG32(CP_HQD_PQ_RPTR); in cik_compute_get_rptr()
4587 wptr = RREG32(CP_HQD_PQ_WPTR); in cik_compute_get_wptr()
4610 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_compute_stop()
4614 if (RREG32(CP_HQD_ACTIVE) & 1) { in cik_compute_stop()
4617 if (!(RREG32(CP_HQD_ACTIVE) & 1)) in cik_compute_stop()
4943 tmp = RREG32(CP_CPF_DEBUG); in cik_cp_compute_resume()
4962 tmp = RREG32(CP_HPD_EOP_CONTROL); in cik_cp_compute_resume()
5023 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_cp_compute_resume()
5029 RREG32(CP_HQD_PQ_DOORBELL_CONTROL); in cik_cp_compute_resume()
5041 if (RREG32(CP_HQD_ACTIVE) & 1) { in cik_cp_compute_resume()
5044 if (!(RREG32(CP_HQD_ACTIVE) & 1)) in cik_cp_compute_resume()
5059 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL); in cik_cp_compute_resume()
5071 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
5115 RREG32(CP_HQD_PQ_DOORBELL_CONTROL); in cik_cp_compute_resume()
5133 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR); in cik_cp_compute_resume()
5209 RREG32(GRBM_STATUS)); in cik_print_gpu_status_regs()
5211 RREG32(GRBM_STATUS2)); in cik_print_gpu_status_regs()
5213 RREG32(GRBM_STATUS_SE0)); in cik_print_gpu_status_regs()
5215 RREG32(GRBM_STATUS_SE1)); in cik_print_gpu_status_regs()
5217 RREG32(GRBM_STATUS_SE2)); in cik_print_gpu_status_regs()
5219 RREG32(GRBM_STATUS_SE3)); in cik_print_gpu_status_regs()
5221 RREG32(SRBM_STATUS)); in cik_print_gpu_status_regs()
5223 RREG32(SRBM_STATUS2)); in cik_print_gpu_status_regs()
5225 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
5227 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
5228 dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT)); in cik_print_gpu_status_regs()
5230 RREG32(CP_STALLED_STAT1)); in cik_print_gpu_status_regs()
5232 RREG32(CP_STALLED_STAT2)); in cik_print_gpu_status_regs()
5234 RREG32(CP_STALLED_STAT3)); in cik_print_gpu_status_regs()
5236 RREG32(CP_CPF_BUSY_STAT)); in cik_print_gpu_status_regs()
5238 RREG32(CP_CPF_STALLED_STAT1)); in cik_print_gpu_status_regs()
5239 dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS)); in cik_print_gpu_status_regs()
5240 dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT)); in cik_print_gpu_status_regs()
5242 RREG32(CP_CPC_STALLED_STAT1)); in cik_print_gpu_status_regs()
5243 dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS)); in cik_print_gpu_status_regs()
5261 tmp = RREG32(GRBM_STATUS); in cik_gpu_check_soft_reset()
5274 tmp = RREG32(GRBM_STATUS2); in cik_gpu_check_soft_reset()
5279 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
5284 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
5289 tmp = RREG32(SRBM_STATUS2); in cik_gpu_check_soft_reset()
5297 tmp = RREG32(SRBM_STATUS); in cik_gpu_check_soft_reset()
5348 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); in cik_gpu_soft_reset()
5350 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); in cik_gpu_soft_reset()
5367 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
5373 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
5422 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5426 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5432 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5436 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5440 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5446 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5467 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE); in kv_save_regs_for_reset()
5468 save->gmcon_misc = RREG32(GMCON_MISC); in kv_save_regs_for_reset()
5469 save->gmcon_misc3 = RREG32(GMCON_MISC3); in kv_save_regs_for_reset()
5570 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5574 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5602 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in cik_gpu_pci_config_reset()
5742 tmp = RREG32(MC_ARB_RAMCFG); in cik_mc_init()
5748 tmp = RREG32(MC_SHARED_CHMAP); in cik_mc_init()
5784 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in cik_mc_init()
5785 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in cik_mc_init()
5925 u32 tmp = RREG32(CHUB_CONTROL); in cik_pcie_gart_enable()
5977 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in cik_pcie_gart_disable()
6053 u64 tmp = RREG32(MC_VM_FB_OFFSET); in cik_vm_init()
6193 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
6206 tmp = RREG32(RLC_LB_CNTL); in cik_enable_lbpw()
6224 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0) in cik_wait_for_rlc_serdes()
6235 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in cik_wait_for_rlc_serdes()
6245 tmp = RREG32(RLC_CNTL); in cik_update_rlc()
6254 orig = data = RREG32(RLC_CNTL); in cik_halt_rlc()
6263 if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0) in cik_halt_rlc()
6283 if ((RREG32(RLC_GPM_STAT) & mask) == mask) in cik_enter_rlc_safe_mode()
6289 if ((RREG32(RLC_GPR_REG2) & REQ) == 0) in cik_enter_rlc_safe_mode()
6354 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc; in cik_rlc_resume()
6431 orig = data = RREG32(RLC_CGCG_CGLS_CTRL); in cik_enable_cgcg()
6452 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6453 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6454 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6455 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6472 orig = data = RREG32(CP_MEM_SLP_CNTL); in cik_enable_mgcg()
6479 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in cik_enable_mgcg()
6498 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6513 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in cik_enable_mgcg()
6518 data = RREG32(RLC_MEM_SLP_CNTL); in cik_enable_mgcg()
6524 data = RREG32(CP_MEM_SLP_CNTL); in cik_enable_mgcg()
6530 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6569 orig = data = RREG32(mc_cg_registers[i]); in cik_enable_mc_ls()
6586 orig = data = RREG32(mc_cg_registers[i]); in cik_enable_mc_mgcg()
6605 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6610 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6623 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6628 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6633 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6638 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6655 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6664 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6694 orig = data = RREG32(HDP_HOST_PATH_CNTL); in cik_enable_hdp_mgcg()
6710 orig = data = RREG32(HDP_MEM_POWER_LS); in cik_enable_hdp_ls()
6800 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pu()
6814 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pd()
6827 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_cp_pg()
6840 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gds_pg()
6943 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6948 orig = data = RREG32(RLC_AUTO_PG_CTRL); in cik_enable_gfx_cgpg()
6953 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6958 orig = data = RREG32(RLC_AUTO_PG_CTRL); in cik_enable_gfx_cgpg()
6963 data = RREG32(DB_RENDER_CONTROL); in cik_enable_gfx_cgpg()
6974 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in cik_get_cu_active_bitmap()
6975 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); in cik_get_cu_active_bitmap()
7019 tmp = RREG32(RLC_MAX_PG_CU); in cik_init_ao_cu_mask()
7030 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_static_mgpg()
7044 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_dynamic_mgpg()
7077 orig = data = RREG32(RLC_PG_CNTL); in cik_init_gfx_cgpg()
7085 data = RREG32(CP_RB_WPTR_POLL_CNTL); in cik_init_gfx_cgpg()
7093 data = RREG32(RLC_PG_DELAY_2); in cik_init_gfx_cgpg()
7098 data = RREG32(RLC_AUTO_PG_CTRL); in cik_init_gfx_cgpg()
7259 u32 ih_cntl = RREG32(IH_CNTL); in cik_enable_interrupts()
7260 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts()
7278 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts()
7279 u32 ih_cntl = RREG32(IH_CNTL); in cik_disable_interrupts()
7304 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
7308 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
7310 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
7354 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7356 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7358 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7360 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7362 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7364 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7404 interrupt_cntl = RREG32(INTERRUPT_CNTL); in cik_irq_init()
7481 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7485 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7486 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7487 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7488 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7489 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7490 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7492 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7493 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7495 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7647 RREG32(SRBM_STATUS); in cik_irq_set()
7665 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7666 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in cik_irq_ack()
7667 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in cik_irq_ack()
7668 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in cik_irq_ack()
7669 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in cik_irq_ack()
7670 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in cik_irq_ack()
7671 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); in cik_irq_ack()
7673 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7675 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7678 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7680 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7684 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7686 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7740 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7745 tmp = RREG32(DC_HPD2_INT_CONTROL); in cik_irq_ack()
7750 tmp = RREG32(DC_HPD3_INT_CONTROL); in cik_irq_ack()
7755 tmp = RREG32(DC_HPD4_INT_CONTROL); in cik_irq_ack()
7760 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7765 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7770 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7775 tmp = RREG32(DC_HPD2_INT_CONTROL); in cik_irq_ack()
7780 tmp = RREG32(DC_HPD3_INT_CONTROL); in cik_irq_ack()
7785 tmp = RREG32(DC_HPD4_INT_CONTROL); in cik_irq_ack()
7790 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7795 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7864 wptr = RREG32(IH_RB_WPTR); in cik_get_ih_wptr()
7875 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr()
8266 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in cik_irq_process()
8275 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in cik_irq_process()
8276 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in cik_irq_process()
8277 mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); in cik_irq_process()
9133 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
9166 u32 tmp = RREG32(MC_SHARED_CHMAP); in cik_get_number_of_dram_channels()
9635 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks()
9644 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks()
9704 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | in cik_get_gpu_clock_counter()
9705 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in cik_get_gpu_clock_counter()