647 		tmp = RREG32(scratch);  in gfx_v8_0_ring_test_ring()
703 		tmp = RREG32(scratch);  in gfx_v8_0_ring_test_ib()
1134 	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);  in gfx_v8_0_gpu_early_init()
1135 	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);  in gfx_v8_0_gpu_early_init()
1142 		tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);  in gfx_v8_0_gpu_early_init()
1146 		tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);  in gfx_v8_0_gpu_early_init()
2766 	data = RREG32(mmCC_RB_BACKEND_DISABLE);  in gfx_v8_0_get_rb_disabled()
2769 	data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);  in gfx_v8_0_get_rb_disabled()
2895 	tmp = RREG32(mmGRBM_CNTL);  in gfx_v8_0_gpu_init()
2975 				if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)  in gfx_v8_0_wait_for_rlc_serdes()
2989 		if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)  in gfx_v8_0_wait_for_rlc_serdes()
2998 	u32 tmp = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_enable_gui_idle_interrupt()
3016 	u32 tmp = RREG32(mmRLC_CNTL);  in gfx_v8_0_rlc_stop()
3028 	u32 tmp = RREG32(mmGRBM_SOFT_RESET);  in gfx_v8_0_rlc_reset()
3040 	u32 tmp = RREG32(mmRLC_CNTL);  in gfx_v8_0_rlc_start()
3110 	u32 tmp = RREG32(mmCP_ME_CNTL);  in gfx_v8_0_cp_gfx_enable()
3341 		tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);  in gfx_v8_0_cp_gfx_resume()
3757 		tmp = RREG32(mmCP_HQD_EOP_CONTROL);  in gfx_v8_0_cp_compute_resume()
3818 		tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);  in gfx_v8_0_cp_compute_resume()
3823 			RREG32(mmCP_HQD_EOP_BASE_ADDR);  in gfx_v8_0_cp_compute_resume()
3825 			RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);  in gfx_v8_0_cp_compute_resume()
3828 		tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);  in gfx_v8_0_cp_compute_resume()
3841 		if (RREG32(mmCP_HQD_ACTIVE) & 1) {  in gfx_v8_0_cp_compute_resume()
3844 				if (!(RREG32(mmCP_HQD_ACTIVE) & 1))  in gfx_v8_0_cp_compute_resume()
3860 		tmp = RREG32(mmCP_MQD_CONTROL);  in gfx_v8_0_cp_compute_resume()
3873 		tmp = RREG32(mmCP_HQD_PQ_CONTROL);  in gfx_v8_0_cp_compute_resume()
3916 			tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);  in gfx_v8_0_cp_compute_resume()
3934 		mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v8_0_cp_compute_resume()
3940 		tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);  in gfx_v8_0_cp_compute_resume()
3957 		tmp = RREG32(mmCP_PQ_STATUS);  in gfx_v8_0_cp_compute_resume()
4084 	if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))  in gfx_v8_0_is_idle()
4098 		tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;  in gfx_v8_0_wait_for_idle()
4114 		 RREG32(mmGRBM_STATUS));  in gfx_v8_0_print_status()
4116 		 RREG32(mmGRBM_STATUS2));  in gfx_v8_0_print_status()
4118 		 RREG32(mmGRBM_STATUS_SE0));  in gfx_v8_0_print_status()
4120 		 RREG32(mmGRBM_STATUS_SE1));  in gfx_v8_0_print_status()
4122 		 RREG32(mmGRBM_STATUS_SE2));  in gfx_v8_0_print_status()
4124 		 RREG32(mmGRBM_STATUS_SE3));  in gfx_v8_0_print_status()
4125 	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));  in gfx_v8_0_print_status()
4127 		 RREG32(mmCP_STALLED_STAT1));  in gfx_v8_0_print_status()
4129 		 RREG32(mmCP_STALLED_STAT2));  in gfx_v8_0_print_status()
4131 		 RREG32(mmCP_STALLED_STAT3));  in gfx_v8_0_print_status()
4133 		 RREG32(mmCP_CPF_BUSY_STAT));  in gfx_v8_0_print_status()
4135 		 RREG32(mmCP_CPF_STALLED_STAT1));  in gfx_v8_0_print_status()
4136 	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));  in gfx_v8_0_print_status()
4137 	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));  in gfx_v8_0_print_status()
4139 		 RREG32(mmCP_CPC_STALLED_STAT1));  in gfx_v8_0_print_status()
4140 	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));  in gfx_v8_0_print_status()
4144 			 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));  in gfx_v8_0_print_status()
4148 			 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));  in gfx_v8_0_print_status()
4154 			 RREG32(mmPA_SC_RASTER_CONFIG));  in gfx_v8_0_print_status()
4156 			 RREG32(mmPA_SC_RASTER_CONFIG_1));  in gfx_v8_0_print_status()
4161 		 RREG32(mmGB_ADDR_CONFIG));  in gfx_v8_0_print_status()
4163 		 RREG32(mmHDP_ADDR_CONFIG));  in gfx_v8_0_print_status()
4165 		 RREG32(mmDMIF_ADDR_CALC));  in gfx_v8_0_print_status()
4167 		 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));  in gfx_v8_0_print_status()
4169 		 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));  in gfx_v8_0_print_status()
4171 		 RREG32(mmUVD_UDEC_ADDR_CONFIG));  in gfx_v8_0_print_status()
4173 		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));  in gfx_v8_0_print_status()
4175 		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));  in gfx_v8_0_print_status()
4178 		 RREG32(mmCP_MEQ_THRESHOLDS));  in gfx_v8_0_print_status()
4180 		 RREG32(mmSX_DEBUG_1));  in gfx_v8_0_print_status()
4182 		 RREG32(mmTA_CNTL_AUX));  in gfx_v8_0_print_status()
4184 		 RREG32(mmSPI_CONFIG_CNTL));  in gfx_v8_0_print_status()
4186 		 RREG32(mmSQ_CONFIG));  in gfx_v8_0_print_status()
4188 		 RREG32(mmDB_DEBUG));  in gfx_v8_0_print_status()
4190 		 RREG32(mmDB_DEBUG2));  in gfx_v8_0_print_status()
4192 		 RREG32(mmDB_DEBUG3));  in gfx_v8_0_print_status()
4194 		 RREG32(mmCB_HW_CONTROL));  in gfx_v8_0_print_status()
4196 		 RREG32(mmSPI_CONFIG_CNTL_1));  in gfx_v8_0_print_status()
4198 		 RREG32(mmPA_SC_FIFO_SIZE));  in gfx_v8_0_print_status()
4200 		 RREG32(mmVGT_NUM_INSTANCES));  in gfx_v8_0_print_status()
4202 		 RREG32(mmCP_PERFMON_CNTL));  in gfx_v8_0_print_status()
4204 		 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));  in gfx_v8_0_print_status()
4206 		 RREG32(mmVGT_CACHE_INVALIDATION));  in gfx_v8_0_print_status()
4208 		 RREG32(mmVGT_GS_VERTEX_REUSE));  in gfx_v8_0_print_status()
4210 		 RREG32(mmPA_SC_LINE_STIPPLE_STATE));  in gfx_v8_0_print_status()
4212 		 RREG32(mmPA_CL_ENHANCE));  in gfx_v8_0_print_status()
4214 		 RREG32(mmPA_SC_ENHANCE));  in gfx_v8_0_print_status()
4217 		 RREG32(mmCP_ME_CNTL));  in gfx_v8_0_print_status()
4219 		 RREG32(mmCP_MAX_CONTEXT));  in gfx_v8_0_print_status()
4221 		 RREG32(mmCP_ENDIAN_SWAP));  in gfx_v8_0_print_status()
4223 		 RREG32(mmCP_DEVICE_ID));  in gfx_v8_0_print_status()
4226 		 RREG32(mmCP_SEM_WAIT_TIMER));  in gfx_v8_0_print_status()
4229 		 RREG32(mmCP_RB_WPTR_DELAY));  in gfx_v8_0_print_status()
4231 		 RREG32(mmCP_RB_VMID));  in gfx_v8_0_print_status()
4233 		 RREG32(mmCP_RB0_CNTL));  in gfx_v8_0_print_status()
4235 		 RREG32(mmCP_RB0_WPTR));  in gfx_v8_0_print_status()
4237 		 RREG32(mmCP_RB0_RPTR_ADDR));  in gfx_v8_0_print_status()
4239 		 RREG32(mmCP_RB0_RPTR_ADDR_HI));  in gfx_v8_0_print_status()
4241 		 RREG32(mmCP_RB0_CNTL));  in gfx_v8_0_print_status()
4243 		 RREG32(mmCP_RB0_BASE));  in gfx_v8_0_print_status()
4245 		 RREG32(mmCP_RB0_BASE_HI));  in gfx_v8_0_print_status()
4247 		 RREG32(mmCP_MEC_CNTL));  in gfx_v8_0_print_status()
4249 		 RREG32(mmCP_CPF_DEBUG));  in gfx_v8_0_print_status()
4252 		 RREG32(mmSCRATCH_ADDR));  in gfx_v8_0_print_status()
4254 		 RREG32(mmSCRATCH_UMSK));  in gfx_v8_0_print_status()
4257 		 RREG32(mmCP_INT_CNTL_RING0));  in gfx_v8_0_print_status()
4259 		 RREG32(mmRLC_LB_CNTL));  in gfx_v8_0_print_status()
4261 		 RREG32(mmRLC_CNTL));  in gfx_v8_0_print_status()
4263 		 RREG32(mmRLC_CGCG_CGLS_CTRL));  in gfx_v8_0_print_status()
4265 		 RREG32(mmRLC_LB_CNTR_INIT));  in gfx_v8_0_print_status()
4267 		 RREG32(mmRLC_LB_CNTR_MAX));  in gfx_v8_0_print_status()
4269 		 RREG32(mmRLC_LB_INIT_CU_MASK));  in gfx_v8_0_print_status()
4271 		 RREG32(mmRLC_LB_PARAMS));  in gfx_v8_0_print_status()
4273 		 RREG32(mmRLC_LB_CNTL));  in gfx_v8_0_print_status()
4275 		 RREG32(mmRLC_MC_CNTL));  in gfx_v8_0_print_status()
4277 		 RREG32(mmRLC_UCODE_CNTL));  in gfx_v8_0_print_status()
4284 			 RREG32(mmSH_MEM_CONFIG));  in gfx_v8_0_print_status()
4286 			 RREG32(mmSH_MEM_APE1_BASE));  in gfx_v8_0_print_status()
4288 			 RREG32(mmSH_MEM_APE1_LIMIT));  in gfx_v8_0_print_status()
4290 			 RREG32(mmSH_MEM_BASES));  in gfx_v8_0_print_status()
4303 	tmp = RREG32(mmGRBM_STATUS);  in gfx_v8_0_soft_reset()
4324 	tmp = RREG32(mmGRBM_STATUS2);  in gfx_v8_0_soft_reset()
4330 	tmp = RREG32(mmSRBM_STATUS);  in gfx_v8_0_soft_reset()
4347 			tmp = RREG32(mmGRBM_SOFT_RESET);  in gfx_v8_0_soft_reset()
4351 			tmp = RREG32(mmGRBM_SOFT_RESET);  in gfx_v8_0_soft_reset()
4357 			tmp = RREG32(mmGRBM_SOFT_RESET);  in gfx_v8_0_soft_reset()
4361 			tmp = RREG32(mmSRBM_SOFT_RESET);  in gfx_v8_0_soft_reset()
4365 			tmp = RREG32(mmSRBM_SOFT_RESET);  in gfx_v8_0_soft_reset()
4371 			tmp = RREG32(mmSRBM_SOFT_RESET);  in gfx_v8_0_soft_reset()
4394 	clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |  in gfx_v8_0_get_gpu_clock_counter()
4395 		((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);  in gfx_v8_0_get_gpu_clock_counter()
4491 		wptr = RREG32(mmCP_RB0_WPTR);  in gfx_v8_0_ring_get_wptr_gfx()
4506 		(void)RREG32(mmCP_RB0_WPTR);  in gfx_v8_0_ring_set_wptr_gfx()
4793 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_set_gfx_eop_interrupt_state()
4799 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_set_gfx_eop_interrupt_state()
4838 		mec_int_cntl = RREG32(mec_int_cntl_reg);  in gfx_v8_0_set_compute_eop_interrupt_state()
4844 		mec_int_cntl = RREG32(mec_int_cntl_reg);  in gfx_v8_0_set_compute_eop_interrupt_state()
4863 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_set_priv_reg_fault_state()
4869 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_set_priv_reg_fault_state()
4890 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_set_priv_inst_fault_state()
4896 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);  in gfx_v8_0_set_priv_inst_fault_state()
5087 	adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);  in gfx_v8_0_set_gds_init()
5119 	tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);  in gfx_v8_0_get_cu_active_bitmap()
5120 	tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);  in gfx_v8_0_get_cu_active_bitmap()