Lines Matching refs:RREG32
1922 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_disabled()
1928 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_disabled()
2170 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); in gfx_v7_0_gpu_init()
2171 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_init()
2178 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_init()
2182 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_init()
2279 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_gpu_init()
2287 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_gpu_init()
2291 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_gpu_init()
2295 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_gpu_init()
2394 tmp = RREG32(scratch); in gfx_v7_0_ring_test_ring()
2686 tmp = RREG32(scratch); in gfx_v7_0_ring_test_ib()
3004 wptr = RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
3014 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
3338 tmp = RREG32(mmCP_CPF_DEBUG); in gfx_v7_0_cp_compute_resume()
3360 tmp = RREG32(mmCP_HPD_EOP_CONTROL); in gfx_v7_0_cp_compute_resume()
3419 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); in gfx_v7_0_cp_compute_resume()
3425 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_cp_compute_resume()
3437 if (RREG32(mmCP_HQD_ACTIVE) & 1) { in gfx_v7_0_cp_compute_resume()
3440 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) in gfx_v7_0_cp_compute_resume()
3455 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); in gfx_v7_0_cp_compute_resume()
3467 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_cp_compute_resume()
3510 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_cp_compute_resume()
3532 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_cp_compute_resume()
3580 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3907 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3925 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3939 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3949 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3958 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3967 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3988 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) in gfx_v7_0_enter_rlc_safe_mode()
3994 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_enter_rlc_safe_mode()
4042 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset()
4080 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
4123 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
4146 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
4147 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
4148 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
4149 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
4166 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
4173 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
4193 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
4208 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
4213 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
4219 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
4225 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
4264 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
4278 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
4291 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
4304 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
4387 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
4392 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
4397 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
4402 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
4407 data = RREG32(mmDB_RENDER_CONTROL); in gfx_v7_0_enable_gfx_cgpg()
4418 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
4419 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
4446 tmp = RREG32(mmRLC_MAX_PG_CU); in gfx_v7_0_init_ao_cu_mask()
4457 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_static_mgpg()
4471 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_dynamic_mgpg()
4504 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_init_gfx_cgpg()
4512 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
4520 data = RREG32(mmRLC_PG_DELAY_2); in gfx_v7_0_init_gfx_cgpg()
4525 data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_init_gfx_cgpg()
4687 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v7_0_get_gpu_clock_counter()
4688 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v7_0_get_gpu_clock_counter()
4931 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) in gfx_v7_0_is_idle()
4945 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; in gfx_v7_0_wait_for_idle()
4961 RREG32(mmGRBM_STATUS)); in gfx_v7_0_print_status()
4963 RREG32(mmGRBM_STATUS2)); in gfx_v7_0_print_status()
4965 RREG32(mmGRBM_STATUS_SE0)); in gfx_v7_0_print_status()
4967 RREG32(mmGRBM_STATUS_SE1)); in gfx_v7_0_print_status()
4969 RREG32(mmGRBM_STATUS_SE2)); in gfx_v7_0_print_status()
4971 RREG32(mmGRBM_STATUS_SE3)); in gfx_v7_0_print_status()
4972 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); in gfx_v7_0_print_status()
4974 RREG32(mmCP_STALLED_STAT1)); in gfx_v7_0_print_status()
4976 RREG32(mmCP_STALLED_STAT2)); in gfx_v7_0_print_status()
4978 RREG32(mmCP_STALLED_STAT3)); in gfx_v7_0_print_status()
4980 RREG32(mmCP_CPF_BUSY_STAT)); in gfx_v7_0_print_status()
4982 RREG32(mmCP_CPF_STALLED_STAT1)); in gfx_v7_0_print_status()
4983 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); in gfx_v7_0_print_status()
4984 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); in gfx_v7_0_print_status()
4986 RREG32(mmCP_CPC_STALLED_STAT1)); in gfx_v7_0_print_status()
4987 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); in gfx_v7_0_print_status()
4991 i, RREG32(mmGB_TILE_MODE0 + (i * 4))); in gfx_v7_0_print_status()
4995 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); in gfx_v7_0_print_status()
5001 RREG32(mmPA_SC_RASTER_CONFIG)); in gfx_v7_0_print_status()
5003 RREG32(mmPA_SC_RASTER_CONFIG_1)); in gfx_v7_0_print_status()
5008 RREG32(mmGB_ADDR_CONFIG)); in gfx_v7_0_print_status()
5010 RREG32(mmHDP_ADDR_CONFIG)); in gfx_v7_0_print_status()
5012 RREG32(mmDMIF_ADDR_CALC)); in gfx_v7_0_print_status()
5014 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); in gfx_v7_0_print_status()
5016 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); in gfx_v7_0_print_status()
5018 RREG32(mmUVD_UDEC_ADDR_CONFIG)); in gfx_v7_0_print_status()
5020 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); in gfx_v7_0_print_status()
5022 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); in gfx_v7_0_print_status()
5025 RREG32(mmCP_MEQ_THRESHOLDS)); in gfx_v7_0_print_status()
5027 RREG32(mmSX_DEBUG_1)); in gfx_v7_0_print_status()
5029 RREG32(mmTA_CNTL_AUX)); in gfx_v7_0_print_status()
5031 RREG32(mmSPI_CONFIG_CNTL)); in gfx_v7_0_print_status()
5033 RREG32(mmSQ_CONFIG)); in gfx_v7_0_print_status()
5035 RREG32(mmDB_DEBUG)); in gfx_v7_0_print_status()
5037 RREG32(mmDB_DEBUG2)); in gfx_v7_0_print_status()
5039 RREG32(mmDB_DEBUG3)); in gfx_v7_0_print_status()
5041 RREG32(mmCB_HW_CONTROL)); in gfx_v7_0_print_status()
5043 RREG32(mmSPI_CONFIG_CNTL_1)); in gfx_v7_0_print_status()
5045 RREG32(mmPA_SC_FIFO_SIZE)); in gfx_v7_0_print_status()
5047 RREG32(mmVGT_NUM_INSTANCES)); in gfx_v7_0_print_status()
5049 RREG32(mmCP_PERFMON_CNTL)); in gfx_v7_0_print_status()
5051 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); in gfx_v7_0_print_status()
5053 RREG32(mmVGT_CACHE_INVALIDATION)); in gfx_v7_0_print_status()
5055 RREG32(mmVGT_GS_VERTEX_REUSE)); in gfx_v7_0_print_status()
5057 RREG32(mmPA_SC_LINE_STIPPLE_STATE)); in gfx_v7_0_print_status()
5059 RREG32(mmPA_CL_ENHANCE)); in gfx_v7_0_print_status()
5061 RREG32(mmPA_SC_ENHANCE)); in gfx_v7_0_print_status()
5064 RREG32(mmCP_ME_CNTL)); in gfx_v7_0_print_status()
5066 RREG32(mmCP_MAX_CONTEXT)); in gfx_v7_0_print_status()
5068 RREG32(mmCP_ENDIAN_SWAP)); in gfx_v7_0_print_status()
5070 RREG32(mmCP_DEVICE_ID)); in gfx_v7_0_print_status()
5073 RREG32(mmCP_SEM_WAIT_TIMER)); in gfx_v7_0_print_status()
5076 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL)); in gfx_v7_0_print_status()
5079 RREG32(mmCP_RB_WPTR_DELAY)); in gfx_v7_0_print_status()
5081 RREG32(mmCP_RB_VMID)); in gfx_v7_0_print_status()
5083 RREG32(mmCP_RB0_CNTL)); in gfx_v7_0_print_status()
5085 RREG32(mmCP_RB0_WPTR)); in gfx_v7_0_print_status()
5087 RREG32(mmCP_RB0_RPTR_ADDR)); in gfx_v7_0_print_status()
5089 RREG32(mmCP_RB0_RPTR_ADDR_HI)); in gfx_v7_0_print_status()
5091 RREG32(mmCP_RB0_CNTL)); in gfx_v7_0_print_status()
5093 RREG32(mmCP_RB0_BASE)); in gfx_v7_0_print_status()
5095 RREG32(mmCP_RB0_BASE_HI)); in gfx_v7_0_print_status()
5097 RREG32(mmCP_MEC_CNTL)); in gfx_v7_0_print_status()
5099 RREG32(mmCP_CPF_DEBUG)); in gfx_v7_0_print_status()
5102 RREG32(mmSCRATCH_ADDR)); in gfx_v7_0_print_status()
5104 RREG32(mmSCRATCH_UMSK)); in gfx_v7_0_print_status()
5116 RREG32(mmCP_HPD_EOP_BASE_ADDR)); in gfx_v7_0_print_status()
5118 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI)); in gfx_v7_0_print_status()
5120 RREG32(mmCP_HPD_EOP_VMID)); in gfx_v7_0_print_status()
5122 RREG32(mmCP_HPD_EOP_CONTROL)); in gfx_v7_0_print_status()
5128 RREG32(mmCP_PQ_WPTR_POLL_CNTL)); in gfx_v7_0_print_status()
5130 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); in gfx_v7_0_print_status()
5132 RREG32(mmCP_HQD_ACTIVE)); in gfx_v7_0_print_status()
5134 RREG32(mmCP_HQD_DEQUEUE_REQUEST)); in gfx_v7_0_print_status()
5136 RREG32(mmCP_HQD_PQ_RPTR)); in gfx_v7_0_print_status()
5138 RREG32(mmCP_HQD_PQ_WPTR)); in gfx_v7_0_print_status()
5140 RREG32(mmCP_HQD_PQ_BASE)); in gfx_v7_0_print_status()
5142 RREG32(mmCP_HQD_PQ_BASE_HI)); in gfx_v7_0_print_status()
5144 RREG32(mmCP_HQD_PQ_CONTROL)); in gfx_v7_0_print_status()
5146 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR)); in gfx_v7_0_print_status()
5148 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)); in gfx_v7_0_print_status()
5150 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR)); in gfx_v7_0_print_status()
5152 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)); in gfx_v7_0_print_status()
5154 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); in gfx_v7_0_print_status()
5156 RREG32(mmCP_HQD_PQ_WPTR)); in gfx_v7_0_print_status()
5158 RREG32(mmCP_HQD_VMID)); in gfx_v7_0_print_status()
5160 RREG32(mmCP_MQD_BASE_ADDR)); in gfx_v7_0_print_status()
5162 RREG32(mmCP_MQD_BASE_ADDR_HI)); in gfx_v7_0_print_status()
5164 RREG32(mmCP_MQD_CONTROL)); in gfx_v7_0_print_status()
5171 RREG32(mmCP_INT_CNTL_RING0)); in gfx_v7_0_print_status()
5173 RREG32(mmRLC_LB_CNTL)); in gfx_v7_0_print_status()
5175 RREG32(mmRLC_CNTL)); in gfx_v7_0_print_status()
5177 RREG32(mmRLC_CGCG_CGLS_CTRL)); in gfx_v7_0_print_status()
5179 RREG32(mmRLC_LB_CNTR_INIT)); in gfx_v7_0_print_status()
5181 RREG32(mmRLC_LB_CNTR_MAX)); in gfx_v7_0_print_status()
5183 RREG32(mmRLC_LB_INIT_CU_MASK)); in gfx_v7_0_print_status()
5185 RREG32(mmRLC_LB_PARAMS)); in gfx_v7_0_print_status()
5187 RREG32(mmRLC_LB_CNTL)); in gfx_v7_0_print_status()
5189 RREG32(mmRLC_MC_CNTL)); in gfx_v7_0_print_status()
5191 RREG32(mmRLC_UCODE_CNTL)); in gfx_v7_0_print_status()
5195 RREG32(mmRLC_DRIVER_CPDMA_STATUS)); in gfx_v7_0_print_status()
5202 RREG32(mmSH_MEM_CONFIG)); in gfx_v7_0_print_status()
5204 RREG32(mmSH_MEM_APE1_BASE)); in gfx_v7_0_print_status()
5206 RREG32(mmSH_MEM_APE1_LIMIT)); in gfx_v7_0_print_status()
5208 RREG32(mmSH_MEM_BASES)); in gfx_v7_0_print_status()
5221 tmp = RREG32(mmGRBM_STATUS); in gfx_v7_0_soft_reset()
5237 tmp = RREG32(mmGRBM_STATUS2); in gfx_v7_0_soft_reset()
5242 tmp = RREG32(mmSRBM_STATUS); in gfx_v7_0_soft_reset()
5262 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5266 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5272 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5276 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5280 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5286 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5302 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
5307 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
5344 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
5349 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
5367 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
5372 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
5392 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
5397 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
5630 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()