51 	return RREG32(mmUVD_RBC_RB_RPTR);  in uvd_v5_0_ring_get_rptr()
65 	return RREG32(mmUVD_RBC_RB_WPTR);  in uvd_v5_0_ring_get_wptr()
366 			status = RREG32(mmUVD_STATUS);  in uvd_v5_0_start()
420 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);  in uvd_v5_0_start()
537 		tmp = RREG32(mmUVD_CONTEXT_ID);  in uvd_v5_0_ring_test_ring()
620 	return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);  in uvd_v5_0_is_idle()
629 		if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))  in uvd_v5_0_wait_for_idle()
653 		 RREG32(mmUVD_SEMA_ADDR_LOW));  in uvd_v5_0_print_status()
655 		 RREG32(mmUVD_SEMA_ADDR_HIGH));  in uvd_v5_0_print_status()
657 		 RREG32(mmUVD_SEMA_CMD));  in uvd_v5_0_print_status()
659 		 RREG32(mmUVD_GPCOM_VCPU_CMD));  in uvd_v5_0_print_status()
661 		 RREG32(mmUVD_GPCOM_VCPU_DATA0));  in uvd_v5_0_print_status()
663 		 RREG32(mmUVD_GPCOM_VCPU_DATA1));  in uvd_v5_0_print_status()
665 		 RREG32(mmUVD_ENGINE_CNTL));  in uvd_v5_0_print_status()
667 		 RREG32(mmUVD_UDEC_ADDR_CONFIG));  in uvd_v5_0_print_status()
669 		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));  in uvd_v5_0_print_status()
671 		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));  in uvd_v5_0_print_status()
673 		 RREG32(mmUVD_SEMA_CNTL));  in uvd_v5_0_print_status()
675 		 RREG32(mmUVD_LMI_EXT40_ADDR));  in uvd_v5_0_print_status()
677 		 RREG32(mmUVD_CTX_INDEX));  in uvd_v5_0_print_status()
679 		 RREG32(mmUVD_CTX_DATA));  in uvd_v5_0_print_status()
681 		 RREG32(mmUVD_CGC_GATE));  in uvd_v5_0_print_status()
683 		 RREG32(mmUVD_CGC_CTRL));  in uvd_v5_0_print_status()
685 		 RREG32(mmUVD_LMI_CTRL2));  in uvd_v5_0_print_status()
687 		 RREG32(mmUVD_MASTINT_EN));  in uvd_v5_0_print_status()
689 		 RREG32(mmUVD_LMI_ADDR_EXT));  in uvd_v5_0_print_status()
691 		 RREG32(mmUVD_LMI_CTRL));  in uvd_v5_0_print_status()
693 		 RREG32(mmUVD_LMI_SWAP_CNTL));  in uvd_v5_0_print_status()
695 		 RREG32(mmUVD_MP_SWAP_CNTL));  in uvd_v5_0_print_status()
697 		 RREG32(mmUVD_MPC_SET_MUXA0));  in uvd_v5_0_print_status()
699 		 RREG32(mmUVD_MPC_SET_MUXA1));  in uvd_v5_0_print_status()
701 		 RREG32(mmUVD_MPC_SET_MUXB0));  in uvd_v5_0_print_status()
703 		 RREG32(mmUVD_MPC_SET_MUXB1));  in uvd_v5_0_print_status()
705 		 RREG32(mmUVD_MPC_SET_MUX));  in uvd_v5_0_print_status()
707 		 RREG32(mmUVD_MPC_SET_ALU));  in uvd_v5_0_print_status()
709 		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));  in uvd_v5_0_print_status()
711 		 RREG32(mmUVD_VCPU_CACHE_SIZE0));  in uvd_v5_0_print_status()
713 		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));  in uvd_v5_0_print_status()
715 		 RREG32(mmUVD_VCPU_CACHE_SIZE1));  in uvd_v5_0_print_status()
717 		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));  in uvd_v5_0_print_status()
719 		 RREG32(mmUVD_VCPU_CACHE_SIZE2));  in uvd_v5_0_print_status()
721 		 RREG32(mmUVD_VCPU_CNTL));  in uvd_v5_0_print_status()
723 		 RREG32(mmUVD_SOFT_RESET));  in uvd_v5_0_print_status()
725 		 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW));  in uvd_v5_0_print_status()
727 		 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH));  in uvd_v5_0_print_status()
729 		 RREG32(mmUVD_RBC_IB_SIZE));  in uvd_v5_0_print_status()
731 		 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW));  in uvd_v5_0_print_status()
733 		 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH));  in uvd_v5_0_print_status()
735 		 RREG32(mmUVD_RBC_RB_RPTR));  in uvd_v5_0_print_status()
737 		 RREG32(mmUVD_RBC_RB_WPTR));  in uvd_v5_0_print_status()
739 		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));  in uvd_v5_0_print_status()
741 		 RREG32(mmUVD_RBC_RB_CNTL));  in uvd_v5_0_print_status()
743 		 RREG32(mmUVD_STATUS));  in uvd_v5_0_print_status()
745 		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));  in uvd_v5_0_print_status()
747 		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));  in uvd_v5_0_print_status()
749 		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));  in uvd_v5_0_print_status()
751 		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));  in uvd_v5_0_print_status()
753 		 RREG32(mmUVD_CONTEXT_ID));  in uvd_v5_0_print_status()