587 				data = RREG32(config_regs->offset << 2);  in ci_program_pt_config_registers()
1663 		*parameter = RREG32(SMC_MSG_ARG_0);  in ci_send_msg_to_smc_return_parameter()
1856 	pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in ci_read_clock_registers()
1857 	pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in ci_read_clock_registers()
1858 	pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in ci_read_clock_registers()
1859 	pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in ci_read_clock_registers()
1860 	pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);  in ci_read_clock_registers()
1861 	pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);  in ci_read_clock_registers()
1862 	pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);  in ci_read_clock_registers()
1863 	pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in ci_read_clock_registers()
1864 	pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in ci_read_clock_registers()
1915 		if (RREG32(SMC_RESP_0) == 1)
2473 	tmp = RREG32(MC_SEQ_MISC0);  in ci_register_patching_mc_arb()
2503 	dram_timing  = RREG32(MC_ARB_DRAM_TIMING);  in ci_populate_memory_timing_parameters()
2504 	dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);  in ci_populate_memory_timing_parameters()
2505 	burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;  in ci_populate_memory_timing_parameters()
2902 	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&  in ci_populate_single_memory_level()
2923 			    ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))  in ci_populate_single_memory_level()
2924 				dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;  in ci_populate_single_memory_level()
2926 				dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;  in ci_populate_single_memory_level()
2932 		dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;  in ci_populate_single_memory_level()
4315 			temp_reg = RREG32(MC_PMG_CMD_EMRS);  in ci_set_mc_special_registers()
4326 			temp_reg = RREG32(MC_PMG_CMD_MRS);  in ci_set_mc_special_registers()
4352 			temp_reg = RREG32(MC_PMG_CMD_MRS1);  in ci_set_mc_special_registers()
4508 	tmp = RREG32(MC_SEQ_MISC0);  in ci_register_patching_mc_seq()
4582 		tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);  in ci_register_patching_mc_seq()
4603 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));  in ci_initialize_mc_reg_table()
4604 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));  in ci_initialize_mc_reg_table()
4605 	WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));  in ci_initialize_mc_reg_table()
4606 	WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));  in ci_initialize_mc_reg_table()
4607 	WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));  in ci_initialize_mc_reg_table()
4608 	WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));  in ci_initialize_mc_reg_table()
4609 	WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));  in ci_initialize_mc_reg_table()
4610 	WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));  in ci_initialize_mc_reg_table()
4611 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));  in ci_initialize_mc_reg_table()
4612 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));  in ci_initialize_mc_reg_table()
4613 	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));  in ci_initialize_mc_reg_table()
4614 	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));  in ci_initialize_mc_reg_table()
4615 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));  in ci_initialize_mc_reg_table()
4616 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));  in ci_initialize_mc_reg_table()
4617 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));  in ci_initialize_mc_reg_table()
4618 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));  in ci_initialize_mc_reg_table()
4619 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));  in ci_initialize_mc_reg_table()
4620 	WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));  in ci_initialize_mc_reg_table()
4621 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));  in ci_initialize_mc_reg_table()
4622 	WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));  in ci_initialize_mc_reg_table()
5063 	tmp = RREG32(MC_SEQ_MISC0);  in ci_get_memory_type()