86 	(void)RREG32(mmPCIE_INDEX);  in vi_pcie_rreg()
87 	r = RREG32(mmPCIE_DATA);  in vi_pcie_rreg()
98 	(void)RREG32(mmPCIE_INDEX);  in vi_pcie_wreg()
100 	(void)RREG32(mmPCIE_DATA);  in vi_pcie_wreg()
111 	r = RREG32(mmSMC_IND_DATA_0);  in vi_smc_rreg()
137 	r = RREG32(mmMP0PUB_IND_DATA);  in cz_smc_rreg()
159 	r = RREG32(mmUVD_CTX_DATA);  in vi_uvd_ctx_rreg()
181 	r = RREG32(mmDIDT_IND_DATA);  in vi_didt_rreg()
345 	bus_cntl = RREG32(mmBUS_CNTL);  in vi_read_disabled_bios()
347 		d1vga_control = RREG32(mmD1VGA_CONTROL);  in vi_read_disabled_bios()
348 		d2vga_control = RREG32(mmD2VGA_CONTROL);  in vi_read_disabled_bios()
349 		vga_render_control = RREG32(mmVGA_RENDER_CONTROL);  in vi_read_disabled_bios()
480 	val = RREG32(reg_offset);  in vi_read_indexed_register()
521 					RREG32(reg_offset);  in vi_read_register()
534 				RREG32(reg_offset);  in vi_read_register()
543 		RREG32(mmGRBM_STATUS));  in vi_print_gpu_status_regs()
545 		RREG32(mmGRBM_STATUS2));  in vi_print_gpu_status_regs()
547 		RREG32(mmGRBM_STATUS_SE0));  in vi_print_gpu_status_regs()
549 		RREG32(mmGRBM_STATUS_SE1));  in vi_print_gpu_status_regs()
551 		RREG32(mmGRBM_STATUS_SE2));  in vi_print_gpu_status_regs()
553 		RREG32(mmGRBM_STATUS_SE3));  in vi_print_gpu_status_regs()
555 		RREG32(mmSRBM_STATUS));  in vi_print_gpu_status_regs()
557 		RREG32(mmSRBM_STATUS2));  in vi_print_gpu_status_regs()
559 		RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));  in vi_print_gpu_status_regs()
562 			RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));  in vi_print_gpu_status_regs()
564 	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));  in vi_print_gpu_status_regs()
566 		 RREG32(mmCP_STALLED_STAT1));  in vi_print_gpu_status_regs()
568 		 RREG32(mmCP_STALLED_STAT2));  in vi_print_gpu_status_regs()
570 		 RREG32(mmCP_STALLED_STAT3));  in vi_print_gpu_status_regs()
572 		 RREG32(mmCP_CPF_BUSY_STAT));  in vi_print_gpu_status_regs()
574 		 RREG32(mmCP_CPF_STALLED_STAT1));  in vi_print_gpu_status_regs()
575 	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));  in vi_print_gpu_status_regs()
576 	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));  in vi_print_gpu_status_regs()
578 		 RREG32(mmCP_CPC_STALLED_STAT1));  in vi_print_gpu_status_regs()
579 	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));  in vi_print_gpu_status_regs()
597 	tmp = RREG32(mmGRBM_STATUS);  in vi_gpu_check_soft_reset()
610 	tmp = RREG32(mmGRBM_STATUS2);  in vi_gpu_check_soft_reset()
620 	tmp = RREG32(mmSRBM_STATUS2);  in vi_gpu_check_soft_reset()
628 	tmp = RREG32(mmSRBM_STATUS);  in vi_gpu_check_soft_reset()
653 	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);  in vi_gpu_check_soft_reset()
659 		tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);  in vi_gpu_check_soft_reset()
666 		tmp = RREG32(mmVCE_STATUS);  in vi_gpu_check_soft_reset()
710 		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));  in vi_gpu_soft_reset()
712 		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));  in vi_gpu_soft_reset()
721 	tmp = RREG32(mmCP_ME_CNTL);  in vi_gpu_soft_reset()
728 	tmp = RREG32(mmCP_MEC_CNTL);  in vi_gpu_soft_reset()
735 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in vi_gpu_soft_reset()
741 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in vi_gpu_soft_reset()
816 		tmp = RREG32(mmGRBM_SOFT_RESET);  in vi_gpu_soft_reset()
820 		tmp = RREG32(mmGRBM_SOFT_RESET);  in vi_gpu_soft_reset()
826 		tmp = RREG32(mmGRBM_SOFT_RESET);  in vi_gpu_soft_reset()
830 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vi_gpu_soft_reset()
834 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vi_gpu_soft_reset()
840 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vi_gpu_soft_reset()
864 	tmp = RREG32(mmCP_ME_CNTL);  in vi_gpu_pci_config_reset()
871 	tmp = RREG32(mmCP_MEC_CNTL);  in vi_gpu_pci_config_reset()
885 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in vi_gpu_pci_config_reset()
890 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in vi_gpu_pci_config_reset()
917 		if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)  in vi_gpu_pci_config_reset()
926 	u32 tmp = RREG32(mmBIOS_SCRATCH_3);  in vi_set_bios_scratch_engine_hung()
1063 	tmp = RREG32(mmBIF_DOORBELL_APER_EN);  in vi_enable_doorbell_aperture()
1359 		return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)  in vi_get_rev_id()
1365 		return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)  in vi_get_rev_id()