Lines Matching refs:RREG32
165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v11_0_audio_endpt_rreg()
184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & in dce_v11_0_is_in_vblank()
195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_is_counter_moving()
196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_is_counter_moving()
219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) in dce_v11_0_vblank_wait()
245 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v11_0_vblank_get_counter()
288 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
297 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
298 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
341 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & in dce_v11_0_hpd_sense()
386 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_set_polarity()
445 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_init()
449 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); in dce_v11_0_hpd_init()
504 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_fini()
524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
526 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
534 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
553 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_stop_mc_access()
554 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); in dce_v11_0_stop_mc_access()
557 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_stop_mc_access()
563 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_stop_mc_access()
571 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
586 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
591 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
599 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
630 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
635 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
640 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
646 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
651 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
681 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v11_0_set_vga_render_state()
689 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_set_vga_render_state()
821 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
825 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
830 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
863 u32 tmp = RREG32(mmMC_SHARED_CHMAP); in cik_get_number_of_dram_channels()
1328 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1331 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1338 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1423 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1680 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1683 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1687 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1690 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1694 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1697 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1745 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); in dce_v11_0_audio_set_dto()
1789 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1795 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1822 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1828 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1835 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1847 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1854 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1859 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1872 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1876 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1880 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1912 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1919 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1923 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
2008 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v11_0_vga_enable()
2208 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2244 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2276 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2294 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2298 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2302 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2327 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2333 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2337 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2341 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2350 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2463 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v11_0_lock_cursor()
3136 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3140 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3146 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3168 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3174 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3197 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vline_interrupt_state()
3203 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vline_interrupt_state()
3227 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3232 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3303 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); in dce_v11_0_set_pageflip_irq_state()
3331 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & in dce_v11_0_pageflip_irq()
3377 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3392 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); in dce_v11_0_crtc_vblank_int_ack()
3407 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v11_0_crtc_vline_int_ack()
3417 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()
3463 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()