149 		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);  in rv515_vga_render_disable()
162 	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);  in rv515_gpu_init()
163 	tmp = RREG32(R300_DST_PIPE_CONFIG);  in rv515_gpu_init()
217 	r = RREG32(MC_IND_DATA);  in rv515_mc_rreg()
243 	tmp = RREG32(GB_PIPE_SELECT);  in rv515_debugfs_pipes_info()
245 	tmp = RREG32(SU_REG_DEST);  in rv515_debugfs_pipes_info()
247 	tmp = RREG32(GB_TILE_CONFIG);  in rv515_debugfs_pipes_info()
249 	tmp = RREG32(DST_PIPE_CONFIG);  in rv515_debugfs_pipes_info()
261 	tmp = RREG32(0x2140);  in rv515_debugfs_ga_info()
264 	tmp = RREG32(0x425C);  in rv515_debugfs_ga_info()
301 	save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);  in rv515_mc_stop()
302 	save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);  in rv515_mc_stop()
308 		crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;  in rv515_mc_stop()
311 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
329 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
344 			blackout = RREG32(R700_MC_CITF_CNTL);  in rv515_mc_stop()
346 			blackout = RREG32(R600_CITF_CNTL);  in rv515_mc_stop()
364 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_stop()
369 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_stop()
408 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);  in rv515_mc_resume()
414 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
419 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_resume()
425 				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
436 			tmp = RREG32(R700_MC_CITF_CNTL);  in rv515_mc_resume()
438 			tmp = RREG32(R600_CITF_CNTL);  in rv515_mc_resume()
450 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_resume()
551 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in rv515_startup()
580 			RREG32(R_000E40_RBBM_STATUS),  in rv515_resume()
581 			RREG32(R_0007C0_CP_STAT));  in rv515_resume()
660 			RREG32(R_000E40_RBBM_STATUS),  in rv515_init()
661 			RREG32(R_0007C0_CP_STAT));  in rv515_init()