Lines Matching refs:RREG32
186 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff); in ci_get_memory_module_index()
204 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING); in ci_copy_and_switch_arb_sets()
205 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2); in ci_copy_and_switch_arb_sets()
206 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >> in ci_copy_and_switch_arb_sets()
210 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1); in ci_copy_and_switch_arb_sets()
211 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1); in ci_copy_and_switch_arb_sets()
212 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >> in ci_copy_and_switch_arb_sets()
236 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F; in ci_copy_and_switch_arb_sets()
705 data = RREG32(config_regs->offset); in ci_program_pt_config_registers()
1791 *parameter = RREG32(mmSMC_MSG_ARG_0); in amdgpu_ci_send_msg_to_smc_return_parameter()
1984 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL); in ci_read_clock_registers()
1985 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1986 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1987 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1988 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL); in ci_read_clock_registers()
1989 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1990 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1991 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1); in ci_read_clock_registers()
1992 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2); in ci_read_clock_registers()
2043 if (RREG32(mmSMC_RESP_0) == 1)
2604 tmp = RREG32(mmMC_SEQ_MISC0); in ci_register_patching_mc_arb()
2633 dram_timing = RREG32(mmMC_ARB_DRAM_TIMING); in ci_populate_memory_timing_parameters()
2634 dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2); in ci_populate_memory_timing_parameters()
2635 burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK; in ci_populate_memory_timing_parameters()
3038 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && in ci_populate_single_memory_level()
3059 ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf)) in ci_populate_single_memory_level()
3060 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in ci_populate_single_memory_level()
3062 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false; in ci_populate_single_memory_level()
3068 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in ci_populate_single_memory_level()
4484 temp_reg = RREG32(mmMC_PMG_CMD_EMRS); in ci_set_mc_special_registers()
4495 temp_reg = RREG32(mmMC_PMG_CMD_MRS); in ci_set_mc_special_registers()
4521 temp_reg = RREG32(mmMC_PMG_CMD_MRS1); in ci_set_mc_special_registers()
4677 tmp = RREG32(mmMC_SEQ_MISC0); in ci_register_patching_mc_seq()
4751 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA); in ci_register_patching_mc_seq()
4772 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING)); in ci_initialize_mc_reg_table()
4773 WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING)); in ci_initialize_mc_reg_table()
4774 WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY)); in ci_initialize_mc_reg_table()
4775 WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0)); in ci_initialize_mc_reg_table()
4776 WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1)); in ci_initialize_mc_reg_table()
4777 WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL)); in ci_initialize_mc_reg_table()
4778 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD)); in ci_initialize_mc_reg_table()
4779 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL)); in ci_initialize_mc_reg_table()
4780 WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING)); in ci_initialize_mc_reg_table()
4781 WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2)); in ci_initialize_mc_reg_table()
4782 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS)); in ci_initialize_mc_reg_table()
4783 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS)); in ci_initialize_mc_reg_table()
4784 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1)); in ci_initialize_mc_reg_table()
4785 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0)); in ci_initialize_mc_reg_table()
4786 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1)); in ci_initialize_mc_reg_table()
4787 WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0)); in ci_initialize_mc_reg_table()
4788 WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1)); in ci_initialize_mc_reg_table()
4789 WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING)); in ci_initialize_mc_reg_table()
4790 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2)); in ci_initialize_mc_reg_table()
4791 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2)); in ci_initialize_mc_reg_table()
6352 RREG32(mmBIOS_SCRATCH_4)); in ci_dpm_print_status()
6354 RREG32(mmMC_ARB_DRAM_TIMING)); in ci_dpm_print_status()
6356 RREG32(mmMC_ARB_DRAM_TIMING2)); in ci_dpm_print_status()
6358 RREG32(mmMC_ARB_BURST_TIME)); in ci_dpm_print_status()
6360 RREG32(mmMC_ARB_DRAM_TIMING_1)); in ci_dpm_print_status()
6362 RREG32(mmMC_ARB_DRAM_TIMING2_1)); in ci_dpm_print_status()
6364 RREG32(mmMC_CG_CONFIG)); in ci_dpm_print_status()
6366 RREG32(mmMC_ARB_CG)); in ci_dpm_print_status()
6382 RREG32(mmMC_SEQ_CNTL_3)); in ci_dpm_print_status()
6392 RREG32(mmBIF_LNCNT_RESET)); in ci_dpm_print_status()
6408 RREG32(mmDLL_CNTL)); in ci_dpm_print_status()
6410 RREG32(mmMCLK_PWRMGT_CNTL)); in ci_dpm_print_status()
6412 RREG32(mmMPLL_AD_FUNC_CNTL)); in ci_dpm_print_status()
6414 RREG32(mmMPLL_DQ_FUNC_CNTL)); in ci_dpm_print_status()
6416 RREG32(mmMPLL_FUNC_CNTL)); in ci_dpm_print_status()
6418 RREG32(mmMPLL_FUNC_CNTL_1)); in ci_dpm_print_status()
6420 RREG32(mmMPLL_FUNC_CNTL_2)); in ci_dpm_print_status()
6422 RREG32(mmMPLL_SS1)); in ci_dpm_print_status()
6424 RREG32(mmMPLL_SS2)); in ci_dpm_print_status()
6452 RREG32(mmMC_SEQ_RAS_TIMING_LP)); in ci_dpm_print_status()
6454 RREG32(mmMC_SEQ_RAS_TIMING)); in ci_dpm_print_status()
6456 RREG32(mmMC_SEQ_CAS_TIMING_LP)); in ci_dpm_print_status()
6458 RREG32(mmMC_SEQ_CAS_TIMING)); in ci_dpm_print_status()
6460 RREG32(mmMC_SEQ_DLL_STBY_LP)); in ci_dpm_print_status()
6462 RREG32(mmMC_SEQ_DLL_STBY)); in ci_dpm_print_status()
6464 RREG32(mmMC_SEQ_G5PDX_CMD0_LP)); in ci_dpm_print_status()
6466 RREG32(mmMC_SEQ_G5PDX_CMD0)); in ci_dpm_print_status()
6468 RREG32(mmMC_SEQ_G5PDX_CMD1_LP)); in ci_dpm_print_status()
6470 RREG32(mmMC_SEQ_G5PDX_CMD1)); in ci_dpm_print_status()
6472 RREG32(mmMC_SEQ_G5PDX_CTRL_LP)); in ci_dpm_print_status()
6474 RREG32(mmMC_SEQ_G5PDX_CTRL)); in ci_dpm_print_status()
6476 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP)); in ci_dpm_print_status()
6478 RREG32(mmMC_SEQ_PMG_DVS_CMD)); in ci_dpm_print_status()
6480 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP)); in ci_dpm_print_status()
6482 RREG32(mmMC_SEQ_PMG_DVS_CTL)); in ci_dpm_print_status()
6484 RREG32(mmMC_SEQ_MISC_TIMING_LP)); in ci_dpm_print_status()
6486 RREG32(mmMC_SEQ_MISC_TIMING)); in ci_dpm_print_status()
6488 RREG32(mmMC_SEQ_MISC_TIMING2_LP)); in ci_dpm_print_status()
6490 RREG32(mmMC_SEQ_MISC_TIMING2)); in ci_dpm_print_status()
6492 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP)); in ci_dpm_print_status()
6494 RREG32(mmMC_PMG_CMD_EMRS)); in ci_dpm_print_status()
6496 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP)); in ci_dpm_print_status()
6498 RREG32(mmMC_PMG_CMD_MRS)); in ci_dpm_print_status()
6500 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP)); in ci_dpm_print_status()
6502 RREG32(mmMC_PMG_CMD_MRS1)); in ci_dpm_print_status()
6504 RREG32(mmMC_SEQ_WR_CTL_D0_LP)); in ci_dpm_print_status()
6506 RREG32(mmMC_SEQ_WR_CTL_D0)); in ci_dpm_print_status()
6508 RREG32(mmMC_SEQ_WR_CTL_D1_LP)); in ci_dpm_print_status()
6510 RREG32(mmMC_SEQ_WR_CTL_D1)); in ci_dpm_print_status()
6512 RREG32(mmMC_SEQ_RD_CTL_D0_LP)); in ci_dpm_print_status()
6514 RREG32(mmMC_SEQ_RD_CTL_D0)); in ci_dpm_print_status()
6516 RREG32(mmMC_SEQ_RD_CTL_D1_LP)); in ci_dpm_print_status()
6518 RREG32(mmMC_SEQ_RD_CTL_D1)); in ci_dpm_print_status()
6520 RREG32(mmMC_SEQ_PMG_TIMING_LP)); in ci_dpm_print_status()
6522 RREG32(mmMC_SEQ_PMG_TIMING)); in ci_dpm_print_status()
6524 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP)); in ci_dpm_print_status()
6526 RREG32(mmMC_PMG_CMD_MRS2)); in ci_dpm_print_status()
6528 RREG32(mmMC_SEQ_WR_CTL_2_LP)); in ci_dpm_print_status()
6530 RREG32(mmMC_SEQ_WR_CTL_2)); in ci_dpm_print_status()
6536 RREG32(mmSMC_IND_INDEX_0)); in ci_dpm_print_status()
6538 RREG32(mmSMC_IND_DATA_0)); in ci_dpm_print_status()
6540 RREG32(mmSMC_IND_ACCESS_CNTL)); in ci_dpm_print_status()
6542 RREG32(mmSMC_RESP_0)); in ci_dpm_print_status()
6544 RREG32(mmSMC_MESSAGE_0)); in ci_dpm_print_status()