1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#include "drmP.h" 24#include "amdgpu.h" 25#include "amdgpu_ih.h" 26#include "vid.h" 27 28#include "oss/oss_3_0_1_d.h" 29#include "oss/oss_3_0_1_sh_mask.h" 30 31#include "bif/bif_5_1_d.h" 32#include "bif/bif_5_1_sh_mask.h" 33 34/* 35 * Interrupts 36 * Starting with r6xx, interrupts are handled via a ring buffer. 37 * Ring buffers are areas of GPU accessible memory that the GPU 38 * writes interrupt vectors into and the host reads vectors out of. 39 * There is a rptr (read pointer) that determines where the 40 * host is currently reading, and a wptr (write pointer) 41 * which determines where the GPU has written. When the 42 * pointers are equal, the ring is idle. When the GPU 43 * writes vectors to the ring buffer, it increments the 44 * wptr. When there is an interrupt, the host then starts 45 * fetching commands and processing them until the pointers are 46 * equal again at which point it updates the rptr. 47 */ 48 49static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev); 50 51/** 52 * cz_ih_enable_interrupts - Enable the interrupt ring buffer 53 * 54 * @adev: amdgpu_device pointer 55 * 56 * Enable the interrupt ring buffer (VI). 57 */ 58static void cz_ih_enable_interrupts(struct amdgpu_device *adev) 59{ 60 u32 ih_cntl = RREG32(mmIH_CNTL); 61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 62 63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 65 WREG32(mmIH_CNTL, ih_cntl); 66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 67 adev->irq.ih.enabled = true; 68} 69 70/** 71 * cz_ih_disable_interrupts - Disable the interrupt ring buffer 72 * 73 * @adev: amdgpu_device pointer 74 * 75 * Disable the interrupt ring buffer (VI). 76 */ 77static void cz_ih_disable_interrupts(struct amdgpu_device *adev) 78{ 79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 80 u32 ih_cntl = RREG32(mmIH_CNTL); 81 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); 84 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 85 WREG32(mmIH_CNTL, ih_cntl); 86 /* set rptr, wptr to 0 */ 87 WREG32(mmIH_RB_RPTR, 0); 88 WREG32(mmIH_RB_WPTR, 0); 89 adev->irq.ih.enabled = false; 90 adev->irq.ih.rptr = 0; 91} 92 93/** 94 * cz_ih_irq_init - init and enable the interrupt ring 95 * 96 * @adev: amdgpu_device pointer 97 * 98 * Allocate a ring buffer for the interrupt controller, 99 * enable the RLC, disable interrupts, enable the IH 100 * ring buffer and enable it (VI). 101 * Called at device load and reume. 102 * Returns 0 for success, errors for failure. 103 */ 104static int cz_ih_irq_init(struct amdgpu_device *adev) 105{ 106 int ret = 0; 107 int rb_bufsz; 108 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 109 u64 wptr_off; 110 111 /* disable irqs */ 112 cz_ih_disable_interrupts(adev); 113 114 /* setup interrupt control */ 115 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 116 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 117 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 118 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 119 */ 120 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 121 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 122 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 123 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 124 125 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 127 128 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 129 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 132 133 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 134 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 135 136 /* set the writeback address whether it's enabled or not */ 137 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); 140 141 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 142 143 /* set rptr, wptr to 0 */ 144 WREG32(mmIH_RB_RPTR, 0); 145 WREG32(mmIH_RB_WPTR, 0); 146 147 /* Default settings for IH_CNTL (disabled at first) */ 148 ih_cntl = RREG32(mmIH_CNTL); 149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); 150 151 if (adev->irq.msi_enabled) 152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); 153 WREG32(mmIH_CNTL, ih_cntl); 154 155 pci_set_master(adev->pdev); 156 157 /* enable interrupts */ 158 cz_ih_enable_interrupts(adev); 159 160 return ret; 161} 162 163/** 164 * cz_ih_irq_disable - disable interrupts 165 * 166 * @adev: amdgpu_device pointer 167 * 168 * Disable interrupts on the hw (VI). 169 */ 170static void cz_ih_irq_disable(struct amdgpu_device *adev) 171{ 172 cz_ih_disable_interrupts(adev); 173 174 /* Wait and acknowledge irq */ 175 mdelay(1); 176} 177 178/** 179 * cz_ih_get_wptr - get the IH ring buffer wptr 180 * 181 * @adev: amdgpu_device pointer 182 * 183 * Get the IH ring buffer wptr from either the register 184 * or the writeback memory buffer (VI). Also check for 185 * ring buffer overflow and deal with it. 186 * Used by cz_irq_process(VI). 187 * Returns the value of the wptr. 188 */ 189static u32 cz_ih_get_wptr(struct amdgpu_device *adev) 190{ 191 u32 wptr, tmp; 192 193 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); 194 195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 196 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 197 /* When a ring buffer overflow happen start parsing interrupt 198 * from the last not overwritten vector (wptr + 16). Hopefully 199 * this should allow us to catchup. 200 */ 201 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 202 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); 203 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; 204 tmp = RREG32(mmIH_RB_CNTL); 205 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 206 WREG32(mmIH_RB_CNTL, tmp); 207 } 208 return (wptr & adev->irq.ih.ptr_mask); 209} 210 211/** 212 * cz_ih_decode_iv - decode an interrupt vector 213 * 214 * @adev: amdgpu_device pointer 215 * 216 * Decodes the interrupt vector at the current rptr 217 * position and also advance the position. 218 */ 219static void cz_ih_decode_iv(struct amdgpu_device *adev, 220 struct amdgpu_iv_entry *entry) 221{ 222 /* wptr/rptr are in bytes! */ 223 u32 ring_index = adev->irq.ih.rptr >> 2; 224 uint32_t dw[4]; 225 226 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 227 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); 228 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); 229 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 230 231 entry->src_id = dw[0] & 0xff; 232 entry->src_data = dw[1] & 0xfffffff; 233 entry->ring_id = dw[2] & 0xff; 234 entry->vm_id = (dw[2] >> 8) & 0xff; 235 entry->pas_id = (dw[2] >> 16) & 0xffff; 236 237 /* wptr/rptr are in bytes! */ 238 adev->irq.ih.rptr += 16; 239} 240 241/** 242 * cz_ih_set_rptr - set the IH ring buffer rptr 243 * 244 * @adev: amdgpu_device pointer 245 * 246 * Set the IH ring buffer rptr. 247 */ 248static void cz_ih_set_rptr(struct amdgpu_device *adev) 249{ 250 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 251} 252 253static int cz_ih_early_init(void *handle) 254{ 255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 256 257 cz_ih_set_interrupt_funcs(adev); 258 return 0; 259} 260 261static int cz_ih_sw_init(void *handle) 262{ 263 int r; 264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 265 266 r = amdgpu_ih_ring_init(adev, 64 * 1024, false); 267 if (r) 268 return r; 269 270 r = amdgpu_irq_init(adev); 271 272 return r; 273} 274 275static int cz_ih_sw_fini(void *handle) 276{ 277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 278 279 amdgpu_irq_fini(adev); 280 amdgpu_ih_ring_fini(adev); 281 282 return 0; 283} 284 285static int cz_ih_hw_init(void *handle) 286{ 287 int r; 288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 289 290 r = cz_ih_irq_init(adev); 291 if (r) 292 return r; 293 294 return 0; 295} 296 297static int cz_ih_hw_fini(void *handle) 298{ 299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 300 301 cz_ih_irq_disable(adev); 302 303 return 0; 304} 305 306static int cz_ih_suspend(void *handle) 307{ 308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 309 310 return cz_ih_hw_fini(adev); 311} 312 313static int cz_ih_resume(void *handle) 314{ 315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 316 317 return cz_ih_hw_init(adev); 318} 319 320static bool cz_ih_is_idle(void *handle) 321{ 322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 323 u32 tmp = RREG32(mmSRBM_STATUS); 324 325 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 326 return false; 327 328 return true; 329} 330 331static int cz_ih_wait_for_idle(void *handle) 332{ 333 unsigned i; 334 u32 tmp; 335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 336 337 for (i = 0; i < adev->usec_timeout; i++) { 338 /* read MC_STATUS */ 339 tmp = RREG32(mmSRBM_STATUS); 340 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 341 return 0; 342 udelay(1); 343 } 344 return -ETIMEDOUT; 345} 346 347static void cz_ih_print_status(void *handle) 348{ 349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 350 351 dev_info(adev->dev, "CZ IH registers\n"); 352 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 353 RREG32(mmSRBM_STATUS)); 354 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 355 RREG32(mmSRBM_STATUS2)); 356 dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", 357 RREG32(mmINTERRUPT_CNTL)); 358 dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", 359 RREG32(mmINTERRUPT_CNTL2)); 360 dev_info(adev->dev, " IH_CNTL=0x%08X\n", 361 RREG32(mmIH_CNTL)); 362 dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", 363 RREG32(mmIH_RB_CNTL)); 364 dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", 365 RREG32(mmIH_RB_BASE)); 366 dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", 367 RREG32(mmIH_RB_WPTR_ADDR_LO)); 368 dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", 369 RREG32(mmIH_RB_WPTR_ADDR_HI)); 370 dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", 371 RREG32(mmIH_RB_RPTR)); 372 dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", 373 RREG32(mmIH_RB_WPTR)); 374} 375 376static int cz_ih_soft_reset(void *handle) 377{ 378 u32 srbm_soft_reset = 0; 379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 380 u32 tmp = RREG32(mmSRBM_STATUS); 381 382 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 383 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 384 SOFT_RESET_IH, 1); 385 386 if (srbm_soft_reset) { 387 cz_ih_print_status((void *)adev); 388 389 tmp = RREG32(mmSRBM_SOFT_RESET); 390 tmp |= srbm_soft_reset; 391 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 392 WREG32(mmSRBM_SOFT_RESET, tmp); 393 tmp = RREG32(mmSRBM_SOFT_RESET); 394 395 udelay(50); 396 397 tmp &= ~srbm_soft_reset; 398 WREG32(mmSRBM_SOFT_RESET, tmp); 399 tmp = RREG32(mmSRBM_SOFT_RESET); 400 401 /* Wait a little for things to settle down */ 402 udelay(50); 403 404 cz_ih_print_status((void *)adev); 405 } 406 407 return 0; 408} 409 410static int cz_ih_set_clockgating_state(void *handle, 411 enum amd_clockgating_state state) 412{ 413 // TODO 414 return 0; 415} 416 417static int cz_ih_set_powergating_state(void *handle, 418 enum amd_powergating_state state) 419{ 420 // TODO 421 return 0; 422} 423 424const struct amd_ip_funcs cz_ih_ip_funcs = { 425 .early_init = cz_ih_early_init, 426 .late_init = NULL, 427 .sw_init = cz_ih_sw_init, 428 .sw_fini = cz_ih_sw_fini, 429 .hw_init = cz_ih_hw_init, 430 .hw_fini = cz_ih_hw_fini, 431 .suspend = cz_ih_suspend, 432 .resume = cz_ih_resume, 433 .is_idle = cz_ih_is_idle, 434 .wait_for_idle = cz_ih_wait_for_idle, 435 .soft_reset = cz_ih_soft_reset, 436 .print_status = cz_ih_print_status, 437 .set_clockgating_state = cz_ih_set_clockgating_state, 438 .set_powergating_state = cz_ih_set_powergating_state, 439}; 440 441static const struct amdgpu_ih_funcs cz_ih_funcs = { 442 .get_wptr = cz_ih_get_wptr, 443 .decode_iv = cz_ih_decode_iv, 444 .set_rptr = cz_ih_set_rptr 445}; 446 447static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev) 448{ 449 if (adev->irq.ih_funcs == NULL) 450 adev->irq.ih_funcs = &cz_ih_funcs; 451} 452 453