58 	if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)  in avivo_is_in_vblank()
68 	pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);  in avivo_is_counter_moving()
69 	pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);  in avivo_is_counter_moving()
92 	if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))  in avivo_wait_for_vblank()
116 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rs600_page_flip()
131 		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)  in rs600_page_flip()
147 	return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &  in rs600_page_flip_pending()
225 			tmp = RREG32(voltage->gpio.reg);  in rs600_pm_misc()
234 			tmp = RREG32(voltage->gpio.reg);  in rs600_pm_misc()
320 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_prepare()
338 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);  in rs600_pm_finish()
353 		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);  in rs600_hpd_sense()
358 		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);  in rs600_hpd_sense()
376 		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);  in rs600_hpd_set_polarity()
384 		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);  in rs600_hpd_set_polarity()
453 	status = RREG32(R_000E40_RBBM_STATUS);  in rs600_asic_reset()
459 	status = RREG32(R_000E40_RBBM_STATUS);  in rs600_asic_reset()
463 	tmp = RREG32(RADEON_CP_RB_CNTL);  in rs600_asic_reset()
475 	RREG32(R_0000F0_RBBM_SOFT_RESET);  in rs600_asic_reset()
479 	status = RREG32(R_000E40_RBBM_STATUS);  in rs600_asic_reset()
483 	RREG32(R_0000F0_RBBM_SOFT_RESET);  in rs600_asic_reset()
487 	status = RREG32(R_000E40_RBBM_STATUS);  in rs600_asic_reset()
491 	RREG32(R_0000F0_RBBM_SOFT_RESET);  in rs600_asic_reset()
495 	status = RREG32(R_000E40_RBBM_STATUS);  in rs600_asic_reset()
560 	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;  in rs600_gart_enable()
655 	u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &  in rs600_irq_set()
657 	u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &  in rs600_irq_set()
661 		hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &  in rs600_irq_set()
699 	RREG32(R_000040_GEN_INT_CNTL);  in rs600_irq_set()
706 	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);  in rs600_irq_ack()
711 		rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);  in rs600_irq_ack()
721 			tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);  in rs600_irq_ack()
726 			tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);  in rs600_irq_ack()
735 		rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &  in rs600_irq_ack()
738 			tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);  in rs600_irq_ack()
753 	u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &  in rs600_irq_disable()
824 			msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;  in rs600_irq_process()
839 		return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);  in rs600_get_vblank_counter()
841 		return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);  in rs600_get_vblank_counter()
872 	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);  in rs600_mc_init()
904 		d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);  in rs600_bandwidth_update()
905 		d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);  in rs600_bandwidth_update()
923 	r = RREG32(R_000074_MC_IND_DATA);  in rs600_mc_rreg()
1010 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in rs600_startup()
1044 			RREG32(R_000E40_RBBM_STATUS),  in rs600_resume()
1045 			RREG32(R_0007C0_CP_STAT));  in rs600_resume()
1119 			RREG32(R_000E40_RBBM_STATUS),  in rs600_init()
1120 			RREG32(R_0007C0_CP_STAT));  in rs600_init()