306 		wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;  in sdma_v3_0_ring_get_wptr()
492 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in sdma_v3_0_gfx_stop()
495 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);  in sdma_v3_0_gfx_stop()
529 		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);  in sdma_v3_0_ctx_switch_enable()
559 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);  in sdma_v3_0_enable()
603 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in sdma_v3_0_gfx_resume()
630 		doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);  in sdma_v3_0_gfx_resume()
645 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);  in sdma_v3_0_gfx_resume()
1215 	u32 tmp = RREG32(mmSRBM_STATUS2);  in sdma_v3_0_is_idle()
1231 		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |  in sdma_v3_0_wait_for_idle()
1248 		 RREG32(mmSRBM_STATUS2));  in sdma_v3_0_print_status()
1251 			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));  in sdma_v3_0_print_status()
1253 			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1255 			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1257 			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1259 			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1261 			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1263 			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));  in sdma_v3_0_print_status()
1265 			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));  in sdma_v3_0_print_status()
1267 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));  in sdma_v3_0_print_status()
1269 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));  in sdma_v3_0_print_status()
1271 			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));  in sdma_v3_0_print_status()
1273 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));  in sdma_v3_0_print_status()
1275 			 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1281 				 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));  in sdma_v3_0_print_status()
1283 				 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));  in sdma_v3_0_print_status()
1294 	u32 tmp = RREG32(mmSRBM_STATUS2);  in sdma_v3_0_soft_reset()
1298 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in sdma_v3_0_soft_reset()
1305 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in sdma_v3_0_soft_reset()
1314 		tmp = RREG32(mmSRBM_SOFT_RESET);  in sdma_v3_0_soft_reset()
1318 		tmp = RREG32(mmSRBM_SOFT_RESET);  in sdma_v3_0_soft_reset()
1324 		tmp = RREG32(mmSRBM_SOFT_RESET);  in sdma_v3_0_soft_reset()
1346 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);  in sdma_v3_0_set_trap_irq_state()
1351 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);  in sdma_v3_0_set_trap_irq_state()
1362 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);  in sdma_v3_0_set_trap_irq_state()
1367 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);  in sdma_v3_0_set_trap_irq_state()