173 	return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;  in cik_sdma_ring_get_wptr()
340 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in cik_sdma_gfx_stop()
380 		me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);  in cik_sdma_enable()
892 		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgcg()
897 		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);  in cik_enable_sdma_mgcg()
910 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
915 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
920 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
925 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
1039 	u32 tmp = RREG32(mmSRBM_STATUS2);  in cik_sdma_is_idle()
1055 		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |  in cik_sdma_wait_for_idle()
1072 		 RREG32(mmSRBM_STATUS2));  in cik_sdma_print_status()
1075 			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));  in cik_sdma_print_status()
1077 			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1079 			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1081 			 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1083 			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1085 			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1087 			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1089 			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));  in cik_sdma_print_status()
1091 			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));  in cik_sdma_print_status()
1093 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));  in cik_sdma_print_status()
1095 			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));  in cik_sdma_print_status()
1097 			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));  in cik_sdma_print_status()
1099 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));  in cik_sdma_print_status()
1105 				 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));  in cik_sdma_print_status()
1107 				 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));  in cik_sdma_print_status()
1118 	u32 tmp = RREG32(mmSRBM_STATUS2);  in cik_sdma_soft_reset()
1122 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in cik_sdma_soft_reset()
1129 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in cik_sdma_soft_reset()
1138 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_sdma_soft_reset()
1142 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_sdma_soft_reset()
1148 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_sdma_soft_reset()
1170 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);  in cik_sdma_set_trap_irq_state()
1175 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);  in cik_sdma_set_trap_irq_state()
1186 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);  in cik_sdma_set_trap_irq_state()
1191 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);  in cik_sdma_set_trap_irq_state()