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/linux-4.4.14/arch/arm/boot/dts/
Ds3c2416.dtsi36 clocks: clock-controller@0x4c000000 { label
47 clocks = <&clocks PCLK_PWM>;
55 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
56 <&clocks SCLK_UART>;
63 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
64 <&clocks SCLK_UART>;
71 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
72 <&clocks SCLK_UART>;
81 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
82 <&clocks SCLK_UART>;
[all …]
Ds5pv210.dtsi60 external-clocks {
89 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
101 clocks: clock-controller@e0100000 { label
105 clocks = <&xxti>, <&xusbxti>;
141 clocks = <&clocks CLK_PDMA0>;
153 clocks = <&clocks CLK_PDMA1>;
168 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
184 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
198 clocks = <&clocks CLK_KEYIF>;
208 clocks = <&clocks CLK_I2C0>;
[all …]
Domap3xxx-clocks.dtsi20 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
27 clocks = <&osc_sys_ck>;
37 clocks = <&osc_sys_ck>;
45 clocks = <&dpll3_ck>;
53 clocks = <&dpll3_m2_ck>;
61 clocks = <&dpll4_ck>;
69 clocks = <&dpll3_m2x2_ck>;
77 clocks = <&sys_ck>;
87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Domap24xx-clocks.dtsi14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
80 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
88 clocks = <&aplls_clkin_ck>;
96 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
105 clocks = <&osc_ck>;
127 clocks = <&sys_ck>, <&sys_ck>;
134 clocks = <&sys_ck>;
[all …]
Domap54xx-clocks.dtsi20 clocks = <&pad_clks_src_ck>;
40 clocks = <&slimbus_src_clk>;
108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
115 clocks = <&dpll_abe_ck>;
121 clocks = <&dpll_abe_x2_ck>;
130 clocks = <&dpll_abe_m2x2_ck>;
138 clocks = <&dpll_abe_m2x2_ck>;
147 clocks = <&aess_fclk>;
156 clocks = <&dpll_abe_m2x2_ck>;
164 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap44xx-clocks.dtsi26 clocks = <&pad_clks_src_ck>;
52 clocks = <&slimbus_src_clk>;
138 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
145 clocks = <&dpll_abe_ck>;
152 clocks = <&dpll_abe_x2_ck>;
163 clocks = <&dpll_abe_m2x2_ck>;
171 clocks = <&dpll_abe_m2x2_ck>;
180 clocks = <&abe_clk>;
189 clocks = <&dpll_abe_x2_ck>;
200 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
[all …]
Dam33xx-clocks.dtsi14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
22 clocks = <&sys_clkin_ck>;
30 clocks = <&sys_clkin_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Dam43xx-clocks.dtsi14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Ds3c64xx.dtsi69 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
70 <&clocks SCLK_MMC0>;
80 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
81 <&clocks SCLK_MMC1>;
91 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
92 <&clocks SCLK_MMC2>;
102 clocks = <&clocks PCLK_WDT>;
112 clocks = <&clocks PCLK_IIC0>;
125 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
126 <&clocks SCLK_UART>;
[all …]
Ddra7xx-clocks.dtsi14 clocks = <&atl_gfclk_mux>;
20 clocks = <&atl_gfclk_mux>;
26 clocks = <&atl_gfclk_mux>;
32 clocks = <&atl_gfclk_mux>;
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
201 clocks = <&dpll_abe_ck>;
207 clocks = <&dpll_abe_x2_ck>;
218 clocks = <&dpll_abe_m2x2_ck>;
227 clocks = <&dpll_abe_ck>;
238 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap2430-clocks.dtsi15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
50 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
58 clocks = <&dsp_fck>;
66 clocks = <&dsp_fck>;
76 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
82 clocks = <&core_ck>;
[all …]
Domap34xx-omap36xx-clocks.dtsi14 clocks = <&l4_ick>;
22 clocks = <&security_l4_ick2>;
30 clocks = <&security_l4_ick2>;
38 clocks = <&security_l4_ick2>;
46 clocks = <&security_l4_ick2>;
54 clocks = <&dpll4_m5x2_ck>;
63 clocks = <&l4_ick>;
71 clocks = <&core_96m_fck>;
79 clocks = <&l3_ick>;
87 clocks = <&security_l3_ick>;
[all …]
Domap2420-clocks.dtsi15 clocks = <&core_ck>;
23 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
31 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
37 clocks = <&sys_clkout2_src>;
47 clocks = <&dsp_fck>;
55 clocks = <&dsp_fck>;
65 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
71 clocks = <&core_ck>;
79 clocks = <&core_ck>;
88 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
[all …]
Dste-nomadik-stn8815.dtsi39 clocks = <&timclk>, <&pclk>;
48 clocks = <&timclk>, <&pclk>;
63 clocks = <&pclk>;
77 clocks = <&pclk>;
91 clocks = <&pclk>;
106 clocks = <&pclk>;
196 clocks = <&mxtal>;
204 clocks = <&mxtal>;
211 clocks = <&pll1>;
219 clocks = <&hclk>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&sys_ck>, <&sys_ck>;
40 clocks = <&dpll5_ck>;
49 clocks = <&core_ck>;
57 clocks = <&core_ck>;
65 clocks = <&core_ck>;
73 clocks = <&core_ck>;
81 clocks = <&dpll4_m2x2_ck>;
89 clocks = <&core_ck>;
[all …]
Dsocfpga.dtsi91 clocks = <&l4_main_clk>;
100 clocks = <&can0_clk>;
108 clocks = <&can1_clk>;
116 clocks {
145 clocks = <&osc1>;
151 clocks = <&main_pll>;
159 clocks = <&main_pll>;
167 clocks = <&main_pll>, <&osc1>;
175 clocks = <&main_pll>;
182 clocks = <&main_pll>;
[all …]
Dr8a7793.dtsi31 clocks = <&cpg_clocks R8A7793_CLK_Z>;
69 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
89 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
113 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
121 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
131 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
141 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
149 clocks {
163 /* Special CPG clocks */
165 compatible = "renesas,r8a7793-cpg-clocks",
[all …]
Domap3430es1-clocks.dtsi14 clocks = <&l3_ick>;
22 clocks = <&l3_ick>;
31 clocks = <&gfx_l3_ck>;
39 clocks = <&gfx_l3_fck>;
47 clocks = <&gfx_l3_fck>;
55 clocks = <&sys_ck>;
63 clocks = <&core_48m_fck>;
71 clocks = <&corex2_fck>;
79 clocks = <&corex2_fck>;
88 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
[all …]
Ddm816x-clocks.dtsi12 clocks = <&sys_clkin_ck &sys_clkin_ck>;
28 clocks = <&sys_clkin_ck &sys_clkin_ck>;
40 clocks = <&sys_clkin_ck &sys_clkin_ck>;
51 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
92 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
100 clocks = <&clkout_pre_ck>;
109 clocks = <&clkout_div_ck>;
114 /* CM_DPLL clocks p1795 */
118 clocks = <&main_fapll 1>;
126 clocks = <&main_fapll 2>;
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
37 clocks = <&ssi_ssr_fck>;
45 clocks = <&core_l3_ick>;
53 clocks = <&l4_ick>;
61 clocks = <&ssi_l4_ick>;
69 clocks = <&omap_96m_fck>;
77 clocks = <&sys_ck>;
85 clocks = <&omap_96m_fck>;
[all …]
Dr8a7794.dtsi74 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
87 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
100 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
113 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
126 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
139 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
152 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
161 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
181 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
213 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
[all …]
Dwm8750.dtsi71 clocks {
90 clocks = <&ref25>;
97 clocks = <&ref25>;
104 clocks = <&ref25>;
111 clocks = <&ref25>;
118 clocks = <&ref25>;
125 clocks = <&plla>;
132 clocks = <&pllb>;
139 clocks = <&pllb>;
146 clocks = <&plld>;
[all …]
Dkeystone-clocks.dtsi11 clocks {
19 clocks = <&mainpllclk>, <&refclksys>;
29 clocks = <&mainmuxclk>;
38 clocks = <&mainmuxclk>;
47 clocks = <&mainmuxclk>;
57 clocks = <&mainmuxclk>;
67 clocks = <&chipclk1>;
76 clocks = <&chipclk1>;
85 clocks = <&papllclk>;
94 clocks = <&chipclk1>;
[all …]
Dr7s72100.dtsi33 clocks {
38 /* External clocks */
55 /* Fixed factor clocks */
59 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
67 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
75 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
81 /* Special CPG clocks */
84 compatible = "renesas,r7s72100-cpg-clocks",
85 "renesas,rz-cpg-clocks";
87 clocks = <&extal_clk>, <&usb_x1_clk>;
[all …]
Dk2hk-clocks.dtsi11 clocks {
15 clocks = <&refclkarm>;
24 clocks = <&refclksys>;
32 clocks = <&refclkpass>;
41 clocks = <&refclkddr3a>;
50 clocks = <&refclkddr3b>;
59 clocks = <&chipclk16>;
69 clocks = <&chipclk1rstiso13>;
79 clocks = <&chipclk12>;
89 clocks = <&chipclk1>;
[all …]
Dsocfpga_arria10.dtsi92 clocks {
121 clocks = <&osc1>, <&cb_intosc_ls_clk>,
128 clocks = <&main_pll>;
135 clocks = <&main_pll>;
142 clocks = <&main_pll>;
149 clocks = <&main_pll>;
156 clocks = <&main_pll>;
163 clocks = <&main_pll>;
171 clocks = <&main_pll>;
178 clocks = <&main_pll>;
[all …]
Dr8a7779.dtsi71 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
186 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
197 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
208 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
217 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
227 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
237 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
247 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
257 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
[all …]
Dsh73a0.dtsi45 clocks = <&twd_clk>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
[all …]
Dr8a7740.dtsi60 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
87 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
109 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
131 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
153 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
162 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
179 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
193 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
202 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
212 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
[all …]
Dwm8850.dtsi68 clocks {
87 clocks = <&ref24>;
94 clocks = <&ref24>;
101 clocks = <&ref24>;
108 clocks = <&ref24>;
115 clocks = <&ref24>;
122 clocks = <&ref24>;
129 clocks = <&ref24>;
136 clocks = <&plla>;
143 clocks = <&pllb>;
[all …]
Dr8a7791.dtsi52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
106 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
119 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
132 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
145 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
158 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
171 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
184 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
192 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
[all …]
Dr8a7790.dtsi53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
136 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
149 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
162 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
175 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
209 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
226 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
246 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
[all …]
Dwm8505.dtsi68 clocks {
87 clocks = <&ref25>;
94 clocks = <&ref25>;
101 clocks = <&ref25>;
108 clocks = <&ref25>;
115 clocks = <&plla>;
122 clocks = <&pllb>;
129 clocks = <&pllb>;
136 clocks = <&plld>;
143 clocks = <&ref24>;
[all …]
Dk2l-clocks.dtsi11 clocks {
15 clocks = <&refclksys>;
24 clocks = <&refclksys>;
32 clocks = <&refclksys>;
41 clocks = <&refclksys>;
50 clocks = <&chipclk12>;
60 clocks = <&chipclk12>;
70 clocks = <&chipclk1>;
80 clocks = <&chipclk1>;
90 clocks = <&chipclk1>;
[all …]
Dhisi-x5hd2.dtsi45 clocks = <&clock HIX5HD2_FIXED_24M>;
59 clocks = <&clock HIX5HD2_FIXED_24M>;
68 clocks = <&clock HIX5HD2_FIXED_24M>;
77 clocks = <&clock HIX5HD2_FIXED_24M>;
86 clocks = <&clock HIX5HD2_FIXED_24M>;
94 clocks = <&clock HIX5HD2_FIXED_83M>;
103 clocks = <&clock HIX5HD2_FIXED_83M>;
112 clocks = <&clock HIX5HD2_FIXED_83M>;
121 clocks = <&clock HIX5HD2_FIXED_83M>;
130 clocks = <&clock HIX5HD2_FIXED_83M>;
[all …]
Dimx27.dtsi49 clocks {
73 clocks = <&clks IMX27_CLK_CPU_DIV>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
142 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
151 clocks = <&clks IMX27_CLK_CKIL>,
160 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
[all …]
Dr8a73a4.dtsi99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
166 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
201 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
241 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
251 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
262 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
273 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
284 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
[all …]
Dexynos5250.dtsi65 clocks = <&clock CLK_ARM_CLK>;
133 clocks = <&clock CLK_FIN_PLL>,
149 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
175 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
231 clocks = <&clock CLK_FIN_PLL>;
247 clocks = <&clock CLK_WDT>;
256 clocks = <&clock CLK_G2D>;
266 clocks = <&clock CLK_MFC>;
276 clocks = <&clock CLK_TMU>;
305 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
[all …]
Dste-u300.dts46 /* Slow bridge clocks under PLL13 */
52 clocks = <&pll13>;
59 clocks = <&slow_clk>;
66 clocks = <&slow_clk>;
73 clocks = <&slow_clk>;
80 clocks = <&slow_clk>;
87 clocks = <&slow_clk>;
99 clocks = <&pll208>;
106 clocks = <&app208>;
113 clocks = <&pll208>;
[all …]
Dexynos4.dtsi63 clocks = <&clock_audss EXYNOS_I2S_BUS>;
168 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
188 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
200 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
212 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
224 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
236 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
251 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
267 clocks = <&clock CLK_WDT>;
277 clocks = <&clock CLK_RTC>;
[all …]
Defm32gg.dtsi29 clocks = <&cmu clk_HFPERCLKADC0>;
41 clocks = <&cmu clk_HFPERCLKGPIO>;
51 clocks = <&cmu clk_HFPERCLKI2C0>;
62 clocks = <&cmu clk_HFPERCLKI2C1>;
73 clocks = <&cmu clk_HFPERCLKUSART0>;
83 clocks = <&cmu clk_HFPERCLKUSART1>;
93 clocks = <&cmu clk_HFPERCLKUSART2>;
101 clocks = <&cmu clk_HFPERCLKUSART0>;
109 clocks = <&cmu clk_HFPERCLKUSART1>;
117 clocks = <&cmu clk_HFPERCLKUSART2>;
[all …]
Dpxa27x.dtsi26 clocks = <&clks CLK_NONE>;
33 clocks = <&clks CLK_USBHOST>;
41 clocks = <&clks CLK_PWM0>;
48 clocks = <&clks CLK_PWM1>;
55 clocks = <&clks CLK_PWM0>;
62 clocks = <&clks CLK_PWM1>;
69 clocks = <&clks CLK_PWRI2C>;
79 clocks = <&clks CLK_USB>;
87 clocks = <&clks CLK_KEYPAD>;
100 clocks = <&clks CLK_CAMERA>;
[all …]
Dversatile-ab.dts40 clocks = <&xtal24mhz>;
49 clocks = <&xtal24mhz>;
57 clocks = <&xtal24mhz>;
124 clocks = <&pclk>;
132 clocks = <&xtal24mhz>, <&pclk>;
140 clocks = <&xtal24mhz>, <&pclk>;
148 clocks = <&xtal24mhz>, <&pclk>;
155 clocks = <&pclk>;
162 clocks = <&pclk>;
170 clocks = <&osc1>, <&pclk>;
[all …]
Dexynos5420.dtsi169 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
178 clocks = <&clock CLK_MFC>;
191 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
203 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
215 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
229 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
255 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
283 clocks = <&clock CLK_FIN_PLL>,
338 clocks = <&clock_audss EXYNOS_ADMA>;
[all …]
Dimx25.dtsi56 clocks {
86 clocks = <&clks 48>;
97 clocks = <&clks 48>;
107 clocks = <&clks 75>, <&clks 75>;
116 clocks = <&clks 76>, <&clks 76>;
125 clocks = <&clks 120>, <&clks 57>;
134 clocks = <&clks 121>, <&clks 57>;
144 clocks = <&clks 48>;
154 clocks = <&clks 51>;
165 clocks = <&clks 78>, <&clks 78>;
[all …]
Dr8a7778.dtsi55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
155 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
166 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
177 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
188 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
199 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
214 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
229 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
244 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
297 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
[all …]
Demev2.dtsi60 clocks@e0110000 {
74 clocks = <&pll3_fo>;
80 clocks = <&iic0_sclkdiv>;
86 clocks = <&pll3_fo>;
92 clocks = <&iic1_sclkdiv>;
97 clocks = <&c32ki>;
105 clocks = <&pll3_fo>;
111 clocks = <&pll3_fo>;
117 clocks = <&pll3_fo>;
123 clocks = <&pll3_fo>;
[all …]
Dlpc18xx.dtsi31 clocks = <&ccu1 CLK_CPU_CORE>;
35 clocks {
74 clocks =<&ccu1 CLK_CPU_SCT>;
86 clocks = <&ccu1 CLK_CPU_DMA>;
105 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
116 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
126 clocks = <&ccu1 CLK_CPU_USB0>;
138 clocks = <&ccu1 CLK_CPU_USB1>;
146 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
163 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
[all …]
Dsun4i-a10.dtsi68 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
77 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
86 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
95 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
108 clocks = <&cpu>;
159 clocks {
166 * other mux clocks when a specific parent clock is not
195 clocks = <&osc24M>;
203 clocks = <&osc24M>;
212 clocks = <&osc24M>;
[all …]
Dwm8650.dtsi65 clocks {
84 clocks = <&ref25>;
91 clocks = <&ref25>;
98 clocks = <&ref25>;
105 clocks = <&ref25>;
112 clocks = <&ref25>;
119 clocks = <&plla>;
126 clocks = <&pllb>;
133 clocks = <&pllb>;
140 clocks = <&plld>;
[all …]
Dsun5i.dtsi62 clocks = <&cpu>;
66 clocks {
73 * other mux clocks when a specific parent clock is not
102 clocks = <&osc24M>;
110 clocks = <&osc24M>;
119 clocks = <&osc24M>;
127 clocks = <&osc24M>;
135 clocks = <&osc24M>;
144 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
152 clocks = <&cpu>;
[all …]
Dvfxxx.dtsi90 clocks = <&clks VF610_CLK_DMAMUX0>,
99 clocks = <&clks VF610_CLK_FLEXCAN0>,
109 clocks = <&clks VF610_CLK_UART0>;
121 clocks = <&clks VF610_CLK_UART1>;
133 clocks = <&clks VF610_CLK_UART2>;
145 clocks = <&clks VF610_CLK_UART3>;
159 clocks = <&clks VF610_CLK_DSPI0>;
171 clocks = <&clks VF610_CLK_DSPI1>;
181 clocks = <&clks VF610_CLK_SAI2>,
195 clocks = <&clks VF610_CLK_PIT>;
[all …]
Dam35xx-clocks.dtsi14 clocks = <&ipss_ick>;
22 clocks = <&rmii_ck>;
30 clocks = <&ipss_ick>;
38 clocks = <&pclk_ck>;
46 clocks = <&ipss_ick>;
54 clocks = <&sys_ck>;
62 clocks = <&sys_ck>;
71 clocks = <&core_l3_ick>;
91 clocks = <&core_l4_ick>;
99 clocks = <&core_48m_fck>;
[all …]
Dimx51.dtsi48 clocks {
85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
231 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
[all …]
Dzynq-7000.dtsi26 clocks = <&clkc 3>;
40 clocks = <&clkc 3>;
72 clocks = <&clkc 12>;
78 clocks = <&clkc 19>, <&clkc 36>;
90 clocks = <&clkc 20>, <&clkc 37>;
102 clocks = <&clkc 42>;
112 clocks = <&clkc 38>;
123 clocks = <&clkc 39>;
157 clocks = <&clkc 23>, <&clkc 40>;
166 clocks = <&clkc 24>, <&clkc 41>;
[all …]
Dbcm2835.dtsi65 clocks: cprman@7e101000 { label
73 clocks = <&clk_osc>;
115 clocks = <&clocks BCM2835_CLOCK_UART>,
116 <&clocks BCM2835_CLOCK_VPU>;
136 clocks = <&clocks BCM2835_CLOCK_VPU>;
146 clocks = <&clocks BCM2835_CLOCK_VPU>;
156 clocks = <&clocks BCM2835_CLOCK_EMMC>;
164 clocks = <&clocks BCM2835_CLOCK_VPU>;
174 clocks = <&clocks BCM2835_CLOCK_VPU>;
191 clocks {
Dimx53.dtsi54 clocks = <&clks IMX5_CLK_ARM>;
80 clocks {
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
205 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
217 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
242 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
256 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
[all …]
Dpxa3xx.dtsi22 clocks = <&clks CLK_PWRI2C>;
32 clocks = <&clks CLK_NAND>;
48 clocks = <&clks CLK_GPIO>;
61 clocks = <&clks CLK_MMC>;
72 clocks = <&clks CLK_MMC1>;
83 clocks = <&clks CLK_MMC2>;
94 clocks = <&clks CLK_USBHOST>;
99 clocks {
101 * The muxing of external clocks/internal dividers for osc* clock
109 compatible = "marvell,pxa300-clocks";
[all …]
Datlas6.dtsi30 clocks = <&clks 12>;
87 clocks = <&clks 42>;
101 clocks = <&clks 5>;
108 clocks = <&clks 32>;
122 clocks = <&clks 34>;
133 clocks = <&clks 35>;
148 clocks = <&clks 32>;
162 clocks = <&clks 33>;
183 clocks = <&clks 9>;
191 clocks = <&clks 8>;
[all …]
Dexynos3250.dtsi56 clocks = <&cmu CLK_ARM_CLK>;
88 fixed-rate-clocks {
195 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
219 clocks = <&cmu CLK_TMU_APBIF>;
241 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
266 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
269 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
281 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
291 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
307 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
[all …]
Dstm32f429.dtsi51 clocks {
64 clocks = <&rcc 0 128>;
72 clocks = <&rcc 0 129>;
80 clocks = <&rcc 0 130>;
88 clocks = <&rcc 0 131>;
95 clocks = <&rcc 0 132>;
103 clocks = <&rcc 0 133>;
111 clocks = <&rcc 0 145>;
119 clocks = <&rcc 0 146>;
127 clocks = <&rcc 0 147>;
[all …]
Dtegra30.dtsi39 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
108 clocks = <&tegra_car TEGRA30_CLK_MPE>;
117 clocks = <&tegra_car TEGRA30_CLK_VI>;
126 clocks = <&tegra_car TEGRA30_CLK_EPP>;
135 clocks = <&tegra_car TEGRA30_CLK_ISP>;
144 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
152 clocks = <&tegra_car TEGRA30_CLK_GR3D
164 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
183 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
[all …]
Dsun7i-a20.dtsi70 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
79 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
87 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
101 clocks = <&cpu>;
175 clocks {
199 clocks = <&osc24M>;
207 clocks = <&osc24M>;
216 clocks = <&osc24M>;
224 clocks = <&osc24M>;
232 clocks = <&osc24M>;
[all …]
Decx-common.dtsi52 clocks = <&eclk>;
60 clocks = <&pclk>;
70 clocks = <&pclk>;
81 clocks = <&pclk>;
92 clocks = <&pclk>;
103 clocks = <&pclk>;
112 clocks = <&pclk>;
120 clocks = <&pclk>;
128 clocks = <&pclk>;
145 clocks {
[all …]
Dtegra20.dtsi17 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
30 clocks = <&tegra_car TEGRA20_CLK_MPE>;
39 clocks = <&tegra_car TEGRA20_CLK_VI>;
48 clocks = <&tegra_car TEGRA20_CLK_EPP>;
57 clocks = <&tegra_car TEGRA20_CLK_ISP>;
66 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
74 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
83 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
100 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
117 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
[all …]
Dsama5d2.dtsi79 clocks {
117 clocks = <&udphs_clk>, <&utmi>;
244 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
253 clocks = <&utmi>, <&uhphs_clk>;
270 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
279 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
293 clocks = <&ddrck>, <&mpddr_clk>;
302 clocks = <&dma0_clk>;
329 clocks = <&main_xtal>;
337 clocks = <&main_rc_osc &main_osc>;
[all …]
Dsun6i-a31.dtsi68 clocks = <&pll6 0>;
76 clocks = <&pll6 0>;
100 clocks = <&cpu>;
177 clocks {
199 clocks = <&osc24M>;
207 clocks = <&osc24M>;
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
230 clocks = <&cpu>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
246 assigned-clocks = <&ahb1>;
[all …]
Dstih416-clock.dtsi13 clocks {
37 clocks = <&clk_sysin>;
49 clocks = <&clk_sysin>;
59 clocks = <&clk_s_a0_osc_prediv>,
74 clocks = <&clk_s_a0_osc_prediv>,
95 clocks = <&clk_sysin>;
107 clocks = <&clk_sysin>;
117 clocks = <&clk_s_a1_osc_prediv>,
132 clocks = <&clk_s_a1_osc_prediv>,
159 clocks = <&clk_sysin>;
[all …]
Dprima2.dtsi32 clocks = <&clks 12>;
98 clocks = <&clks 42>;
112 clocks = <&clks 5>;
119 clocks = <&clks 32>;
139 clocks = <&clks 35>;
154 clocks = <&clks 32>;
168 clocks = <&clks 33>;
189 clocks = <&clks 9>;
197 clocks = <&clks 8>;
213 clocks = <&clks 11>;
[all …]
Dstih415-clock.dtsi12 clocks {
36 clocks = <&clk_sysin>;
48 clocks = <&clk_sysin>;
58 clocks = <&clk_s_a0_osc_prediv>,
73 clocks = <&clk_s_a0_osc_prediv>,
94 clocks = <&clk_sysin>;
106 clocks = <&clk_sysin>;
116 clocks = <&clk_s_a1_osc_prediv>,
131 clocks = <&clk_s_a1_osc_prediv>,
157 clocks = <&clk_sysin>;
[all …]
Dimx50.dtsi51 clocks {
105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
154 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
166 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
178 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
191 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
[all …]
Dtegra114.dtsi18 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
31 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
39 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
48 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
67 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
86 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
97 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
113 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
161 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
211 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
[all …]
Dintegratorcp.dts18 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
35 clocks = <&xtal_codec>;
74 clocks = <&xtal24mhz>;
83 clocks = <&xtal24mhz>;
92 clocks = <&xtal24mhz>;
104 clocks = <&xtal25mhz>;
110 clocks = <&timclk>;
116 clocks = <&timclk>;
159 clocks = <&pclk>;
165 clocks = <&uartclk>, <&pclk>;
[all …]
Dat91sam9261.dtsi49 clocks {
78 clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
89 clocks = <&lcd_clk>, <&hclk1>;
122 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
130 clocks = <&udc_clk>, <&udpck>;
144 clocks = <&mci0_clk>;
157 clocks = <&twi0_clk>;
169 clocks = <&usart0_clk>;
182 clocks = <&usart1_clk>;
195 clocks = <&usart2_clk>;
[all …]
Drk3xxx.dtsi80 clocks = <&cru ACLK_DMA1>;
90 clocks = <&cru ACLK_DMA1>;
101 clocks = <&cru ACLK_DMA2>;
129 clocks = <&cru CORE_PERI>;
136 clocks = <&cru CORE_PERI>;
154 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
165 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
173 clocks = <&cru HCLK_OTG0>;
189 clocks = <&cru HCLK_OTG1>;
206 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
[all …]
Dsun9i-a80.dtsi122 clocks {
150 clocks = <&ahb1_gates 1>;
161 clocks = <&ahb1_gates 1>;
171 clocks = <&osc24M>;
179 clocks = <&osc24M>;
187 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
195 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
203 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
211 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
219 clocks = <&osc24M>, <&pll4>;
[all …]
Dimx6sx.dtsi74 clocks = <&clks IMX6SX_CLK_ARM>,
95 clocks {
147 clocks = <&clks IMX6SX_CLK_OCRAM>;
170 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
181 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
214 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
235 clocks = <&clks IMX6SX_CLK_ECSPI1>,
247 clocks = <&clks IMX6SX_CLK_ECSPI2>,
259 clocks = <&clks IMX6SX_CLK_ECSPI3>,
271 clocks = <&clks IMX6SX_CLK_ECSPI4>,
[all …]
Dimx35.dtsi70 clocks = <&clks 51>;
81 clocks = <&clks 53>;
90 clocks = <&clks 9>, <&clks 70>;
99 clocks = <&clks 9>, <&clks 71>;
110 clocks = <&clks 52>;
121 clocks = <&clks 68>;
134 clocks = <&clks 35 &clks 35>;
156 clocks = <&clks 9>, <&clks 72>;
168 clocks = <&clks 36 &clks 36>;
176 clocks = <&clks 46>, <&clks 8>;
[all …]
Dkirkwood.dtsi19 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
53 clocks = <&gate_clk 7>;
62 clocks = <&gate_clk 17>;
120 core_clk: core-clocks@10030 {
133 clocks = <&gate_clk 7>;
148 clocks = <&gate_clk 7>;
160 clocks = <&gate_clk 7>;
170 clocks = <&gate_clk 7>;
181 clocks = <&gate_clk 7>;
192 clocks = <&gate_clk 7>;
[all …]
Dstih407-family.dtsi54 clocks = <&arm_periph_clk>;
174 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
185 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
196 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
208 clocks = <&clk_sysin>;
219 clocks = <&clk_sysin>;
228 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
241 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
254 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
267 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
[all …]
Dhi3620.dtsi115 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
125 clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
135 clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
145 clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
155 clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
170 clocks = <&clock HI3620_UARTCLK0>;
179 clocks = <&clock HI3620_UARTCLK1>;
188 clocks = <&clock HI3620_UARTCLK2>;
197 clocks = <&clock HI3620_UARTCLK3>;
206 clocks = <&clock HI3620_UARTCLK4>;
[all …]
Dsun8i-a23-a33.dtsi63 clocks = <&pll6 0>;
96 clocks {
119 clocks = <&osc24M>;
135 clocks = <&osc24M>;
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
158 clocks = <&cpu>;
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
174 clocks = <&ahb1>;
182 clocks = <&apb1>;
193 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
[all …]
Dat91sam9n12.dtsi53 clocks {
95 clocks = <&ddrck>;
120 clocks = <&main_xtal>;
127 clocks = <&main_rc_osc>, <&main_osc>;
134 clocks = <&main>;
151 clocks = <&plla>;
158 clocks = <&main>;
169 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
178 clocks = <&pllb>;
186 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
[all …]
Domap36xx-clocks.dtsi14 clocks = <&sys_ck>, <&sys_ck>;
21 clocks = <&dpll4_m5x2_mul_ck>;
31 clocks = <&dpll4_m2x2_mul_ck>;
40 clocks = <&dpll3_m3x2_mul_ck>;
49 clocks = <&dpll4_m3x2_mul_ck>;
58 clocks = <&dpll4_m6x2_mul_ck>;
67 clocks = <&per_48m_fck>;
96 clocks = <&dpll4_ck>;
101 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
Dk2e-clocks.dtsi11 clocks {
15 clocks = <&refclksys>;
23 clocks = <&refclkpass>;
32 clocks = <&refclkddr3a>;
41 clocks = <&chipclk16>;
51 clocks = <&chipclk12>;
61 clocks = <&chipclk12>;
71 clocks = <&chipclk13>;
Dat91sam9263.dtsi51 clocks {
108 clocks = <&main_xtal>;
114 clocks = <&main_osc>;
121 clocks = <&main>;
133 clocks = <&main>;
145 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
154 clocks = <&pllb>;
162 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
197 clocks = <&usb>;
203 clocks = <&usb>;
[all …]
Dimx6sl.dtsi58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
78 clocks {
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
145 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
164 clocks = <&clks IMX6SL_CLK_ECSPI1>,
176 clocks = <&clks IMX6SL_CLK_ECSPI2>,
188 clocks = <&clks IMX6SL_CLK_ECSPI3>,
200 clocks = <&clks IMX6SL_CLK_ECSPI4>,
211 clocks = <&clks IMX6SL_CLK_UART>,
224 clocks = <&clks IMX6SL_CLK_UART>,
[all …]
Dstih407-clock.dtsi10 clocks {
31 clocks = <&clk_m_a9>;
47 clocks = <&clk_sysin>;
54 * ARM CPU related clocks.
61 clocks = <&clockgen_a9_pll 0>,
74 clocks = <&clk_s_c0_flexgen 13>;
101 clocks = <&clk_sysin>;
111 clocks = <&clk_s_a0_pll 0>,
123 clocks = <&clk_sysin>;
139 clocks = <&clk_sysin>;
[all …]
Dimx7d.dtsi88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
429 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
[all …]
Dimx6ul.dtsi67 clocks = <&clks IMX6UL_CLK_ARM>,
163 clocks = <&clks IMX6UL_CLK_ECSPI1>,
175 clocks = <&clks IMX6UL_CLK_ECSPI2>,
187 clocks = <&clks IMX6UL_CLK_ECSPI3>,
199 clocks = <&clks IMX6UL_CLK_ECSPI4>,
210 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
221 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
232 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
243 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
308 clocks = <&clks IMX6UL_CLK_ENET>,
[all …]
Dtegra124.dtsi43 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
102 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
117 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
132 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
144 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
187 clocks = <&tegra_car TEGRA124_CLK_GPU>,
219 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
239 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
[all …]
Dimx6qdl.dtsi59 clocks {
99 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
110 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
128 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
155 clocks = <&clks IMX6QDL_CLK_TWD>;
188 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
221 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
240 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
254 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
268 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
[all …]
Dstih416.dtsi116 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
129 clocks = <&clk_sysin>;
136 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
149 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
162 clocks = <&clk_sysin>;
175 clocks = <&clk_sysin>;
203 clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
225 clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
233 clocks = <&clk_sysin>;
257 clocks = <&clk_sysin>;
[all …]
Dvt8500.dtsi58 clocks {
71 clocks = <&ref24>;
79 clocks = <&ref24>;
87 clocks = <&ref24>;
95 clocks = <&ref24>;
135 clocks = <&clkuart0>;
143 clocks = <&clkuart1>;
151 clocks = <&clkuart2>;
159 clocks = <&clkuart3>;
Darmada-38x.dtsi91 clocks = <&coreclk 0>;
101 clocks = <&coreclk 0>;
111 clocks = <&coreclk 0>;
121 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
161 clocks = <&coreclk 2>;
181 clocks = <&coreclk 0>;
193 clocks = <&coreclk 0>;
204 clocks = <&coreclk 0>;
215 clocks = <&coreclk 0>;
[all …]
Dat91sam9x5.dtsi55 clocks {
103 clocks = <&ddrck>;
128 clocks = <&main_xtal>;
135 clocks = <&main_rc_osc>, <&main_osc>;
142 clocks = <&main>;
159 clocks = <&plla>;
166 clocks = <&main>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
182 clocks = <&plladiv>, <&utmi>;
190 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
[all …]
Dqcom-ipq8064.dtsi64 clocks {
81 clocks = <&lcc AHBIX_CLK>,
122 clocks = <&sleep_clk>;
153 clocks = <&gcc GSBI2_H_CLK>;
167 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
177 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
191 clocks = <&gcc GSBI4_H_CLK>;
205 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
215 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
228 clocks = <&gcc GSBI5_H_CLK>;
[all …]
Dexynos5440.dtsi111 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
119 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
131 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
167 clocks = <&clock CLK_B_125>;
177 clocks = <&clock CLK_B_125>;
185 clocks = <&clock CLK_B_125>;
196 clocks = <&clock CLK_GMAC0>;
212 clocks = <&clock CLK_B_125>;
220 clocks = <&clock CLK_B_125>;
229 clocks = <&clock CLK_B_125>;
[all …]
Darm-realview-pb1176.dts67 clocks = <&xtal24mhz>;
75 clocks = <&xtal24mhz>;
83 clocks = <&xtal24mhz>;
91 clocks = <&xtal24mhz>;
99 clocks = <&xtal24mhz>;
102 /* FIXME: this actually hangs off the PLL clocks */
220 clocks = <&timclk>, <&timclk>, <&pclk>;
230 clocks = <&timclk>, <&timclk>, <&pclk>;
239 clocks = <&pclk>;
252 clocks = <&pclk>;
[all …]
Dexynos4415.dtsi191 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
249 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
265 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
277 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
286 clocks = <&cmu CLK_USBDEVICE>;
297 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
309 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
321 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
333 clocks = <&cmu CLK_USBHOST>;
359 clocks = <&cmu CLK_USBHOST>;
[all …]
Darmada-375.dtsi67 clocks {
124 clocks = <&coreclk 0>;
134 clocks = <&coreclk 0>;
144 clocks = <&coreclk 0>;
154 clocks = <&coreclk 0>;
164 clocks = <&coreclk 0>;
194 clocks = <&coreclk 2>;
211 clocks = <&gateclk 19>;
221 clocks = <&gateclk 3>, <&gateclk 19>;
252 clocks = <&coreclk 0>;
[all …]
Dstih410-clock.dtsi10 clocks {
33 clocks = <&clk_m_a9>;
49 clocks = <&clk_sysin>;
56 * ARM CPU related clocks.
63 clocks = <&clockgen_a9_pll 0>,
76 clocks = <&clk_s_c0_flexgen 13>;
103 clocks = <&clk_sysin>;
113 clocks = <&clk_s_a0_pll 0>,
126 clocks = <&clk_sysin>;
142 clocks = <&clk_sysin>;
[all …]
Dstih418-clock.dtsi10 clocks {
33 clocks = <&clk_m_a9>;
49 clocks = <&clk_sysin>;
56 * ARM CPU related clocks.
63 clocks = <&clockgen_a9_pll 0>,
76 clocks = <&clk_s_c0_flexgen 13>;
103 clocks = <&clk_sysin>;
113 clocks = <&clk_s_a0_pll 0>,
126 clocks = <&clk_sysin>;
142 clocks = <&clk_sysin>;
[all …]
Darmada-370-xp.dtsi95 clocks = <&coreclk 0>;
105 clocks = <&coreclk 0>;
115 clocks = <&coreclk 0>;
125 clocks = <&coreclk 0>;
135 clocks = <&coreclk 0>;
157 clocks = <&coreclk 0>;
167 clocks = <&coreclk 0>;
177 clocks = <&coreclk 0>;
187 clocks = <&coreclk 0>;
197 clocks = <&coreclk 0>;
[all …]
Dste-dbx5x0.dtsi56 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
70 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
84 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
120 clocks = <&prcmu_clk PRCMU_APEATCLK>;
156 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
170 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
221 clocks {
258 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
267 clocks = <&smp_twd_clk>;
274 clocks = <&smp_twd_clk>;
[all …]
Dat91sam9g45.dtsi57 clocks {
105 clocks = <&ddrck>;
112 clocks = <&ddrck>;
129 clocks = <&main_xtal>;
135 clocks = <&main_osc>;
142 clocks = <&main>;
159 clocks = <&plla>;
166 clocks = <&main>;
173 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
181 clocks = <&plladiv>, <&utmi>;
[all …]
Drk3288.dtsi113 clocks = <&cru ARMCLK>;
147 clocks = <&cru ACLK_DMAC2>;
157 clocks = <&cru ACLK_DMAC1>;
168 clocks = <&cru ACLK_DMAC1>;
214 clocks = <&xin24m>, <&cru PCLK_TIMER>;
226 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
238 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
250 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
262 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
276 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
[all …]
Dimx1.dtsi49 clocks = <&clks IMX1_CLK_MCU>;
72 clocks = <&clks IMX1_CLK_HCLK>,
81 clocks = <&clks IMX1_CLK_HCLK>,
90 clocks = <&clks IMX1_CLK_DUMMY>,
101 clocks = <&clks IMX1_CLK_HCLK>,
111 clocks = <&clks IMX1_CLK_HCLK>,
122 clocks = <&clks IMX1_CLK_DUMMY>,
131 clocks = <&clks IMX1_CLK_HCLK>,
141 clocks = <&clks IMX1_CLK_UART3_GATE>,
161 clocks = <&clks IMX1_CLK_DUMMY>,
[all …]
Dat91sam9260.dtsi52 clocks {
115 clocks = <&main_xtal>;
121 clocks = <&main_osc>;
134 clocks = <&slow_rc_osc>, <&slow_xtal>;
141 clocks = <&main>;
153 clocks = <&main>;
164 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
173 clocks = <&pllb>;
181 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
204 clocks = <&usb>;
[all …]
Dbcm21664.dtsi67 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
77 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
87 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
109 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
130 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
138 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
146 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
154 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
164 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
174 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
[all …]
Dat91rm9200.dtsi55 clocks {
112 clocks = <&main_xtal>;
118 clocks = <&main_osc>;
125 clocks = <&main>;
137 clocks = <&main>;
149 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
158 clocks = <&pllb>;
166 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
201 clocks = <&usb>;
207 clocks = <&usb>;
[all …]
Dhip04.dtsi232 clocks = <&clk_50m>, <&clk_50m>;
260 clocks = <&clk_168m>;
278 clocks = <&clk_375m>;
292 clocks = <&clk_375m>;
306 clocks = <&clk_375m>;
320 clocks = <&clk_375m>;
334 clocks = <&clk_375m>;
492 clocks = <&clk_375m>;
546 clocks = <&clk_375m>;
600 clocks = <&clk_375m>;
[all …]
Dexynos4x12.dtsi84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
104 clocks = <&clock CLK_TSADC>;
116 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
123 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
133 clocks = <&clock CLK_FIMC_LITE0>;
144 clocks = <&clock CLK_FIMC_LITE1>;
155 clocks = <&clock CLK_FIMC_LITE0>,
190 clocks = <&clock CLK_I2C1_ISP>;
205 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
216 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
[all …]
Dsama5d3.dtsi62 clocks {
110 clocks = <&mci0_clk>;
125 clocks = <&spi0_clk>;
139 clocks = <&ssc0_clk>;
148 clocks = <&tcb0_clk>, <&clk32k>;
163 clocks = <&twi0_clk>;
178 clocks = <&twi1_clk>;
191 clocks = <&usart0_clk>;
205 clocks = <&usart1_clk>;
216 clocks = <&uart0_clk>;
[all …]
Dberlin2q.dtsi62 clocks = <&chip_clk CLKID_CPU>;
121 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
130 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
140 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
161 clocks = <&chip_clk CLKID_TWD>;
184 clocks = <&chip_clk CLKID_USB2>;
209 clocks = <&chip_clk CLKID_GETH0>;
316 clocks = <&chip_clk CLKID_CFG>;
329 clocks = <&chip_clk CLKID_CFG>;
338 clocks = <&chip_clk CLKID_CFG>;
[all …]
Dbcm-cygnus-clock.dtsi33 clocks {
48 clocks = <&osc>;
56 clocks = <&armpll>;
65 clocks = <&armpll>;
74 clocks = <&osc>;
83 clocks = <&genpll 1>;
92 clocks = <&genpll 1>;
101 clocks = <&osc>;
110 clocks = <&osc>;
121 clocks = <&osc>;
Datlas7.dtsi45 clocks {
91 clocks = <&car 62>;
102 clocks = <&car 62>;
1235 clocks = <&car 138>, <&car 139>, <&car 237>,
1263 clocks = <&car 89>;
1278 clocks = <&car 90>;
1289 clocks = <&car 88>;
1298 clocks = <&car 91>;
1309 clocks = <&car 92>;
1320 clocks = <&car 93>;
[all …]
Dat91sam9rl.dtsi53 clocks {
90 clocks = <&lcd_clk>, <&lcd_clk>;
124 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
135 clocks = <&mci0_clk>;
146 clocks = <&twi0_clk>;
167 clocks = <&usart0_clk>;
180 clocks = <&usart1_clk>;
193 clocks = <&usart2_clk>;
206 clocks = <&usart3_clk>;
234 clocks = <&pwm_clk>;
[all …]
Dkeystone.dtsi87 /include/ "keystone-clocks.dtsi"
95 clocks = <&clkuart0>;
105 clocks = <&clkuart1>;
113 clocks = <&clki2c>;
123 clocks = <&clki2c>;
133 clocks = <&clki2c>;
145 clocks = <&clkspi>;
156 clocks = <&clkspi>;
167 clocks = <&clkspi>;
185 clocks = <&clkusb>;
[all …]
Dberlin2.dtsi67 clocks = <&chip_clk CLKID_CPU>;
103 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
112 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
122 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
152 clocks = <&chip_clk CLKID_TWD>;
158 clocks = <&chip_clk CLKID_GETH1>;
181 clocks = <&chip_clk CLKID_GETH0>;
280 clocks = <&chip_clk CLKID_CFG>;
289 clocks = <&chip_clk CLKID_CFG>;
298 clocks = <&chip_clk CLKID_CFG>;
[all …]
Dsama5d4.dtsi96 clocks {
134 clocks = <&udphs_clk>, <&utmi>;
261 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
270 clocks = <&utmi>, <&uhphs_clk>;
309 clocks = <&hsmc_clk>;
324 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
353 clocks = <&dma1_clk>;
363 clocks = <&isi_clk>;
375 clocks = <&ddrck>, <&mpddr_clk>;
384 clocks = <&dma0_clk>;
[all …]
Ddove.dtsi108 clocks = <&gate_clk 4>;
126 clocks = <&gate_clk 5>;
156 clocks = <&core_clk 0>;
170 clocks = <&core_clk 0>;
179 clocks = <&core_clk 0>;
188 clocks = <&core_clk 0>;
199 clocks = <&core_clk 0>;
208 clocks = <&core_clk 0>;
219 clocks = <&core_clk 0>;
254 clocks = <&core_clk 0>;
[all …]
Domap36xx.dtsi52 clocks = <&sys_ck>;
94 clocks = <&dss_tv_fck>, <&dss_96m_fck>;
101 clocks = <&ssi_ssr_fck>,
109 /include/ "omap34xx-omap36xx-clocks.dtsi"
110 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
111 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
112 /include/ "omap36xx-clocks.dtsi"
Dpxa168.dtsi63 clocks = <&soc_clocks PXA168_CLK_UART0>;
72 clocks = <&soc_clocks PXA168_CLK_UART1>;
81 clocks = <&soc_clocks PXA168_CLK_UART2>;
94 clocks = <&soc_clocks PXA168_CLK_GPIO>;
122 clocks = <&soc_clocks PXA168_CLK_TWSI0>;
132 clocks = <&soc_clocks PXA168_CLK_TWSI1>;
142 clocks = <&soc_clocks PXA168_CLK_RTC>;
148 soc_clocks: clocks{
Darmada-39x.dtsi122 clocks = <&coreclk 2>;
142 clocks = <&coreclk 0>;
154 clocks = <&coreclk 0>;
165 clocks = <&coreclk 0>;
176 clocks = <&coreclk 0>;
187 clocks = <&coreclk 0>;
198 clocks = <&coreclk 0>;
208 clocks = <&coreclk 0>;
218 clocks = <&coreclk 0>;
228 clocks = <&coreclk 0>;
[all …]
Dberlin2cd.dtsi65 clocks = <&chip_clk CLKID_CPU>;
97 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
121 clocks = <&chip_clk CLKID_TWD>;
143 clocks = <&chip_clk CLKID_GETH1>;
161 clocks = <&chip_clk CLKID_GETH0>;
260 clocks = <&chip_clk CLKID_CFG>;
269 clocks = <&chip_clk CLKID_CFG>;
278 clocks = <&chip_clk CLKID_CFG>;
287 clocks = <&chip_clk CLKID_CFG>;
296 clocks = <&chip_clk CLKID_CFG>;
[all …]
Dbcm11351.dtsi67 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
77 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
87 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
97 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
119 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
142 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
150 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
158 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
166 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
181 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
[all …]
Duniphier-proxstream2.dtsi84 clocks {
136 clocks = <&uart_clk>;
146 clocks = <&uart_clk>;
156 clocks = <&uart_clk>;
166 clocks = <&uart_clk>;
178 clocks = <&i2c_clk>;
191 clocks = <&i2c_clk>;
204 clocks = <&i2c_clk>;
217 clocks = <&i2c_clk>;
228 clocks = <&i2c_clk>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
20 - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
[all …]
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]
Dexynos5260-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
[all …]
Drenesas,cpg-div6-clocks.txt3 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
10 - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11 - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
12 - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
13 - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
14 - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
15 - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
16 - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
19 - clocks: Reference to the parent clock(s); either one, four, or eight
20 clocks must be specified. For clocks with multiple parents, invalid
[all …]
Dexynos7-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
45 - clocks: list of clock identifiers which are fed as the input to
47 find the input clocks for a given controller.
49 - clock-names: list of names of clocks which are fed as the input
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
67 Input clocks for ccore clock controller:
[all …]
Drenesas,rcar-gen2-cpg-clocks.txt3 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
13 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
14 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
15 and "renesas,rcar-gen2-cpg-clocks" as a fallback.
19 - clocks: References to the parent clocks: first to the EXTAL clock, second
22 - clock-output-names: The names of the clocks. Supported clocks are "main",
39 compatible = "renesas,r8a7790-cpg-clocks",
40 "renesas,rcar-gen2-cpg-clocks";
[all …]
Drenesas,rz-cpg-clocks.txt3 The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
4 CPU and GPU clocks, and several fixed ratio dividers.
11 - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
12 and "renesas,rz-cpg-clocks" as a fallback.
14 - clocks: References to possible parent clocks. Order must match clock modes
17 - clock-output-names: The names of the clocks. Supported clocks are "pll",
34 compatible = "renesas,r7s72100-cpg-clocks",
35 "renesas,rz-cpg-clocks";
37 clocks = <&extal_clk>, <&usb_x1_clk>;
50 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
Dvf610-clock.txt9 - clocks: list of clock identifiers which are external input clocks to the
11 the input clocks for a given controller.
12 - clock-names: list of names of clocks which are exteral input clocks to the
15 Input clocks for top clock controller:
22 ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
31 clocks = <&sxosc>, <&fxosc>;
39 clocks = <&clks VF610_CLK_UART1>;
Drenesas,r8a73a4-cpg-clocks.txt3 The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
8 - compatible: Must be "renesas,r8a73a4-cpg-clocks"
12 - clocks: Reference to the parent clocks ("extal1" and "extal2")
16 - clock-output-names: The names of the clocks. Supported clocks are "main",
25 compatible = "renesas,r8a73a4-cpg-clocks";
27 clocks = <&extal1_clk>, <&extal2_clk>;
Dat91-clock.txt25 All at91 specific clocks (clocks defined below) must be child
47 at91 peripheral clocks
53 at91 pll clocks
61 at91 programmable clocks
67 at91 system clocks
96 /* put at91 slow clocks here */
116 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
126 clocks = <&slow_xtal>;
131 - clocks : shall encode the slow clk sources (see atmel datasheet).
137 clocks = <&slow_rc_osc &slow_osc>;
[all …]
Drenesas,sh73a0-cpg-clocks.txt5 The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
10 - compatible: Must be "renesas,sh73a0-cpg-clocks"
14 - clocks: Reference to the parent clocks ("extal1" and "extal2")
18 - clock-output-names: The names of the clocks. Supported clocks are "main",
27 compatible = "renesas,sh73a0-cpg-clocks";
29 clocks = <&extal1_clk>, <&extal2_clk>;
Dsamsung,s3c2412-clock.txt15 to specify the clock which they consume. Some of the clocks are available only
18 All available clocks are defined as preprocessor macros in
22 External clocks:
24 There are several clocks that are generated outside the SoC. It is expected
32 clocks: clock-controller@4c000000 {
40 "clocks" and "clock-names" properties):
47 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
48 <&clocks SCLK_UART>;
Drenesas,r8a7740-cpg-clocks.txt5 The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
10 - compatible: Must be "renesas,r8a7740-cpg-clocks"
14 - clocks: Reference to the three parent clocks
16 - clock-output-names: The names of the clocks. Supported clocks are
27 compatible = "renesas,r8a7740-cpg-clocks";
29 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
Dclk-s5pv210-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
13 - clocks:
23 - clock-names: Aliases for the above clocks. They should be "hclk",
26 All available clocks are defined as preprocessor macros in
38 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
39 <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
44 about 'clocks' and 'clock-names' property.
50 clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
Dsamsung,s5pv210-clock.txt20 All available clocks are defined as preprocessor macros in
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
33 A subset of above clocks available on given board shall be specified in
36 documentation[1] for more information how to specify these clocks.
48 Example: Required external clocks:
66 "clocks" and "clock-names" properties):
75 clocks = <&clocks UART0>, <&clocks UART0>,
76 <&clocks SCLK_UART0>;
Dsamsung,s3c2443-clock.txt18 to specify the clock which they consume. Some of the clocks are available only
21 All available clocks are defined as preprocessor macros in
25 External clocks:
27 There are several clocks that are generated outside the SoC. It is expected
37 clocks: clock-controller@4c000000 {
45 "clocks" and "clock-names" properties):
53 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
54 <&clocks SCLK_UART>;
Dingenic,cgu.txt3 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
6 clocks.
12 - clocks : List of phandle & clock specifiers for clocks external to the CGU.
13 Two such external clocks should be specified - first the external crystal
15 - clock-names : List of name strings for the external clocks.
30 clocks = <&cgu JZ4740_CLK_UART0>;
50 clocks = <&ext> <&rtc>;
Dpistachio-clock.txt8 External clocks:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
37 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
57 - clocks: Must contain an entry for each clock in clock-names.
65 clocks = <&clk_core CLK_PERIPH_SYS>;
74 The peripheral general control block generates system interface clocks and
85 - clocks: Must contain an entry for each clock in clock-names.
[all …]
Demev2-clock.txt7 This is not a clock provider, but clocks under SMU depend on it.
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
34 - clocks: Input clock as described in clock-bindings.txt
42 clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
49 clocks = <&usia_u0_sclkdiv>;
59 clocks = <&usia_u0_sclk>;
81 clocks = <&c32ki>;
89 clocks = <&pll3_fo>;
95 clocks = <&usia_u0_sclkdiv>;
Dlpc1850-ccu.txt5 branch clocks are distributed between CCU1 and CCU2.
21 - clocks:
22 Shall contain a list of phandles for the base clocks routed
23 from the CGU to the specific CCU. See mapping of base clocks
35 Which branch clocks that are available on the CCU depends on the
38 A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
71 /* A user of CCU brach clocks */
74 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
Dqoriq-clock.txt36 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
37 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
52 - clocks: If clock-frequency is not specified, sysclk may be provided
53 as an input clock. Either clock-frequency or clocks must be
83 clocks = <&clockgen 3 0>;
97 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
98 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
99 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
100 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
109 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
[all …]
Dst,stm32-rcc.txt14 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
16 between gated clocks and other clocks and an index specifying the clock to
27 Specifying gated clocks
42 clocks = <&rcc 0 0>
47 clocks = <&rcc 0 36>
50 Specifying other clocks
64 clocks = <&rcc 1 1>
Drenesas,r8a7779-cpg-clocks.txt3 The CPG generates core clocks for the R8A7779. It includes one PLL and
10 - compatible: Must be "renesas,r8a7779-cpg-clocks"
13 - clocks: Reference to the parent clock
15 - clock-output-names: The names of the clocks. Supported clocks are "plla",
31 compatible = "renesas,r8a7779-cpg-clocks";
33 clocks = <&extal_clk>;
47 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
Dste-u300-syscon-clock.txt3 Bindings for the gated system controller clocks:
15 - clocks: parent clock(s)
17 The available clocks per type are as follows:
50 clocks = <&slow_clk>;
56 clocks = <&gpio_clk>;
67 - clocks: parent clock(s)
72 clocks = <&mmc_pclk>;
77 clocks = <&mmc_pclk>, <&mmc_mclk>;
Dnvidia,tegra124-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
19 (for Tegra124-specific clocks).
40 - clocks : Must contain an entry for each entry in clock-names.
41 See ../clocks/clock-bindings.txt for details.
58 clocks = <&tegra_car TEGRA124_CLK_USB2>;
65 clocks {
86 clocks = <&clk_32k> <&osc>;
96 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
102 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
Dbrcm,bcm2835-cprman.txt1 Broadcom BCM2835 CPRMAN clocks
6 The CPRMAN clock controller generates clocks in the audio power domain
19 - clocks: The external oscillator clock phandle
31 clocks: cprman@7e101000 {
35 clocks = <&clk_osc>;
42 clocks = <&clocks BCM2835_CLOCK_VPU>;
Dvt8500.txt15 Required properties for PLL clocks:
17 - clocks : shall be the input parent clock phandle for the clock. This should
21 Required properties for device clocks:
22 - clocks : shall be the input parent clock phandle for the clock. This should
29 Device clocks are required to have one or both of the following sets of
33 Gated device clocks:
41 Divisor device clocks:
62 clocks = <&ref25>;
69 clocks = <&pllb>;
Dsamsung,s3c2410-clock.txt18 to specify the clock which they consume. Some of the clocks are available only
21 All available clocks are defined as preprocessor macros in
25 External clocks:
33 clocks: clock-controller@4c000000 {
41 "clocks" and "clock-names" properties):
48 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
Drenesas,r8a7778-cpg-clocks.txt3 The CPG generates core clocks for the R8A7778. It includes two PLLs and
10 - compatible: Must be "renesas,r8a7778-cpg-clocks"
13 - clock-output-names: The names of the clocks. Supported clocks are
29 compatible = "renesas,r8a7778-cpg-clocks";
32 clocks = <&extal_clk>;
45 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
Dclock-bindings.txt44 clocks by index. The names should reflect the clock output signal
47 clock-indices: If the identifying number for the clocks in the node
51 For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
66 clocks: List of phandle and clock specifier pairs, one pair
73 order as the clocks property. Consumers drivers
75 with clocks specifiers.
77 clocks from this node. Useful for bus nodes to provide a
83 clocks = <&osc 1>, <&ref 0>;
107 clocks = <&osc 0>;
120 clocks = <&osc 0>, <&pll 1>;
[all …]
Dclk-exynos-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
19 - clocks:
31 - clock-names: Aliases for the above clocks. They should be "pll_ref",
34 The following is the list of clocks generated by the controller. Each clock is
36 clock which they consume. Some of the clocks are available only on a particular
39 Provided clocks:
65 Example 2: An example of a clock controller node with the input clocks
72 clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
79 about 'clocks' and 'clock-names' property.
88 clocks = <&clock_audss EXYNOS_I2S_BUS>,
Dsamsung,s3c64xx-clock.txt19 to specify the clock which they consume. Some of the clocks are available only
22 All available clocks are defined as preprocessor macros in
26 External clocks:
28 There are several clocks that are generated outside the SoC. It is expected
47 Example: Required external clocks:
65 "clocks" and "clock-names" properties):
74 clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
Dbrcm,iproc-clocks.txt6 The iProc clock controller manages clocks that are common to the iProc family.
9 comprises of several leaf clocks
11 Required properties for a PLL and its leaf clocks:
24 - clocks:
29 An ordered list of strings defining the names of the clocks
43 clocks = <&osc>;
48 Required properties for ASIU clocks:
50 ASIU clocks are a special case. These clocks are derived directly from the
55 clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
58 Have a value of <1> since there are more than 1 ASIU clocks
[all …]
Dsunxi.txt24 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
60 "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
62 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
63 "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
65 "allwinner,sun7i-a20-out-clk" - for the external output clocks
74 Required properties for all clocks:
76 - clocks : shall be the input parent clock(s) phandle for the clock. For
77 multiplexed clocks, the list order must match the hardware
89 And "allwinner,*-usb-clk" clocks also require:
96 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
[all …]
Dnvidia,tegra30-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
33 clocks = <&tegra_car TEGRA30_CLK_USB2>;
40 clocks {
61 clocks = <&clk_32k> <&osc>;
Dnvidia,tegra114-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
33 clocks = <&tegra_car TEGRA114_CLK_USB2>;
40 clocks {
61 clocks = <&clk_32k> <&osc>;
Dnvidia,tegra20-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
12 - clocks : Should contain phandle and clock specifiers for two clocks:
33 clocks = <&tegra_car TEGRA20_CLK_USB2>;
40 clocks {
61 clocks = <&clk_32k> <&osc>;
Drockchip.txt7 == Gate clocks ==
15 the 10 individual gates containing 16 clocks each.
23 - clocks : should contain the parent clock for each individual gate,
24 therefore the number of clocks elements should match the number of
27 Example using multiple gate clocks:
32 clocks = <&dummy>, <&dummy>,
57 clocks = <&xin24m>, <&xin24m>,
Dxgene.txt13 Required properties for SoC or PCP PLL clocks:
15 - clocks : shall be the input parent clock phandle for the clock. This should
20 Optional properties for PLL clocks:
23 Required properties for device clocks:
31 - clocks : shall be the input parent clock phandle for the clock.
34 Optional properties for device clocks:
53 clocks = <&refclk 0>;
63 clocks = <&refclk 0>;
73 clocks = <&socplldiv2 0>;
83 clocks = <&socplldiv2 0>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]
/linux-4.4.14/drivers/clk/bcm/
Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks = CLOCKS("ref_crystal",
[all …]
Dclk-bcm21664.c25 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
67 .clocks = CLOCKS("ref_crystal",
79 .clocks = CLOCKS("ref_crystal",
91 .clocks = CLOCKS("ref_crystal",
103 .clocks = CLOCKS("ref_crystal",
114 .clocks = CLOCKS("ref_32k"), /* Verify */
119 .clocks = CLOCKS("ref_32k"), /* Verify */
124 .clocks = CLOCKS("ref_32k"), /* Verify */
129 .clocks = CLOCKS("ref_32k"), /* Verify */
[all …]
/linux-4.4.14/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi108 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
121 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
134 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
142 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
152 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
164 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
172 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
182 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
193 clocks = <&clock_peric0 PCLK_UART0>,
203 clocks = <&clock_peric1 PCLK_UART1>,
[all …]
/linux-4.4.14/arch/powerpc/boot/dts/
Dmpc5121.dtsi54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
71 clocks = <&clks MPC512x_CLK_NFC>;
83 clocks {
142 clocks = <&osc>;
163 clocks = <&clks MPC512x_CLK_BDLC>,
175 clocks = <&clks MPC512x_CLK_BDLC>,
189 clocks = <&clks MPC512x_CLK_IPS>,
200 clocks = <&clks MPC512x_CLK_I2C>;
210 clocks = <&clks MPC512x_CLK_I2C>;
220 clocks = <&clks MPC512x_CLK_I2C>;
[all …]
Dmpc5125twr.dts59 clocks {
107 clocks = <&osc>;
133 clocks = <&clks MPC512x_CLK_BDLC>,
145 clocks = <&clks MPC512x_CLK_BDLC>,
157 clocks = <&clks MPC512x_CLK_IPS>,
168 clocks = <&clks MPC512x_CLK_I2C>;
178 clocks = <&clks MPC512x_CLK_I2C>;
188 clocks = <&clks MPC512x_CLK_I2C>;
201 clocks = <&clks MPC512x_CLK_DIU>;
222 clocks = <&clks MPC512x_CLK_FEC>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt5 functional clock but can be configured to provide different clocks.
9 In order to provide the support for ATL and it's output clocks (which can be used
14 To be able to integrate the ATL clocks with DT clock tree.
15 Provides ccf level representation of the ATL clocks to be used by drivers.
25 - clocks : link phandles to functional clock of ATL
34 - ti,provided-clocks : List of phandles to the clocks associated with the ATL
35 - clocks : link phandles to functional clock of ATL
50 /* clock bindings for atl provided clocks */
54 clocks = <&atl_gfclk_mux>;
60 clocks = <&atl_gfclk_mux>;
[all …]
Dcomposite.txt16 The binding must provide a list of the component clocks that shall be
17 merged to this clock. The component clocks shall be of one of the
27 - clocks : link phandles of component clocks
35 clocks = <&l4_ick>;
43 clocks = <&l4_ick>;
53 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
/linux-4.4.14/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi102 clocks = <&misc_clk &misc_clk>;
114 clocks = <&misc_clk &misc_clk>;
133 clocks = <&misc_clk>;
146 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
158 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
170 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
182 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
199 clocks = <&i2c_clk>;
210 clocks = <&i2c_clk>;
227 clocks = <&sata_clk>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dst,stih4xx.txt9 - clocks: from common clock binding: handle hardware IP needed clocks, the
10 number of clocks may depend on the SoC type.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: names of the clocks listed in clocks property in the same order.
21 clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
Dimg-ir-rev1.txt13 - clocks: List of clock specifiers as described in standard
15 Up to 3 clocks may be specified in the following order:
19 - clock-names: List of clock names corresponding to the clocks
20 specified in the clocks property.
32 clocks = <&clk_32khz>;
/linux-4.4.14/Documentation/devicetree/bindings/serial/
Dcdns,uart.txt7 - clocks: Must contain phandles to the UART clocks
8 See ../clocks/clock-bindings.txt for details.
9 - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
10 See ../clocks/clock-bindings.txt for details.
16 clocks = <&clkc 23>, <&clkc 40>;
Dsamsung_uart.txt21 - clock-names: input names of clocks used by the controller:
26 - clocks: phandles and specifiers for all clocks specified in "clock-names"
55 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
56 <&clocks SCLK_UART>;
/linux-4.4.14/arch/arm/mach-w90x900/
Dclock.c66 unsigned int clocks = clk->cken; in nuc900_clk_enable() local
72 clken |= clocks; in nuc900_clk_enable()
74 clken &= ~clocks; in nuc900_clk_enable()
81 unsigned int clocks = clk->cken; in nuc900_subclk_enable() local
87 clken |= clocks; in nuc900_subclk_enable()
89 clken &= ~clocks; in nuc900_subclk_enable()
/linux-4.4.14/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
[all …]
/linux-4.4.14/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi73 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
77 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
85 clocks = <&v2m_clk24mhz>;
97 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
105 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
113 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
121 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
129 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
137 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
145 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
[all …]
Djuno-base.dtsi28 clocks = <&soc_refclk100mhz>;
83 clocks {
84 compatible = "arm,scpi-clocks";
87 compatible = "arm,scpi-dvfs-clocks";
93 compatible = "arm,scpi-variable-clocks";
106 /include/ "juno-clocks.dtsi"
122 clocks = <&soc_faxiclk>;
130 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
142 clocks = <&soc_smc50mhz>;
159 clocks = <&soc_usb48mhz>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Darm,scpi.txt23 Clock bindings for the clocks based on SCPI Message Protocol
31 - compatible : should be "arm,scpi-clocks"
32 All the clocks provided by SCP firmware via SCPI message
39 "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
40 These clocks don't provide an entire range of values between the
45 "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
49 Other required properties for all clocks(all from common clock binding):
52 - clock-indices: The identifying number for the clocks(i.e.clock_id) in the
126 clocks {
127 compatible = "arm,scpi-clocks";
[all …]
/linux-4.4.14/arch/h8300/boot/dts/
Dedosk2674.dts26 clocks = <&xclk>;
32 clocks = <&pllclk>;
39 clocks = <&core_clk>;
74 clocks = <&fclk>;
82 clocks = <&fclk>;
90 clocks = <&fclk>;
97 clocks = <&fclk>;
104 clocks = <&fclk>;
Dh8s_sim.dts25 clocks = <&xclk>;
31 clocks = <&pllclk>;
38 clocks = <&core_clk>;
73 clocks = <&fclk>;
81 clocks = <&fclk>;
89 clocks = <&fclk>;
96 clocks = <&fclk>;
Dh8300h_sim.dts25 clocks = <&xclk>;
32 clocks = <&core_clk>;
68 clocks = <&fclk>;
77 clocks = <&fclk>;
85 clocks = <&fclk>;
93 clocks = <&fclk>;
/linux-4.4.14/Documentation/devicetree/bindings/display/msm/
Dmdp.txt9 - clocks: device clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: the following clocks are required:
20 - clock-names: the following clocks are optional:
41 clocks =
/linux-4.4.14/Documentation/devicetree/bindings/input/touchscreen/
Dstmpe.txt8 - st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 ->
9 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6
10 -> 144 clocks), recommended is 4.
/linux-4.4.14/arch/powerpc/boot/dts/fsl/
Dt4240si-pre.dtsi91 clocks = <&mux0>;
98 clocks = <&mux0>;
105 clocks = <&mux0>;
112 clocks = <&mux0>;
119 clocks = <&mux1>;
126 clocks = <&mux1>;
133 clocks = <&mux1>;
140 clocks = <&mux1>;
147 clocks = <&mux2>;
154 clocks = <&mux2>;
[all …]
/linux-4.4.14/drivers/clk/
Dclk-max-gen.c116 struct clk **clocks; in max_gen_clk_probe() local
121 clocks = devm_kzalloc(dev, sizeof(struct clk *) * num_init, GFP_KERNEL); in max_gen_clk_probe()
122 if (!clocks) in max_gen_clk_probe()
152 clocks[i] = max_gen_clk_register(dev, &max_gen_clks[i]); in max_gen_clk_probe()
153 if (IS_ERR(clocks[i])) { in max_gen_clk_probe()
154 ret = PTR_ERR(clocks[i]); in max_gen_clk_probe()
161 platform_set_drvdata(pdev, clocks); in max_gen_clk_probe()
170 of_data->clks = clocks; in max_gen_clk_probe()
/linux-4.4.14/Documentation/devicetree/bindings/power/
Dpd-samsung.txt15 - clocks: List of clock handles. The parent clocks of the input clocks to the
20 - clock-names: The following clocks can be specified:
22 - clkN: Input clocks to the devices in this power domain. These clocks
25 the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
46 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
/linux-4.4.14/Documentation/devicetree/bindings/crypto/
Dqcom-qce.txt7 - clocks : phandle to clock-controller plus clock-specifier pair
8 - clock-names : "iface" clocks register interface
9 "bus" clocks data transfer interface
10 "core" clocks rest of the crypto block
19 clocks = <&gcc GCC_CE2_AHB_CLK>,
/linux-4.4.14/Documentation/devicetree/bindings/usb/
Datmel-usb.txt10 - clocks: Should reference the peripheral, host and system clocks
24 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
37 - clocks: Should reference the peripheral and the UTMI clocks
46 clocks = <&utmi>, <&uhphs_clk>;
60 - clocks: Should reference the peripheral and the AHB clocks
73 clocks = <&udc_clk>, <&udpck>;
87 - clocks: Should reference the peripheral and host clocks
112 clocks = <&utmi>, <&udphs_clk>;
/linux-4.4.14/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi112 clocks {
126 clocks = <&refclk 0>;
136 clocks = <&refclk 0>;
146 clocks = <&socpll 0>;
156 clocks = <&socplldiv2 0>;
166 clocks = <&socplldiv2 0>;
179 clocks = <&ethclk 0>;
188 clocks = <&socplldiv2 0>;
198 clocks = <&socplldiv2 0>;
208 clocks = <&socplldiv2 0>;
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/gpu/
Dsamsung-g2d.txt13 - clocks : from common clock binding: handle to G2D clocks.
14 - clock-names : names of clocks listed in clocks property, in the same
25 clocks = <&clock 177>, <&clock 277>;
/linux-4.4.14/arch/mips/boot/dts/ingenic/
Djz4780.dtsi41 clocks = <&ext>, <&rtc>;
54 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
67 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
80 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
93 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
106 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
/linux-4.4.14/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi236 clocks = <&clk26m>,
257 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
294 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
304 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
314 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
324 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
335 clocks = <&pericfg CLK_PERI_I2C0>,
351 clocks = <&pericfg CLK_PERI_I2C1>,
367 clocks = <&pericfg CLK_PERI_I2C2>,
383 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
[all …]
/linux-4.4.14/arch/xtensa/boot/dts/
Dxtfpga.dtsi38 clocks {
64 clocks = <&osc>;
72 clocks = <&osc>;
80 clocks = <&cdce706 4>;
91 clocks = <&osc>;
97 clocks = <&clk54>;
130 clocks = <&cdce706 4>;

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