Lines Matching refs:clocks

55 		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
155 		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
166 		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
177 		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
188 		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
199 		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
214 		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
229 		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
244 		clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
297 		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
307 		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
317 		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
327 		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
337 		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
347 		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
357 		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
366 		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
375 		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
384 		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
393 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
404 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
415 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
422 	clocks {
435 		/* Special CPG clocks */
437 			compatible = "renesas,r8a7778-cpg-clocks";
440 			clocks = <&extal_clk>;
446 		/* Audio clocks; frequencies are set by boards if applicable. */
463 		/* Fixed ratio clocks */
466 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
474 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
482 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
490 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
498 			clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
505 		/* Gate clocks */
507 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
509 			clocks = <&cpg_clocks R8A7778_CLK_P>,
548 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
550 			clocks = <&cpg_clocks R8A7778_CLK_P>,
563 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
565 			clocks = <&s4_clk>,
587 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
589 			clocks = <&cpg_clocks R8A7778_CLK_P>,