1/*
2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
3 *
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
11
12/ {
13	compatible = "apm,xgene-storm";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu@000 {
23			device_type = "cpu";
24			compatible = "apm,potenza", "arm,armv8";
25			reg = <0x0 0x000>;
26			enable-method = "spin-table";
27			cpu-release-addr = <0x1 0x0000fff8>;
28		};
29		cpu@001 {
30			device_type = "cpu";
31			compatible = "apm,potenza", "arm,armv8";
32			reg = <0x0 0x001>;
33			enable-method = "spin-table";
34			cpu-release-addr = <0x1 0x0000fff8>;
35		};
36		cpu@100 {
37			device_type = "cpu";
38			compatible = "apm,potenza", "arm,armv8";
39			reg = <0x0 0x100>;
40			enable-method = "spin-table";
41			cpu-release-addr = <0x1 0x0000fff8>;
42		};
43		cpu@101 {
44			device_type = "cpu";
45			compatible = "apm,potenza", "arm,armv8";
46			reg = <0x0 0x101>;
47			enable-method = "spin-table";
48			cpu-release-addr = <0x1 0x0000fff8>;
49		};
50		cpu@200 {
51			device_type = "cpu";
52			compatible = "apm,potenza", "arm,armv8";
53			reg = <0x0 0x200>;
54			enable-method = "spin-table";
55			cpu-release-addr = <0x1 0x0000fff8>;
56		};
57		cpu@201 {
58			device_type = "cpu";
59			compatible = "apm,potenza", "arm,armv8";
60			reg = <0x0 0x201>;
61			enable-method = "spin-table";
62			cpu-release-addr = <0x1 0x0000fff8>;
63		};
64		cpu@300 {
65			device_type = "cpu";
66			compatible = "apm,potenza", "arm,armv8";
67			reg = <0x0 0x300>;
68			enable-method = "spin-table";
69			cpu-release-addr = <0x1 0x0000fff8>;
70		};
71		cpu@301 {
72			device_type = "cpu";
73			compatible = "apm,potenza", "arm,armv8";
74			reg = <0x0 0x301>;
75			enable-method = "spin-table";
76			cpu-release-addr = <0x1 0x0000fff8>;
77		};
78	};
79
80	gic: interrupt-controller@78010000 {
81		compatible = "arm,cortex-a15-gic";
82		#interrupt-cells = <3>;
83		interrupt-controller;
84		reg = <0x0 0x78010000 0x0 0x1000>,	/* GIC Dist */
85		      <0x0 0x78020000 0x0 0x1000>,	/* GIC CPU */
86		      <0x0 0x78040000 0x0 0x2000>,	/* GIC VCPU Control */
87		      <0x0 0x78060000 0x0 0x2000>;	/* GIC VCPU */
88		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
89	};
90
91	timer {
92		compatible = "arm,armv8-timer";
93		interrupts = <1 0 0xff01>,	/* Secure Phys IRQ */
94			     <1 13 0xff01>,	/* Non-secure Phys IRQ */
95			     <1 14 0xff01>,	/* Virt IRQ */
96			     <1 15 0xff01>;	/* Hyp IRQ */
97		clock-frequency = <50000000>;
98	};
99
100	pmu {
101		compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
102		interrupts = <1 12 0xff04>;
103	};
104
105	soc {
106		compatible = "simple-bus";
107		#address-cells = <2>;
108		#size-cells = <2>;
109		ranges;
110		dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
111
112		clocks {
113			#address-cells = <2>;
114			#size-cells = <2>;
115			ranges;
116			refclk: refclk {
117				compatible = "fixed-clock";
118				#clock-cells = <1>;
119				clock-frequency = <100000000>;
120				clock-output-names = "refclk";
121			};
122
123			pcppll: pcppll@17000100 {
124				compatible = "apm,xgene-pcppll-clock";
125				#clock-cells = <1>;
126				clocks = <&refclk 0>;
127				clock-names = "pcppll";
128				reg = <0x0 0x17000100 0x0 0x1000>;
129				clock-output-names = "pcppll";
130				type = <0>;
131			};
132
133			socpll: socpll@17000120 {
134				compatible = "apm,xgene-socpll-clock";
135				#clock-cells = <1>;
136				clocks = <&refclk 0>;
137				clock-names = "socpll";
138				reg = <0x0 0x17000120 0x0 0x1000>;
139				clock-output-names = "socpll";
140				type = <1>;
141			};
142
143			socplldiv2: socplldiv2  {
144				compatible = "fixed-factor-clock";
145				#clock-cells = <1>;
146				clocks = <&socpll 0>;
147				clock-names = "socplldiv2";
148				clock-mult = <1>;
149				clock-div = <2>;
150				clock-output-names = "socplldiv2";
151			};
152
153			qmlclk: qmlclk {
154				compatible = "apm,xgene-device-clock";
155				#clock-cells = <1>;
156				clocks = <&socplldiv2 0>;
157				clock-names = "qmlclk";
158				reg = <0x0 0x1703C000 0x0 0x1000>;
159				reg-names = "csr-reg";
160				clock-output-names = "qmlclk";
161			};
162
163			ethclk: ethclk {
164				compatible = "apm,xgene-device-clock";
165				#clock-cells = <1>;
166				clocks = <&socplldiv2 0>;
167				clock-names = "ethclk";
168				reg = <0x0 0x17000000 0x0 0x1000>;
169				reg-names = "div-reg";
170				divider-offset = <0x238>;
171				divider-width = <0x9>;
172				divider-shift = <0x0>;
173				clock-output-names = "ethclk";
174			};
175
176			menetclk: menetclk {
177				compatible = "apm,xgene-device-clock";
178				#clock-cells = <1>;
179				clocks = <&ethclk 0>;
180				reg = <0x0 0x1702C000 0x0 0x1000>;
181				reg-names = "csr-reg";
182				clock-output-names = "menetclk";
183			};
184
185			sge0clk: sge0clk@1f21c000 {
186				compatible = "apm,xgene-device-clock";
187				#clock-cells = <1>;
188				clocks = <&socplldiv2 0>;
189				reg = <0x0 0x1f21c000 0x0 0x1000>;
190				reg-names = "csr-reg";
191				csr-mask = <0x3>;
192				clock-output-names = "sge0clk";
193			};
194
195			sge1clk: sge1clk@1f21c000 {
196				compatible = "apm,xgene-device-clock";
197				#clock-cells = <1>;
198				clocks = <&socplldiv2 0>;
199				reg = <0x0 0x1f21c000 0x0 0x1000>;
200				reg-names = "csr-reg";
201				csr-mask = <0xc>;
202				clock-output-names = "sge1clk";
203			};
204
205			xge0clk: xge0clk@1f61c000 {
206				compatible = "apm,xgene-device-clock";
207				#clock-cells = <1>;
208				clocks = <&socplldiv2 0>;
209				reg = <0x0 0x1f61c000 0x0 0x1000>;
210				reg-names = "csr-reg";
211				csr-mask = <0x3>;
212				clock-output-names = "xge0clk";
213			};
214
215			xge1clk: xge1clk@1f62c000 {
216				compatible = "apm,xgene-device-clock";
217				status = "disabled";
218				#clock-cells = <1>;
219				clocks = <&socplldiv2 0>;
220				reg = <0x0 0x1f62c000 0x0 0x1000>;
221				reg-names = "csr-reg";
222				csr-mask = <0x3>;
223				clock-output-names = "xge1clk";
224			};
225
226			sataphy1clk: sataphy1clk@1f21c000 {
227				compatible = "apm,xgene-device-clock";
228				#clock-cells = <1>;
229				clocks = <&socplldiv2 0>;
230				reg = <0x0 0x1f21c000 0x0 0x1000>;
231				reg-names = "csr-reg";
232				clock-output-names = "sataphy1clk";
233				status = "disabled";
234				csr-offset = <0x4>;
235				csr-mask = <0x00>;
236				enable-offset = <0x0>;
237				enable-mask = <0x06>;
238			};
239
240			sataphy2clk: sataphy1clk@1f22c000 {
241				compatible = "apm,xgene-device-clock";
242				#clock-cells = <1>;
243				clocks = <&socplldiv2 0>;
244				reg = <0x0 0x1f22c000 0x0 0x1000>;
245				reg-names = "csr-reg";
246				clock-output-names = "sataphy2clk";
247				status = "ok";
248				csr-offset = <0x4>;
249				csr-mask = <0x3a>;
250				enable-offset = <0x0>;
251				enable-mask = <0x06>;
252			};
253
254			sataphy3clk: sataphy1clk@1f23c000 {
255				compatible = "apm,xgene-device-clock";
256				#clock-cells = <1>;
257				clocks = <&socplldiv2 0>;
258				reg = <0x0 0x1f23c000 0x0 0x1000>;
259				reg-names = "csr-reg";
260				clock-output-names = "sataphy3clk";
261				status = "ok";
262				csr-offset = <0x4>;
263				csr-mask = <0x3a>;
264				enable-offset = <0x0>;
265				enable-mask = <0x06>;
266			};
267
268			sata01clk: sata01clk@1f21c000 {
269				compatible = "apm,xgene-device-clock";
270				#clock-cells = <1>;
271				clocks = <&socplldiv2 0>;
272				reg = <0x0 0x1f21c000 0x0 0x1000>;
273				reg-names = "csr-reg";
274				clock-output-names = "sata01clk";
275				csr-offset = <0x4>;
276				csr-mask = <0x05>;
277				enable-offset = <0x0>;
278				enable-mask = <0x39>;
279			};
280
281			sata23clk: sata23clk@1f22c000 {
282				compatible = "apm,xgene-device-clock";
283				#clock-cells = <1>;
284				clocks = <&socplldiv2 0>;
285				reg = <0x0 0x1f22c000 0x0 0x1000>;
286				reg-names = "csr-reg";
287				clock-output-names = "sata23clk";
288				csr-offset = <0x4>;
289				csr-mask = <0x05>;
290				enable-offset = <0x0>;
291				enable-mask = <0x39>;
292			};
293
294			sata45clk: sata45clk@1f23c000 {
295				compatible = "apm,xgene-device-clock";
296				#clock-cells = <1>;
297				clocks = <&socplldiv2 0>;
298				reg = <0x0 0x1f23c000 0x0 0x1000>;
299				reg-names = "csr-reg";
300				clock-output-names = "sata45clk";
301				csr-offset = <0x4>;
302				csr-mask = <0x05>;
303				enable-offset = <0x0>;
304				enable-mask = <0x39>;
305			};
306
307			rtcclk: rtcclk@17000000 {
308				compatible = "apm,xgene-device-clock";
309				#clock-cells = <1>;
310				clocks = <&socplldiv2 0>;
311				reg = <0x0 0x17000000 0x0 0x2000>;
312				reg-names = "csr-reg";
313				csr-offset = <0xc>;
314				csr-mask = <0x2>;
315				enable-offset = <0x10>;
316				enable-mask = <0x2>;
317				clock-output-names = "rtcclk";
318			};
319
320			rngpkaclk: rngpkaclk@17000000 {
321				compatible = "apm,xgene-device-clock";
322				#clock-cells = <1>;
323				clocks = <&socplldiv2 0>;
324				reg = <0x0 0x17000000 0x0 0x2000>;
325				reg-names = "csr-reg";
326				csr-offset = <0xc>;
327				csr-mask = <0x10>;
328				enable-offset = <0x10>;
329				enable-mask = <0x10>;
330				clock-output-names = "rngpkaclk";
331			};
332
333			pcie0clk: pcie0clk@1f2bc000 {
334				status = "disabled";
335				compatible = "apm,xgene-device-clock";
336				#clock-cells = <1>;
337				clocks = <&socplldiv2 0>;
338				reg = <0x0 0x1f2bc000 0x0 0x1000>;
339				reg-names = "csr-reg";
340				clock-output-names = "pcie0clk";
341			};
342
343			pcie1clk: pcie1clk@1f2cc000 {
344				status = "disabled";
345				compatible = "apm,xgene-device-clock";
346				#clock-cells = <1>;
347				clocks = <&socplldiv2 0>;
348				reg = <0x0 0x1f2cc000 0x0 0x1000>;
349				reg-names = "csr-reg";
350				clock-output-names = "pcie1clk";
351			};
352
353			pcie2clk: pcie2clk@1f2dc000 {
354				status = "disabled";
355				compatible = "apm,xgene-device-clock";
356				#clock-cells = <1>;
357				clocks = <&socplldiv2 0>;
358				reg = <0x0 0x1f2dc000 0x0 0x1000>;
359				reg-names = "csr-reg";
360				clock-output-names = "pcie2clk";
361			};
362
363			pcie3clk: pcie3clk@1f50c000 {
364				status = "disabled";
365				compatible = "apm,xgene-device-clock";
366				#clock-cells = <1>;
367				clocks = <&socplldiv2 0>;
368				reg = <0x0 0x1f50c000 0x0 0x1000>;
369				reg-names = "csr-reg";
370				clock-output-names = "pcie3clk";
371			};
372
373			pcie4clk: pcie4clk@1f51c000 {
374				status = "disabled";
375				compatible = "apm,xgene-device-clock";
376				#clock-cells = <1>;
377				clocks = <&socplldiv2 0>;
378				reg = <0x0 0x1f51c000 0x0 0x1000>;
379				reg-names = "csr-reg";
380				clock-output-names = "pcie4clk";
381			};
382
383			dmaclk: dmaclk@1f27c000 {
384				compatible = "apm,xgene-device-clock";
385				#clock-cells = <1>;
386				clocks = <&socplldiv2 0>;
387				reg = <0x0 0x1f27c000 0x0 0x1000>;
388				reg-names = "csr-reg";
389				clock-output-names = "dmaclk";
390			};
391		};
392
393		msi: msi@79000000 {
394			compatible = "apm,xgene1-msi";
395			msi-controller;
396			reg = <0x00 0x79000000 0x0 0x900000>;
397			interrupts = <  0x0 0x10 0x4
398					0x0 0x11 0x4
399					0x0 0x12 0x4
400					0x0 0x13 0x4
401					0x0 0x14 0x4
402					0x0 0x15 0x4
403					0x0 0x16 0x4
404					0x0 0x17 0x4
405					0x0 0x18 0x4
406					0x0 0x19 0x4
407					0x0 0x1a 0x4
408					0x0 0x1b 0x4
409					0x0 0x1c 0x4
410					0x0 0x1d 0x4
411					0x0 0x1e 0x4
412					0x0 0x1f 0x4>;
413		};
414
415		scu: system-clk-controller@17000000 {
416			compatible = "apm,xgene-scu","syscon";
417			reg = <0x0 0x17000000 0x0 0x400>;
418		};
419
420		reboot: reboot@17000014 {
421			compatible = "syscon-reboot";
422			regmap = <&scu>;
423			offset = <0x14>;
424			mask = <0x1>;
425		};
426
427		csw: csw@7e200000 {
428			compatible = "apm,xgene-csw", "syscon";
429			reg = <0x0 0x7e200000 0x0 0x1000>;
430		};
431
432		mcba: mcba@7e700000 {
433			compatible = "apm,xgene-mcb", "syscon";
434			reg = <0x0 0x7e700000 0x0 0x1000>;
435		};
436
437		mcbb: mcbb@7e720000 {
438			compatible = "apm,xgene-mcb", "syscon";
439			reg = <0x0 0x7e720000 0x0 0x1000>;
440		};
441
442		efuse: efuse@1054a000 {
443			compatible = "apm,xgene-efuse", "syscon";
444			reg = <0x0 0x1054a000 0x0 0x20>;
445		};
446
447		edac@78800000 {
448			compatible = "apm,xgene-edac";
449			#address-cells = <2>;
450			#size-cells = <2>;
451			ranges;
452			regmap-csw = <&csw>;
453			regmap-mcba = <&mcba>;
454			regmap-mcbb = <&mcbb>;
455			regmap-efuse = <&efuse>;
456			reg = <0x0 0x78800000 0x0 0x100>;
457			interrupts = <0x0 0x20 0x4>,
458				     <0x0 0x21 0x4>,
459				     <0x0 0x27 0x4>;
460
461			edacmc@7e800000 {
462				compatible = "apm,xgene-edac-mc";
463				reg = <0x0 0x7e800000 0x0 0x1000>;
464				memory-controller = <0>;
465			};
466
467			edacmc@7e840000 {
468				compatible = "apm,xgene-edac-mc";
469				reg = <0x0 0x7e840000 0x0 0x1000>;
470				memory-controller = <1>;
471			};
472
473			edacmc@7e880000 {
474				compatible = "apm,xgene-edac-mc";
475				reg = <0x0 0x7e880000 0x0 0x1000>;
476				memory-controller = <2>;
477			};
478
479			edacmc@7e8c0000 {
480				compatible = "apm,xgene-edac-mc";
481				reg = <0x0 0x7e8c0000 0x0 0x1000>;
482				memory-controller = <3>;
483			};
484
485			edacpmd@7c000000 {
486				compatible = "apm,xgene-edac-pmd";
487				reg = <0x0 0x7c000000 0x0 0x200000>;
488				pmd-controller = <0>;
489			};
490
491			edacpmd@7c200000 {
492				compatible = "apm,xgene-edac-pmd";
493				reg = <0x0 0x7c200000 0x0 0x200000>;
494				pmd-controller = <1>;
495			};
496
497			edacpmd@7c400000 {
498				compatible = "apm,xgene-edac-pmd";
499				reg = <0x0 0x7c400000 0x0 0x200000>;
500				pmd-controller = <2>;
501			};
502
503			edacpmd@7c600000 {
504				compatible = "apm,xgene-edac-pmd";
505				reg = <0x0 0x7c600000 0x0 0x200000>;
506				pmd-controller = <3>;
507			};
508
509			edacl3@7e600000 {
510				compatible = "apm,xgene-edac-l3";
511				reg = <0x0 0x7e600000 0x0 0x1000>;
512			};
513
514			edacsoc@7e930000 {
515				compatible = "apm,xgene-edac-soc-v1";
516				reg = <0x0 0x7e930000 0x0 0x1000>;
517			};
518		};
519
520		pcie0: pcie@1f2b0000 {
521			status = "disabled";
522			device_type = "pci";
523			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
524			#interrupt-cells = <1>;
525			#size-cells = <2>;
526			#address-cells = <3>;
527			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
528				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
529			reg-names = "csr", "cfg";
530			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
531				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
532				  0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
533			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
534				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
535			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
536			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
537					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
538					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
539					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
540			dma-coherent;
541			clocks = <&pcie0clk 0>;
542			msi-parent = <&msi>;
543		};
544
545		pcie1: pcie@1f2c0000 {
546			status = "disabled";
547			device_type = "pci";
548			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
549			#interrupt-cells = <1>;
550			#size-cells = <2>;
551			#address-cells = <3>;
552			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
553				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
554			reg-names = "csr", "cfg";
555			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
556				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
557				  0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
558			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
559				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
560			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
561			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
562					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
563					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
564					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
565			dma-coherent;
566			clocks = <&pcie1clk 0>;
567			msi-parent = <&msi>;
568		};
569
570		pcie2: pcie@1f2d0000 {
571			status = "disabled";
572			device_type = "pci";
573			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
574			#interrupt-cells = <1>;
575			#size-cells = <2>;
576			#address-cells = <3>;
577			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
578				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
579			reg-names = "csr", "cfg";
580			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
581				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
582				  0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
583			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
584				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
585			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
586			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
587					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
588					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
589					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
590			dma-coherent;
591			clocks = <&pcie2clk 0>;
592			msi-parent = <&msi>;
593		};
594
595		pcie3: pcie@1f500000 {
596			status = "disabled";
597			device_type = "pci";
598			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
599			#interrupt-cells = <1>;
600			#size-cells = <2>;
601			#address-cells = <3>;
602			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
603				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
604			reg-names = "csr", "cfg";
605			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
606				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
607				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
608			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
609				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
610			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
611			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
612					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
613					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
614					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
615			dma-coherent;
616			clocks = <&pcie3clk 0>;
617			msi-parent = <&msi>;
618		};
619
620		pcie4: pcie@1f510000 {
621			status = "disabled";
622			device_type = "pci";
623			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
624			#interrupt-cells = <1>;
625			#size-cells = <2>;
626			#address-cells = <3>;
627			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
628				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
629			reg-names = "csr", "cfg";
630			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
631				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
632				  0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
633			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
634				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
635			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
636			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
637					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
638					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
639					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
640			dma-coherent;
641			clocks = <&pcie4clk 0>;
642			msi-parent = <&msi>;
643		};
644
645		serial0: serial@1c020000 {
646			status = "disabled";
647			device_type = "serial";
648			compatible = "ns16550a";
649			reg = <0 0x1c020000 0x0 0x1000>;
650			reg-shift = <2>;
651			clock-frequency = <10000000>; /* Updated by bootloader */
652			interrupt-parent = <&gic>;
653			interrupts = <0x0 0x4c 0x4>;
654		};
655
656		serial1: serial@1c021000 {
657			status = "disabled";
658			device_type = "serial";
659			compatible = "ns16550a";
660			reg = <0 0x1c021000 0x0 0x1000>;
661			reg-shift = <2>;
662			clock-frequency = <10000000>; /* Updated by bootloader */
663			interrupt-parent = <&gic>;
664			interrupts = <0x0 0x4d 0x4>;
665		};
666
667		serial2: serial@1c022000 {
668			status = "disabled";
669			device_type = "serial";
670			compatible = "ns16550a";
671			reg = <0 0x1c022000 0x0 0x1000>;
672			reg-shift = <2>;
673			clock-frequency = <10000000>; /* Updated by bootloader */
674			interrupt-parent = <&gic>;
675			interrupts = <0x0 0x4e 0x4>;
676		};
677
678		serial3: serial@1c023000 {
679			status = "disabled";
680			device_type = "serial";
681			compatible = "ns16550a";
682			reg = <0 0x1c023000 0x0 0x1000>;
683			reg-shift = <2>;
684			clock-frequency = <10000000>; /* Updated by bootloader */
685			interrupt-parent = <&gic>;
686			interrupts = <0x0 0x4f 0x4>;
687		};
688
689		phy1: phy@1f21a000 {
690			compatible = "apm,xgene-phy";
691			reg = <0x0 0x1f21a000 0x0 0x100>;
692			#phy-cells = <1>;
693			clocks = <&sataphy1clk 0>;
694			status = "disabled";
695			apm,tx-boost-gain = <30 30 30 30 30 30>;
696			apm,tx-eye-tuning = <2 10 10 2 10 10>;
697		};
698
699		phy2: phy@1f22a000 {
700			compatible = "apm,xgene-phy";
701			reg = <0x0 0x1f22a000 0x0 0x100>;
702			#phy-cells = <1>;
703			clocks = <&sataphy2clk 0>;
704			status = "ok";
705			apm,tx-boost-gain = <30 30 30 30 30 30>;
706			apm,tx-eye-tuning = <1 10 10 2 10 10>;
707		};
708
709		phy3: phy@1f23a000 {
710			compatible = "apm,xgene-phy";
711			reg = <0x0 0x1f23a000 0x0 0x100>;
712			#phy-cells = <1>;
713			clocks = <&sataphy3clk 0>;
714			status = "ok";
715			apm,tx-boost-gain = <31 31 31 31 31 31>;
716			apm,tx-eye-tuning = <2 10 10 2 10 10>;
717		};
718
719		sata1: sata@1a000000 {
720			compatible = "apm,xgene-ahci";
721			reg = <0x0 0x1a000000 0x0 0x1000>,
722			      <0x0 0x1f210000 0x0 0x1000>,
723			      <0x0 0x1f21d000 0x0 0x1000>,
724			      <0x0 0x1f21e000 0x0 0x1000>,
725			      <0x0 0x1f217000 0x0 0x1000>;
726			interrupts = <0x0 0x86 0x4>;
727			dma-coherent;
728			status = "disabled";
729			clocks = <&sata01clk 0>;
730			phys = <&phy1 0>;
731			phy-names = "sata-phy";
732		};
733
734		sata2: sata@1a400000 {
735			compatible = "apm,xgene-ahci";
736			reg = <0x0 0x1a400000 0x0 0x1000>,
737			      <0x0 0x1f220000 0x0 0x1000>,
738			      <0x0 0x1f22d000 0x0 0x1000>,
739			      <0x0 0x1f22e000 0x0 0x1000>,
740			      <0x0 0x1f227000 0x0 0x1000>;
741			interrupts = <0x0 0x87 0x4>;
742			dma-coherent;
743			status = "ok";
744			clocks = <&sata23clk 0>;
745			phys = <&phy2 0>;
746			phy-names = "sata-phy";
747		};
748
749		sata3: sata@1a800000 {
750			compatible = "apm,xgene-ahci";
751			reg = <0x0 0x1a800000 0x0 0x1000>,
752			      <0x0 0x1f230000 0x0 0x1000>,
753			      <0x0 0x1f23d000 0x0 0x1000>,
754			      <0x0 0x1f23e000 0x0 0x1000>;
755			interrupts = <0x0 0x88 0x4>;
756			dma-coherent;
757			status = "ok";
758			clocks = <&sata45clk 0>;
759			phys = <&phy3 0>;
760			phy-names = "sata-phy";
761		};
762
763		sbgpio: sbgpio@17001000{
764			compatible = "apm,xgene-gpio-sb";
765			reg = <0x0 0x17001000 0x0 0x400>;
766			#gpio-cells = <2>;
767			gpio-controller;
768			interrupts = 	<0x0 0x28 0x1>,
769					<0x0 0x29 0x1>,
770					<0x0 0x2a 0x1>,
771					<0x0 0x2b 0x1>,
772					<0x0 0x2c 0x1>,
773					<0x0 0x2d 0x1>;
774		};
775
776		rtc: rtc@10510000 {
777			compatible = "apm,xgene-rtc";
778			reg = <0x0 0x10510000 0x0 0x400>;
779			interrupts = <0x0 0x46 0x4>;
780			#clock-cells = <1>;
781			clocks = <&rtcclk 0>;
782		};
783
784		menet: ethernet@17020000 {
785			compatible = "apm,xgene-enet";
786			status = "disabled";
787			reg = <0x0 0x17020000 0x0 0xd100>,
788			      <0x0 0X17030000 0x0 0Xc300>,
789			      <0x0 0X10000000 0x0 0X200>;
790			reg-names = "enet_csr", "ring_csr", "ring_cmd";
791			interrupts = <0x0 0x3c 0x4>;
792			dma-coherent;
793			clocks = <&menetclk 0>;
794			/* mac address will be overwritten by the bootloader */
795			local-mac-address = [00 00 00 00 00 00];
796			phy-connection-type = "rgmii";
797			phy-handle = <&menetphy>;
798			mdio {
799				compatible = "apm,xgene-mdio";
800				#address-cells = <1>;
801				#size-cells = <0>;
802				menetphy: menetphy@3 {
803					compatible = "ethernet-phy-id001c.c915";
804					reg = <0x3>;
805				};
806
807			};
808		};
809
810		sgenet0: ethernet@1f210000 {
811			compatible = "apm,xgene1-sgenet";
812			status = "disabled";
813			reg = <0x0 0x1f210000 0x0 0xd100>,
814			      <0x0 0x1f200000 0x0 0Xc300>,
815			      <0x0 0x1B000000 0x0 0X200>;
816			reg-names = "enet_csr", "ring_csr", "ring_cmd";
817			interrupts = <0x0 0xA0 0x4>,
818				     <0x0 0xA1 0x4>;
819			dma-coherent;
820			clocks = <&sge0clk 0>;
821			local-mac-address = [00 00 00 00 00 00];
822			phy-connection-type = "sgmii";
823		};
824
825		sgenet1: ethernet@1f210030 {
826			compatible = "apm,xgene1-sgenet";
827			status = "disabled";
828			reg = <0x0 0x1f210030 0x0 0xd100>,
829			      <0x0 0x1f200000 0x0 0Xc300>,
830			      <0x0 0x1B000000 0x0 0X8000>;
831			reg-names = "enet_csr", "ring_csr", "ring_cmd";
832			interrupts = <0x0 0xAC 0x4>,
833				     <0x0 0xAD 0x4>;
834			port-id = <1>;
835			dma-coherent;
836			clocks = <&sge1clk 0>;
837			local-mac-address = [00 00 00 00 00 00];
838			phy-connection-type = "sgmii";
839		};
840
841		xgenet: ethernet@1f610000 {
842			compatible = "apm,xgene1-xgenet";
843			status = "disabled";
844			reg = <0x0 0x1f610000 0x0 0xd100>,
845			      <0x0 0x1f600000 0x0 0Xc300>,
846			      <0x0 0x18000000 0x0 0X200>;
847			reg-names = "enet_csr", "ring_csr", "ring_cmd";
848			interrupts = <0x0 0x60 0x4>,
849				     <0x0 0x61 0x4>;
850			dma-coherent;
851			clocks = <&xge0clk 0>;
852			/* mac address will be overwritten by the bootloader */
853			local-mac-address = [00 00 00 00 00 00];
854			phy-connection-type = "xgmii";
855		};
856
857		xgenet1: ethernet@1f620000 {
858			compatible = "apm,xgene1-xgenet";
859			status = "disabled";
860			reg = <0x0 0x1f620000 0x0 0xd100>,
861			      <0x0 0x1f600000 0x0 0Xc300>,
862			      <0x0 0x18000000 0x0 0X8000>;
863			reg-names = "enet_csr", "ring_csr", "ring_cmd";
864			interrupts = <0x0 0x6C 0x4>,
865				     <0x0 0x6D 0x4>;
866			port-id = <1>;
867			dma-coherent;
868			clocks = <&xge1clk 0>;
869			/* mac address will be overwritten by the bootloader */
870			local-mac-address = [00 00 00 00 00 00];
871			phy-connection-type = "xgmii";
872		};
873
874		rng: rng@10520000 {
875			compatible = "apm,xgene-rng";
876			reg = <0x0 0x10520000 0x0 0x100>;
877			interrupts = <0x0 0x41 0x4>;
878			clocks = <&rngpkaclk 0>;
879		};
880
881		dma: dma@1f270000 {
882			compatible = "apm,xgene-storm-dma";
883			device_type = "dma";
884			reg = <0x0 0x1f270000 0x0 0x10000>,
885			      <0x0 0x1f200000 0x0 0x10000>,
886			      <0x0 0x1b000000 0x0 0x400000>,
887			      <0x0 0x1054a000 0x0 0x100>;
888			interrupts = <0x0 0x82 0x4>,
889				     <0x0 0xb8 0x4>,
890				     <0x0 0xb9 0x4>,
891				     <0x0 0xba 0x4>,
892				     <0x0 0xbb 0x4>;
893			dma-coherent;
894			clocks = <&dmaclk 0>;
895		};
896	};
897};
898