1/*
2 * T4240 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40	compatible = "fsl,T4240";
41	#address-cells = <2>;
42	#size-cells = <2>;
43	interrupt-parent = <&mpic>;
44
45	aliases {
46		ccsr = &soc;
47		dcsr = &dcsr;
48
49		serial0 = &serial0;
50		serial1 = &serial1;
51		serial2 = &serial2;
52		serial3 = &serial3;
53		crypto = &crypto;
54
55		pci0 = &pci0;
56		pci1 = &pci1;
57		pci2 = &pci2;
58		pci3 = &pci3;
59		dma0 = &dma0;
60		dma1 = &dma1;
61		dma2 = &dma2;
62		sdhc = &sdhc;
63
64		fman0 = &fman0;
65		fman1 = &fman1;
66		ethernet0 = &enet0;
67		ethernet1 = &enet1;
68		ethernet2 = &enet2;
69		ethernet3 = &enet3;
70		ethernet4 = &enet4;
71		ethernet5 = &enet5;
72		ethernet6 = &enet6;
73		ethernet7 = &enet7;
74		ethernet8 = &enet8;
75		ethernet9 = &enet9;
76		ethernet10 = &enet10;
77		ethernet11 = &enet11;
78		ethernet12 = &enet12;
79		ethernet13 = &enet13;
80		ethernet14 = &enet14;
81		ethernet15 = &enet15;
82	};
83
84	cpus {
85		#address-cells = <1>;
86		#size-cells = <0>;
87
88		cpu0: PowerPC,e6500@0 {
89			device_type = "cpu";
90			reg = <0 1>;
91			clocks = <&mux0>;
92			next-level-cache = <&L2_1>;
93			fsl,portid-mapping = <0x80000000>;
94		};
95		cpu1: PowerPC,e6500@2 {
96			device_type = "cpu";
97			reg = <2 3>;
98			clocks = <&mux0>;
99			next-level-cache = <&L2_1>;
100			fsl,portid-mapping = <0x80000000>;
101		};
102		cpu2: PowerPC,e6500@4 {
103			device_type = "cpu";
104			reg = <4 5>;
105			clocks = <&mux0>;
106			next-level-cache = <&L2_1>;
107			fsl,portid-mapping = <0x80000000>;
108		};
109		cpu3: PowerPC,e6500@6 {
110			device_type = "cpu";
111			reg = <6 7>;
112			clocks = <&mux0>;
113			next-level-cache = <&L2_1>;
114			fsl,portid-mapping = <0x80000000>;
115		};
116		cpu4: PowerPC,e6500@8 {
117			device_type = "cpu";
118			reg = <8 9>;
119			clocks = <&mux1>;
120			next-level-cache = <&L2_2>;
121			fsl,portid-mapping = <0x40000000>;
122		};
123		cpu5: PowerPC,e6500@10 {
124			device_type = "cpu";
125			reg = <10 11>;
126			clocks = <&mux1>;
127			next-level-cache = <&L2_2>;
128			fsl,portid-mapping = <0x40000000>;
129		};
130		cpu6: PowerPC,e6500@12 {
131			device_type = "cpu";
132			reg = <12 13>;
133			clocks = <&mux1>;
134			next-level-cache = <&L2_2>;
135			fsl,portid-mapping = <0x40000000>;
136		};
137		cpu7: PowerPC,e6500@14 {
138			device_type = "cpu";
139			reg = <14 15>;
140			clocks = <&mux1>;
141			next-level-cache = <&L2_2>;
142			fsl,portid-mapping = <0x40000000>;
143		};
144		cpu8: PowerPC,e6500@16 {
145			device_type = "cpu";
146			reg = <16 17>;
147			clocks = <&mux2>;
148			next-level-cache = <&L2_3>;
149			fsl,portid-mapping = <0x20000000>;
150		};
151		cpu9: PowerPC,e6500@18 {
152			device_type = "cpu";
153			reg = <18 19>;
154			clocks = <&mux2>;
155			next-level-cache = <&L2_3>;
156			fsl,portid-mapping = <0x20000000>;
157		};
158		cpu10: PowerPC,e6500@20 {
159			device_type = "cpu";
160			reg = <20 21>;
161			clocks = <&mux2>;
162			next-level-cache = <&L2_3>;
163			fsl,portid-mapping = <0x20000000>;
164		};
165		cpu11: PowerPC,e6500@22 {
166			device_type = "cpu";
167			reg = <22 23>;
168			clocks = <&mux2>;
169			next-level-cache = <&L2_3>;
170			fsl,portid-mapping = <0x20000000>;
171		};
172	};
173};
174