1/*
2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
3 *
4 *  Copyright (C) 2015 Atmel,
5 *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 *  a) This file is free software; you can redistribute it and/or
13 *     modify it under the terms of the GNU General Public License as
14 *     published by the Free Software Foundation; either version 2 of the
15 *     License, or (at your option) any later version.
16 *
17 *     This file is distributed in the hope that it will be useful,
18 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
19 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20 *     GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 *  b) Permission is hereby granted, free of charge, to any person
25 *     obtaining a copy of this software and associated documentation
26 *     files (the "Software"), to deal in the Software without
27 *     restriction, including without limitation the rights to use,
28 *     copy, modify, merge, publish, distribute, sublicense, and/or
29 *     sell copies of the Software, and to permit persons to whom the
30 *     Software is furnished to do so, subject to the following
31 *     conditions:
32 *
33 *     The above copyright notice and this permission notice shall be
34 *     included in all copies or substantial portions of the Software.
35 *
36 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 *     OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/dma/at91.h>
48#include <dt-bindings/interrupt-controller/irq.h>
49#include <dt-bindings/clock/at91.h>
50
51/ {
52	model = "Atmel SAMA5D2 family SoC";
53	compatible = "atmel,sama5d2";
54	interrupt-parent = <&aic>;
55
56	aliases {
57		serial0 = &uart1;
58		serial1 = &uart3;
59		tcb0 = &tcb0;
60		tcb1 = &tcb1;
61	};
62
63	cpus {
64		#address-cells = <1>;
65		#size-cells = <0>;
66
67		cpu@0 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a5";
70			reg = <0>;
71			next-level-cache = <&L2>;
72		};
73	};
74
75	memory {
76		reg = <0x20000000 0x20000000>;
77	};
78
79	clocks {
80		slow_xtal: slow_xtal {
81			compatible = "fixed-clock";
82			#clock-cells = <0>;
83			clock-frequency = <0>;
84		};
85
86		main_xtal: main_xtal {
87			compatible = "fixed-clock";
88			#clock-cells = <0>;
89			clock-frequency = <0>;
90		};
91
92		adc_op_clk: adc_op_clk{
93			compatible = "fixed-clock";
94			#clock-cells = <0>;
95			clock-frequency = <1000000>;
96		};
97	};
98
99	ns_sram: sram@00200000 {
100		compatible = "mmio-sram";
101		reg = <0x00200000 0x20000>;
102	};
103
104	ahb {
105		compatible = "simple-bus";
106		#address-cells = <1>;
107		#size-cells = <1>;
108		ranges;
109
110		usb0: gadget@00300000 {
111			#address-cells = <1>;
112			#size-cells = <0>;
113			compatible = "atmel,sama5d3-udc";
114			reg = <0x00300000 0x100000
115			       0xfc02c000 0x400>;
116			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
117			clocks = <&udphs_clk>, <&utmi>;
118			clock-names = "pclk", "hclk";
119			status = "disabled";
120
121			ep0 {
122				reg = <0>;
123				atmel,fifo-size = <64>;
124				atmel,nb-banks = <1>;
125			};
126
127			ep1 {
128				reg = <1>;
129				atmel,fifo-size = <1024>;
130				atmel,nb-banks = <3>;
131				atmel,can-dma;
132				atmel,can-isoc;
133			};
134
135			ep2 {
136				reg = <2>;
137				atmel,fifo-size = <1024>;
138				atmel,nb-banks = <3>;
139				atmel,can-dma;
140				atmel,can-isoc;
141			};
142
143			ep3 {
144				reg = <3>;
145				atmel,fifo-size = <1024>;
146				atmel,nb-banks = <2>;
147				atmel,can-dma;
148				atmel,can-isoc;
149			};
150
151			ep4 {
152				reg = <4>;
153				atmel,fifo-size = <1024>;
154				atmel,nb-banks = <2>;
155				atmel,can-dma;
156				atmel,can-isoc;
157			};
158
159			ep5 {
160				reg = <5>;
161				atmel,fifo-size = <1024>;
162				atmel,nb-banks = <2>;
163				atmel,can-dma;
164				atmel,can-isoc;
165			};
166
167			ep6 {
168				reg = <6>;
169				atmel,fifo-size = <1024>;
170				atmel,nb-banks = <2>;
171				atmel,can-dma;
172				atmel,can-isoc;
173			};
174
175			ep7 {
176				reg = <7>;
177				atmel,fifo-size = <1024>;
178				atmel,nb-banks = <2>;
179				atmel,can-dma;
180				atmel,can-isoc;
181			};
182
183			ep8 {
184				reg = <8>;
185				atmel,fifo-size = <1024>;
186				atmel,nb-banks = <2>;
187				atmel,can-isoc;
188			};
189
190			ep9 {
191				reg = <9>;
192				atmel,fifo-size = <1024>;
193				atmel,nb-banks = <2>;
194				atmel,can-isoc;
195			};
196
197			ep10 {
198				reg = <10>;
199				atmel,fifo-size = <1024>;
200				atmel,nb-banks = <2>;
201				atmel,can-isoc;
202			};
203
204			ep11 {
205				reg = <11>;
206				atmel,fifo-size = <1024>;
207				atmel,nb-banks = <2>;
208				atmel,can-isoc;
209			};
210
211			ep12 {
212				reg = <12>;
213				atmel,fifo-size = <1024>;
214				atmel,nb-banks = <2>;
215				atmel,can-isoc;
216			};
217
218			ep13 {
219				reg = <13>;
220				atmel,fifo-size = <1024>;
221				atmel,nb-banks = <2>;
222				atmel,can-isoc;
223			};
224
225			ep14 {
226				reg = <14>;
227				atmel,fifo-size = <1024>;
228				atmel,nb-banks = <2>;
229				atmel,can-isoc;
230			};
231
232			ep15 {
233				reg = <15>;
234				atmel,fifo-size = <1024>;
235				atmel,nb-banks = <2>;
236				atmel,can-isoc;
237			};
238		};
239
240		usb1: ohci@00400000 {
241			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
242			reg = <0x00400000 0x100000>;
243			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
244			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
245			clock-names = "ohci_clk", "hclk", "uhpck";
246			status = "disabled";
247		};
248
249		usb2: ehci@00500000 {
250			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
251			reg = <0x00500000 0x100000>;
252			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
253			clocks = <&utmi>, <&uhphs_clk>;
254			clock-names = "usb_clk", "ehci_clk";
255			status = "disabled";
256		};
257
258		L2: cache-controller@00a00000 {
259			compatible = "arm,pl310-cache";
260			reg = <0x00a00000 0x1000>;
261			interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
262			cache-unified;
263			cache-level = <2>;
264		};
265
266		sdmmc0: sdio-host@a0000000 {
267			compatible = "atmel,sama5d2-sdhci";
268			reg = <0xa0000000 0x300>;
269			interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
270			clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
271			clock-names = "hclock", "multclk", "baseclk";
272			status = "disabled";
273		};
274
275		sdmmc1: sdio-host@b0000000 {
276			compatible = "atmel,sama5d2-sdhci";
277			reg = <0xb0000000 0x300>;
278			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
279			clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
280			clock-names = "hclock", "multclk", "baseclk";
281			status = "disabled";
282		};
283
284		apb {
285			compatible = "simple-bus";
286			#address-cells = <1>;
287			#size-cells = <1>;
288			ranges;
289
290			ramc0: ramc@f000c000 {
291				compatible = "atmel,sama5d3-ddramc";
292				reg = <0xf000c000 0x200>;
293				clocks = <&ddrck>, <&mpddr_clk>;
294				clock-names = "ddrck", "mpddr";
295			};
296
297			dma0: dma-controller@f0010000 {
298				compatible = "atmel,sama5d4-dma";
299				reg = <0xf0010000 0x1000>;
300				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
301				#dma-cells = <1>;
302				clocks = <&dma0_clk>;
303				clock-names = "dma_clk";
304			};
305
306			pmc: pmc@f0014000 {
307				compatible = "atmel,sama5d2-pmc", "syscon";
308				reg = <0xf0014000 0x160>;
309				interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
310				interrupt-controller;
311				#address-cells = <1>;
312				#size-cells = <0>;
313				#interrupt-cells = <1>;
314
315				main_rc_osc: main_rc_osc {
316					compatible = "atmel,at91sam9x5-clk-main-rc-osc";
317					#clock-cells = <0>;
318					interrupt-parent = <&pmc>;
319					interrupts = <AT91_PMC_MOSCRCS>;
320					clock-frequency = <12000000>;
321					clock-accuracy = <100000000>;
322				};
323
324				main_osc: main_osc {
325					compatible = "atmel,at91rm9200-clk-main-osc";
326					#clock-cells = <0>;
327					interrupt-parent = <&pmc>;
328					interrupts = <AT91_PMC_MOSCS>;
329					clocks = <&main_xtal>;
330				};
331
332				main: mainck {
333					compatible = "atmel,at91sam9x5-clk-main";
334					#clock-cells = <0>;
335					interrupt-parent = <&pmc>;
336					interrupts = <AT91_PMC_MOSCSELS>;
337					clocks = <&main_rc_osc &main_osc>;
338				};
339
340				plla: pllack {
341					compatible = "atmel,sama5d3-clk-pll";
342					#clock-cells = <0>;
343					interrupt-parent = <&pmc>;
344					interrupts = <AT91_PMC_LOCKA>;
345					clocks = <&main>;
346					reg = <0>;
347					atmel,clk-input-range = <12000000 12000000>;
348					#atmel,pll-clk-output-range-cells = <4>;
349					atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
350				};
351
352				plladiv: plladivck {
353					compatible = "atmel,at91sam9x5-clk-plldiv";
354					#clock-cells = <0>;
355					clocks = <&plla>;
356				};
357
358				utmi: utmick {
359					compatible = "atmel,at91sam9x5-clk-utmi";
360					#clock-cells = <0>;
361					interrupt-parent = <&pmc>;
362					interrupts = <AT91_PMC_LOCKU>;
363					clocks = <&main>;
364				};
365
366				mck: masterck {
367					compatible = "atmel,at91sam9x5-clk-master";
368					#clock-cells = <0>;
369					interrupt-parent = <&pmc>;
370					interrupts = <AT91_PMC_MCKRDY>;
371					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
372					atmel,clk-output-range = <124000000 166000000>;
373					atmel,clk-divisors = <1 2 4 3>;
374				};
375
376				h32ck: h32mxck {
377					#clock-cells = <0>;
378					compatible = "atmel,sama5d4-clk-h32mx";
379					clocks = <&mck>;
380				};
381
382				usb: usbck {
383					compatible = "atmel,at91sam9x5-clk-usb";
384					#clock-cells = <0>;
385					clocks = <&plladiv>, <&utmi>;
386				};
387
388				prog: progck {
389					compatible = "atmel,at91sam9x5-clk-programmable";
390					#address-cells = <1>;
391					#size-cells = <0>;
392					interrupt-parent = <&pmc>;
393					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
394
395					prog0: prog0 {
396						#clock-cells = <0>;
397						reg = <0>;
398						interrupts = <AT91_PMC_PCKRDY(0)>;
399					};
400
401					prog1: prog1 {
402						#clock-cells = <0>;
403						reg = <1>;
404						interrupts = <AT91_PMC_PCKRDY(1)>;
405					};
406
407					prog2: prog2 {
408						#clock-cells = <0>;
409						reg = <2>;
410						interrupts = <AT91_PMC_PCKRDY(2)>;
411					};
412				};
413
414				systemck {
415					compatible = "atmel,at91rm9200-clk-system";
416					#address-cells = <1>;
417					#size-cells = <0>;
418
419					ddrck: ddrck {
420						#clock-cells = <0>;
421						reg = <2>;
422						clocks = <&mck>;
423					};
424
425					lcdck: lcdck {
426						#clock-cells = <0>;
427						reg = <3>;
428						clocks = <&mck>;
429					};
430
431					uhpck: uhpck {
432						#clock-cells = <0>;
433						reg = <6>;
434						clocks = <&usb>;
435					};
436
437					udpck: udpck {
438						#clock-cells = <0>;
439						reg = <7>;
440						clocks = <&usb>;
441					};
442
443					pck0: pck0 {
444						#clock-cells = <0>;
445						reg = <8>;
446						clocks = <&prog0>;
447					};
448
449					pck1: pck1 {
450						#clock-cells = <0>;
451						reg = <9>;
452						clocks = <&prog1>;
453					};
454
455					pck2: pck2 {
456						#clock-cells = <0>;
457						reg = <10>;
458						clocks = <&prog2>;
459					};
460
461					iscck: iscck {
462						#clock-cells = <0>;
463						reg = <18>;
464						clocks = <&mck>;
465					};
466				};
467
468				periph32ck {
469					compatible = "atmel,at91sam9x5-clk-peripheral";
470					#address-cells = <1>;
471					#size-cells = <0>;
472					clocks = <&h32ck>;
473
474					macb0_clk: macb0_clk {
475						#clock-cells = <0>;
476						reg = <5>;
477						atmel,clk-output-range = <0 83000000>;
478					};
479
480					tdes_clk: tdes_clk {
481						#clock-cells = <0>;
482						reg = <11>;
483						atmel,clk-output-range = <0 83000000>;
484					};
485
486					matrix1_clk: matrix1_clk {
487						#clock-cells = <0>;
488						reg = <14>;
489					};
490
491					hsmc_clk: hsmc_clk {
492						#clock-cells = <0>;
493						reg = <17>;
494					};
495
496					pioA_clk: pioA_clk {
497						#clock-cells = <0>;
498						reg = <18>;
499						atmel,clk-output-range = <0 83000000>;
500					};
501
502					flx0_clk: flx0_clk {
503						#clock-cells = <0>;
504						reg = <19>;
505						atmel,clk-output-range = <0 83000000>;
506					};
507
508					flx1_clk: flx1_clk {
509						#clock-cells = <0>;
510						reg = <20>;
511						atmel,clk-output-range = <0 83000000>;
512					};
513
514					flx2_clk: flx2_clk {
515						#clock-cells = <0>;
516						reg = <21>;
517						atmel,clk-output-range = <0 83000000>;
518					};
519
520					flx3_clk: flx3_clk {
521						#clock-cells = <0>;
522						reg = <22>;
523						atmel,clk-output-range = <0 83000000>;
524					};
525
526					flx4_clk: flx4_clk {
527						#clock-cells = <0>;
528						reg = <23>;
529						atmel,clk-output-range = <0 83000000>;
530					};
531
532					uart0_clk: uart0_clk {
533						#clock-cells = <0>;
534						reg = <24>;
535						atmel,clk-output-range = <0 83000000>;
536					};
537
538					uart1_clk: uart1_clk {
539						#clock-cells = <0>;
540						reg = <25>;
541						atmel,clk-output-range = <0 83000000>;
542					};
543
544					uart2_clk: uart2_clk {
545						#clock-cells = <0>;
546						reg = <26>;
547						atmel,clk-output-range = <0 83000000>;
548					};
549
550					uart3_clk: uart3_clk {
551						#clock-cells = <0>;
552						reg = <27>;
553						atmel,clk-output-range = <0 83000000>;
554					};
555
556					uart4_clk: uart4_clk {
557						#clock-cells = <0>;
558						reg = <28>;
559						atmel,clk-output-range = <0 83000000>;
560					};
561
562					twi0_clk: twi0_clk {
563						reg = <29>;
564						#clock-cells = <0>;
565						atmel,clk-output-range = <0 83000000>;
566					};
567
568					twi1_clk: twi1_clk {
569						#clock-cells = <0>;
570						reg = <30>;
571						atmel,clk-output-range = <0 83000000>;
572					};
573
574					spi0_clk: spi0_clk {
575						#clock-cells = <0>;
576						reg = <33>;
577						atmel,clk-output-range = <0 83000000>;
578					};
579
580					spi1_clk: spi1_clk {
581						#clock-cells = <0>;
582						reg = <34>;
583						atmel,clk-output-range = <0 83000000>;
584					};
585
586					tcb0_clk: tcb0_clk {
587						#clock-cells = <0>;
588						reg = <35>;
589						atmel,clk-output-range = <0 83000000>;
590					};
591
592					tcb1_clk: tcb1_clk {
593						#clock-cells = <0>;
594						reg = <36>;
595						atmel,clk-output-range = <0 83000000>;
596					};
597
598					pwm_clk: pwm_clk {
599						#clock-cells = <0>;
600						reg = <38>;
601						atmel,clk-output-range = <0 83000000>;
602					};
603
604					adc_clk: adc_clk {
605						#clock-cells = <0>;
606						reg = <40>;
607						atmel,clk-output-range = <0 83000000>;
608					};
609
610					uhphs_clk: uhphs_clk {
611						#clock-cells = <0>;
612						reg = <41>;
613						atmel,clk-output-range = <0 83000000>;
614					};
615
616					udphs_clk: udphs_clk {
617						#clock-cells = <0>;
618						reg = <42>;
619						atmel,clk-output-range = <0 83000000>;
620					};
621
622					ssc0_clk: ssc0_clk {
623						#clock-cells = <0>;
624						reg = <43>;
625						atmel,clk-output-range = <0 83000000>;
626					};
627
628					ssc1_clk: ssc1_clk {
629						#clock-cells = <0>;
630						reg = <44>;
631						atmel,clk-output-range = <0 83000000>;
632					};
633
634					trng_clk: trng_clk {
635						#clock-cells = <0>;
636						reg = <47>;
637						atmel,clk-output-range = <0 83000000>;
638					};
639
640					i2s0_clk: i2s0_clk {
641						#clock-cells = <0>;
642						reg = <54>;
643						atmel,clk-output-range = <0 83000000>;
644					};
645
646					i2s1_clk: i2s1_clk {
647						#clock-cells = <0>;
648						reg = <55>;
649						atmel,clk-output-range = <0 83000000>;
650					};
651
652					classd_clk: classd_clk {
653						#clock-cells = <0>;
654						reg = <59>;
655						atmel,clk-output-range = <0 83000000>;
656					};
657				};
658
659				periph64ck {
660					compatible = "atmel,at91sam9x5-clk-peripheral";
661					#address-cells = <1>;
662					#size-cells = <0>;
663					clocks = <&mck>;
664
665					dma0_clk: dma0_clk {
666						#clock-cells = <0>;
667						reg = <6>;
668					};
669
670					dma1_clk: dma1_clk {
671						#clock-cells = <0>;
672						reg = <7>;
673					};
674
675					aes_clk: aes_clk {
676						#clock-cells = <0>;
677						reg = <9>;
678					};
679
680					aesb_clk: aesb_clk {
681						#clock-cells = <0>;
682						reg = <10>;
683					};
684
685					sha_clk: sha_clk {
686						#clock-cells = <0>;
687						reg = <12>;
688					};
689
690					mpddr_clk: mpddr_clk {
691						#clock-cells = <0>;
692						reg = <13>;
693					};
694
695					matrix0_clk: matrix0_clk {
696						#clock-cells = <0>;
697						reg = <15>;
698					};
699
700					sdmmc0_hclk: sdmmc0_hclk {
701						#clock-cells = <0>;
702						reg = <31>;
703					};
704
705					sdmmc1_hclk: sdmmc1_hclk {
706						#clock-cells = <0>;
707						reg = <32>;
708					};
709
710					lcdc_clk: lcdc_clk {
711						#clock-cells = <0>;
712						reg = <45>;
713					};
714
715					isc_clk: isc_clk {
716						#clock-cells = <0>;
717						reg = <46>;
718					};
719
720					qspi0_clk: qspi0_clk {
721						#clock-cells = <0>;
722						reg = <52>;
723					};
724
725					qspi1_clk: qspi1_clk {
726						#clock-cells = <0>;
727						reg = <53>;
728					};
729				};
730
731				gck {
732					compatible = "atmel,sama5d2-clk-generated";
733					#address-cells = <1>;
734					#size-cells = <0>;
735					interrupt-parent = <&pmc>;
736					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
737
738					sdmmc0_gclk: sdmmc0_gclk {
739						#clock-cells = <0>;
740						reg = <31>;
741					};
742
743					sdmmc1_gclk: sdmmc1_gclk {
744						#clock-cells = <0>;
745						reg = <32>;
746					};
747
748					tcb0_gclk: tcb0_gclk {
749						#clock-cells = <0>;
750						reg = <35>;
751						atmel,clk-output-range = <0 83000000>;
752					};
753
754					tcb1_gclk: tcb1_gclk {
755						#clock-cells = <0>;
756						reg = <36>;
757						atmel,clk-output-range = <0 83000000>;
758					};
759
760					pwm_gclk: pwm_gclk {
761						#clock-cells = <0>;
762						reg = <38>;
763						atmel,clk-output-range = <0 83000000>;
764					};
765
766					i2s0_gclk: i2s0_gclk {
767						#clock-cells = <0>;
768						reg = <54>;
769					};
770
771					i2s1_gclk: i2s1_gclk {
772						#clock-cells = <0>;
773						reg = <55>;
774					};
775				};
776			};
777
778			sha@f0028000 {
779				compatible = "atmel,at91sam9g46-sha";
780				reg = <0xf0028000 0x100>;
781				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
782				dmas = <&dma0
783					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
784					 AT91_XDMAC_DT_PERID(30))>;
785				dma-names = "tx";
786				clocks = <&sha_clk>;
787				clock-names = "sha_clk";
788				status = "okay";
789			};
790
791			aes@f002c000 {
792				compatible = "atmel,at91sam9g46-aes";
793				reg = <0xf002c000 0x100>;
794				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
795				dmas = <&dma0
796					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
797					 AT91_XDMAC_DT_PERID(26))>,
798				       <&dma0
799					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
800					 AT91_XDMAC_DT_PERID(27))>;
801				dma-names = "tx", "rx";
802				clocks = <&aes_clk>;
803				clock-names = "aes_clk";
804				status = "okay";
805			};
806
807			spi0: spi@f8000000 {
808				compatible = "atmel,at91rm9200-spi";
809				reg = <0xf8000000 0x100>;
810				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
811				dmas = <&dma0
812					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
813					 AT91_XDMAC_DT_PERID(6))>,
814				       <&dma0
815					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
816					 AT91_XDMAC_DT_PERID(7))>;
817				dma-names = "tx", "rx";
818				clocks = <&spi0_clk>;
819				clock-names = "spi_clk";
820				atmel,fifo-size = <16>;
821				#address-cells = <1>;
822				#size-cells = <0>;
823				status = "disabled";
824			};
825
826			macb0: ethernet@f8008000 {
827				compatible = "atmel,sama5d2-gem";
828				reg = <0xf8008000 0x1000>;
829				interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3		/* Queue 0 */
830					      66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
831					      67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
832				#address-cells = <1>;
833				#size-cells = <0>;
834				clocks = <&macb0_clk>, <&macb0_clk>;
835				clock-names = "hclk", "pclk";
836				status = "disabled";
837			};
838
839			tcb0: timer@f800c000 {
840				compatible = "atmel,at91sam9x5-tcb";
841				reg = <0xf800c000 0x100>;
842				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
843				clocks = <&tcb0_clk>, <&clk32k>;
844				clock-names = "t0_clk", "slow_clk";
845			};
846
847			tcb1: timer@f8010000 {
848				compatible = "atmel,at91sam9x5-tcb";
849				reg = <0xf8010000 0x100>;
850				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
851				clocks = <&tcb1_clk>, <&clk32k>;
852				clock-names = "t0_clk", "slow_clk";
853			};
854
855			uart0: serial@f801c000 {
856				compatible = "atmel,at91sam9260-usart";
857				reg = <0xf801c000 0x100>;
858				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
859				clocks = <&uart0_clk>;
860				clock-names = "usart";
861				status = "disabled";
862			};
863
864			uart1: serial@f8020000 {
865				compatible = "atmel,at91sam9260-usart";
866				reg = <0xf8020000 0x100>;
867				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
868				clocks = <&uart1_clk>;
869				clock-names = "usart";
870				status = "disabled";
871			};
872
873			uart2: serial@f8024000 {
874				compatible = "atmel,at91sam9260-usart";
875				reg = <0xf8024000 0x100>;
876				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
877				clocks = <&uart2_clk>;
878				clock-names = "usart";
879				status = "disabled";
880			};
881
882			i2c0: i2c@f8028000 {
883				compatible = "atmel,sama5d2-i2c";
884				reg = <0xf8028000 0x100>;
885				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
886				dmas = <&dma0
887					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
888					 AT91_XDMAC_DT_PERID(0))>,
889				       <&dma0
890					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
891					 AT91_XDMAC_DT_PERID(1))>;
892				dma-names = "tx", "rx";
893				#address-cells = <1>;
894				#size-cells = <0>;
895				clocks = <&twi0_clk>;
896				status = "disabled";
897			};
898
899			flx0: flexcom@f8034000 {
900				compatible = "atmel,sama5d2-flexcom";
901				reg = <0xf8034000 0x200>;
902				clocks = <&flx0_clk>;
903				#address-cells = <1>;
904				#size-cells = <1>;
905				ranges = <0x0 0xf8034000 0x800>;
906				status = "disabled";
907			};
908
909			flx1: flexcom@f8038000 {
910				compatible = "atmel,sama5d2-flexcom";
911				reg = <0xf8038000 0x200>;
912				clocks = <&flx1_clk>;
913				#address-cells = <1>;
914				#size-cells = <1>;
915				ranges = <0x0 0xf8038000 0x800>;
916				status = "disabled";
917			};
918
919			rstc@f8048000 {
920				compatible = "atmel,sama5d3-rstc";
921				reg = <0xf8048000 0x10>;
922				clocks = <&clk32k>;
923			};
924
925			pit: timer@f8048030 {
926				compatible = "atmel,at91sam9260-pit";
927				reg = <0xf8048030 0x10>;
928				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
929				clocks = <&h32ck>;
930			};
931
932			sckc@f8048050 {
933				compatible = "atmel,at91sam9x5-sckc";
934				reg = <0xf8048050 0x4>;
935
936				slow_rc_osc: slow_rc_osc {
937					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
938					#clock-cells = <0>;
939					clock-frequency = <32768>;
940					clock-accuracy = <250000000>;
941					atmel,startup-time-usec = <75>;
942				};
943
944				slow_osc: slow_osc {
945					compatible = "atmel,at91sam9x5-clk-slow-osc";
946					#clock-cells = <0>;
947					clocks = <&slow_xtal>;
948					atmel,startup-time-usec = <1200000>;
949				};
950
951				clk32k: slowck {
952					compatible = "atmel,at91sam9x5-clk-slow";
953					#clock-cells = <0>;
954					clocks = <&slow_rc_osc &slow_osc>;
955				};
956			};
957
958			rtc@f80480b0 {
959				compatible = "atmel,at91rm9200-rtc";
960				reg = <0xf80480b0 0x30>;
961				interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
962				clocks = <&clk32k>;
963			};
964
965			spi1: spi@fc000000 {
966				compatible = "atmel,at91rm9200-spi";
967				reg = <0xfc000000 0x100>;
968				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
969				dmas = <&dma0
970					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
971					 AT91_XDMAC_DT_PERID(8))>,
972				       <&dma0
973					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
974					 AT91_XDMAC_DT_PERID(9))>;
975				dma-names = "tx", "rx";
976				clocks = <&spi1_clk>;
977				clock-names = "spi_clk";
978				atmel,fifo-size = <16>;
979				#address-cells = <1>;
980				#size-cells = <0>;
981				status = "disabled";
982			};
983
984			uart3: serial@fc008000 {
985				compatible = "atmel,at91sam9260-usart";
986				reg = <0xfc008000 0x100>;
987				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
988				clocks = <&uart3_clk>;
989				clock-names = "usart";
990				status = "disabled";
991			};
992
993			uart4: serial@fc00c000 {
994				compatible = "atmel,at91sam9260-usart";
995				reg = <0xfc00c000 0x100>;
996				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
997				clocks = <&uart4_clk>;
998				clock-names = "usart";
999				status = "disabled";
1000			};
1001
1002			flx2: flexcom@fc010000 {
1003				compatible = "atmel,sama5d2-flexcom";
1004				reg = <0xfc010000 0x200>;
1005				clocks = <&flx2_clk>;
1006				#address-cells = <1>;
1007				#size-cells = <1>;
1008				ranges = <0x0 0xfc010000 0x800>;
1009				status = "disabled";
1010			};
1011
1012			flx3: flexcom@fc014000 {
1013				compatible = "atmel,sama5d2-flexcom";
1014				reg = <0xfc014000 0x200>;
1015				clocks = <&flx3_clk>;
1016				#address-cells = <1>;
1017				#size-cells = <1>;
1018				ranges = <0x0 0xfc014000 0x800>;
1019				status = "disabled";
1020			};
1021
1022			flx4: flexcom@fc018000 {
1023				compatible = "atmel,sama5d2-flexcom";
1024				reg = <0xfc018000 0x200>;
1025				clocks = <&flx4_clk>;
1026				#address-cells = <1>;
1027				#size-cells = <1>;
1028				ranges = <0x0 0xfc018000 0x800>;
1029				status = "disabled";
1030			};
1031
1032			aic: interrupt-controller@fc020000 {
1033				#interrupt-cells = <3>;
1034				compatible = "atmel,sama5d2-aic";
1035				interrupt-controller;
1036				reg = <0xfc020000 0x200>;
1037				atmel,external-irqs = <49>;
1038			};
1039
1040			i2c1: i2c@fc028000 {
1041				compatible = "atmel,sama5d2-i2c";
1042				reg = <0xfc028000 0x100>;
1043				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1044				dmas = <&dma0
1045					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1046					 AT91_XDMAC_DT_PERID(2))>,
1047				       <&dma0
1048					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1049					 AT91_XDMAC_DT_PERID(3))>;
1050				dma-names = "tx", "rx";
1051				#address-cells = <1>;
1052				#size-cells = <0>;
1053				clocks = <&twi1_clk>;
1054				status = "disabled";
1055			};
1056
1057			pioA: pinctrl@fc038000 {
1058				compatible = "atmel,sama5d2-pinctrl";
1059				reg = <0xfc038000 0x600>;
1060				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1061					     <68 IRQ_TYPE_LEVEL_HIGH 7>,
1062					     <69 IRQ_TYPE_LEVEL_HIGH 7>,
1063					     <70 IRQ_TYPE_LEVEL_HIGH 7>;
1064				interrupt-controller;
1065				#interrupt-cells = <2>;
1066				gpio-controller;
1067				#gpio-cells = <2>;
1068				clocks = <&pioA_clk>;
1069			};
1070
1071			tdes@fc044000 {
1072				compatible = "atmel,at91sam9g46-tdes";
1073				reg = <0xfc044000 0x100>;
1074				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1075				dmas = <&dma0
1076					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1077					 AT91_XDMAC_DT_PERID(28))>,
1078				       <&dma0
1079					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1080					 AT91_XDMAC_DT_PERID(29))>;
1081				dma-names = "tx", "rx";
1082				clocks = <&tdes_clk>;
1083				clock-names = "tdes_clk";
1084				status = "okay";
1085			};
1086		};
1087	};
1088};
1089