Lines Matching refs:clocks
36 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
37 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
52 - clocks: If clock-frequency is not specified, sysclk may be provided
53 as an input clock. Either clock-frequency or clocks must be
83 clocks = <&clockgen 3 0>;
97 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
98 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
99 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
100 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
109 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
110 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
117 - clocks: Should be the phandle of input parent clock
120 output clocks
144 clocks = <&sysclk>;
152 clocks = <&sysclk>;
160 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
169 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
178 clocks = <&sysclk>;
189 clocks = <&mux0>;