1* Clock Block on Freescale QorIQ Platforms
2
3Freescale QorIQ chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version		Example Chips
14---------------		-------------
151.0			p4080, p5020, p5040
162.0			t4240, b4860
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a chip-specific clock block compatible
22	string and (if applicable) may contain a chassis-version clock
23	compatible string.
24
25	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26	* "fsl,p2041-clockgen"
27	* "fsl,p3041-clockgen"
28	* "fsl,p4080-clockgen"
29	* "fsl,p5020-clockgen"
30	* "fsl,p5040-clockgen"
31	* "fsl,t4240-clockgen"
32	* "fsl,b4420-clockgen"
33	* "fsl,b4860-clockgen"
34	* "fsl,ls1021a-clockgen"
35	Chassis-version clock strings include:
36	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
37	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
38- reg: Describes the address of the device's resources within the
39	address space defined by its parent bus, and resource zero
40	represents the clock register set
41
42Optional properties:
43- ranges: Allows valid translation between child's address space and
44	parent's. Must be present if the device has sub-nodes.
45- #address-cells: Specifies the number of cells used to represent
46	physical base addresses.  Must be present if the device has
47	sub-nodes and set to 1 if present
48- #size-cells: Specifies the number of cells used to represent
49	the size of an address. Must be present if the device has
50	sub-nodes and set to 1 if present
51- clock-frequency: Input system clock frequency (SYSCLK)
52- clocks: If clock-frequency is not specified, sysclk may be provided
53	as an input clock.  Either clock-frequency or clocks must be
54	provided.
55
562. Clock Provider
57
58The clockgen node should act as a clock provider, though in older device
59trees the children of the clockgen node are the clock providers.
60
61When the clockgen node is a clock provider, #clock-cells = <2>.
62The first cell of the clock specifier is the clock type, and the
63second cell is the clock index for the specified type.
64
65	Type#	Name		Index Cell
66	0	sysclk		must be 0
67	1	cmux		index (n in CLKCnCSR)
68	2	hwaccel		index (n in CLKCGnHWACSR)
69	3	fman		0 for fm1, 1 for fm2
70	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
71
723. Example
73
74	clockgen: global-utilities@e1000 {
75		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
76		clock-frequency = <133333333>;
77		reg = <0xe1000 0x1000>;
78		#clock-cells = <2>;
79	};
80
81	fman@400000 {
82		...
83		clocks = <&clockgen 3 0>;
84		...
85	};
86}
874. Legacy Child Nodes
88
89NOTE: These nodes are deprecated.  Kernels should continue to support
90device trees with these nodes, but new device trees should not use them.
91
92Most of the bindings are from the common clock binding[1].
93 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
94
95Required properties:
96- compatible : Should include one of the following:
97	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
98	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
99	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
100	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
101	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
102		It takes parent's clock-frequency as its clock.
103	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
104		It takes parent's clock-frequency as its clock.
105	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
106	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
107- #clock-cells: From common clock binding. The number of cells in a
108	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
109	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
110	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
111	clock-specifier cell may take the following values:
112	* 0 - equal to the PLL frequency
113	* 1 - equal to the PLL frequency divided by 2
114	* 2 - equal to the PLL frequency divided by 4
115
116Recommended properties:
117- clocks: Should be the phandle of input parent clock
118- clock-names: From common clock binding, indicates the clock name
119- clock-output-names: From common clock binding, indicates the names of
120	output clocks
121- reg: Should be the offset and length of clock block base address.
122	The length should be 4.
123
124Legacy Example:
125/ {
126	clockgen: global-utilities@e1000 {
127		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
128		ranges = <0x0 0xe1000 0x1000>;
129		clock-frequency = <133333333>;
130		reg = <0xe1000 0x1000>;
131		#address-cells = <1>;
132		#size-cells = <1>;
133
134		sysclk: sysclk {
135			#clock-cells = <0>;
136			compatible = "fsl,qoriq-sysclk-1.0";
137			clock-output-names = "sysclk";
138		};
139
140		pll0: pll0@800 {
141			#clock-cells = <1>;
142			reg = <0x800 0x4>;
143			compatible = "fsl,qoriq-core-pll-1.0";
144			clocks = <&sysclk>;
145			clock-output-names = "pll0", "pll0-div2";
146		};
147
148		pll1: pll1@820 {
149			#clock-cells = <1>;
150			reg = <0x820 0x4>;
151			compatible = "fsl,qoriq-core-pll-1.0";
152			clocks = <&sysclk>;
153			clock-output-names = "pll1", "pll1-div2";
154		};
155
156		mux0: mux0@0 {
157			#clock-cells = <0>;
158			reg = <0x0 0x4>;
159			compatible = "fsl,qoriq-core-mux-1.0";
160			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
161			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
162			clock-output-names = "cmux0";
163		};
164
165		mux1: mux1@20 {
166			#clock-cells = <0>;
167			reg = <0x20 0x4>;
168			compatible = "fsl,qoriq-core-mux-1.0";
169			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
170			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
171			clock-output-names = "cmux1";
172		};
173
174		platform-pll: platform-pll@c00 {
175			#clock-cells = <1>;
176			reg = <0xc00 0x4>;
177			compatible = "fsl,qoriq-platform-pll-1.0";
178			clocks = <&sysclk>;
179			clock-output-names = "platform-pll", "platform-pll-div2";
180		};
181	};
182};
183
184Example for legacy clock consumer:
185
186/ {
187	cpu0: PowerPC,e5500@0 {
188		...
189		clocks = <&mux0>;
190		...
191	};
192};
193